[OpenSPARC-T2-DV] / libs / n2sram / dp / n2_l2t_dp_32x128_cust_l / n2_l2t_dp_32x128_cust / rtl / n2_l2t_dp_32x128_cust.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_l2t_dp_32x128_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_l2t_dp_32x128_cust (
  din, 
  rd_wl, 
  wr_wl, 
  read_en, 
  wr_en, 
  tcu_array_wr_inhibit, 
  l2clk, 
  scan_in, 
  tcu_se_scancollar_in, 
  tcu_scan_en, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_pce_ov, 
  pce, 
  dout, 
  scan_out) ;
wire siclk;
wire soclk;
wire stop;
wire pce_ov;
wire l1clk;
wire l1clk_mem;
wire ff_wdata_0_scanin;
wire ff_wdata_0_scanout;
wire [127:0] wrdata_d1;
wire ff_wdata_1_scanin;
wire ff_wdata_1_scanout;
wire ff_wr_en_scanin;
wire ff_wr_en_scanout;
wire wr_en_d1;
wire ff_wr_wl_scanin;
wire ff_wr_wl_scanout;
wire [31:0] wr_wl_d1;
wire ff_ren_scanin;
wire ff_ren_scanout;
wire ff_ren0_unused;
wire ff_ren1_unused;
wire ff_ren2_unused;
wire ren_d1;
wire ff_rd_wl_scanin;
wire ff_rd_wl_scanout;
wire [31:0] rd_wl_d1;


input [127:0]  	din; 		// data input
input [31:0]    rd_wl;   	// read addr 
input [31:0]	wr_wl;  	// write addr
input          	read_en;  
input	  	wr_en;		//   used in conjunction with
     				//  word_wen and byte_wen 
input	  	tcu_array_wr_inhibit ; 	// gates off writes during SCAN.
input          	l2clk;
input          	scan_in; 

input	  	tcu_se_scancollar_in; // hold scan in data.
input	  	tcu_scan_en; // hold scan in data.
input          	tcu_aclk;
input          	tcu_bclk;

input          	tcu_pce_ov;
input          	pce;


output [127:0] 	dout;
output         	scan_out;

// JDL 05/17/07
// synopsys translate_off

wire   [127:0] dout_array;

assign dout[127:0] = dout_array[127:0];

// scan chain connections ////
assign siclk = tcu_aclk;
assign soclk = tcu_bclk;
assign stop  = 1'b0;
assign pce_ov = tcu_pce_ov;

//// Input Flops /////
n2_l2t_dp_32x128_cust_l1clkhdr_ctl_macro	clkgen_clk_en
	(
	.l2clk	(l2clk	),
	.l1en	(pce	),
	.pce_ov (pce_ov	),
	.stop	(stop	),
	.se	(tcu_se_scancollar_in),
	.l1clk	(l1clk	)
	);

n2_l2t_dp_32x128_cust_l1clkhdr_ctl_macro      clkgen_clk_en0
        (
        .l2clk  (l2clk  ),
        .l1en   (pce    ),
        .pce_ov (pce_ov ),
        .stop   (stop   ),
        .se     (tcu_scan_en),
        .l1clk  (l1clk_mem  )
        );


n2_l2t_dp_32x128_cust_msff_ctl_macro__scanreverse_1__width_64 ff_wdata_0     
	(
	.scan_in(ff_wdata_0_scanin),
	.scan_out(ff_wdata_0_scanout),
	.l1clk(l1clk),
	.din(din[63:0]),
	.dout(wrdata_d1[63:0]),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2t_dp_32x128_cust_msff_ctl_macro__scanreverse_1__width_64 ff_wdata_1  
	(
        .scan_in(ff_wdata_1_scanin),
        .scan_out(ff_wdata_1_scanout),
        .l1clk(l1clk),
        .din(din[127:64]),
        .dout(wrdata_d1[127:64]),
  .siclk(siclk),
  .soclk(soclk)
        );


n2_l2t_dp_32x128_cust_msff_ctl_macro__width_1 ff_wr_en  
	 (
         .scan_in(ff_wr_en_scanin),
         .scan_out(ff_wr_en_scanout),
         .l1clk(l1clk),
         .din(wr_en),
         .dout(wr_en_d1),
  .siclk(siclk),
  .soclk(soclk)
         );


n2_l2t_dp_32x128_cust_msff_ctl_macro__width_32 ff_wr_wl  
	 (
          .scan_in(ff_wr_wl_scanin),
          .scan_out(ff_wr_wl_scanout),
          .l1clk(l1clk),
          .din(wr_wl[31:0]),
	  .dout(wr_wl_d1[31:0]),
  .siclk(siclk),
  .soclk(soclk)
         );


n2_l2t_dp_32x128_cust_sram_msff_mo_macro__width_1 ff_ren  
	 (
         .scan_in(ff_ren_scanin),
         .scan_out(ff_ren_scanout),
         .l1clk(l1clk),
	 .and_clk(l1clk_mem),
	 .q(ff_ren0_unused),
	 .q_l(ff_ren1_unused),
	 .mq_l(ff_ren2_unused),
         .d(read_en),
         .mq(ren_d1),
  .siclk(siclk),
  .soclk(soclk)
         );


n2_l2t_dp_32x128_cust_msff_ctl_macro__width_32 ff_rd_wl  
	 (
         .scan_in(ff_rd_wl_scanin),
         .scan_out(ff_rd_wl_scanout),
         .l1clk(l1clk),
         .din(rd_wl[31:0]),
         .dout(rd_wl_d1[31:0]),
  .siclk(siclk),
  .soclk(soclk)
         );


//msff_ctl_macro ff_tcu_array_wr_inhibit (width=1)
//	(  // not a real flop ( only used as a trigger ). Works only for accesses made in PH1
//        .scan_in(ff_tcu_se_scanin),
//        .scan_out(ff_tcu_se_scanout),
//        .l1clk(l1clk),
//        .din(tcu_array_wr_inhibit),
//        .dout(tcu_se_d1)
//        );
//

/// Memory array ////

n2_l2t_dp_32x128_cust_array array (
                .wr_en (wr_en_d1),
		.rd_en (ren_d1),
		.l1clk (l1clk_mem),
                .wr_addr(wr_wl_d1[31:0]),
                .rd_addr(rd_wl_d1[31:0]),
                .din(wrdata_d1[127:0]),
                .dout(dout_array[127:0]),
                .write_disable(tcu_array_wr_inhibit)
                 );

// fixscan start:
assign ff_wr_en_scanin           = scan_in       	;
assign ff_ren_scanin             = ff_wr_en_scanout	;
assign ff_rd_wl_scanin           = ff_ren_scanout	;
assign ff_wr_wl_scanin           = ff_rd_wl_scanout	;
assign ff_wdata_0_scanin         = ff_wr_wl_scanout	;
assign ff_wdata_1_scanin         = ff_wdata_0_scanout	;
assign scan_out          	 = ff_wdata_1_scanout	;
//assign scan_out			 = ff_tcu_se_scanout	;
// fixscan end:

// synopsys translate_on

endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//		ARRAY MODELLING					    //
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////


module n2_l2t_dp_32x128_cust_array (
  wr_en, 
  rd_en, 
  l1clk, 
  wr_addr, 
  rd_addr, 
  write_disable, 
  din, 
  dout) ;

input 		wr_en;
input 		rd_en;
input 		l1clk;
input 	[31:0] 	wr_addr;
input 	[31:0] 	rd_addr;
input 		write_disable;
input 	[127:0] din;

output 	[127:0] dout;

// memory array
reg [127:0]  	inq_ary [31:0];
// internal variable
reg 	[127:0] temp; 
reg	[127:0]	data_in;
reg 	[4:0]   rdptr_d1; 
reg	[4:0]	wrptr_d1;
reg 	[127:0] dout;

reg 	[127:0] rd_data;

`ifndef NOINITMEM
// Emulate reset
integer i;
initial begin
  for (i=0; i<32; i=i+1) begin
   inq_ary[i] = {128{1'b0}};
  end
end
`endif

 
//////////////////////////////////////////////////////////////////////
// Read Operation
//////////////////////////////////////////////////////////////////////


always @(rd_addr or rd_en or write_disable or wr_en or wr_addr or l1clk)
begin


	// ---- \/ added the write_disable qual on 11/11 \/------
           if (l1clk )  begin

             if (rd_en & ~write_disable) begin  

		case(rd_addr & {32{~write_disable}})
          		32'b0000_0000_0000_0000_0000_0000_0000_0000: ;  // do nothing
          		32'b0000_0000_0000_0000_0000_0000_0000_0001: rdptr_d1     = 5'b00000;
          		32'b0000_0000_0000_0000_0000_0000_0000_0010: rdptr_d1     = 5'b00001;
          		32'b0000_0000_0000_0000_0000_0000_0000_0100: rdptr_d1     = 5'b00010;
          		32'b0000_0000_0000_0000_0000_0000_0000_1000: rdptr_d1     = 5'b00011;
          		32'b0000_0000_0000_0000_0000_0000_0001_0000: rdptr_d1     = 5'b00100;
          		32'b0000_0000_0000_0000_0000_0000_0010_0000: rdptr_d1     = 5'b00101;
          		32'b0000_0000_0000_0000_0000_0000_0100_0000: rdptr_d1     = 5'b00110;
          		32'b0000_0000_0000_0000_0000_0000_1000_0000: rdptr_d1     = 5'b00111;
          		32'b0000_0000_0000_0000_0000_0001_0000_0000: rdptr_d1     = 5'b01000;
          		32'b0000_0000_0000_0000_0000_0010_0000_0000: rdptr_d1     = 5'b01001;
          		32'b0000_0000_0000_0000_0000_0100_0000_0000: rdptr_d1     = 5'b01010;
          		32'b0000_0000_0000_0000_0000_1000_0000_0000: rdptr_d1     = 5'b01011;
          		32'b0000_0000_0000_0000_0001_0000_0000_0000: rdptr_d1     = 5'b01100;
          		32'b0000_0000_0000_0000_0010_0000_0000_0000: rdptr_d1     = 5'b01101;
          		32'b0000_0000_0000_0000_0100_0000_0000_0000: rdptr_d1     = 5'b01110;
          		32'b0000_0000_0000_0000_1000_0000_0000_0000: rdptr_d1     = 5'b01111;
          		32'b0000_0000_0000_0001_0000_0000_0000_0000: rdptr_d1     = 5'b10000;
          		32'b0000_0000_0000_0010_0000_0000_0000_0000: rdptr_d1     = 5'b10001;
          		32'b0000_0000_0000_0100_0000_0000_0000_0000: rdptr_d1     = 5'b10010;
          		32'b0000_0000_0000_1000_0000_0000_0000_0000: rdptr_d1     = 5'b10011;
          		32'b0000_0000_0001_0000_0000_0000_0000_0000: rdptr_d1     = 5'b10100;
          		32'b0000_0000_0010_0000_0000_0000_0000_0000: rdptr_d1     = 5'b10101;
          		32'b0000_0000_0100_0000_0000_0000_0000_0000: rdptr_d1     = 5'b10110;
          		32'b0000_0000_1000_0000_0000_0000_0000_0000: rdptr_d1     = 5'b10111;
          		32'b0000_0001_0000_0000_0000_0000_0000_0000: rdptr_d1     = 5'b11000;
          		32'b0000_0010_0000_0000_0000_0000_0000_0000: rdptr_d1     = 5'b11001;
          		32'b0000_0100_0000_0000_0000_0000_0000_0000: rdptr_d1     = 5'b11010;
          		32'b0000_1000_0000_0000_0000_0000_0000_0000: rdptr_d1     = 5'b11011;
          		32'b0001_0000_0000_0000_0000_0000_0000_0000: rdptr_d1     = 5'b11100;
          		32'b0010_0000_0000_0000_0000_0000_0000_0000: rdptr_d1     = 5'b11101;
          		32'b0100_0000_0000_0000_0000_0000_0000_0000: rdptr_d1     = 5'b11110;
          		32'b1000_0000_0000_0000_0000_0000_0000_0000: rdptr_d1     = 5'b11111;
         		default: rdptr_d1 = 5'bx ; 
       		endcase
                      rd_data = inq_ary[rdptr_d1];
                      dout = rd_data;

                end 
                //else      
                      //dout[127:0] = 128'h0 ;
            end  //l1clk
end // always @ (...


//////////////////////////////////////////////////////////////////////
// Write Operation
//////////////////////////////////////////////////////////////////////
always @ (write_disable or wr_en or wr_addr or din or l1clk)
begin


	//`ifdef  INNO_MUXEX
		if((wr_en==1'bx) & ~l1clk) 
		begin
			// do nothing
		end
	//`endif
	 	else if(wr_en & ~write_disable & ~l1clk)  
		begin
			case(wr_addr)
		          32'b0000_0000_0000_0000_0000_0000_0000_0000: ;  // do nothing
		          32'b0000_0000_0000_0000_0000_0000_0000_0001: wrptr_d1     = 5'b00000;
		          32'b0000_0000_0000_0000_0000_0000_0000_0010: wrptr_d1     = 5'b00001;
		          32'b0000_0000_0000_0000_0000_0000_0000_0100: wrptr_d1     = 5'b00010;
		          32'b0000_0000_0000_0000_0000_0000_0000_1000: wrptr_d1     = 5'b00011;
		          32'b0000_0000_0000_0000_0000_0000_0001_0000: wrptr_d1     = 5'b00100;
		          32'b0000_0000_0000_0000_0000_0000_0010_0000: wrptr_d1     = 5'b00101;
		          32'b0000_0000_0000_0000_0000_0000_0100_0000: wrptr_d1     = 5'b00110;
		          32'b0000_0000_0000_0000_0000_0000_1000_0000: wrptr_d1     = 5'b00111;
		          32'b0000_0000_0000_0000_0000_0001_0000_0000: wrptr_d1     = 5'b01000;
		          32'b0000_0000_0000_0000_0000_0010_0000_0000: wrptr_d1     = 5'b01001;
		          32'b0000_0000_0000_0000_0000_0100_0000_0000: wrptr_d1     = 5'b01010;
		          32'b0000_0000_0000_0000_0000_1000_0000_0000: wrptr_d1     = 5'b01011;
		          32'b0000_0000_0000_0000_0001_0000_0000_0000: wrptr_d1     = 5'b01100;
		          32'b0000_0000_0000_0000_0010_0000_0000_0000: wrptr_d1     = 5'b01101;
		          32'b0000_0000_0000_0000_0100_0000_0000_0000: wrptr_d1     = 5'b01110;
		          32'b0000_0000_0000_0000_1000_0000_0000_0000: wrptr_d1     = 5'b01111;
		          32'b0000_0000_0000_0001_0000_0000_0000_0000: wrptr_d1     = 5'b10000;
		          32'b0000_0000_0000_0010_0000_0000_0000_0000: wrptr_d1     = 5'b10001;
		          32'b0000_0000_0000_0100_0000_0000_0000_0000: wrptr_d1     = 5'b10010;
		          32'b0000_0000_0000_1000_0000_0000_0000_0000: wrptr_d1     = 5'b10011;
		          32'b0000_0000_0001_0000_0000_0000_0000_0000: wrptr_d1     = 5'b10100;
		          32'b0000_0000_0010_0000_0000_0000_0000_0000: wrptr_d1     = 5'b10101;
		          32'b0000_0000_0100_0000_0000_0000_0000_0000: wrptr_d1     = 5'b10110;
		          32'b0000_0000_1000_0000_0000_0000_0000_0000: wrptr_d1     = 5'b10111;
		          32'b0000_0001_0000_0000_0000_0000_0000_0000: wrptr_d1     = 5'b11000;
		          32'b0000_0010_0000_0000_0000_0000_0000_0000: wrptr_d1     = 5'b11001;
		          32'b0000_0100_0000_0000_0000_0000_0000_0000: wrptr_d1     = 5'b11010;
		          32'b0000_1000_0000_0000_0000_0000_0000_0000: wrptr_d1     = 5'b11011;
		          32'b0001_0000_0000_0000_0000_0000_0000_0000: wrptr_d1     = 5'b11100;
		          32'b0010_0000_0000_0000_0000_0000_0000_0000: wrptr_d1     = 5'b11101;
		          32'b0100_0000_0000_0000_0000_0000_0000_0000: wrptr_d1     = 5'b11110;
		          32'b1000_0000_0000_0000_0000_0000_0000_0000: wrptr_d1     = 5'b11111;
          		  default:  wrptr_d1= 5'bx ; 
			endcase
			//`ifdef  INNO_MUXEX
			      if(wr_addr!=32'b0)
             			inq_ary[wrptr_d1] = din ;
			//`else
	 		else   
			begin
		       if(wr_addr!=32'b0)
             			inq_ary[wrptr_d1] = din ;
         		end
			//`endif
	 	end	
	 	else  
		begin
			// do nothing
	 	end	

end // always @ (...

endmodule // rf_32x128d


// any PARAMS parms go into naming of macro

module n2_l2t_dp_32x128_cust_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module n2_l2t_dp_32x128_cust_msff_ctl_macro__scanreverse_1__width_64 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [63:0] fdin;
wire [0:62] so;

  input [63:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [63:0] dout;
  output scan_out;
assign fdin[63:0] = din[63:0];


dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[63:0]),
.si({so[0:62],scan_in}),
.so({scan_out,so[0:62]}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_l2t_dp_32x128_cust_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_l2t_dp_32x128_cust_msff_ctl_macro__width_32 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [31:0] fdin;
wire [30:0] so;

  input [31:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [31:0] dout;
  output scan_out;
assign fdin[31:0] = din[31:0];


dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_l2t_dp_32x128_cust_sram_msff_mo_macro__width_1 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [0:0] d;
  input scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [0:0] mq;
output [0:0] mq_l;
  output scan_out;
output [0:0] q;
output [0:0] q_l;


new_dlata #(1)  d0_0 (
.d(d[0:0]),
.si(scan_in),
.so(scan_out),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[0:0]),
.q_l(q_l[0:0]),
.mq(mq[0:0]),
.mq_l(mq_l[0:0])
);


//place::generic_place($width,$stack,$left);

endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: n2_l2t_dp_32x128_cust.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module n2_l2t_dp_32x128_cust (
	36	din,
	37	rd_wl,
	38	wr_wl,
	39	read_en,
	40	wr_en,
	41	tcu_array_wr_inhibit,
	42	l2clk,
	43	scan_in,
	44	tcu_se_scancollar_in,
	45	tcu_scan_en,
	46	tcu_aclk,
	47	tcu_bclk,
	48	tcu_pce_ov,
	49	pce,
	50	dout,
	51	scan_out) ;
	52	wire siclk;
	53	wire soclk;
	54	wire stop;
	55	wire pce_ov;
	56	wire l1clk;
	57	wire l1clk_mem;
	58	wire ff_wdata_0_scanin;
	59	wire ff_wdata_0_scanout;
	60	wire [127:0] wrdata_d1;
	61	wire ff_wdata_1_scanin;
	62	wire ff_wdata_1_scanout;
	63	wire ff_wr_en_scanin;
	64	wire ff_wr_en_scanout;
65	wire wr_en_d1;
66	wire ff_wr_wl_scanin;
67	wire ff_wr_wl_scanout;
68	wire [31:0] wr_wl_d1;
69	wire ff_ren_scanin;
70	wire ff_ren_scanout;
71	wire ff_ren0_unused;
72	wire ff_ren1_unused;
73	wire ff_ren2_unused;
74	wire ren_d1;
75	wire ff_rd_wl_scanin;
76	wire ff_rd_wl_scanout;
77	wire [31:0] rd_wl_d1;
78
79
80	input [127:0] din; // data input
81	input [31:0] rd_wl; // read addr
82	input [31:0] wr_wl; // write addr
83	input read_en;
84	input wr_en; // used in conjunction with
85	// word_wen and byte_wen
86	input tcu_array_wr_inhibit ; // gates off writes during SCAN.
87	input l2clk;
88	input scan_in;
89
90	input tcu_se_scancollar_in; // hold scan in data.
91	input tcu_scan_en; // hold scan in data.
92	input tcu_aclk;
93	input tcu_bclk;
94
95	input tcu_pce_ov;
96	input pce;
97
98
99
100	output [127:0] dout;
101	output scan_out;
102
103	// JDL 05/17/07
104	// synopsys translate_off
105
106	wire [127:0] dout_array;
107
108	assign dout[127:0] = dout_array[127:0];
109
110	// scan chain connections ////
111	assign siclk = tcu_aclk;
112	assign soclk = tcu_bclk;
113	assign stop = 1'b0;
114	assign pce_ov = tcu_pce_ov;
115
116	//// Input Flops /////
117	n2_l2t_dp_32x128_cust_l1clkhdr_ctl_macro clkgen_clk_en
118	(
119	.l2clk (l2clk ),
120	.l1en (pce ),
121	.pce_ov (pce_ov ),
122	.stop (stop ),
123	.se (tcu_se_scancollar_in),
124	.l1clk (l1clk )
125	);
126
127	n2_l2t_dp_32x128_cust_l1clkhdr_ctl_macro clkgen_clk_en0
128	(
129	.l2clk (l2clk ),
130	.l1en (pce ),
131	.pce_ov (pce_ov ),
132	.stop (stop ),
133	.se (tcu_scan_en),
134	.l1clk (l1clk_mem )
135	);
136
137
138
139
140	n2_l2t_dp_32x128_cust_msff_ctl_macro__scanreverse_1__width_64 ff_wdata_0
141	(
142	.scan_in(ff_wdata_0_scanin),
143	.scan_out(ff_wdata_0_scanout),
144	.l1clk(l1clk),
145	.din(din[63:0]),
146	.dout(wrdata_d1[63:0]),
147	.siclk(siclk),
148	.soclk(soclk)
149	);
150
151	n2_l2t_dp_32x128_cust_msff_ctl_macro__scanreverse_1__width_64 ff_wdata_1
152	(
153	.scan_in(ff_wdata_1_scanin),
154	.scan_out(ff_wdata_1_scanout),
155	.l1clk(l1clk),
156	.din(din[127:64]),
157	.dout(wrdata_d1[127:64]),
158	.siclk(siclk),
159	.soclk(soclk)
160	);
161
162
163	n2_l2t_dp_32x128_cust_msff_ctl_macro__width_1 ff_wr_en
164	(
165	.scan_in(ff_wr_en_scanin),
166	.scan_out(ff_wr_en_scanout),
167	.l1clk(l1clk),
168	.din(wr_en),
169	.dout(wr_en_d1),
170	.siclk(siclk),
171	.soclk(soclk)
172	);
173
174
175	n2_l2t_dp_32x128_cust_msff_ctl_macro__width_32 ff_wr_wl
176	(
177	.scan_in(ff_wr_wl_scanin),
178	.scan_out(ff_wr_wl_scanout),
179	.l1clk(l1clk),
180	.din(wr_wl[31:0]),
181	.dout(wr_wl_d1[31:0]),
182	.siclk(siclk),
183	.soclk(soclk)
184	);
185
186
187	n2_l2t_dp_32x128_cust_sram_msff_mo_macro__width_1 ff_ren
188	(
189	.scan_in(ff_ren_scanin),
190	.scan_out(ff_ren_scanout),
191	.l1clk(l1clk),
192	.and_clk(l1clk_mem),
193	.q(ff_ren0_unused),
194	.q_l(ff_ren1_unused),
195	.mq_l(ff_ren2_unused),
196	.d(read_en),
197	.mq(ren_d1),
198	.siclk(siclk),
199	.soclk(soclk)
200	);
201
202
203	n2_l2t_dp_32x128_cust_msff_ctl_macro__width_32 ff_rd_wl
204	(
205	.scan_in(ff_rd_wl_scanin),
206	.scan_out(ff_rd_wl_scanout),
207	.l1clk(l1clk),
208	.din(rd_wl[31:0]),
209	.dout(rd_wl_d1[31:0]),
210	.siclk(siclk),
211	.soclk(soclk)
212	);
213
214
215	//msff_ctl_macro ff_tcu_array_wr_inhibit (width=1)
216	// ( // not a real flop ( only used as a trigger ). Works only for accesses made in PH1
217	// .scan_in(ff_tcu_se_scanin),
218	// .scan_out(ff_tcu_se_scanout),
219	// .l1clk(l1clk),
220	// .din(tcu_array_wr_inhibit),
221	// .dout(tcu_se_d1)
222	// );
223	//
224
225	/// Memory array ////
226
227	n2_l2t_dp_32x128_cust_array array (
228	.wr_en (wr_en_d1),
229	.rd_en (ren_d1),
230	.l1clk (l1clk_mem),
231	.wr_addr(wr_wl_d1[31:0]),
232	.rd_addr(rd_wl_d1[31:0]),
233	.din(wrdata_d1[127:0]),
234	.dout(dout_array[127:0]),
235	.write_disable(tcu_array_wr_inhibit)
236	);
237
238	// fixscan start:
239	assign ff_wr_en_scanin = scan_in ;
240	assign ff_ren_scanin = ff_wr_en_scanout ;
241	assign ff_rd_wl_scanin = ff_ren_scanout ;
242	assign ff_wr_wl_scanin = ff_rd_wl_scanout ;
243	assign ff_wdata_0_scanin = ff_wr_wl_scanout ;
244	assign ff_wdata_1_scanin = ff_wdata_0_scanout ;
245	assign scan_out = ff_wdata_1_scanout ;
246	//assign scan_out = ff_tcu_se_scanout ;
247	// fixscan end:
248
249	// synopsys translate_on
250
251	endmodule
252	//////////////////////////////////////////////////////////////////////
253	//////////////////////////////////////////////////////////////////////
254	//////////////////////////////////////////////////////////////////////
255	// ARRAY MODELLING //
256	//////////////////////////////////////////////////////////////////////
257	//////////////////////////////////////////////////////////////////////
258	//////////////////////////////////////////////////////////////////////
259	//////////////////////////////////////////////////////////////////////
260
261
262	module n2_l2t_dp_32x128_cust_array (
263	wr_en,
264	rd_en,
265	l1clk,
266	wr_addr,
267	rd_addr,
268	write_disable,
269	din,
270	dout) ;
271
272	input wr_en;
273	input rd_en;
274	input l1clk;
275	input [31:0] wr_addr;
276	input [31:0] rd_addr;
277	input write_disable;
278	input [127:0] din;
279
280	output [127:0] dout;
281
282	// memory array
283	reg [127:0] inq_ary [31:0];
284	// internal variable
285	reg [127:0] temp;
286	reg [127:0] data_in;
287	reg [4:0] rdptr_d1;
288	reg [4:0] wrptr_d1;
289	reg [127:0] dout;
290
291	reg [127:0] rd_data;
292
293	`ifndef NOINITMEM
294	// Emulate reset
295	integer i;
296	initial begin
297	for (i=0; i<32; i=i+1) begin
298	inq_ary[i] = {128{1'b0}};
299	end
300	end
301	`endif
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319	//////////////////////////////////////////////////////////////////////
320	// Read Operation
321	//////////////////////////////////////////////////////////////////////
322
323
324	always @(rd_addr or rd_en or write_disable or wr_en or wr_addr or l1clk)
325	begin
326
327
328	// ---- \/ added the write_disable qual on 11/11 \/------
329	if (l1clk ) begin
330
331	if (rd_en & ~write_disable) begin
332
333	case(rd_addr & {32{~write_disable}})
334	32'b0000_0000_0000_0000_0000_0000_0000_0000: ; // do nothing
335	32'b0000_0000_0000_0000_0000_0000_0000_0001: rdptr_d1 = 5'b00000;
336	32'b0000_0000_0000_0000_0000_0000_0000_0010: rdptr_d1 = 5'b00001;
337	32'b0000_0000_0000_0000_0000_0000_0000_0100: rdptr_d1 = 5'b00010;
338	32'b0000_0000_0000_0000_0000_0000_0000_1000: rdptr_d1 = 5'b00011;
339	32'b0000_0000_0000_0000_0000_0000_0001_0000: rdptr_d1 = 5'b00100;
340	32'b0000_0000_0000_0000_0000_0000_0010_0000: rdptr_d1 = 5'b00101;
341	32'b0000_0000_0000_0000_0000_0000_0100_0000: rdptr_d1 = 5'b00110;
342	32'b0000_0000_0000_0000_0000_0000_1000_0000: rdptr_d1 = 5'b00111;
343	32'b0000_0000_0000_0000_0000_0001_0000_0000: rdptr_d1 = 5'b01000;
344	32'b0000_0000_0000_0000_0000_0010_0000_0000: rdptr_d1 = 5'b01001;
345	32'b0000_0000_0000_0000_0000_0100_0000_0000: rdptr_d1 = 5'b01010;
346	32'b0000_0000_0000_0000_0000_1000_0000_0000: rdptr_d1 = 5'b01011;
347	32'b0000_0000_0000_0000_0001_0000_0000_0000: rdptr_d1 = 5'b01100;
348	32'b0000_0000_0000_0000_0010_0000_0000_0000: rdptr_d1 = 5'b01101;
349	32'b0000_0000_0000_0000_0100_0000_0000_0000: rdptr_d1 = 5'b01110;
350	32'b0000_0000_0000_0000_1000_0000_0000_0000: rdptr_d1 = 5'b01111;
351	32'b0000_0000_0000_0001_0000_0000_0000_0000: rdptr_d1 = 5'b10000;
352	32'b0000_0000_0000_0010_0000_0000_0000_0000: rdptr_d1 = 5'b10001;
353	32'b0000_0000_0000_0100_0000_0000_0000_0000: rdptr_d1 = 5'b10010;
354	32'b0000_0000_0000_1000_0000_0000_0000_0000: rdptr_d1 = 5'b10011;
355	32'b0000_0000_0001_0000_0000_0000_0000_0000: rdptr_d1 = 5'b10100;
356	32'b0000_0000_0010_0000_0000_0000_0000_0000: rdptr_d1 = 5'b10101;
357	32'b0000_0000_0100_0000_0000_0000_0000_0000: rdptr_d1 = 5'b10110;
358	32'b0000_0000_1000_0000_0000_0000_0000_0000: rdptr_d1 = 5'b10111;
359	32'b0000_0001_0000_0000_0000_0000_0000_0000: rdptr_d1 = 5'b11000;
360	32'b0000_0010_0000_0000_0000_0000_0000_0000: rdptr_d1 = 5'b11001;
361	32'b0000_0100_0000_0000_0000_0000_0000_0000: rdptr_d1 = 5'b11010;
362	32'b0000_1000_0000_0000_0000_0000_0000_0000: rdptr_d1 = 5'b11011;
363	32'b0001_0000_0000_0000_0000_0000_0000_0000: rdptr_d1 = 5'b11100;
364	32'b0010_0000_0000_0000_0000_0000_0000_0000: rdptr_d1 = 5'b11101;
365	32'b0100_0000_0000_0000_0000_0000_0000_0000: rdptr_d1 = 5'b11110;
366	32'b1000_0000_0000_0000_0000_0000_0000_0000: rdptr_d1 = 5'b11111;
367	default: rdptr_d1 = 5'bx ;
368	endcase
369	rd_data = inq_ary[rdptr_d1];
370	dout = rd_data;
371
372	end
373	//else
374	//dout[127:0] = 128'h0 ;
375	end //l1clk
376	end // always @ (...
377
378
379	//////////////////////////////////////////////////////////////////////
380	// Write Operation
381	//////////////////////////////////////////////////////////////////////
382	always @ (write_disable or wr_en or wr_addr or din or l1clk)
383	begin
384
385
386	//`ifdef INNO_MUXEX
387	if((wr_en==1'bx) & ~l1clk)
388	begin
389	// do nothing
390	end
391	//`endif
392	else if(wr_en & ~write_disable & ~l1clk)
393	begin
394	case(wr_addr)
395	32'b0000_0000_0000_0000_0000_0000_0000_0000: ; // do nothing
396	32'b0000_0000_0000_0000_0000_0000_0000_0001: wrptr_d1 = 5'b00000;
397	32'b0000_0000_0000_0000_0000_0000_0000_0010: wrptr_d1 = 5'b00001;
398	32'b0000_0000_0000_0000_0000_0000_0000_0100: wrptr_d1 = 5'b00010;
399	32'b0000_0000_0000_0000_0000_0000_0000_1000: wrptr_d1 = 5'b00011;
400	32'b0000_0000_0000_0000_0000_0000_0001_0000: wrptr_d1 = 5'b00100;
401	32'b0000_0000_0000_0000_0000_0000_0010_0000: wrptr_d1 = 5'b00101;
402	32'b0000_0000_0000_0000_0000_0000_0100_0000: wrptr_d1 = 5'b00110;
403	32'b0000_0000_0000_0000_0000_0000_1000_0000: wrptr_d1 = 5'b00111;
404	32'b0000_0000_0000_0000_0000_0001_0000_0000: wrptr_d1 = 5'b01000;
405	32'b0000_0000_0000_0000_0000_0010_0000_0000: wrptr_d1 = 5'b01001;
406	32'b0000_0000_0000_0000_0000_0100_0000_0000: wrptr_d1 = 5'b01010;
407	32'b0000_0000_0000_0000_0000_1000_0000_0000: wrptr_d1 = 5'b01011;
408	32'b0000_0000_0000_0000_0001_0000_0000_0000: wrptr_d1 = 5'b01100;
409	32'b0000_0000_0000_0000_0010_0000_0000_0000: wrptr_d1 = 5'b01101;
410	32'b0000_0000_0000_0000_0100_0000_0000_0000: wrptr_d1 = 5'b01110;
411	32'b0000_0000_0000_0000_1000_0000_0000_0000: wrptr_d1 = 5'b01111;
412	32'b0000_0000_0000_0001_0000_0000_0000_0000: wrptr_d1 = 5'b10000;
413	32'b0000_0000_0000_0010_0000_0000_0000_0000: wrptr_d1 = 5'b10001;
414	32'b0000_0000_0000_0100_0000_0000_0000_0000: wrptr_d1 = 5'b10010;
415	32'b0000_0000_0000_1000_0000_0000_0000_0000: wrptr_d1 = 5'b10011;
416	32'b0000_0000_0001_0000_0000_0000_0000_0000: wrptr_d1 = 5'b10100;
417	32'b0000_0000_0010_0000_0000_0000_0000_0000: wrptr_d1 = 5'b10101;
418	32'b0000_0000_0100_0000_0000_0000_0000_0000: wrptr_d1 = 5'b10110;
419	32'b0000_0000_1000_0000_0000_0000_0000_0000: wrptr_d1 = 5'b10111;
420	32'b0000_0001_0000_0000_0000_0000_0000_0000: wrptr_d1 = 5'b11000;
421	32'b0000_0010_0000_0000_0000_0000_0000_0000: wrptr_d1 = 5'b11001;
422	32'b0000_0100_0000_0000_0000_0000_0000_0000: wrptr_d1 = 5'b11010;
423	32'b0000_1000_0000_0000_0000_0000_0000_0000: wrptr_d1 = 5'b11011;
424	32'b0001_0000_0000_0000_0000_0000_0000_0000: wrptr_d1 = 5'b11100;
425	32'b0010_0000_0000_0000_0000_0000_0000_0000: wrptr_d1 = 5'b11101;
426	32'b0100_0000_0000_0000_0000_0000_0000_0000: wrptr_d1 = 5'b11110;
427	32'b1000_0000_0000_0000_0000_0000_0000_0000: wrptr_d1 = 5'b11111;
428	default: wrptr_d1= 5'bx ;
429	endcase
430	//`ifdef INNO_MUXEX
431	if(wr_addr!=32'b0)
432	inq_ary[wrptr_d1] = din ;
433	//`else
434	else
435	begin
436	if(wr_addr!=32'b0)
437	inq_ary[wrptr_d1] = din ;
438	end
439	//`endif
440	end
441	else
442	begin
443	// do nothing
444	end
445
446	end // always @ (...
447
448	endmodule // rf_32x128d
449
450
451
452
453
454
455	// any PARAMS parms go into naming of macro
456
457	module n2_l2t_dp_32x128_cust_l1clkhdr_ctl_macro (
458	l2clk,
459	l1en,
460	pce_ov,
461	stop,
462	se,
463	l1clk);
464
465
466	input l2clk;
467	input l1en;
468	input pce_ov;
469	input stop;
470	input se;
471	output l1clk;
472
473
474
475
476
477	cl_sc1_l1hdr_8x c_0 (
478
479
480	.l2clk(l2clk),
481	.pce(l1en),
482	.l1clk(l1clk),
483	.se(se),
484	.pce_ov(pce_ov),
485	.stop(stop)
486	);
487
488
489
490	endmodule
491
492
493
494
495
496
497
498
499
500
501
502
503
504	// any PARAMS parms go into naming of macro
505
506	module n2_l2t_dp_32x128_cust_msff_ctl_macro__scanreverse_1__width_64 (
507	din,
508	l1clk,
509	scan_in,
510	siclk,
511	soclk,
512	dout,
513	scan_out);
514	wire [63:0] fdin;
515	wire [0:62] so;
516
517	input [63:0] din;
518	input l1clk;
519	input scan_in;
520
521
522	input siclk;
523	input soclk;
524
525	output [63:0] dout;
526	output scan_out;
527	assign fdin[63:0] = din[63:0];
528
529
530
531
532
533
534	dff #(64) d0_0 (
535	.l1clk(l1clk),
536	.siclk(siclk),
537	.soclk(soclk),
538	.d(fdin[63:0]),
539	.si({so[0:62],scan_in}),
540	.so({scan_out,so[0:62]}),
541	.q(dout[63:0])
542	);
543
544
545
546
547
548
549
550
551
552
553
554
555	endmodule
556
557
558
559
560
561
562
563
564
565
566
567
568
569	// any PARAMS parms go into naming of macro
570
571	module n2_l2t_dp_32x128_cust_msff_ctl_macro__width_1 (
572	din,
573	l1clk,
574	scan_in,
575	siclk,
576	soclk,
577	dout,
578	scan_out);
579	wire [0:0] fdin;
580
581	input [0:0] din;
582	input l1clk;
583	input scan_in;
584
585
586	input siclk;
587	input soclk;
588
589	output [0:0] dout;
590	output scan_out;
591	assign fdin[0:0] = din[0:0];
592
593
594
595
596
597
598	dff #(1) d0_0 (
599	.l1clk(l1clk),
600	.siclk(siclk),
601	.soclk(soclk),
602	.d(fdin[0:0]),
603	.si(scan_in),
604	.so(scan_out),
605	.q(dout[0:0])
606	);
607
608
609
610
611
612
613
614
615
616
617
618
619	endmodule
620
621
622
623
624
625
626
627
628
629
630
631
632
633	// any PARAMS parms go into naming of macro
634
635	module n2_l2t_dp_32x128_cust_msff_ctl_macro__width_32 (
636	din,
637	l1clk,
638	scan_in,
639	siclk,
640	soclk,
641	dout,
642	scan_out);
643	wire [31:0] fdin;
644	wire [30:0] so;
645
646	input [31:0] din;
647	input l1clk;
648	input scan_in;
649
650
651	input siclk;
652	input soclk;
653
654	output [31:0] dout;
655	output scan_out;
656	assign fdin[31:0] = din[31:0];
657
658
659
660
661
662
663	dff #(32) d0_0 (
664	.l1clk(l1clk),
665	.siclk(siclk),
666	.soclk(soclk),
667	.d(fdin[31:0]),
668	.si({scan_in,so[30:0]}),
669	.so({so[30:0],scan_out}),
670	.q(dout[31:0])
671	);
672
673
674
675
676
677
678
679
680
681
682
683
684	endmodule
685
686
687
688
689
690
691
692
693
694	//
695	// macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
696	//
697	//
698
699
700
701
702
703	module n2_l2t_dp_32x128_cust_sram_msff_mo_macro__width_1 (
704	d,
705	scan_in,
706	l1clk,
707	and_clk,
708	siclk,
709	soclk,
710	mq,
711	mq_l,
712	scan_out,
713	q,
714	q_l);
715	input [0:0] d;
716	input scan_in;
717	input l1clk;
718	input and_clk;
719	input siclk;
720	input soclk;
721	output [0:0] mq;
722	output [0:0] mq_l;
723	output scan_out;
724	output [0:0] q;
725	output [0:0] q_l;
726
727
728
729
730
731
732	new_dlata #(1) d0_0 (
733	.d(d[0:0]),
734	.si(scan_in),
735	.so(scan_out),
736	.l1clk(l1clk),
737	.and_clk(and_clk),
738	.siclk(siclk),
739	.soclk(soclk),
740	.q(q[0:0]),
741	.q_l(q_l[0:0]),
742	.mq(mq[0:0]),
743	.mq_l(mq_l[0:0])
744	);
745
746
747
748
749
750
751
752
753
754
755	//place::generic_place($width,$stack,$left);
756
757	endmodule
758
759
760
761