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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / libs / n2sram / dp / n2_niu_dp_1024x152s_cust_l / n2_niu_dp_1024x152s_cust / rtl / n2_niu_dp_1024x152s_cust.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: n2_niu_dp_1024x152s_cust.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module n2_niu_dp_1024x152s_cust (
36 reset,
37 tcu_aclk,
38 tcu_bclk,
39 tcu_scan_en,
40 tcu_se_scancollar_in,
41 tcu_se_scancollar_out,
42 tcu_pce_ov,
43 pce,
44 tcu_array_wr_inhibit,
45 scan_in,
46 scan_out,
47 hdr_sram_rvalue,
48 hdr_sram_rid,
49 hdr_sram_wr_en,
50 hdr_sram_red_clr,
51 sram_hdr_read_data,
52 wr_adr,
53 wr_en,
54 rd_adr,
55 rd_en,
56 din,
57 dout,
58 l2clk_2x,
59 l2clk);
60wire array_scanout;
61
62
63input reset;
64input tcu_aclk;
65input tcu_bclk;
66input tcu_scan_en;
67input tcu_se_scancollar_in;
68input tcu_se_scancollar_out;
69input tcu_pce_ov;
70input pce;
71input tcu_array_wr_inhibit;
72input scan_in;
73output scan_out;
74
75input [6:0] hdr_sram_rvalue;
76input [2:0] hdr_sram_rid;
77input hdr_sram_wr_en;
78input hdr_sram_red_clr;
79output [6:0] sram_hdr_read_data;
80
81input [9:0] wr_adr;
82input wr_en;
83input [9:0] rd_adr;
84input rd_en;
85input [151:0] din;
86output [151:0] dout;
87input l2clk_2x;
88input l2clk;
89
90
91wire [151:0] din;
92wire [151:0] dout;
93wire [6:0] hdr_sram_rvalue;
94wire [2:0] hdr_sram_rid;
95wire [9:0] wr_adr;
96wire [9:0] rd_adr;
97wire [6:0] sram_hdr_read_data;
98
99wire [7:0] repair_en_bk;
100wire [5:0] red_value_b7;
101wire [5:0] red_value_b6;
102wire [5:0] red_value_b5;
103wire [5:0] red_value_b4;
104wire [5:0] red_value_b3;
105wire [5:0] red_value_b2;
106wire [5:0] red_value_b1;
107wire [5:0] red_value_b0;
108
109wire scan_out;
110wire reset;
111
112
113
114
115
116 n2_niu_dp_1024x152s_bank niu_dp_1024x152s_bank_0 (
117 .reset (reset),
118 .tcu_aclk (tcu_aclk),
119 .tcu_bclk (tcu_bclk),
120 .pce (pce),
121 .tcu_pce_ov (tcu_pce_ov),
122 .tcu_scan_en (tcu_scan_en),
123 .tcu_se_scancollar_in (tcu_se_scancollar_in),
124 .tcu_array_wr_inhibit (tcu_array_wr_inhibit),
125 .l2clk (l2clk),
126 .l2clk_2x (l2clk_2x),
127 .wr_adr (wr_adr),
128 .wr_en (wr_en),
129 .rd_adr (rd_adr),
130 .rd_en (rd_en),
131 .din (din),
132 .scan_in (scan_in),
133 .scan_out (array_scanout),
134 .red_v_blm (red_value_b7),
135 .red_v_bll (red_value_b6),
136 .red_v_tll (red_value_b5),
137 .red_v_tlm (red_value_b4),
138 .red_v_trm (red_value_b3),
139 .red_v_trr (red_value_b2),
140 .red_v_brr (red_value_b1),
141 .red_v_brm (red_value_b0),
142 .red_en_blm (repair_en_bk[7]),
143 .red_en_bll (repair_en_bk[6]),
144 .red_en_tlm (repair_en_bk[5]),
145 .red_en_tll (repair_en_bk[4]),
146 .red_en_trm (repair_en_bk[3]),
147 .red_en_trr (repair_en_bk[2]),
148 .red_en_brr (repair_en_bk[1]),
149 .red_en_brm (repair_en_bk[0]),
150 .dout (dout)
151 );
152
153 n2_niu_dp_1024x152s_repair niu_dp_1024x152s_repair_0 (
154 .tcu_aclk (tcu_aclk),
155 .tcu_bclk (tcu_bclk),
156 .pce (pce),
157 .tcu_pce_ov (tcu_pce_ov),
158 .tcu_scan_en (tcu_scan_en),
159 .tcu_se_scancollar_in (tcu_se_scancollar_in),
160 .tcu_se_scancollar_out (tcu_se_scancollar_out),
161 .tcu_array_wr_inhibit (tcu_array_wr_inhibit),
162 .scan_in (array_scanout),
163 .hdr_sram_rvalue (hdr_sram_rvalue),
164 .hdr_sram_rid (hdr_sram_rid),
165 .hdr_sram_wr_en (hdr_sram_wr_en),
166 .hdr_sram_red_clr (hdr_sram_red_clr),
167 .l2clk (l2clk),
168 .sram_hdr_read_data (sram_hdr_read_data),
169 .red_v_blm (red_value_b7),
170 .red_v_bll (red_value_b6),
171 .red_v_tll (red_value_b5),
172 .red_v_tlm (red_value_b4),
173 .red_v_trm (red_value_b3),
174 .red_v_trr (red_value_b2),
175 .red_v_brr (red_value_b1),
176 .red_v_brm (red_value_b0),
177 .red_en_blm (repair_en_bk[7]),
178 .red_en_bll (repair_en_bk[6]),
179 .red_en_tlm (repair_en_bk[5]),
180 .red_en_tll (repair_en_bk[4]),
181 .red_en_trm (repair_en_bk[3]),
182 .red_en_trr (repair_en_bk[2]),
183 .red_en_brr (repair_en_bk[1]),
184 .red_en_brm (repair_en_bk[0]),
185 .scan_out (scan_out)
186 );
187
188
189
190endmodule
191
192
193
194
195module n2_niu_dp_1024x152s_bank (
196 reset,
197 tcu_aclk,
198 tcu_bclk,
199 tcu_pce_ov,
200 pce,
201 tcu_scan_en,
202 tcu_se_scancollar_in,
203 tcu_array_wr_inhibit,
204 l2clk,
205 l2clk_2x,
206 wr_adr,
207 wr_en,
208 rd_adr,
209 rd_en,
210 din,
211 scan_in,
212 scan_out,
213 red_v_blm,
214 red_v_bll,
215 red_v_tll,
216 red_v_tlm,
217 red_v_trm,
218 red_v_trr,
219 red_v_brr,
220 red_v_brm,
221 red_en_blm,
222 red_en_bll,
223 red_en_tlm,
224 red_en_tll,
225 red_en_trm,
226 red_en_trr,
227 red_en_brr,
228 red_en_brm,
229 dout);
230wire l1clk_in_en;
231wire l1clk_in;
232wire l1clk_gate_en;
233wire l1clk_gate;
234wire [9:0] dff_wr_adr_m_scanin;
235wire [9:0] dff_wr_adr_m_scanout;
236wire [9:0] dff_rd_adr_m_scanin;
237wire [9:0] dff_rd_adr_m_scanout;
238wire dff_rd_en_m_scanin;
239wire dff_rd_en_m_scanout;
240wire dff_wr_en_m_scanin;
241wire dff_wr_en_m_scanout;
242wire test_mode;
243wire dff_test_mode_scanin;
244wire dff_test_mode_scanout;
245wire test_clk;
246wire dff_test_clk_scanin;
247wire dff_test_clk_scanout;
248wire [1:0] rd_addr_column_b1;
249wire [1:0] rd_addr_column_b;
250wire rd_addr_msb;
251wire [151:0] wdata_2x_b;
252
253
254input reset;
255input tcu_aclk;
256input tcu_bclk;
257input tcu_pce_ov;
258input pce;
259input tcu_scan_en;
260input tcu_se_scancollar_in;
261input tcu_array_wr_inhibit;
262input l2clk;
263input l2clk_2x;
264input [9:0] wr_adr;
265input wr_en;
266input [9:0] rd_adr;
267input rd_en;
268input [151:0] din;
269input scan_in;
270output scan_out;
271
272input [5:0] red_v_blm;
273input [5:0] red_v_bll;
274input [5:0] red_v_tll;
275input [5:0] red_v_tlm;
276input [5:0] red_v_trm;
277input [5:0] red_v_trr;
278input [5:0] red_v_brr;
279input [5:0] red_v_brm;
280input red_en_blm;
281input red_en_bll;
282input red_en_tlm;
283input red_en_tll;
284input red_en_trm;
285input red_en_trr;
286input red_en_brr;
287input red_en_brm;
288output [151:0] dout;
289
290
291wire [151:0] dout;
292
293wire scan_out;
294wire reset_l;
295wire siclk, soclk;
296assign siclk = tcu_aclk;
297assign soclk = tcu_bclk;
298
299assign reset_l = ~reset;
300
301//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
302//================================================
303// l2 clock Domain: Clock headers
304//================================================
305//cl_sc1_l1hdr_8x l1ch_in (
306// .l1clk (l1clk_in),
307// .l2clk (l2clk),
308// .se (tcu_se_scancollar_in),
309// .pce (pce),
310// .pce_ov (tcu_pce_ov),
311// .stop (1'b0)
312// );
313
314//cl_sc1_l1hdr_8x l1ch_gate (
315// .l1clk (l1clk_gate),
316// .l2clk (l2clk),
317// .se (tcu_scan_en),
318// .pce (pce),
319// .pce_ov (tcu_pce_ov),
320// .stop (1'b0)
321// );
322
323///////////////////////////////////
324// decomposed l1hdr for l1clk_in
325///////////////////////////////////
326
327cl_mc1_l1enable_12x l1ch_in_l1en (
328 .l2clk (l2clk),
329 .pce (pce),
330 .pce_ov (tcu_pce_ov),
331 .l1en (l1clk_in_en)
332 );
333
334cl_mc1_l1driver_12x l1ch_in_l1drvr (
335 .se (tcu_se_scancollar_in),
336 .l1en (l1clk_in_en),
337 .l1clk (l1clk_in),
338 .l2clk(l2clk)
339 );
340
341///////////////////////////////////
342// decomposed l1hdr for l1clk_gate
343///////////////////////////////////
344
345cl_mc1_l1enable_12x l1ch_gate_l1en (
346 .l2clk (l2clk),
347 .pce (pce),
348 .pce_ov (tcu_pce_ov),
349 .l1en (l1clk_gate_en)
350 );
351
352cl_mc1_l1driver_12x l1ch_gate_l1drvr (
353 .se (tcu_scan_en),
354 .l1en (l1clk_gate_en),
355 .l1clk (l1clk_gate),
356 .l2clk(l2clk)
357 );
358
359
360
361//================================================
362// l2 clock Domain: Input flops
363//================================================
364
365// ------------ controls_ph.a register --------------
366wire [9:0] rd_adr_m;
367wire [9:0] wr_adr_m;
368wire rd_en_m;
369wire wr_en_m;
370wire [151:0] din_m;
371
372// msff_ctl_macro dff_ctrls_m (width=(10*2+2), clr_=1) (
373// .scan_in (scan_in),
374// .scan_out (dff_ctrls_m_scan_out),
375// .clr_ (reset_l),
376// .l1clk (l1clk_in),
377// .din ({rd_en, wr_en, rd_adr[9:0], wr_adr[9:0]}),
378// .dout ({rd_en_m,wr_en_m,rd_adr_m[9:0],wr_adr_m[9:0]}));
379// ------------ write_data_ph.a register ------------
380//
381// msff_ctl_macro dff_wdata_m (width=152, clr_=1) (
382// .scan_in (dff_ctrls_m_scan_out),
383// .scan_out (dff_wdata_m_scanout),
384// .clr_ (reset_l),
385// .l1clk (l1clk_in),
386// .din (din[151:0]),
387// .dout (din_m[151:0]));
388//
389
390 cl_sc1_msff_syrst_4x wr_adr_m00 (.d(wr_adr[0]), .si(dff_wr_adr_m_scanin[0]), .q(wr_adr_m[0]), .so(dff_wr_adr_m_scanout[0]),
391 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
392 cl_sc1_msff_syrst_4x wr_adr_m01 (.d(wr_adr[1]), .si(dff_wr_adr_m_scanin[1]), .q(wr_adr_m[1]), .so(dff_wr_adr_m_scanout[1]),
393 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
394 cl_sc1_msff_syrst_4x wr_adr_m02 (.d(wr_adr[2]), .si(dff_wr_adr_m_scanin[2]), .q(wr_adr_m[2]), .so(dff_wr_adr_m_scanout[2]),
395 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
396 cl_sc1_msff_syrst_4x wr_adr_m03 (.d(wr_adr[3]), .si(dff_wr_adr_m_scanin[3]), .q(wr_adr_m[3]), .so(dff_wr_adr_m_scanout[3]),
397 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
398 cl_sc1_msff_syrst_4x wr_adr_m04 (.d(wr_adr[4]), .si(dff_wr_adr_m_scanin[4]), .q(wr_adr_m[4]), .so(dff_wr_adr_m_scanout[4]),
399 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
400 cl_sc1_msff_syrst_4x wr_adr_m05 (.d(wr_adr[5]), .si(dff_wr_adr_m_scanin[5]), .q(wr_adr_m[5]), .so(dff_wr_adr_m_scanout[5]),
401 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
402 cl_sc1_msff_syrst_4x wr_adr_m06 (.d(wr_adr[6]), .si(dff_wr_adr_m_scanin[6]), .q(wr_adr_m[6]), .so(dff_wr_adr_m_scanout[6]),
403 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
404 cl_sc1_msff_syrst_4x wr_adr_m07 (.d(wr_adr[7]), .si(dff_wr_adr_m_scanin[7]), .q(wr_adr_m[7]), .so(dff_wr_adr_m_scanout[7]),
405 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
406 cl_sc1_msff_syrst_4x wr_adr_m08 (.d(wr_adr[8]), .si(dff_wr_adr_m_scanin[8]), .q(wr_adr_m[8]), .so(dff_wr_adr_m_scanout[8]),
407 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
408 cl_sc1_msff_syrst_4x wr_adr_m09 (.d(wr_adr[9]), .si(dff_wr_adr_m_scanin[9]), .q(wr_adr_m[9]), .so(dff_wr_adr_m_scanout[9]),
409 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
410
411 cl_sc1_msff_syrst_4x rd_adr_m00 (.d(rd_adr[0]), .si(dff_rd_adr_m_scanin[0]), .q(rd_adr_m[0]), .so(dff_rd_adr_m_scanout[0]),
412 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
413 cl_sc1_msff_syrst_4x rd_adr_m01 (.d(rd_adr[1]), .si(dff_rd_adr_m_scanin[1]), .q(rd_adr_m[1]), .so(dff_rd_adr_m_scanout[1]),
414 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
415 cl_sc1_msff_syrst_4x rd_adr_m02 (.d(rd_adr[2]), .si(dff_rd_adr_m_scanin[2]), .q(rd_adr_m[2]), .so(dff_rd_adr_m_scanout[2]),
416 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
417 cl_sc1_msff_syrst_4x rd_adr_m03 (.d(rd_adr[3]), .si(dff_rd_adr_m_scanin[3]), .q(rd_adr_m[3]), .so(dff_rd_adr_m_scanout[3]),
418 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
419 cl_sc1_msff_syrst_4x rd_adr_m04 (.d(rd_adr[4]), .si(dff_rd_adr_m_scanin[4]), .q(rd_adr_m[4]), .so(dff_rd_adr_m_scanout[4]),
420 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
421 cl_sc1_msff_syrst_4x rd_adr_m05 (.d(rd_adr[5]), .si(dff_rd_adr_m_scanin[5]), .q(rd_adr_m[5]), .so(dff_rd_adr_m_scanout[5]),
422 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
423 cl_sc1_msff_syrst_4x rd_adr_m06 (.d(rd_adr[6]), .si(dff_rd_adr_m_scanin[6]), .q(rd_adr_m[6]), .so(dff_rd_adr_m_scanout[6]),
424 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
425 cl_sc1_msff_syrst_4x rd_adr_m07 (.d(rd_adr[7]), .si(dff_rd_adr_m_scanin[7]), .q(rd_adr_m[7]), .so(dff_rd_adr_m_scanout[7]),
426 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
427 cl_sc1_msff_syrst_4x rd_adr_m08 (.d(rd_adr[8]), .si(dff_rd_adr_m_scanin[8]), .q(rd_adr_m[8]), .so(dff_rd_adr_m_scanout[8]),
428 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
429 cl_sc1_msff_syrst_4x rd_adr_m09 (.d(rd_adr[9]), .si(dff_rd_adr_m_scanin[9]), .q(rd_adr_m[9]), .so(dff_rd_adr_m_scanout[9]),
430 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
431
432 cl_sc1_msff_syrst_4x rd_en_m0 (.d(rd_en), .si(dff_rd_en_m_scanin), .q(rd_en_m), .so(dff_rd_en_m_scanout),
433 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
434 cl_sc1_msff_syrst_4x wr_en_m0 (.d(wr_en), .si(dff_wr_en_m_scanin), .q(wr_en_m), .so(dff_wr_en_m_scanout),
435 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
436
437// ------------ write_data_ph.a register ------------
438
439wire [151:0] dff_wdata_m_scanin, dff_wdata_m_scanout;
440
441 cl_sc1_msff_syrst_4x din_m000 (.d(din[0]), .si(dff_wdata_m_scanin[0]), .q(din_m[0]), .so(dff_wdata_m_scanout[0]),
442 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
443 cl_sc1_msff_syrst_4x din_m001 (.d(din[1]), .si(dff_wdata_m_scanin[1]), .q(din_m[1]), .so(dff_wdata_m_scanout[1]),
444 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
445 cl_sc1_msff_syrst_4x din_m002 (.d(din[2]), .si(dff_wdata_m_scanin[2]), .q(din_m[2]), .so(dff_wdata_m_scanout[2]),
446 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
447 cl_sc1_msff_syrst_4x din_m003 (.d(din[3]), .si(dff_wdata_m_scanin[3]), .q(din_m[3]), .so(dff_wdata_m_scanout[3]),
448 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
449 cl_sc1_msff_syrst_4x din_m004 (.d(din[4]), .si(dff_wdata_m_scanin[4]), .q(din_m[4]), .so(dff_wdata_m_scanout[4]),
450 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
451 cl_sc1_msff_syrst_4x din_m005 (.d(din[5]), .si(dff_wdata_m_scanin[5]), .q(din_m[5]), .so(dff_wdata_m_scanout[5]),
452 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
453 cl_sc1_msff_syrst_4x din_m006 (.d(din[6]), .si(dff_wdata_m_scanin[6]), .q(din_m[6]), .so(dff_wdata_m_scanout[6]),
454 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
455 cl_sc1_msff_syrst_4x din_m007 (.d(din[7]), .si(dff_wdata_m_scanin[7]), .q(din_m[7]), .so(dff_wdata_m_scanout[7]),
456 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
457 cl_sc1_msff_syrst_4x din_m008 (.d(din[8]), .si(dff_wdata_m_scanin[8]), .q(din_m[8]), .so(dff_wdata_m_scanout[8]),
458 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
459 cl_sc1_msff_syrst_4x din_m009 (.d(din[9]), .si(dff_wdata_m_scanin[9]), .q(din_m[9]), .so(dff_wdata_m_scanout[9]),
460 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
461
462 cl_sc1_msff_syrst_4x din_m010 (.d(din[10]), .si(dff_wdata_m_scanin[10]), .q(din_m[10]), .so(dff_wdata_m_scanout[10]),
463 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
464 cl_sc1_msff_syrst_4x din_m011 (.d(din[11]), .si(dff_wdata_m_scanin[11]), .q(din_m[11]), .so(dff_wdata_m_scanout[11]),
465 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
466 cl_sc1_msff_syrst_4x din_m012 (.d(din[12]), .si(dff_wdata_m_scanin[12]), .q(din_m[12]), .so(dff_wdata_m_scanout[12]),
467 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
468 cl_sc1_msff_syrst_4x din_m013 (.d(din[13]), .si(dff_wdata_m_scanin[13]), .q(din_m[13]), .so(dff_wdata_m_scanout[13]),
469 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
470 cl_sc1_msff_syrst_4x din_m014 (.d(din[14]), .si(dff_wdata_m_scanin[14]), .q(din_m[14]), .so(dff_wdata_m_scanout[14]),
471 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
472 cl_sc1_msff_syrst_4x din_m015 (.d(din[15]), .si(dff_wdata_m_scanin[15]), .q(din_m[15]), .so(dff_wdata_m_scanout[15]),
473 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
474 cl_sc1_msff_syrst_4x din_m016 (.d(din[16]), .si(dff_wdata_m_scanin[16]), .q(din_m[16]), .so(dff_wdata_m_scanout[16]),
475 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
476 cl_sc1_msff_syrst_4x din_m017 (.d(din[17]), .si(dff_wdata_m_scanin[17]), .q(din_m[17]), .so(dff_wdata_m_scanout[17]),
477 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
478 cl_sc1_msff_syrst_4x din_m018 (.d(din[18]), .si(dff_wdata_m_scanin[18]), .q(din_m[18]), .so(dff_wdata_m_scanout[18]),
479 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
480 cl_sc1_msff_syrst_4x din_m019 (.d(din[19]), .si(dff_wdata_m_scanin[19]), .q(din_m[19]), .so(dff_wdata_m_scanout[19]),
481 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
482
483 cl_sc1_msff_syrst_4x din_m020 (.d(din[20]), .si(dff_wdata_m_scanin[20]), .q(din_m[20]), .so(dff_wdata_m_scanout[20]),
484 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
485 cl_sc1_msff_syrst_4x din_m021 (.d(din[21]), .si(dff_wdata_m_scanin[21]), .q(din_m[21]), .so(dff_wdata_m_scanout[21]),
486 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
487 cl_sc1_msff_syrst_4x din_m022 (.d(din[22]), .si(dff_wdata_m_scanin[22]), .q(din_m[22]), .so(dff_wdata_m_scanout[22]),
488 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
489 cl_sc1_msff_syrst_4x din_m023 (.d(din[23]), .si(dff_wdata_m_scanin[23]), .q(din_m[23]), .so(dff_wdata_m_scanout[23]),
490 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
491 cl_sc1_msff_syrst_4x din_m024 (.d(din[24]), .si(dff_wdata_m_scanin[24]), .q(din_m[24]), .so(dff_wdata_m_scanout[24]),
492 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
493 cl_sc1_msff_syrst_4x din_m025 (.d(din[25]), .si(dff_wdata_m_scanin[25]), .q(din_m[25]), .so(dff_wdata_m_scanout[25]),
494 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
495 cl_sc1_msff_syrst_4x din_m026 (.d(din[26]), .si(dff_wdata_m_scanin[26]), .q(din_m[26]), .so(dff_wdata_m_scanout[26]),
496 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
497 cl_sc1_msff_syrst_4x din_m027 (.d(din[27]), .si(dff_wdata_m_scanin[27]), .q(din_m[27]), .so(dff_wdata_m_scanout[27]),
498 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
499 cl_sc1_msff_syrst_4x din_m028 (.d(din[28]), .si(dff_wdata_m_scanin[28]), .q(din_m[28]), .so(dff_wdata_m_scanout[28]),
500 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
501 cl_sc1_msff_syrst_4x din_m029 (.d(din[29]), .si(dff_wdata_m_scanin[29]), .q(din_m[29]), .so(dff_wdata_m_scanout[29]),
502 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
503
504 cl_sc1_msff_syrst_4x din_m030 (.d(din[30]), .si(dff_wdata_m_scanin[30]), .q(din_m[30]), .so(dff_wdata_m_scanout[30]),
505 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
506 cl_sc1_msff_syrst_4x din_m031 (.d(din[31]), .si(dff_wdata_m_scanin[31]), .q(din_m[31]), .so(dff_wdata_m_scanout[31]),
507 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
508 cl_sc1_msff_syrst_4x din_m032 (.d(din[32]), .si(dff_wdata_m_scanin[32]), .q(din_m[32]), .so(dff_wdata_m_scanout[32]),
509 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
510 cl_sc1_msff_syrst_4x din_m033 (.d(din[33]), .si(dff_wdata_m_scanin[33]), .q(din_m[33]), .so(dff_wdata_m_scanout[33]),
511 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
512 cl_sc1_msff_syrst_4x din_m034 (.d(din[34]), .si(dff_wdata_m_scanin[34]), .q(din_m[34]), .so(dff_wdata_m_scanout[34]),
513 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
514 cl_sc1_msff_syrst_4x din_m035 (.d(din[35]), .si(dff_wdata_m_scanin[35]), .q(din_m[35]), .so(dff_wdata_m_scanout[35]),
515 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
516 cl_sc1_msff_syrst_4x din_m036 (.d(din[36]), .si(dff_wdata_m_scanin[36]), .q(din_m[36]), .so(dff_wdata_m_scanout[36]),
517 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
518 cl_sc1_msff_syrst_4x din_m037 (.d(din[37]), .si(dff_wdata_m_scanin[37]), .q(din_m[37]), .so(dff_wdata_m_scanout[37]),
519 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
520 cl_sc1_msff_syrst_4x din_m038 (.d(din[38]), .si(dff_wdata_m_scanin[38]), .q(din_m[38]), .so(dff_wdata_m_scanout[38]),
521 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
522 cl_sc1_msff_syrst_4x din_m039 (.d(din[39]), .si(dff_wdata_m_scanin[39]), .q(din_m[39]), .so(dff_wdata_m_scanout[39]),
523 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
524
525 cl_sc1_msff_syrst_4x din_m040 (.d(din[40]), .si(dff_wdata_m_scanin[40]), .q(din_m[40]), .so(dff_wdata_m_scanout[40]),
526 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
527 cl_sc1_msff_syrst_4x din_m041 (.d(din[41]), .si(dff_wdata_m_scanin[41]), .q(din_m[41]), .so(dff_wdata_m_scanout[41]),
528 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
529 cl_sc1_msff_syrst_4x din_m042 (.d(din[42]), .si(dff_wdata_m_scanin[42]), .q(din_m[42]), .so(dff_wdata_m_scanout[42]),
530 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
531 cl_sc1_msff_syrst_4x din_m043 (.d(din[43]), .si(dff_wdata_m_scanin[43]), .q(din_m[43]), .so(dff_wdata_m_scanout[43]),
532 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
533 cl_sc1_msff_syrst_4x din_m044 (.d(din[44]), .si(dff_wdata_m_scanin[44]), .q(din_m[44]), .so(dff_wdata_m_scanout[44]),
534 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
535 cl_sc1_msff_syrst_4x din_m045 (.d(din[45]), .si(dff_wdata_m_scanin[45]), .q(din_m[45]), .so(dff_wdata_m_scanout[45]),
536 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
537 cl_sc1_msff_syrst_4x din_m046 (.d(din[46]), .si(dff_wdata_m_scanin[46]), .q(din_m[46]), .so(dff_wdata_m_scanout[46]),
538 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
539 cl_sc1_msff_syrst_4x din_m047 (.d(din[47]), .si(dff_wdata_m_scanin[47]), .q(din_m[47]), .so(dff_wdata_m_scanout[47]),
540 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
541 cl_sc1_msff_syrst_4x din_m048 (.d(din[48]), .si(dff_wdata_m_scanin[48]), .q(din_m[48]), .so(dff_wdata_m_scanout[48]),
542 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
543 cl_sc1_msff_syrst_4x din_m049 (.d(din[49]), .si(dff_wdata_m_scanin[49]), .q(din_m[49]), .so(dff_wdata_m_scanout[49]),
544 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
545
546 cl_sc1_msff_syrst_4x din_m050 (.d(din[50]), .si(dff_wdata_m_scanin[50]), .q(din_m[50]), .so(dff_wdata_m_scanout[50]),
547 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
548 cl_sc1_msff_syrst_4x din_m051 (.d(din[51]), .si(dff_wdata_m_scanin[51]), .q(din_m[51]), .so(dff_wdata_m_scanout[51]),
549 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
550 cl_sc1_msff_syrst_4x din_m052 (.d(din[52]), .si(dff_wdata_m_scanin[52]), .q(din_m[52]), .so(dff_wdata_m_scanout[52]),
551 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
552 cl_sc1_msff_syrst_4x din_m053 (.d(din[53]), .si(dff_wdata_m_scanin[53]), .q(din_m[53]), .so(dff_wdata_m_scanout[53]),
553 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
554 cl_sc1_msff_syrst_4x din_m054 (.d(din[54]), .si(dff_wdata_m_scanin[54]), .q(din_m[54]), .so(dff_wdata_m_scanout[54]),
555 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
556 cl_sc1_msff_syrst_4x din_m055 (.d(din[55]), .si(dff_wdata_m_scanin[55]), .q(din_m[55]), .so(dff_wdata_m_scanout[55]),
557 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
558 cl_sc1_msff_syrst_4x din_m056 (.d(din[56]), .si(dff_wdata_m_scanin[56]), .q(din_m[56]), .so(dff_wdata_m_scanout[56]),
559 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
560 cl_sc1_msff_syrst_4x din_m057 (.d(din[57]), .si(dff_wdata_m_scanin[57]), .q(din_m[57]), .so(dff_wdata_m_scanout[57]),
561 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
562 cl_sc1_msff_syrst_4x din_m058 (.d(din[58]), .si(dff_wdata_m_scanin[58]), .q(din_m[58]), .so(dff_wdata_m_scanout[58]),
563 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
564 cl_sc1_msff_syrst_4x din_m059 (.d(din[59]), .si(dff_wdata_m_scanin[59]), .q(din_m[59]), .so(dff_wdata_m_scanout[59]),
565 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
566
567 cl_sc1_msff_syrst_4x din_m060 (.d(din[60]), .si(dff_wdata_m_scanin[60]), .q(din_m[60]), .so(dff_wdata_m_scanout[60]),
568 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
569 cl_sc1_msff_syrst_4x din_m061 (.d(din[61]), .si(dff_wdata_m_scanin[61]), .q(din_m[61]), .so(dff_wdata_m_scanout[61]),
570 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
571 cl_sc1_msff_syrst_4x din_m062 (.d(din[62]), .si(dff_wdata_m_scanin[62]), .q(din_m[62]), .so(dff_wdata_m_scanout[62]),
572 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
573 cl_sc1_msff_syrst_4x din_m063 (.d(din[63]), .si(dff_wdata_m_scanin[63]), .q(din_m[63]), .so(dff_wdata_m_scanout[63]),
574 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
575 cl_sc1_msff_syrst_4x din_m064 (.d(din[64]), .si(dff_wdata_m_scanin[64]), .q(din_m[64]), .so(dff_wdata_m_scanout[64]),
576 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
577 cl_sc1_msff_syrst_4x din_m065 (.d(din[65]), .si(dff_wdata_m_scanin[65]), .q(din_m[65]), .so(dff_wdata_m_scanout[65]),
578 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
579 cl_sc1_msff_syrst_4x din_m066 (.d(din[66]), .si(dff_wdata_m_scanin[66]), .q(din_m[66]), .so(dff_wdata_m_scanout[66]),
580 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
581 cl_sc1_msff_syrst_4x din_m067 (.d(din[67]), .si(dff_wdata_m_scanin[67]), .q(din_m[67]), .so(dff_wdata_m_scanout[67]),
582 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
583 cl_sc1_msff_syrst_4x din_m068 (.d(din[68]), .si(dff_wdata_m_scanin[68]), .q(din_m[68]), .so(dff_wdata_m_scanout[68]),
584 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
585 cl_sc1_msff_syrst_4x din_m069 (.d(din[69]), .si(dff_wdata_m_scanin[69]), .q(din_m[69]), .so(dff_wdata_m_scanout[69]),
586 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
587
588 cl_sc1_msff_syrst_4x din_m070 (.d(din[70]), .si(dff_wdata_m_scanin[70]), .q(din_m[70]), .so(dff_wdata_m_scanout[70]),
589 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
590 cl_sc1_msff_syrst_4x din_m071 (.d(din[71]), .si(dff_wdata_m_scanin[71]), .q(din_m[71]), .so(dff_wdata_m_scanout[71]),
591 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
592 cl_sc1_msff_syrst_4x din_m072 (.d(din[72]), .si(dff_wdata_m_scanin[72]), .q(din_m[72]), .so(dff_wdata_m_scanout[72]),
593 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
594 cl_sc1_msff_syrst_4x din_m073 (.d(din[73]), .si(dff_wdata_m_scanin[73]), .q(din_m[73]), .so(dff_wdata_m_scanout[73]),
595 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
596 cl_sc1_msff_syrst_4x din_m074 (.d(din[74]), .si(dff_wdata_m_scanin[74]), .q(din_m[74]), .so(dff_wdata_m_scanout[74]),
597 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
598 cl_sc1_msff_syrst_4x din_m075 (.d(din[75]), .si(dff_wdata_m_scanin[75]), .q(din_m[75]), .so(dff_wdata_m_scanout[75]),
599 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
600 cl_sc1_msff_syrst_4x din_m076 (.d(din[76]), .si(dff_wdata_m_scanin[76]), .q(din_m[76]), .so(dff_wdata_m_scanout[76]),
601 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
602 cl_sc1_msff_syrst_4x din_m077 (.d(din[77]), .si(dff_wdata_m_scanin[77]), .q(din_m[77]), .so(dff_wdata_m_scanout[77]),
603 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
604 cl_sc1_msff_syrst_4x din_m078 (.d(din[78]), .si(dff_wdata_m_scanin[78]), .q(din_m[78]), .so(dff_wdata_m_scanout[78]),
605 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
606 cl_sc1_msff_syrst_4x din_m079 (.d(din[79]), .si(dff_wdata_m_scanin[79]), .q(din_m[79]), .so(dff_wdata_m_scanout[79]),
607 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
608
609 cl_sc1_msff_syrst_4x din_m080 (.d(din[80]), .si(dff_wdata_m_scanin[80]), .q(din_m[80]), .so(dff_wdata_m_scanout[80]),
610 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
611 cl_sc1_msff_syrst_4x din_m081 (.d(din[81]), .si(dff_wdata_m_scanin[81]), .q(din_m[81]), .so(dff_wdata_m_scanout[81]),
612 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
613 cl_sc1_msff_syrst_4x din_m082 (.d(din[82]), .si(dff_wdata_m_scanin[82]), .q(din_m[82]), .so(dff_wdata_m_scanout[82]),
614 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
615 cl_sc1_msff_syrst_4x din_m083 (.d(din[83]), .si(dff_wdata_m_scanin[83]), .q(din_m[83]), .so(dff_wdata_m_scanout[83]),
616 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
617 cl_sc1_msff_syrst_4x din_m084 (.d(din[84]), .si(dff_wdata_m_scanin[84]), .q(din_m[84]), .so(dff_wdata_m_scanout[84]),
618 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
619 cl_sc1_msff_syrst_4x din_m085 (.d(din[85]), .si(dff_wdata_m_scanin[85]), .q(din_m[85]), .so(dff_wdata_m_scanout[85]),
620 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
621 cl_sc1_msff_syrst_4x din_m086 (.d(din[86]), .si(dff_wdata_m_scanin[86]), .q(din_m[86]), .so(dff_wdata_m_scanout[86]),
622 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
623 cl_sc1_msff_syrst_4x din_m087 (.d(din[87]), .si(dff_wdata_m_scanin[87]), .q(din_m[87]), .so(dff_wdata_m_scanout[87]),
624 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
625 cl_sc1_msff_syrst_4x din_m088 (.d(din[88]), .si(dff_wdata_m_scanin[88]), .q(din_m[88]), .so(dff_wdata_m_scanout[88]),
626 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
627 cl_sc1_msff_syrst_4x din_m089 (.d(din[89]), .si(dff_wdata_m_scanin[89]), .q(din_m[89]), .so(dff_wdata_m_scanout[89]),
628 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
629
630 cl_sc1_msff_syrst_4x din_m090 (.d(din[90]), .si(dff_wdata_m_scanin[90]), .q(din_m[90]), .so(dff_wdata_m_scanout[90]),
631 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
632 cl_sc1_msff_syrst_4x din_m091 (.d(din[91]), .si(dff_wdata_m_scanin[91]), .q(din_m[91]), .so(dff_wdata_m_scanout[91]),
633 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
634 cl_sc1_msff_syrst_4x din_m092 (.d(din[92]), .si(dff_wdata_m_scanin[92]), .q(din_m[92]), .so(dff_wdata_m_scanout[92]),
635 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
636 cl_sc1_msff_syrst_4x din_m093 (.d(din[93]), .si(dff_wdata_m_scanin[93]), .q(din_m[93]), .so(dff_wdata_m_scanout[93]),
637 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
638 cl_sc1_msff_syrst_4x din_m094 (.d(din[94]), .si(dff_wdata_m_scanin[94]), .q(din_m[94]), .so(dff_wdata_m_scanout[94]),
639 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
640 cl_sc1_msff_syrst_4x din_m095 (.d(din[95]), .si(dff_wdata_m_scanin[95]), .q(din_m[95]), .so(dff_wdata_m_scanout[95]),
641 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
642 cl_sc1_msff_syrst_4x din_m096 (.d(din[96]), .si(dff_wdata_m_scanin[96]), .q(din_m[96]), .so(dff_wdata_m_scanout[96]),
643 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
644 cl_sc1_msff_syrst_4x din_m097 (.d(din[97]), .si(dff_wdata_m_scanin[97]), .q(din_m[97]), .so(dff_wdata_m_scanout[97]),
645 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
646 cl_sc1_msff_syrst_4x din_m098 (.d(din[98]), .si(dff_wdata_m_scanin[98]), .q(din_m[98]), .so(dff_wdata_m_scanout[98]),
647 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
648 cl_sc1_msff_syrst_4x din_m099 (.d(din[99]), .si(dff_wdata_m_scanin[99]), .q(din_m[99]), .so(dff_wdata_m_scanout[99]),
649 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
650
651 cl_sc1_msff_syrst_4x din_m100 (.d(din[100]), .si(dff_wdata_m_scanin[100]), .q(din_m[100]), .so(dff_wdata_m_scanout[100]),
652 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
653 cl_sc1_msff_syrst_4x din_m101 (.d(din[101]), .si(dff_wdata_m_scanin[101]), .q(din_m[101]), .so(dff_wdata_m_scanout[101]),
654 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
655 cl_sc1_msff_syrst_4x din_m102 (.d(din[102]), .si(dff_wdata_m_scanin[102]), .q(din_m[102]), .so(dff_wdata_m_scanout[102]),
656 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
657 cl_sc1_msff_syrst_4x din_m103 (.d(din[103]), .si(dff_wdata_m_scanin[103]), .q(din_m[103]), .so(dff_wdata_m_scanout[103]),
658 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
659 cl_sc1_msff_syrst_4x din_m104 (.d(din[104]), .si(dff_wdata_m_scanin[104]), .q(din_m[104]), .so(dff_wdata_m_scanout[104]),
660 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
661 cl_sc1_msff_syrst_4x din_m105 (.d(din[105]), .si(dff_wdata_m_scanin[105]), .q(din_m[105]), .so(dff_wdata_m_scanout[105]),
662 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
663 cl_sc1_msff_syrst_4x din_m106 (.d(din[106]), .si(dff_wdata_m_scanin[106]), .q(din_m[106]), .so(dff_wdata_m_scanout[106]),
664 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
665 cl_sc1_msff_syrst_4x din_m107 (.d(din[107]), .si(dff_wdata_m_scanin[107]), .q(din_m[107]), .so(dff_wdata_m_scanout[107]),
666 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
667 cl_sc1_msff_syrst_4x din_m108 (.d(din[108]), .si(dff_wdata_m_scanin[108]), .q(din_m[108]), .so(dff_wdata_m_scanout[108]),
668 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
669 cl_sc1_msff_syrst_4x din_m109 (.d(din[109]), .si(dff_wdata_m_scanin[109]), .q(din_m[109]), .so(dff_wdata_m_scanout[109]),
670 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
671
672 cl_sc1_msff_syrst_4x din_m110 (.d(din[110]), .si(dff_wdata_m_scanin[110]), .q(din_m[110]), .so(dff_wdata_m_scanout[110]),
673 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
674 cl_sc1_msff_syrst_4x din_m111 (.d(din[111]), .si(dff_wdata_m_scanin[111]), .q(din_m[111]), .so(dff_wdata_m_scanout[111]),
675 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
676 cl_sc1_msff_syrst_4x din_m112 (.d(din[112]), .si(dff_wdata_m_scanin[112]), .q(din_m[112]), .so(dff_wdata_m_scanout[112]),
677 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
678 cl_sc1_msff_syrst_4x din_m113 (.d(din[113]), .si(dff_wdata_m_scanin[113]), .q(din_m[113]), .so(dff_wdata_m_scanout[113]),
679 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
680 cl_sc1_msff_syrst_4x din_m114 (.d(din[114]), .si(dff_wdata_m_scanin[114]), .q(din_m[114]), .so(dff_wdata_m_scanout[114]),
681 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
682 cl_sc1_msff_syrst_4x din_m115 (.d(din[115]), .si(dff_wdata_m_scanin[115]), .q(din_m[115]), .so(dff_wdata_m_scanout[115]),
683 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
684 cl_sc1_msff_syrst_4x din_m116 (.d(din[116]), .si(dff_wdata_m_scanin[116]), .q(din_m[116]), .so(dff_wdata_m_scanout[116]),
685 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
686 cl_sc1_msff_syrst_4x din_m117 (.d(din[117]), .si(dff_wdata_m_scanin[117]), .q(din_m[117]), .so(dff_wdata_m_scanout[117]),
687 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
688 cl_sc1_msff_syrst_4x din_m118 (.d(din[118]), .si(dff_wdata_m_scanin[118]), .q(din_m[118]), .so(dff_wdata_m_scanout[118]),
689 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
690 cl_sc1_msff_syrst_4x din_m119 (.d(din[119]), .si(dff_wdata_m_scanin[119]), .q(din_m[119]), .so(dff_wdata_m_scanout[119]),
691 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
692
693 cl_sc1_msff_syrst_4x din_m120 (.d(din[120]), .si(dff_wdata_m_scanin[120]), .q(din_m[120]), .so(dff_wdata_m_scanout[120]),
694 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
695 cl_sc1_msff_syrst_4x din_m121 (.d(din[121]), .si(dff_wdata_m_scanin[121]), .q(din_m[121]), .so(dff_wdata_m_scanout[121]),
696 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
697 cl_sc1_msff_syrst_4x din_m122 (.d(din[122]), .si(dff_wdata_m_scanin[122]), .q(din_m[122]), .so(dff_wdata_m_scanout[122]),
698 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
699 cl_sc1_msff_syrst_4x din_m123 (.d(din[123]), .si(dff_wdata_m_scanin[123]), .q(din_m[123]), .so(dff_wdata_m_scanout[123]),
700 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
701 cl_sc1_msff_syrst_4x din_m124 (.d(din[124]), .si(dff_wdata_m_scanin[124]), .q(din_m[124]), .so(dff_wdata_m_scanout[124]),
702 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
703 cl_sc1_msff_syrst_4x din_m125 (.d(din[125]), .si(dff_wdata_m_scanin[125]), .q(din_m[125]), .so(dff_wdata_m_scanout[125]),
704 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
705 cl_sc1_msff_syrst_4x din_m126 (.d(din[126]), .si(dff_wdata_m_scanin[126]), .q(din_m[126]), .so(dff_wdata_m_scanout[126]),
706 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
707 cl_sc1_msff_syrst_4x din_m127 (.d(din[127]), .si(dff_wdata_m_scanin[127]), .q(din_m[127]), .so(dff_wdata_m_scanout[127]),
708 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
709 cl_sc1_msff_syrst_4x din_m128 (.d(din[128]), .si(dff_wdata_m_scanin[128]), .q(din_m[128]), .so(dff_wdata_m_scanout[128]),
710 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
711 cl_sc1_msff_syrst_4x din_m129 (.d(din[129]), .si(dff_wdata_m_scanin[129]), .q(din_m[129]), .so(dff_wdata_m_scanout[129]),
712 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
713
714 cl_sc1_msff_syrst_4x din_m130 (.d(din[130]), .si(dff_wdata_m_scanin[130]), .q(din_m[130]), .so(dff_wdata_m_scanout[130]),
715 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
716 cl_sc1_msff_syrst_4x din_m131 (.d(din[131]), .si(dff_wdata_m_scanin[131]), .q(din_m[131]), .so(dff_wdata_m_scanout[131]),
717 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
718 cl_sc1_msff_syrst_4x din_m132 (.d(din[132]), .si(dff_wdata_m_scanin[132]), .q(din_m[132]), .so(dff_wdata_m_scanout[132]),
719 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
720 cl_sc1_msff_syrst_4x din_m133 (.d(din[133]), .si(dff_wdata_m_scanin[133]), .q(din_m[133]), .so(dff_wdata_m_scanout[133]),
721 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
722 cl_sc1_msff_syrst_4x din_m134 (.d(din[134]), .si(dff_wdata_m_scanin[134]), .q(din_m[134]), .so(dff_wdata_m_scanout[134]),
723 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
724 cl_sc1_msff_syrst_4x din_m135 (.d(din[135]), .si(dff_wdata_m_scanin[135]), .q(din_m[135]), .so(dff_wdata_m_scanout[135]),
725 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
726 cl_sc1_msff_syrst_4x din_m136 (.d(din[136]), .si(dff_wdata_m_scanin[136]), .q(din_m[136]), .so(dff_wdata_m_scanout[136]),
727 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
728 cl_sc1_msff_syrst_4x din_m137 (.d(din[137]), .si(dff_wdata_m_scanin[137]), .q(din_m[137]), .so(dff_wdata_m_scanout[137]),
729 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
730 cl_sc1_msff_syrst_4x din_m138 (.d(din[138]), .si(dff_wdata_m_scanin[138]), .q(din_m[138]), .so(dff_wdata_m_scanout[138]),
731 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
732 cl_sc1_msff_syrst_4x din_m139 (.d(din[139]), .si(dff_wdata_m_scanin[139]), .q(din_m[139]), .so(dff_wdata_m_scanout[139]),
733 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
734
735 cl_sc1_msff_syrst_4x din_m140 (.d(din[140]), .si(dff_wdata_m_scanin[140]), .q(din_m[140]), .so(dff_wdata_m_scanout[140]),
736 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
737 cl_sc1_msff_syrst_4x din_m141 (.d(din[141]), .si(dff_wdata_m_scanin[141]), .q(din_m[141]), .so(dff_wdata_m_scanout[141]),
738 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
739 cl_sc1_msff_syrst_4x din_m142 (.d(din[142]), .si(dff_wdata_m_scanin[142]), .q(din_m[142]), .so(dff_wdata_m_scanout[142]),
740 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
741 cl_sc1_msff_syrst_4x din_m143 (.d(din[143]), .si(dff_wdata_m_scanin[143]), .q(din_m[143]), .so(dff_wdata_m_scanout[143]),
742 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
743 cl_sc1_msff_syrst_4x din_m144 (.d(din[144]), .si(dff_wdata_m_scanin[144]), .q(din_m[144]), .so(dff_wdata_m_scanout[144]),
744 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
745 cl_sc1_msff_syrst_4x din_m145 (.d(din[145]), .si(dff_wdata_m_scanin[145]), .q(din_m[145]), .so(dff_wdata_m_scanout[145]),
746 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
747 cl_sc1_msff_syrst_4x din_m146 (.d(din[146]), .si(dff_wdata_m_scanin[146]), .q(din_m[146]), .so(dff_wdata_m_scanout[146]),
748 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
749 cl_sc1_msff_syrst_4x din_m147 (.d(din[147]), .si(dff_wdata_m_scanin[147]), .q(din_m[147]), .so(dff_wdata_m_scanout[147]),
750 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
751 cl_sc1_msff_syrst_4x din_m148 (.d(din[148]), .si(dff_wdata_m_scanin[148]), .q(din_m[148]), .so(dff_wdata_m_scanout[148]),
752 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
753 cl_sc1_msff_syrst_4x din_m149 (.d(din[149]), .si(dff_wdata_m_scanin[149]), .q(din_m[149]), .so(dff_wdata_m_scanout[149]),
754 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
755
756 cl_sc1_msff_syrst_4x din_m150 (.d(din[150]), .si(dff_wdata_m_scanin[150]), .q(din_m[150]), .so(dff_wdata_m_scanout[150]),
757 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
758 cl_sc1_msff_syrst_4x din_m151 (.d(din[151]), .si(dff_wdata_m_scanin[151]), .q(din_m[151]), .so(dff_wdata_m_scanout[151]),
759 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
760
761// ------------ test registers ------------
762 cl_sc1_msff_syrst_4x test_mode_reg (
763 .d (test_mode),
764 .reset (reset_l),
765 .si (dff_test_mode_scanin),
766 .q (test_mode),
767 .so (dff_test_mode_scanout),
768 .l1clk (l1clk_in),
769 .siclk (tcu_aclk),
770 .soclk (tcu_bclk) );
771
772 cl_sc1_msff_syrst_4x test_clk_reg (
773 .d (test_clk),
774 .reset (reset_l),
775 .si (dff_test_clk_scanin),
776 .q (test_clk),
777 .so (dff_test_clk_scanout),
778 .l1clk (l1clk_in),
779 .siclk (tcu_aclk),
780 .soclk (tcu_bclk) );
781
782wire l1clk_testclk;
783
784 assign l1clk_testclk = test_mode ? test_clk : l1clk_gate;
785
786//================================================
787// l2 clock Domain: Control signals
788//================================================
789wire do_B_write_m, l1clk_testclk_not, wr_inhibit_not, wr_en_and_clk_not;
790wire do_A_read_m;
791wire [9:0] rw_addr_m, sc11, sc12;
792wire do_A_read_temp;
793
794// assign do_B_write_m = wr_en_m && !l1clk_gate && !tcu_array_wr_inhibit;
795// assign do_A_read_m = rd_en_m && l1clk_gate && !tcu_array_wr_inhibit;
796// assign rw_addr_m = {10{do_B_write_m}} & wr_adr_m |
797// {10{do_A_read_m}} & rd_adr_m;
798
799 niu1024_inv_macro__width_1 a1 (.dout(l1clk_testclk_not), .din(l1clk_testclk) );
800 niu1024_inv_macro__width_1 a2 (.dout(wr_inhibit_not), .din(tcu_array_wr_inhibit) );
801 niu1024_and_macro__width_1 a3 (.dout(wr_en_and_clk_not), .din0(wr_en_m), .din1(l1clk_testclk_not) );
802 niu1024_and_macro__width_1 a4 (.dout(do_B_write_m), .din0(wr_en_and_clk_not), .din1(wr_inhibit_not) );
803
804 niu1024_and_macro__width_1 b1 (.dout(do_A_read_temp), .din0(rd_en_m), .din1(l1clk_testclk) );
805 niu1024_and_macro__width_1 b2 (.dout(do_A_read_m), .din0(wr_inhibit_not), .din1(do_A_read_temp) );
806
807 niu1024_niu1024_and_macro__width_10 c1 (.dout(sc11[9:0]), .din0({10{do_B_write_m}}),.din1(wr_adr_m[9:0]));
808 niu1024_niu1024_and_macro__width_10 c2 (.dout(sc12[9:0]), .din0({10{do_A_read_m}}), .din1(rd_adr_m[9:0]));
809 niu1024_niu1024_or_macro__width_10 c3 (.dout(rw_addr_m[9:0]),.din0(sc11[9:0]), .din1(sc12[9:0]));
810
811//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
812
813wire scan_in_repair;
814wire scan_out_repair;
815
816wire rd_en_a;
817wire wr_en_a;
818wire [151:0] wdata_b;
819wire [9:0] addr_a;
820
821wire wcs_a;
822
823wire [7:0] rd_en_column;
824wire [7:0] wt_en_column;
825
826wire [37:0] ary_rdout_brr;
827wire [37:0] ary_rdout_brm;
828wire [37:0] ary_rdout_blm;
829wire [37:0] ary_rdout_bll;
830wire [37:0] ary_rdout_trr;
831wire [37:0] ary_rdout_trm;
832wire [37:0] ary_rdout_tlm;
833wire [37:0] ary_rdout_tll;
834
835
836//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
837//================================================
838// l2x2 clock Domain: Clock headers
839//================================================
840wire l1clk_2x_free;
841
842cl_sc1_l1hdr_8x l1ch_2x_free (
843 .l2clk (l2clk_2x),
844 .pce (pce),
845 .pce_ov (tcu_pce_ov),
846 .l1clk (l1clk_2x_free),
847 .se (tcu_scan_en),
848 .stop (1'b0)
849 );
850
851//================================================
852// l2x2 clock Domain: Input Logic
853//================================================
854// ------------ controls_ph.a Latch @ posedge -------
855wire do_B_write_2x_a;
856wire do_A_read_2x_a;
857wire [9:0] rw_addr_2x_a;
858
859cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat0 (.latout(rw_addr_2x_a[0]), .d(rw_addr_m[0]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
860cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat1 (.latout(rw_addr_2x_a[1]), .d(rw_addr_m[1]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
861cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat2 (.latout(rw_addr_2x_a[2]), .d(rw_addr_m[2]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
862cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat3 (.latout(rw_addr_2x_a[3]), .d(rw_addr_m[3]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
863cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat4 (.latout(rw_addr_2x_a[4]), .d(rw_addr_m[4]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
864cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat5 (.latout(rw_addr_2x_a[5]), .d(rw_addr_m[5]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
865cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat6 (.latout(rw_addr_2x_a[6]), .d(rw_addr_m[6]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
866cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat7 (.latout(rw_addr_2x_a[7]), .d(rw_addr_m[7]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
867cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat8 (.latout(rw_addr_2x_a[8]), .d(rw_addr_m[8]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
868cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat9 (.latout(rw_addr_2x_a[9]), .d(rw_addr_m[9]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
869
870cl_mc1_scm_msff_lat_4x do_A_read_2x_a_lat (.latout(do_A_read_2x_a), .d(do_A_read_m), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
871cl_mc1_scm_msff_lat_4x do_B_write_2x_a_lat (.latout(do_B_write_2x_a), .d(do_B_write_m), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
872
873
874cl_mc1_scm_msff_lat_4x rd_addr_column_b1_lat0 (.latout(rd_addr_column_b1[0]), .d(rw_addr_2x_a[0]), .l1clk(~(!l1clk_2x_free && rd_en_a)), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
875cl_mc1_scm_msff_lat_4x rd_addr_column_b1_lat1 (.latout(rd_addr_column_b1[1]), .d(rw_addr_2x_a[1]), .l1clk(~(!l1clk_2x_free && rd_en_a)), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
876
877cl_mc1_scm_msff_lat_4x rd_addr_column_b_lat0 (.latout(rd_addr_column_b[0]), .d(rd_addr_column_b1[0]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
878cl_mc1_scm_msff_lat_4x rd_addr_column_b_lat1 (.latout(rd_addr_column_b[1]), .d(rd_addr_column_b1[1]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
879
880cl_mc1_scm_msff_lat_4x rd_addr_msb_lat (.latout(rd_addr_msb), .d(rd_adr_m[9]), .l1clk(~(!l1clk_2x_free && rd_en_a)), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
881
882
883cl_sc1_msff_4x wdata_2x_b_reg0 (.d(din_m[0]), .si(1'b0), .q(wdata_2x_b[0]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
884cl_sc1_msff_4x wdata_2x_b_reg1 (.d(din_m[1]), .si(1'b0), .q(wdata_2x_b[1]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
885cl_sc1_msff_4x wdata_2x_b_reg2 (.d(din_m[2]), .si(1'b0), .q(wdata_2x_b[2]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
886cl_sc1_msff_4x wdata_2x_b_reg3 (.d(din_m[3]), .si(1'b0), .q(wdata_2x_b[3]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
887cl_sc1_msff_4x wdata_2x_b_reg4 (.d(din_m[4]), .si(1'b0), .q(wdata_2x_b[4]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
888cl_sc1_msff_4x wdata_2x_b_reg5 (.d(din_m[5]), .si(1'b0), .q(wdata_2x_b[5]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
889cl_sc1_msff_4x wdata_2x_b_reg6 (.d(din_m[6]), .si(1'b0), .q(wdata_2x_b[6]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
890cl_sc1_msff_4x wdata_2x_b_reg7 (.d(din_m[7]), .si(1'b0), .q(wdata_2x_b[7]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
891cl_sc1_msff_4x wdata_2x_b_reg8 (.d(din_m[8]), .si(1'b0), .q(wdata_2x_b[8]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
892cl_sc1_msff_4x wdata_2x_b_reg9 (.d(din_m[9]), .si(1'b0), .q(wdata_2x_b[9]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
893cl_sc1_msff_4x wdata_2x_b_reg10 (.d(din_m[10]), .si(1'b0), .q(wdata_2x_b[10]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
894cl_sc1_msff_4x wdata_2x_b_reg11 (.d(din_m[11]), .si(1'b0), .q(wdata_2x_b[11]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
895cl_sc1_msff_4x wdata_2x_b_reg12 (.d(din_m[12]), .si(1'b0), .q(wdata_2x_b[12]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
896cl_sc1_msff_4x wdata_2x_b_reg13 (.d(din_m[13]), .si(1'b0), .q(wdata_2x_b[13]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
897cl_sc1_msff_4x wdata_2x_b_reg14 (.d(din_m[14]), .si(1'b0), .q(wdata_2x_b[14]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
898cl_sc1_msff_4x wdata_2x_b_reg15 (.d(din_m[15]), .si(1'b0), .q(wdata_2x_b[15]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
899cl_sc1_msff_4x wdata_2x_b_reg16 (.d(din_m[16]), .si(1'b0), .q(wdata_2x_b[16]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
900cl_sc1_msff_4x wdata_2x_b_reg17 (.d(din_m[17]), .si(1'b0), .q(wdata_2x_b[17]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
901cl_sc1_msff_4x wdata_2x_b_reg18 (.d(din_m[18]), .si(1'b0), .q(wdata_2x_b[18]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
902cl_sc1_msff_4x wdata_2x_b_reg19 (.d(din_m[19]), .si(1'b0), .q(wdata_2x_b[19]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
903cl_sc1_msff_4x wdata_2x_b_reg20 (.d(din_m[20]), .si(1'b0), .q(wdata_2x_b[20]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
904cl_sc1_msff_4x wdata_2x_b_reg21 (.d(din_m[21]), .si(1'b0), .q(wdata_2x_b[21]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
905cl_sc1_msff_4x wdata_2x_b_reg22 (.d(din_m[22]), .si(1'b0), .q(wdata_2x_b[22]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
906cl_sc1_msff_4x wdata_2x_b_reg23 (.d(din_m[23]), .si(1'b0), .q(wdata_2x_b[23]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
907cl_sc1_msff_4x wdata_2x_b_reg24 (.d(din_m[24]), .si(1'b0), .q(wdata_2x_b[24]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
908cl_sc1_msff_4x wdata_2x_b_reg25 (.d(din_m[25]), .si(1'b0), .q(wdata_2x_b[25]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
909cl_sc1_msff_4x wdata_2x_b_reg26 (.d(din_m[26]), .si(1'b0), .q(wdata_2x_b[26]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
910cl_sc1_msff_4x wdata_2x_b_reg27 (.d(din_m[27]), .si(1'b0), .q(wdata_2x_b[27]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
911cl_sc1_msff_4x wdata_2x_b_reg28 (.d(din_m[28]), .si(1'b0), .q(wdata_2x_b[28]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
912cl_sc1_msff_4x wdata_2x_b_reg29 (.d(din_m[29]), .si(1'b0), .q(wdata_2x_b[29]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
913cl_sc1_msff_4x wdata_2x_b_reg30 (.d(din_m[30]), .si(1'b0), .q(wdata_2x_b[30]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
914cl_sc1_msff_4x wdata_2x_b_reg31 (.d(din_m[31]), .si(1'b0), .q(wdata_2x_b[31]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
915cl_sc1_msff_4x wdata_2x_b_reg32 (.d(din_m[32]), .si(1'b0), .q(wdata_2x_b[32]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
916cl_sc1_msff_4x wdata_2x_b_reg33 (.d(din_m[33]), .si(1'b0), .q(wdata_2x_b[33]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
917cl_sc1_msff_4x wdata_2x_b_reg34 (.d(din_m[34]), .si(1'b0), .q(wdata_2x_b[34]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
918cl_sc1_msff_4x wdata_2x_b_reg35 (.d(din_m[35]), .si(1'b0), .q(wdata_2x_b[35]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
919cl_sc1_msff_4x wdata_2x_b_reg36 (.d(din_m[36]), .si(1'b0), .q(wdata_2x_b[36]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
920cl_sc1_msff_4x wdata_2x_b_reg37 (.d(din_m[37]), .si(1'b0), .q(wdata_2x_b[37]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
921cl_sc1_msff_4x wdata_2x_b_reg38 (.d(din_m[38]), .si(1'b0), .q(wdata_2x_b[38]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
922cl_sc1_msff_4x wdata_2x_b_reg39 (.d(din_m[39]), .si(1'b0), .q(wdata_2x_b[39]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
923cl_sc1_msff_4x wdata_2x_b_reg40 (.d(din_m[40]), .si(1'b0), .q(wdata_2x_b[40]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
924cl_sc1_msff_4x wdata_2x_b_reg41 (.d(din_m[41]), .si(1'b0), .q(wdata_2x_b[41]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
925cl_sc1_msff_4x wdata_2x_b_reg42 (.d(din_m[42]), .si(1'b0), .q(wdata_2x_b[42]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
926cl_sc1_msff_4x wdata_2x_b_reg43 (.d(din_m[43]), .si(1'b0), .q(wdata_2x_b[43]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
927cl_sc1_msff_4x wdata_2x_b_reg44 (.d(din_m[44]), .si(1'b0), .q(wdata_2x_b[44]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
928cl_sc1_msff_4x wdata_2x_b_reg45 (.d(din_m[45]), .si(1'b0), .q(wdata_2x_b[45]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
929cl_sc1_msff_4x wdata_2x_b_reg46 (.d(din_m[46]), .si(1'b0), .q(wdata_2x_b[46]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
930cl_sc1_msff_4x wdata_2x_b_reg47 (.d(din_m[47]), .si(1'b0), .q(wdata_2x_b[47]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
931cl_sc1_msff_4x wdata_2x_b_reg48 (.d(din_m[48]), .si(1'b0), .q(wdata_2x_b[48]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
932cl_sc1_msff_4x wdata_2x_b_reg49 (.d(din_m[49]), .si(1'b0), .q(wdata_2x_b[49]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
933cl_sc1_msff_4x wdata_2x_b_reg50 (.d(din_m[50]), .si(1'b0), .q(wdata_2x_b[50]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
934cl_sc1_msff_4x wdata_2x_b_reg51 (.d(din_m[51]), .si(1'b0), .q(wdata_2x_b[51]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
935cl_sc1_msff_4x wdata_2x_b_reg52 (.d(din_m[52]), .si(1'b0), .q(wdata_2x_b[52]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
936cl_sc1_msff_4x wdata_2x_b_reg53 (.d(din_m[53]), .si(1'b0), .q(wdata_2x_b[53]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
937cl_sc1_msff_4x wdata_2x_b_reg54 (.d(din_m[54]), .si(1'b0), .q(wdata_2x_b[54]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
938cl_sc1_msff_4x wdata_2x_b_reg55 (.d(din_m[55]), .si(1'b0), .q(wdata_2x_b[55]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
939cl_sc1_msff_4x wdata_2x_b_reg56 (.d(din_m[56]), .si(1'b0), .q(wdata_2x_b[56]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
940cl_sc1_msff_4x wdata_2x_b_reg57 (.d(din_m[57]), .si(1'b0), .q(wdata_2x_b[57]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
941cl_sc1_msff_4x wdata_2x_b_reg58 (.d(din_m[58]), .si(1'b0), .q(wdata_2x_b[58]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
942cl_sc1_msff_4x wdata_2x_b_reg59 (.d(din_m[59]), .si(1'b0), .q(wdata_2x_b[59]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
943cl_sc1_msff_4x wdata_2x_b_reg60 (.d(din_m[60]), .si(1'b0), .q(wdata_2x_b[60]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
944cl_sc1_msff_4x wdata_2x_b_reg61 (.d(din_m[61]), .si(1'b0), .q(wdata_2x_b[61]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
945cl_sc1_msff_4x wdata_2x_b_reg62 (.d(din_m[62]), .si(1'b0), .q(wdata_2x_b[62]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
946cl_sc1_msff_4x wdata_2x_b_reg63 (.d(din_m[63]), .si(1'b0), .q(wdata_2x_b[63]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
947cl_sc1_msff_4x wdata_2x_b_reg64 (.d(din_m[64]), .si(1'b0), .q(wdata_2x_b[64]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
948cl_sc1_msff_4x wdata_2x_b_reg65 (.d(din_m[65]), .si(1'b0), .q(wdata_2x_b[65]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
949cl_sc1_msff_4x wdata_2x_b_reg66 (.d(din_m[66]), .si(1'b0), .q(wdata_2x_b[66]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
950cl_sc1_msff_4x wdata_2x_b_reg67 (.d(din_m[67]), .si(1'b0), .q(wdata_2x_b[67]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
951cl_sc1_msff_4x wdata_2x_b_reg68 (.d(din_m[68]), .si(1'b0), .q(wdata_2x_b[68]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
952cl_sc1_msff_4x wdata_2x_b_reg69 (.d(din_m[69]), .si(1'b0), .q(wdata_2x_b[69]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
953cl_sc1_msff_4x wdata_2x_b_reg70 (.d(din_m[70]), .si(1'b0), .q(wdata_2x_b[70]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
954cl_sc1_msff_4x wdata_2x_b_reg71 (.d(din_m[71]), .si(1'b0), .q(wdata_2x_b[71]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
955cl_sc1_msff_4x wdata_2x_b_reg72 (.d(din_m[72]), .si(1'b0), .q(wdata_2x_b[72]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
956cl_sc1_msff_4x wdata_2x_b_reg73 (.d(din_m[73]), .si(1'b0), .q(wdata_2x_b[73]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
957cl_sc1_msff_4x wdata_2x_b_reg74 (.d(din_m[74]), .si(1'b0), .q(wdata_2x_b[74]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
958cl_sc1_msff_4x wdata_2x_b_reg75 (.d(din_m[75]), .si(1'b0), .q(wdata_2x_b[75]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
959cl_sc1_msff_4x wdata_2x_b_reg76 (.d(din_m[76]), .si(1'b0), .q(wdata_2x_b[76]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
960cl_sc1_msff_4x wdata_2x_b_reg77 (.d(din_m[77]), .si(1'b0), .q(wdata_2x_b[77]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
961cl_sc1_msff_4x wdata_2x_b_reg78 (.d(din_m[78]), .si(1'b0), .q(wdata_2x_b[78]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
962cl_sc1_msff_4x wdata_2x_b_reg79 (.d(din_m[79]), .si(1'b0), .q(wdata_2x_b[79]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
963cl_sc1_msff_4x wdata_2x_b_reg80 (.d(din_m[80]), .si(1'b0), .q(wdata_2x_b[80]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
964cl_sc1_msff_4x wdata_2x_b_reg81 (.d(din_m[81]), .si(1'b0), .q(wdata_2x_b[81]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
965cl_sc1_msff_4x wdata_2x_b_reg82 (.d(din_m[82]), .si(1'b0), .q(wdata_2x_b[82]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
966cl_sc1_msff_4x wdata_2x_b_reg83 (.d(din_m[83]), .si(1'b0), .q(wdata_2x_b[83]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
967cl_sc1_msff_4x wdata_2x_b_reg84 (.d(din_m[84]), .si(1'b0), .q(wdata_2x_b[84]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
968cl_sc1_msff_4x wdata_2x_b_reg85 (.d(din_m[85]), .si(1'b0), .q(wdata_2x_b[85]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
969cl_sc1_msff_4x wdata_2x_b_reg86 (.d(din_m[86]), .si(1'b0), .q(wdata_2x_b[86]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
970cl_sc1_msff_4x wdata_2x_b_reg87 (.d(din_m[87]), .si(1'b0), .q(wdata_2x_b[87]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
971cl_sc1_msff_4x wdata_2x_b_reg88 (.d(din_m[88]), .si(1'b0), .q(wdata_2x_b[88]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
972cl_sc1_msff_4x wdata_2x_b_reg89 (.d(din_m[89]), .si(1'b0), .q(wdata_2x_b[89]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
973cl_sc1_msff_4x wdata_2x_b_reg90 (.d(din_m[90]), .si(1'b0), .q(wdata_2x_b[90]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
974cl_sc1_msff_4x wdata_2x_b_reg91 (.d(din_m[91]), .si(1'b0), .q(wdata_2x_b[91]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
975cl_sc1_msff_4x wdata_2x_b_reg92 (.d(din_m[92]), .si(1'b0), .q(wdata_2x_b[92]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
976cl_sc1_msff_4x wdata_2x_b_reg93 (.d(din_m[93]), .si(1'b0), .q(wdata_2x_b[93]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
977cl_sc1_msff_4x wdata_2x_b_reg94 (.d(din_m[94]), .si(1'b0), .q(wdata_2x_b[94]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
978cl_sc1_msff_4x wdata_2x_b_reg95 (.d(din_m[95]), .si(1'b0), .q(wdata_2x_b[95]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
979cl_sc1_msff_4x wdata_2x_b_reg96 (.d(din_m[96]), .si(1'b0), .q(wdata_2x_b[96]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
980cl_sc1_msff_4x wdata_2x_b_reg97 (.d(din_m[97]), .si(1'b0), .q(wdata_2x_b[97]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
981cl_sc1_msff_4x wdata_2x_b_reg98 (.d(din_m[98]), .si(1'b0), .q(wdata_2x_b[98]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
982cl_sc1_msff_4x wdata_2x_b_reg99 (.d(din_m[99]), .si(1'b0), .q(wdata_2x_b[99]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
983cl_sc1_msff_4x wdata_2x_b_reg100 (.d(din_m[100]), .si(1'b0), .q(wdata_2x_b[100]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
984cl_sc1_msff_4x wdata_2x_b_reg101 (.d(din_m[101]), .si(1'b0), .q(wdata_2x_b[101]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
985cl_sc1_msff_4x wdata_2x_b_reg102 (.d(din_m[102]), .si(1'b0), .q(wdata_2x_b[102]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
986cl_sc1_msff_4x wdata_2x_b_reg103 (.d(din_m[103]), .si(1'b0), .q(wdata_2x_b[103]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
987cl_sc1_msff_4x wdata_2x_b_reg104 (.d(din_m[104]), .si(1'b0), .q(wdata_2x_b[104]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
988cl_sc1_msff_4x wdata_2x_b_reg105 (.d(din_m[105]), .si(1'b0), .q(wdata_2x_b[105]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
989cl_sc1_msff_4x wdata_2x_b_reg106 (.d(din_m[106]), .si(1'b0), .q(wdata_2x_b[106]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
990cl_sc1_msff_4x wdata_2x_b_reg107 (.d(din_m[107]), .si(1'b0), .q(wdata_2x_b[107]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
991cl_sc1_msff_4x wdata_2x_b_reg108 (.d(din_m[108]), .si(1'b0), .q(wdata_2x_b[108]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
992cl_sc1_msff_4x wdata_2x_b_reg109 (.d(din_m[109]), .si(1'b0), .q(wdata_2x_b[109]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
993cl_sc1_msff_4x wdata_2x_b_reg110 (.d(din_m[110]), .si(1'b0), .q(wdata_2x_b[110]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
994cl_sc1_msff_4x wdata_2x_b_reg111 (.d(din_m[111]), .si(1'b0), .q(wdata_2x_b[111]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
995cl_sc1_msff_4x wdata_2x_b_reg112 (.d(din_m[112]), .si(1'b0), .q(wdata_2x_b[112]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
996cl_sc1_msff_4x wdata_2x_b_reg113 (.d(din_m[113]), .si(1'b0), .q(wdata_2x_b[113]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
997cl_sc1_msff_4x wdata_2x_b_reg114 (.d(din_m[114]), .si(1'b0), .q(wdata_2x_b[114]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
998cl_sc1_msff_4x wdata_2x_b_reg115 (.d(din_m[115]), .si(1'b0), .q(wdata_2x_b[115]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
999cl_sc1_msff_4x wdata_2x_b_reg116 (.d(din_m[116]), .si(1'b0), .q(wdata_2x_b[116]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1000cl_sc1_msff_4x wdata_2x_b_reg117 (.d(din_m[117]), .si(1'b0), .q(wdata_2x_b[117]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1001cl_sc1_msff_4x wdata_2x_b_reg118 (.d(din_m[118]), .si(1'b0), .q(wdata_2x_b[118]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1002cl_sc1_msff_4x wdata_2x_b_reg119 (.d(din_m[119]), .si(1'b0), .q(wdata_2x_b[119]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1003cl_sc1_msff_4x wdata_2x_b_reg120 (.d(din_m[120]), .si(1'b0), .q(wdata_2x_b[120]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1004cl_sc1_msff_4x wdata_2x_b_reg121 (.d(din_m[121]), .si(1'b0), .q(wdata_2x_b[121]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1005cl_sc1_msff_4x wdata_2x_b_reg122 (.d(din_m[122]), .si(1'b0), .q(wdata_2x_b[122]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1006cl_sc1_msff_4x wdata_2x_b_reg123 (.d(din_m[123]), .si(1'b0), .q(wdata_2x_b[123]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1007cl_sc1_msff_4x wdata_2x_b_reg124 (.d(din_m[124]), .si(1'b0), .q(wdata_2x_b[124]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1008cl_sc1_msff_4x wdata_2x_b_reg125 (.d(din_m[125]), .si(1'b0), .q(wdata_2x_b[125]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1009cl_sc1_msff_4x wdata_2x_b_reg126 (.d(din_m[126]), .si(1'b0), .q(wdata_2x_b[126]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1010cl_sc1_msff_4x wdata_2x_b_reg127 (.d(din_m[127]), .si(1'b0), .q(wdata_2x_b[127]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1011cl_sc1_msff_4x wdata_2x_b_reg128 (.d(din_m[128]), .si(1'b0), .q(wdata_2x_b[128]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1012cl_sc1_msff_4x wdata_2x_b_reg129 (.d(din_m[129]), .si(1'b0), .q(wdata_2x_b[129]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1013cl_sc1_msff_4x wdata_2x_b_reg130 (.d(din_m[130]), .si(1'b0), .q(wdata_2x_b[130]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1014cl_sc1_msff_4x wdata_2x_b_reg131 (.d(din_m[131]), .si(1'b0), .q(wdata_2x_b[131]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1015cl_sc1_msff_4x wdata_2x_b_reg132 (.d(din_m[132]), .si(1'b0), .q(wdata_2x_b[132]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1016cl_sc1_msff_4x wdata_2x_b_reg133 (.d(din_m[133]), .si(1'b0), .q(wdata_2x_b[133]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1017cl_sc1_msff_4x wdata_2x_b_reg134 (.d(din_m[134]), .si(1'b0), .q(wdata_2x_b[134]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1018cl_sc1_msff_4x wdata_2x_b_reg135 (.d(din_m[135]), .si(1'b0), .q(wdata_2x_b[135]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1019cl_sc1_msff_4x wdata_2x_b_reg136 (.d(din_m[136]), .si(1'b0), .q(wdata_2x_b[136]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1020cl_sc1_msff_4x wdata_2x_b_reg137 (.d(din_m[137]), .si(1'b0), .q(wdata_2x_b[137]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1021cl_sc1_msff_4x wdata_2x_b_reg138 (.d(din_m[138]), .si(1'b0), .q(wdata_2x_b[138]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1022cl_sc1_msff_4x wdata_2x_b_reg139 (.d(din_m[139]), .si(1'b0), .q(wdata_2x_b[139]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1023cl_sc1_msff_4x wdata_2x_b_reg140 (.d(din_m[140]), .si(1'b0), .q(wdata_2x_b[140]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1024cl_sc1_msff_4x wdata_2x_b_reg141 (.d(din_m[141]), .si(1'b0), .q(wdata_2x_b[141]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1025cl_sc1_msff_4x wdata_2x_b_reg142 (.d(din_m[142]), .si(1'b0), .q(wdata_2x_b[142]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1026cl_sc1_msff_4x wdata_2x_b_reg143 (.d(din_m[143]), .si(1'b0), .q(wdata_2x_b[143]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1027cl_sc1_msff_4x wdata_2x_b_reg144 (.d(din_m[144]), .si(1'b0), .q(wdata_2x_b[144]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1028cl_sc1_msff_4x wdata_2x_b_reg145 (.d(din_m[145]), .si(1'b0), .q(wdata_2x_b[145]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1029cl_sc1_msff_4x wdata_2x_b_reg146 (.d(din_m[146]), .si(1'b0), .q(wdata_2x_b[146]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1030cl_sc1_msff_4x wdata_2x_b_reg147 (.d(din_m[147]), .si(1'b0), .q(wdata_2x_b[147]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1031cl_sc1_msff_4x wdata_2x_b_reg148 (.d(din_m[148]), .si(1'b0), .q(wdata_2x_b[148]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1032cl_sc1_msff_4x wdata_2x_b_reg149 (.d(din_m[149]), .si(1'b0), .q(wdata_2x_b[149]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1033cl_sc1_msff_4x wdata_2x_b_reg150 (.d(din_m[150]), .si(1'b0), .q(wdata_2x_b[150]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1034cl_sc1_msff_4x wdata_2x_b_reg151 (.d(din_m[151]), .si(1'b0), .q(wdata_2x_b[151]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1035//================================================
1036 assign wdata_b = wdata_2x_b;
1037 assign addr_a = rw_addr_2x_a;
1038 assign rd_en_a = do_A_read_2x_a && !do_B_write_2x_a;
1039 assign wr_en_a = do_B_write_2x_a;
1040
1041// geo: assign wcs_a = wr_en_a & ~tcu_array_wr_inhibit & ~rd_en_a ;
1042 assign wcs_a = wr_en_a & ~tcu_array_wr_inhibit;
1043
1044 assign rd_en_column[0] = rd_en_a && !addr_a[9] && !addr_a[1] && !addr_a[0];
1045 assign rd_en_column[1] = rd_en_a && !addr_a[9] && !addr_a[1] && addr_a[0];
1046 assign rd_en_column[2] = rd_en_a && !addr_a[9] && addr_a[1] && !addr_a[0];
1047 assign rd_en_column[3] = rd_en_a && !addr_a[9] && addr_a[1] && addr_a[0];
1048 assign rd_en_column[4] = rd_en_a && addr_a[9] && !addr_a[1] && !addr_a[0];
1049 assign rd_en_column[5] = rd_en_a && addr_a[9] && !addr_a[1] && addr_a[0];
1050 assign rd_en_column[6] = rd_en_a && addr_a[9] && addr_a[1] && !addr_a[0];
1051 assign rd_en_column[7] = rd_en_a && addr_a[9] && addr_a[1] && addr_a[0];
1052
1053 assign wt_en_column[0] = wcs_a && !addr_a[9] && !addr_a[1] && !addr_a[0];
1054 assign wt_en_column[1] = wcs_a && !addr_a[9] && !addr_a[1] && addr_a[0];
1055 assign wt_en_column[2] = wcs_a && !addr_a[9] && addr_a[1] && !addr_a[0];
1056 assign wt_en_column[3] = wcs_a && !addr_a[9] && addr_a[1] && addr_a[0];
1057 assign wt_en_column[4] = wcs_a && addr_a[9] && !addr_a[1] && !addr_a[0];
1058 assign wt_en_column[5] = wcs_a && addr_a[9] && !addr_a[1] && addr_a[0];
1059 assign wt_en_column[6] = wcs_a && addr_a[9] && addr_a[1] && !addr_a[0];
1060 assign wt_en_column[7] = wcs_a && addr_a[9] && addr_a[1] && addr_a[0];
1061
1062//================================================
1063
1064//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
1065
1066 n2_niu_sp_1024x152s_array niu_sp_1024x152s_array_brr (
1067 .din (wdata_b[37:0]),
1068 .rw_addr_subbank (addr_a[8:2]),
1069 .rd_addr_column (rd_addr_column_b[1:0]),
1070 .rd_en_column (rd_en_column[3:0]),
1071 .wt_en_column (wt_en_column[3:0]),
1072 .red_value (red_v_brr),
1073 .repair_en (red_en_brr),
1074 .l1clk (l1clk_2x_free),
1075 .ary_rdout (ary_rdout_brr)
1076 );
1077
1078 n2_niu_sp_1024x152s_array niu_sp_1024x152s_array_brm (
1079 .din (wdata_b[75:38]),
1080 .rw_addr_subbank (addr_a[8:2]),
1081 .rd_addr_column (rd_addr_column_b[1:0]),
1082 .rd_en_column (rd_en_column[3:0]),
1083 .wt_en_column (wt_en_column[3:0]),
1084 .red_value (red_v_brm),
1085 .repair_en (red_en_brm),
1086 .l1clk (l1clk_2x_free),
1087 .ary_rdout (ary_rdout_brm)
1088 );
1089 n2_niu_sp_1024x152s_array niu_sp_1024x152s_array_blm (
1090 .din (wdata_b[113:76]),
1091 .rw_addr_subbank (addr_a[8:2]),
1092 .rd_addr_column (rd_addr_column_b[1:0]),
1093 .rd_en_column (rd_en_column[3:0]),
1094 .wt_en_column (wt_en_column[3:0]),
1095 .red_value (red_v_blm),
1096 .repair_en (red_en_blm),
1097 .l1clk (l1clk_2x_free),
1098 .ary_rdout (ary_rdout_blm)
1099 );
1100
1101 n2_niu_sp_1024x152s_array niu_sp_1024x152s_array_bll (
1102 .din (wdata_b[151:114]),
1103 .rw_addr_subbank (addr_a[8:2]),
1104 .rd_addr_column (rd_addr_column_b[1:0]),
1105 .rd_en_column (rd_en_column[3:0]),
1106 .wt_en_column (wt_en_column[3:0]),
1107 .red_value (red_v_bll),
1108 .repair_en (red_en_bll),
1109 .l1clk (l1clk_2x_free),
1110 .ary_rdout (ary_rdout_bll)
1111 );
1112 n2_niu_sp_1024x152s_array niu_sp_1024x152s_array_trr (
1113 .din (wdata_b[37:0]),
1114 .rw_addr_subbank (addr_a[8:2]),
1115 .rd_addr_column (rd_addr_column_b[1:0]),
1116 .rd_en_column (rd_en_column[7:4]),
1117 .wt_en_column (wt_en_column[7:4]),
1118 .red_value (red_v_trr),
1119 .repair_en (red_en_trr),
1120 .l1clk (l1clk_2x_free),
1121 .ary_rdout (ary_rdout_trr)
1122 );
1123
1124 n2_niu_sp_1024x152s_array niu_sp_1024x152s_array_trm (
1125 .din (wdata_b[75:38]),
1126 .rw_addr_subbank (addr_a[8:2]),
1127 .rd_addr_column (rd_addr_column_b[1:0]),
1128 .rd_en_column (rd_en_column[7:4]),
1129 .wt_en_column (wt_en_column[7:4]),
1130 .red_value (red_v_trm),
1131 .repair_en (red_en_trm),
1132 .l1clk (l1clk_2x_free),
1133 .ary_rdout (ary_rdout_trm)
1134 );
1135 n2_niu_sp_1024x152s_array niu_sp_1024x152s_array_tlm (
1136 .din (wdata_b[113:76]),
1137 .rw_addr_subbank (addr_a[8:2]),
1138 .rd_addr_column (rd_addr_column_b[1:0]),
1139 .rd_en_column (rd_en_column[7:4]),
1140 .wt_en_column (wt_en_column[7:4]),
1141 .red_value (red_v_tlm),
1142 .repair_en (red_en_tlm),
1143 .l1clk (l1clk_2x_free),
1144 .ary_rdout (ary_rdout_tlm)
1145 );
1146
1147 n2_niu_sp_1024x152s_array niu_sp_1024x152s_array_tll (
1148 .din (wdata_b[151:114]),
1149 .rw_addr_subbank (addr_a[8:2]),
1150 .rd_addr_column (rd_addr_column_b[1:0]),
1151 .rd_en_column (rd_en_column[7:4]),
1152 .wt_en_column (wt_en_column[7:4]),
1153 .red_value (red_v_tll),
1154 .repair_en (red_en_tll),
1155 .l1clk (l1clk_2x_free),
1156 .ary_rdout (ary_rdout_tll)
1157 );
1158
1159 assign dout = {152{!rd_addr_msb}} & {ary_rdout_bll,ary_rdout_blm,ary_rdout_brm,ary_rdout_brr} |
1160 {152{ rd_addr_msb}} & {ary_rdout_tll,ary_rdout_tlm,ary_rdout_trm,ary_rdout_trr};
1161
1162
1163
1164// fixscan start:
1165 assign dff_wdata_m_scanin[151] = scan_in ;
1166 assign dff_wdata_m_scanin[150] = dff_wdata_m_scanout[151] ;
1167 assign dff_wdata_m_scanin[149] = dff_wdata_m_scanout[150] ;
1168 assign dff_wdata_m_scanin[148] = dff_wdata_m_scanout[149] ;
1169 assign dff_wdata_m_scanin[147] = dff_wdata_m_scanout[148] ;
1170 assign dff_wdata_m_scanin[146] = dff_wdata_m_scanout[147] ;
1171 assign dff_wdata_m_scanin[145] = dff_wdata_m_scanout[146] ;
1172 assign dff_wdata_m_scanin[144] = dff_wdata_m_scanout[145] ;
1173 assign dff_wdata_m_scanin[143] = dff_wdata_m_scanout[144] ;
1174 assign dff_wdata_m_scanin[142] = dff_wdata_m_scanout[143] ;
1175 assign dff_wdata_m_scanin[141] = dff_wdata_m_scanout[142] ;
1176 assign dff_wdata_m_scanin[140] = dff_wdata_m_scanout[141] ;
1177 assign dff_wdata_m_scanin[139] = dff_wdata_m_scanout[140] ;
1178 assign dff_wdata_m_scanin[138] = dff_wdata_m_scanout[139] ;
1179 assign dff_wdata_m_scanin[137] = dff_wdata_m_scanout[138] ;
1180 assign dff_wdata_m_scanin[136] = dff_wdata_m_scanout[137] ;
1181 assign dff_wdata_m_scanin[135] = dff_wdata_m_scanout[136] ;
1182 assign dff_wdata_m_scanin[134] = dff_wdata_m_scanout[135] ;
1183 assign dff_wdata_m_scanin[133] = dff_wdata_m_scanout[134] ;
1184 assign dff_wdata_m_scanin[132] = dff_wdata_m_scanout[133] ;
1185 assign dff_wdata_m_scanin[131] = dff_wdata_m_scanout[132] ;
1186 assign dff_wdata_m_scanin[130] = dff_wdata_m_scanout[131] ;
1187 assign dff_wdata_m_scanin[129] = dff_wdata_m_scanout[130] ;
1188 assign dff_wdata_m_scanin[128] = dff_wdata_m_scanout[129] ;
1189 assign dff_wdata_m_scanin[127] = dff_wdata_m_scanout[128] ;
1190 assign dff_wdata_m_scanin[126] = dff_wdata_m_scanout[127] ;
1191 assign dff_wdata_m_scanin[125] = dff_wdata_m_scanout[126] ;
1192 assign dff_wdata_m_scanin[124] = dff_wdata_m_scanout[125] ;
1193 assign dff_wdata_m_scanin[123] = dff_wdata_m_scanout[124] ;
1194 assign dff_wdata_m_scanin[122] = dff_wdata_m_scanout[123] ;
1195 assign dff_wdata_m_scanin[121] = dff_wdata_m_scanout[122] ;
1196 assign dff_wdata_m_scanin[120] = dff_wdata_m_scanout[121] ;
1197 assign dff_wdata_m_scanin[119] = dff_wdata_m_scanout[120] ;
1198 assign dff_wdata_m_scanin[118] = dff_wdata_m_scanout[119] ;
1199 assign dff_wdata_m_scanin[117] = dff_wdata_m_scanout[118] ;
1200 assign dff_wdata_m_scanin[116] = dff_wdata_m_scanout[117] ;
1201 assign dff_wdata_m_scanin[115] = dff_wdata_m_scanout[116] ;
1202 assign dff_wdata_m_scanin[114] = dff_wdata_m_scanout[115] ;
1203 assign dff_wdata_m_scanin[113] = dff_wdata_m_scanout[114] ;
1204 assign dff_wdata_m_scanin[112] = dff_wdata_m_scanout[113] ;
1205 assign dff_wdata_m_scanin[111] = dff_wdata_m_scanout[112] ;
1206 assign dff_wdata_m_scanin[110] = dff_wdata_m_scanout[111] ;
1207 assign dff_wdata_m_scanin[109] = dff_wdata_m_scanout[110] ;
1208 assign dff_wdata_m_scanin[108] = dff_wdata_m_scanout[109] ;
1209 assign dff_wdata_m_scanin[107] = dff_wdata_m_scanout[108] ;
1210 assign dff_wdata_m_scanin[106] = dff_wdata_m_scanout[107] ;
1211 assign dff_wdata_m_scanin[105] = dff_wdata_m_scanout[106] ;
1212 assign dff_wdata_m_scanin[104] = dff_wdata_m_scanout[105] ;
1213 assign dff_wdata_m_scanin[103] = dff_wdata_m_scanout[104] ;
1214 assign dff_wdata_m_scanin[102] = dff_wdata_m_scanout[103] ;
1215 assign dff_wdata_m_scanin[101] = dff_wdata_m_scanout[102] ;
1216 assign dff_wdata_m_scanin[100] = dff_wdata_m_scanout[101] ;
1217 assign dff_wdata_m_scanin[99] = dff_wdata_m_scanout[100] ;
1218 assign dff_wdata_m_scanin[98] = dff_wdata_m_scanout[99] ;
1219 assign dff_wdata_m_scanin[97] = dff_wdata_m_scanout[98] ;
1220 assign dff_wdata_m_scanin[96] = dff_wdata_m_scanout[97] ;
1221 assign dff_wdata_m_scanin[95] = dff_wdata_m_scanout[96] ;
1222 assign dff_wdata_m_scanin[94] = dff_wdata_m_scanout[95] ;
1223 assign dff_wdata_m_scanin[93] = dff_wdata_m_scanout[94] ;
1224 assign dff_wdata_m_scanin[92] = dff_wdata_m_scanout[93] ;
1225 assign dff_wdata_m_scanin[91] = dff_wdata_m_scanout[92] ;
1226 assign dff_wdata_m_scanin[90] = dff_wdata_m_scanout[91] ;
1227 assign dff_wdata_m_scanin[89] = dff_wdata_m_scanout[90] ;
1228 assign dff_wdata_m_scanin[88] = dff_wdata_m_scanout[89] ;
1229 assign dff_wdata_m_scanin[87] = dff_wdata_m_scanout[88] ;
1230 assign dff_wdata_m_scanin[86] = dff_wdata_m_scanout[87] ;
1231 assign dff_wdata_m_scanin[85] = dff_wdata_m_scanout[86] ;
1232 assign dff_wdata_m_scanin[84] = dff_wdata_m_scanout[85] ;
1233 assign dff_wdata_m_scanin[83] = dff_wdata_m_scanout[84] ;
1234 assign dff_wdata_m_scanin[82] = dff_wdata_m_scanout[83] ;
1235 assign dff_wdata_m_scanin[81] = dff_wdata_m_scanout[82] ;
1236 assign dff_wdata_m_scanin[80] = dff_wdata_m_scanout[81] ;
1237 assign dff_wdata_m_scanin[79] = dff_wdata_m_scanout[80] ;
1238 assign dff_wdata_m_scanin[78] = dff_wdata_m_scanout[79] ;
1239 assign dff_wdata_m_scanin[77] = dff_wdata_m_scanout[78] ;
1240 assign dff_wdata_m_scanin[76] = dff_wdata_m_scanout[77] ;
1241
1242 assign dff_wr_adr_m_scanin[0] = dff_wdata_m_scanout[76] ;
1243 assign dff_rd_adr_m_scanin[0] = dff_wr_adr_m_scanout[0] ;
1244 assign dff_wr_adr_m_scanin[1] = dff_rd_adr_m_scanout[0] ;
1245 assign dff_rd_adr_m_scanin[1] = dff_wr_adr_m_scanout[1] ;
1246 assign dff_wr_adr_m_scanin[2] = dff_rd_adr_m_scanout[1] ;
1247 assign dff_rd_adr_m_scanin[2] = dff_wr_adr_m_scanout[2] ;
1248 assign dff_wr_adr_m_scanin[3] = dff_rd_adr_m_scanout[2] ;
1249 assign dff_rd_adr_m_scanin[3] = dff_wr_adr_m_scanout[3] ;
1250 assign dff_wr_adr_m_scanin[4] = dff_rd_adr_m_scanout[3] ;
1251 assign dff_rd_adr_m_scanin[4] = dff_wr_adr_m_scanout[4] ;
1252 assign dff_wr_adr_m_scanin[5] = dff_rd_adr_m_scanout[4] ;
1253 assign dff_rd_adr_m_scanin[5] = dff_wr_adr_m_scanout[5] ;
1254 assign dff_wr_adr_m_scanin[6] = dff_rd_adr_m_scanout[5] ;
1255 assign dff_rd_adr_m_scanin[6] = dff_wr_adr_m_scanout[6] ;
1256 assign dff_wr_adr_m_scanin[7] = dff_rd_adr_m_scanout[6] ;
1257 assign dff_rd_adr_m_scanin[7] = dff_wr_adr_m_scanout[7] ;
1258 assign dff_wr_adr_m_scanin[8] = dff_rd_adr_m_scanout[7] ;
1259 assign dff_rd_adr_m_scanin[8] = dff_wr_adr_m_scanout[8] ;
1260 assign dff_wr_adr_m_scanin[9] = dff_rd_adr_m_scanout[8] ;
1261 assign dff_rd_adr_m_scanin[9] = dff_wr_adr_m_scanout[9] ;
1262 assign dff_wr_en_m_scanin = dff_rd_adr_m_scanout[9] ;
1263 assign dff_rd_en_m_scanin = dff_wr_en_m_scanout ;
1264 assign dff_test_clk_scanin = dff_rd_en_m_scanout ;
1265 assign dff_test_mode_scanin = dff_test_clk_scanout ;
1266 assign dff_wdata_m_scanin[75] = dff_test_mode_scanout ;
1267 assign dff_wdata_m_scanin[74] = dff_wdata_m_scanout[75] ;
1268 assign dff_wdata_m_scanin[73] = dff_wdata_m_scanout[74] ;
1269 assign dff_wdata_m_scanin[72] = dff_wdata_m_scanout[73] ;
1270 assign dff_wdata_m_scanin[71] = dff_wdata_m_scanout[72] ;
1271 assign dff_wdata_m_scanin[70] = dff_wdata_m_scanout[71] ;
1272 assign dff_wdata_m_scanin[69] = dff_wdata_m_scanout[70] ;
1273 assign dff_wdata_m_scanin[68] = dff_wdata_m_scanout[69] ;
1274 assign dff_wdata_m_scanin[67] = dff_wdata_m_scanout[68] ;
1275 assign dff_wdata_m_scanin[66] = dff_wdata_m_scanout[67] ;
1276 assign dff_wdata_m_scanin[65] = dff_wdata_m_scanout[66] ;
1277 assign dff_wdata_m_scanin[64] = dff_wdata_m_scanout[65] ;
1278 assign dff_wdata_m_scanin[63] = dff_wdata_m_scanout[64] ;
1279 assign dff_wdata_m_scanin[62] = dff_wdata_m_scanout[63] ;
1280 assign dff_wdata_m_scanin[61] = dff_wdata_m_scanout[62] ;
1281 assign dff_wdata_m_scanin[60] = dff_wdata_m_scanout[61] ;
1282 assign dff_wdata_m_scanin[59] = dff_wdata_m_scanout[60] ;
1283 assign dff_wdata_m_scanin[58] = dff_wdata_m_scanout[59] ;
1284 assign dff_wdata_m_scanin[57] = dff_wdata_m_scanout[58] ;
1285 assign dff_wdata_m_scanin[56] = dff_wdata_m_scanout[57] ;
1286 assign dff_wdata_m_scanin[55] = dff_wdata_m_scanout[56] ;
1287 assign dff_wdata_m_scanin[54] = dff_wdata_m_scanout[55] ;
1288 assign dff_wdata_m_scanin[53] = dff_wdata_m_scanout[54] ;
1289 assign dff_wdata_m_scanin[52] = dff_wdata_m_scanout[53] ;
1290 assign dff_wdata_m_scanin[51] = dff_wdata_m_scanout[52] ;
1291 assign dff_wdata_m_scanin[50] = dff_wdata_m_scanout[51] ;
1292 assign dff_wdata_m_scanin[49] = dff_wdata_m_scanout[50] ;
1293 assign dff_wdata_m_scanin[48] = dff_wdata_m_scanout[49] ;
1294 assign dff_wdata_m_scanin[47] = dff_wdata_m_scanout[48] ;
1295 assign dff_wdata_m_scanin[46] = dff_wdata_m_scanout[47] ;
1296 assign dff_wdata_m_scanin[45] = dff_wdata_m_scanout[46] ;
1297 assign dff_wdata_m_scanin[44] = dff_wdata_m_scanout[45] ;
1298 assign dff_wdata_m_scanin[43] = dff_wdata_m_scanout[44] ;
1299 assign dff_wdata_m_scanin[42] = dff_wdata_m_scanout[43] ;
1300 assign dff_wdata_m_scanin[41] = dff_wdata_m_scanout[42] ;
1301 assign dff_wdata_m_scanin[40] = dff_wdata_m_scanout[41] ;
1302 assign dff_wdata_m_scanin[39] = dff_wdata_m_scanout[40] ;
1303 assign dff_wdata_m_scanin[38] = dff_wdata_m_scanout[39] ;
1304 assign dff_wdata_m_scanin[37] = dff_wdata_m_scanout[38] ;
1305 assign dff_wdata_m_scanin[36] = dff_wdata_m_scanout[37] ;
1306 assign dff_wdata_m_scanin[35] = dff_wdata_m_scanout[36] ;
1307 assign dff_wdata_m_scanin[34] = dff_wdata_m_scanout[35] ;
1308 assign dff_wdata_m_scanin[33] = dff_wdata_m_scanout[34] ;
1309 assign dff_wdata_m_scanin[32] = dff_wdata_m_scanout[33] ;
1310 assign dff_wdata_m_scanin[31] = dff_wdata_m_scanout[32] ;
1311 assign dff_wdata_m_scanin[30] = dff_wdata_m_scanout[31] ;
1312 assign dff_wdata_m_scanin[29] = dff_wdata_m_scanout[30] ;
1313 assign dff_wdata_m_scanin[28] = dff_wdata_m_scanout[29] ;
1314 assign dff_wdata_m_scanin[27] = dff_wdata_m_scanout[28] ;
1315 assign dff_wdata_m_scanin[26] = dff_wdata_m_scanout[27] ;
1316 assign dff_wdata_m_scanin[25] = dff_wdata_m_scanout[26] ;
1317 assign dff_wdata_m_scanin[24] = dff_wdata_m_scanout[25] ;
1318 assign dff_wdata_m_scanin[23] = dff_wdata_m_scanout[24] ;
1319 assign dff_wdata_m_scanin[22] = dff_wdata_m_scanout[23] ;
1320 assign dff_wdata_m_scanin[21] = dff_wdata_m_scanout[22] ;
1321 assign dff_wdata_m_scanin[20] = dff_wdata_m_scanout[21] ;
1322 assign dff_wdata_m_scanin[19] = dff_wdata_m_scanout[20] ;
1323 assign dff_wdata_m_scanin[18] = dff_wdata_m_scanout[19] ;
1324 assign dff_wdata_m_scanin[17] = dff_wdata_m_scanout[18] ;
1325 assign dff_wdata_m_scanin[16] = dff_wdata_m_scanout[17] ;
1326 assign dff_wdata_m_scanin[15] = dff_wdata_m_scanout[16] ;
1327 assign dff_wdata_m_scanin[14] = dff_wdata_m_scanout[15] ;
1328 assign dff_wdata_m_scanin[13] = dff_wdata_m_scanout[14] ;
1329 assign dff_wdata_m_scanin[12] = dff_wdata_m_scanout[13] ;
1330 assign dff_wdata_m_scanin[11] = dff_wdata_m_scanout[12] ;
1331 assign dff_wdata_m_scanin[10] = dff_wdata_m_scanout[11] ;
1332 assign dff_wdata_m_scanin[9] = dff_wdata_m_scanout[10] ;
1333 assign dff_wdata_m_scanin[8] = dff_wdata_m_scanout[9] ;
1334 assign dff_wdata_m_scanin[7] = dff_wdata_m_scanout[8] ;
1335 assign dff_wdata_m_scanin[6] = dff_wdata_m_scanout[7] ;
1336 assign dff_wdata_m_scanin[5] = dff_wdata_m_scanout[6] ;
1337 assign dff_wdata_m_scanin[4] = dff_wdata_m_scanout[5] ;
1338 assign dff_wdata_m_scanin[3] = dff_wdata_m_scanout[4] ;
1339 assign dff_wdata_m_scanin[2] = dff_wdata_m_scanout[3] ;
1340 assign dff_wdata_m_scanin[1] = dff_wdata_m_scanout[2] ;
1341 assign dff_wdata_m_scanin[0] = dff_wdata_m_scanout[1] ;
1342 assign scan_out = dff_wdata_m_scanout[0] ;
1343
1344// fixscan end:
1345endmodule
1346
1347
1348
1349//
1350// invert macro
1351//
1352//
1353
1354
1355
1356
1357
1358module niu1024_inv_macro__width_1 (
1359 din,
1360 dout);
1361 input [0:0] din;
1362 output [0:0] dout;
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372cl_u1_inv_1x d0_0 (
1373.in(din[0]),
1374.out(dout[0])
1375);
1376
1377
1378
1379
1380
1381endmodule
1382
1383
1384
1385
1386
1387//
1388// and macro for ports = 2,3,4
1389//
1390//
1391
1392
1393
1394
1395
1396module niu1024_and_macro__width_1 (
1397 din0,
1398 din1,
1399 dout);
1400wire [0:0] nandout;
1401
1402 input [0:0] din0;
1403 input [0:0] din1;
1404 output [0:0] dout;
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414cl_u1_nand2_1x d0_0 (
1415.in0(din0[0]),
1416.in1(din1[0]),
1417.out(nandout[0])
1418);
1419
1420cl_u1_inv_1x d1_0 (
1421.in(nandout[0]),
1422.out(dout[0])
1423);
1424
1425
1426
1427
1428endmodule
1429
1430
1431
1432
1433
1434//
1435// and macro for ports = 2,3,4
1436//
1437//
1438
1439
1440
1441
1442
1443module niu1024_niu1024_and_macro__width_10 (
1444 din0,
1445 din1,
1446 dout);
1447wire [9:0] nandout;
1448
1449 input [9:0] din0;
1450 input [9:0] din1;
1451 output [9:0] dout;
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461cl_u1_nand2_1x d0_0 (
1462.in0(din0[0]),
1463.in1(din1[0]),
1464.out(nandout[0])
1465);
1466
1467cl_u1_nand2_1x d0_1 (
1468.in0(din0[1]),
1469.in1(din1[1]),
1470.out(nandout[1])
1471);
1472
1473cl_u1_nand2_1x d0_2 (
1474.in0(din0[2]),
1475.in1(din1[2]),
1476.out(nandout[2])
1477);
1478
1479cl_u1_nand2_1x d0_3 (
1480.in0(din0[3]),
1481.in1(din1[3]),
1482.out(nandout[3])
1483);
1484
1485cl_u1_nand2_1x d0_4 (
1486.in0(din0[4]),
1487.in1(din1[4]),
1488.out(nandout[4])
1489);
1490
1491cl_u1_nand2_1x d0_5 (
1492.in0(din0[5]),
1493.in1(din1[5]),
1494.out(nandout[5])
1495);
1496
1497cl_u1_nand2_1x d0_6 (
1498.in0(din0[6]),
1499.in1(din1[6]),
1500.out(nandout[6])
1501);
1502
1503cl_u1_nand2_1x d0_7 (
1504.in0(din0[7]),
1505.in1(din1[7]),
1506.out(nandout[7])
1507);
1508
1509cl_u1_nand2_1x d0_8 (
1510.in0(din0[8]),
1511.in1(din1[8]),
1512.out(nandout[8])
1513);
1514
1515cl_u1_nand2_1x d0_9 (
1516.in0(din0[9]),
1517.in1(din1[9]),
1518.out(nandout[9])
1519);
1520
1521cl_u1_inv_1x d1_0 (
1522.in(nandout[0]),
1523.out(dout[0])
1524);
1525cl_u1_inv_1x d1_1 (
1526.in(nandout[1]),
1527.out(dout[1])
1528);
1529cl_u1_inv_1x d1_2 (
1530.in(nandout[2]),
1531.out(dout[2])
1532);
1533cl_u1_inv_1x d1_3 (
1534.in(nandout[3]),
1535.out(dout[3])
1536);
1537cl_u1_inv_1x d1_4 (
1538.in(nandout[4]),
1539.out(dout[4])
1540);
1541cl_u1_inv_1x d1_5 (
1542.in(nandout[5]),
1543.out(dout[5])
1544);
1545cl_u1_inv_1x d1_6 (
1546.in(nandout[6]),
1547.out(dout[6])
1548);
1549cl_u1_inv_1x d1_7 (
1550.in(nandout[7]),
1551.out(dout[7])
1552);
1553cl_u1_inv_1x d1_8 (
1554.in(nandout[8]),
1555.out(dout[8])
1556);
1557cl_u1_inv_1x d1_9 (
1558.in(nandout[9]),
1559.out(dout[9])
1560);
1561
1562
1563
1564
1565endmodule
1566
1567
1568
1569
1570
1571//
1572// or macro for ports = 2,3
1573//
1574//
1575
1576
1577
1578
1579
1580module niu1024_niu1024_or_macro__width_10 (
1581 din0,
1582 din1,
1583 dout);
1584wire [9:0] norout;
1585
1586 input [9:0] din0;
1587 input [9:0] din1;
1588 output [9:0] dout;
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598cl_u1_nor2_1x d0_0 (
1599.in0(din0[0]),
1600.in1(din1[0]),
1601.out(norout[0])
1602);
1603
1604cl_u1_nor2_1x d0_1 (
1605.in0(din0[1]),
1606.in1(din1[1]),
1607.out(norout[1])
1608);
1609
1610cl_u1_nor2_1x d0_2 (
1611.in0(din0[2]),
1612.in1(din1[2]),
1613.out(norout[2])
1614);
1615
1616cl_u1_nor2_1x d0_3 (
1617.in0(din0[3]),
1618.in1(din1[3]),
1619.out(norout[3])
1620);
1621
1622cl_u1_nor2_1x d0_4 (
1623.in0(din0[4]),
1624.in1(din1[4]),
1625.out(norout[4])
1626);
1627
1628cl_u1_nor2_1x d0_5 (
1629.in0(din0[5]),
1630.in1(din1[5]),
1631.out(norout[5])
1632);
1633
1634cl_u1_nor2_1x d0_6 (
1635.in0(din0[6]),
1636.in1(din1[6]),
1637.out(norout[6])
1638);
1639
1640cl_u1_nor2_1x d0_7 (
1641.in0(din0[7]),
1642.in1(din1[7]),
1643.out(norout[7])
1644);
1645
1646cl_u1_nor2_1x d0_8 (
1647.in0(din0[8]),
1648.in1(din1[8]),
1649.out(norout[8])
1650);
1651
1652cl_u1_nor2_1x d0_9 (
1653.in0(din0[9]),
1654.in1(din1[9]),
1655.out(norout[9])
1656);
1657
1658cl_u1_inv_1x d1_0 (
1659.in(norout[0]),
1660.out(dout[0])
1661);
1662cl_u1_inv_1x d1_1 (
1663.in(norout[1]),
1664.out(dout[1])
1665);
1666cl_u1_inv_1x d1_2 (
1667.in(norout[2]),
1668.out(dout[2])
1669);
1670cl_u1_inv_1x d1_3 (
1671.in(norout[3]),
1672.out(dout[3])
1673);
1674cl_u1_inv_1x d1_4 (
1675.in(norout[4]),
1676.out(dout[4])
1677);
1678cl_u1_inv_1x d1_5 (
1679.in(norout[5]),
1680.out(dout[5])
1681);
1682cl_u1_inv_1x d1_6 (
1683.in(norout[6]),
1684.out(dout[6])
1685);
1686cl_u1_inv_1x d1_7 (
1687.in(norout[7]),
1688.out(dout[7])
1689);
1690cl_u1_inv_1x d1_8 (
1691.in(norout[8]),
1692.out(dout[8])
1693);
1694cl_u1_inv_1x d1_9 (
1695.in(norout[9]),
1696.out(dout[9])
1697);
1698
1699
1700
1701
1702endmodule
1703
1704
1705
1706
1707
1708
1709module n2_niu_sp_1024x152s_array (
1710 din,
1711 rw_addr_subbank,
1712 rd_addr_column,
1713 rd_en_column,
1714 wt_en_column,
1715 red_value,
1716 repair_en,
1717 l1clk,
1718 ary_rdout);
1719
1720input [37:0] din;
1721input [6:0] rw_addr_subbank;
1722input [1:0] rd_addr_column;
1723input [3:0] rd_en_column;
1724input [3:0] wt_en_column;
1725input [5:0] red_value;
1726input repair_en;
1727input l1clk;
1728
1729output [37:0] ary_rdout;
1730
1731wire [37:0] ary_rdout;
1732
1733wire [37:0] ary_rdout_c0;
1734wire [37:0] ary_rdout_c1;
1735wire [37:0] ary_rdout_c2;
1736wire [37:0] ary_rdout_c3;
1737
1738 n2_niu_sp_1024x152s_subbank niu_sp_1024x152s_subbank_c0 (
1739 .din (din),
1740 .rw_addr (rw_addr_subbank),
1741 .rd_en (rd_en_column[0]),
1742 .wt_en (wt_en_column[0]),
1743 .red_value (red_value),
1744 .repair_en (repair_en),
1745 .l1clk (l1clk),
1746 .ary_rdout (ary_rdout_c0)
1747 );
1748
1749 n2_niu_sp_1024x152s_subbank niu_sp_1024x152s_subbank_c1 (
1750 .din (din),
1751 .rw_addr (rw_addr_subbank),
1752 .rd_en (rd_en_column[1]),
1753 .wt_en (wt_en_column[1]),
1754 .red_value (red_value),
1755 .repair_en (repair_en),
1756 .l1clk (l1clk),
1757 .ary_rdout (ary_rdout_c1)
1758 );
1759
1760 n2_niu_sp_1024x152s_subbank niu_sp_1024x152s_subbank_c2 (
1761 .din (din),
1762 .rw_addr (rw_addr_subbank),
1763 .rd_en (rd_en_column[2]),
1764 .wt_en (wt_en_column[2]),
1765 .red_value (red_value),
1766 .repair_en (repair_en),
1767 .l1clk (l1clk),
1768 .ary_rdout (ary_rdout_c2)
1769 );
1770
1771 n2_niu_sp_1024x152s_subbank niu_sp_1024x152s_subbank_c3 (
1772 .din (din),
1773 .rw_addr (rw_addr_subbank),
1774 .rd_en (rd_en_column[3]),
1775 .wt_en (wt_en_column[3]),
1776 .red_value (red_value),
1777 .repair_en (repair_en),
1778 .l1clk (l1clk),
1779 .ary_rdout (ary_rdout_c3)
1780 );
1781
1782
1783assign ary_rdout = rd_addr_column[1]? (rd_addr_column[0]? ary_rdout_c3: ary_rdout_c2) :
1784 (rd_addr_column[0]? ary_rdout_c1: ary_rdout_c0);
1785endmodule
1786
1787
1788
1789
1790module n2_niu_sp_1024x152s_subbank (
1791 din,
1792 rw_addr,
1793 rd_en,
1794 wt_en,
1795 red_value,
1796 repair_en,
1797 l1clk,
1798 ary_rdout);
1799// din,
1800// rw_addr,
1801// rd_en,
1802// wt_en,
1803// red_value,
1804// repair_en,
1805// l1clk,
1806// ary_rdout
1807// );
1808
1809input [37:0] din;
1810input [6:0] rw_addr;
1811input rd_en;
1812input wt_en;
1813input [5:0] red_value;
1814input repair_en;
1815input l1clk;
1816
1817output [37:0] ary_rdout;
1818
1819// ----------------------------------------------------------------------------
1820// Zero In Checkers
1821// ----------------------------------------------------------------------------
1822// checker to verify on accesses's that no bits are x
1823// 0in kndr -var rw_addr
1824// 0in kndr -var rd_en
1825// 0in kndr -var wt_en
1826// 0in kndr -var red_value
1827// 0in kndr -var repair_en
1828
1829
1830wire [37:0] ary_rdout;
1831
1832wire [38:0] wr_data;
1833
1834reg [38:0] mem_ary_dout;
1835
1836integer n;
1837
1838//`ifndef INNOLOGIC
1839//// Emulate reset
1840//integer i;
1841//initial begin
1842// for (i=0; i<128; i=i+1) begin
1843// mem[i] = {39{1'b0}};
1844// end
1845// mem_ary_dout = {39{1'b0}};
1846//end
1847//`endif
1848
1849//////////////////////////////
1850// Redundancy write shifter //
1851//////////////////////////////
1852wire [31:0] red_value_32bit = {{(32-6){1'h0}},red_value}; // 0in < max 37 -active ( (repair_en==1'b1) && (l1clk==1'b1) ) -group mbist_mode
1853
1854
1855wire [38:0] shift_col_en = {39{~repair_en}} |
1856 ( { {37{1'b1}}, {2'b00} } << red_value[5:0] ) ;
1857
1858assign wr_data[38:0] = (~shift_col_en & {{1'b0}, din}) | (shift_col_en & {din, {din[0]}}) ;
1859
1860
1861//////////////////////////////
1862// Read/write array //
1863//////////////////////////////
1864
1865reg rd_en_blat;
1866
1867 always @ (l1clk or rd_en)
1868 if (!l1clk)
1869 rd_en_blat = rd_en;
1870 else
1871 rd_en_blat = rd_en_blat;
1872
1873`ifdef AXIS_SMEM_BAD
1874
1875// internal variable
1876integer k, l;
1877
1878reg [38:0] write_mask;
1879
1880wire [38:0] axis_dout ;
1881wire [38:0] axis_din = wr_data ;
1882wire [6:0] axis_waddr = rw_addr ;
1883wire [6:0] axis_raddr = rw_addr ;
1884wire axis_wen = wt_en ;
1885wire axis_ren = rd_en ;
1886wire axis_clk = l1clk ;
1887
1888axis_smem #(7, 39, 2, 1'b0) mem // addr_width,data_width,num_ports,init_value
1889( {axis_dout , {39{1'bz}} }, // Output Port (1,2)
1890 {{39{1'bz}} , axis_din }, // Input Port (1,2)
1891 {axis_raddr , axis_waddr }, // Address Port (1,2)
1892 {1'b0 , axis_wen }, // Write Enable (1,2)
1893 {1'b1 , 1'b1 }, // Chip Enable (1,2)
1894 {axis_clk , axis_clk }, // Port Clocks (1,2)
1895 {{39{1'bz}} , {39{1'bz}}} ); // Write Mask (1,2)
1896
1897always @(posedge l1clk) begin
1898 if (rd_en_blat) begin
1899 if (axis_wen)
1900 mem_ary_dout <= 39'hx;
1901 else
1902 mem_ary_dout <= axis_dout;
1903 end
1904end
1905
1906`else
1907
1908reg [38:0] mem[0:128-1];
1909
1910 always @ (negedge l1clk) begin
1911 if (wt_en) begin
1912 if(rd_en)
1913 mem[rw_addr[6:0]] <= {39{1'hx}}; // 0in < fire -severity 1 -message "Detected rd/wr collision in NIU 1024x152s RAM, dout driven as X's" -group mbist_mode
1914
1915
1916 else
1917 mem[rw_addr[6:0]] <= wr_data;
1918 end
1919 end
1920
1921
1922 always @(posedge l1clk) begin
1923 if (rd_en_blat) begin
1924 if (wt_en)
1925 mem_ary_dout <= {39{1'hx}}; // 0in < fire -severity 1 -message "Detected rd/wr collision in NIU 1024x152s RAM, dout driven as X's" -group mbist_mode
1926
1927 else
1928 mem_ary_dout <= mem[rw_addr[6:0]] ;
1929 end
1930 end
1931
1932// Initialize the arrays.
1933`ifndef NOINITMEM
1934integer j;
1935initial begin
1936 for (j=0;j<128;j=j+1) begin
1937 mem[j] = 39'd0;
1938 end
1939 mem_ary_dout[38:0] = 39'd0;
1940end
1941`endif // NOINITMEM
1942
1943`endif // AXIS_SMEM
1944
1945//////////////////////////////
1946// Redundancy read shifter //
1947//////////////////////////////
1948reg [37:0] mem_ary_dout_rep;
1949
1950 always @(red_value_32bit or mem_ary_dout) begin
1951 for (n = 0; n < 38; n = n + 1) begin
1952 if ( n <= (red_value_32bit))
1953 mem_ary_dout_rep[n] = mem_ary_dout[n];
1954 else
1955 mem_ary_dout_rep[n] = mem_ary_dout[n+1];
1956 end
1957 end
1958
1959 assign ary_rdout = repair_en ? mem_ary_dout_rep : mem_ary_dout[38:1];
1960
1961
1962supply0 vss;
1963supply1 vdd;
1964
1965endmodule
1966
1967
1968
1969
1970module n2_niu_dp_1024x152s_repair (
1971 tcu_aclk,
1972 tcu_bclk,
1973 tcu_pce_ov,
1974 pce,
1975 tcu_scan_en,
1976 tcu_se_scancollar_in,
1977 tcu_se_scancollar_out,
1978 tcu_array_wr_inhibit,
1979 scan_in,
1980 hdr_sram_rvalue,
1981 hdr_sram_rid,
1982 hdr_sram_wr_en,
1983 hdr_sram_red_clr,
1984 l2clk,
1985 sram_hdr_read_data,
1986 red_v_blm,
1987 red_v_bll,
1988 red_v_tll,
1989 red_v_tlm,
1990 red_v_trm,
1991 red_v_trr,
1992 red_v_brr,
1993 red_v_brm,
1994 red_en_blm,
1995 red_en_bll,
1996 red_en_tlm,
1997 red_en_tll,
1998 red_en_trm,
1999 red_en_trr,
2000 red_en_brr,
2001 red_en_brm,
2002 scan_out);
2003wire l1clk_in_en;
2004wire l1clk_out_en;
2005wire l1clk_gate_en;
2006
2007
2008input tcu_aclk;
2009input tcu_bclk;
2010input tcu_pce_ov;
2011input pce;
2012input tcu_scan_en;
2013input tcu_se_scancollar_in;
2014input tcu_se_scancollar_out;
2015input tcu_array_wr_inhibit; // direct input, not flopped
2016input scan_in;
2017input [6:0] hdr_sram_rvalue;
2018input [2:0] hdr_sram_rid;
2019input hdr_sram_wr_en;
2020input hdr_sram_red_clr;
2021
2022input l2clk;
2023
2024output [6:0] sram_hdr_read_data;
2025
2026output [5:0] red_v_blm;
2027output [5:0] red_v_bll;
2028output [5:0] red_v_tll;
2029output [5:0] red_v_tlm;
2030output [5:0] red_v_trm;
2031output [5:0] red_v_trr;
2032output [5:0] red_v_brr;
2033output [5:0] red_v_brm;
2034output red_en_blm;
2035output red_en_bll;
2036output red_en_tlm;
2037output red_en_tll;
2038output red_en_trm;
2039output red_en_trr;
2040output red_en_brr;
2041output red_en_brm;
2042
2043output scan_out;
2044
2045wire [6:0] sram_hdr_read_data;
2046
2047wire scan_out;
2048
2049wire [5:0] red_v_blm;
2050wire [5:0] red_v_bll;
2051wire [5:0] red_v_tll;
2052wire [5:0] red_v_tlm;
2053wire [5:0] red_v_trm;
2054wire [5:0] red_v_trr;
2055wire [5:0] red_v_brr;
2056wire [5:0] red_v_brm;
2057
2058wire red_en_blm;
2059wire red_en_bll;
2060wire red_en_tlm;
2061wire red_en_tll;
2062wire red_en_trm;
2063wire red_en_trr;
2064wire red_en_brr;
2065wire red_en_brm;
2066
2067
2068// scan renames
2069wire siclk = tcu_aclk;
2070wire soclk = tcu_bclk;
2071// end scan
2072
2073wire [7:0] red_id;
2074wire [7:0] red_reg_clk_p;
2075wire [5:0] fuse_red_data;
2076wire fuse_red_enable;
2077
2078wire [5:0] red_data_reg_b0;
2079wire [5:0] red_data_reg_b1;
2080wire [5:0] red_data_reg_b2;
2081wire [5:0] red_data_reg_b3;
2082wire [5:0] red_data_reg_b4;
2083wire [5:0] red_data_reg_b5;
2084wire [5:0] red_data_reg_b6;
2085wire [5:0] red_data_reg_b7;
2086wire [7:0] red_en_reg_bk;
2087
2088wire [7:0] scan_input_bk;
2089wire [7:0] scan_output_bk;
2090
2091//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2092//================================================
2093// l2 clock Domain: Clock headers
2094//================================================
2095wire l1clk_in;
2096wire l1clk_gate;
2097wire l1clk_out;
2098
2099//cl_sc1_l1hdr_8x l1ch_in (
2100// .l2clk (l2clk),
2101// .l1clk (l1clk_in),
2102// .pce (pce),
2103// .pce_ov (tcu_pce_ov),
2104// .se (tcu_se_scancollar_in),
2105// .stop (1'b0)
2106// );
2107
2108
2109//cl_sc1_l1hdr_8x l1ch_out (
2110// .l2clk (l2clk),
2111// .l1clk (l1clk_out),
2112// .pce (pce),
2113// .pce_ov (tcu_pce_ov),
2114// .se (tcu_se_scancollar_out),
2115// .stop (1'b0)
2116// );
2117
2118//cl_sc1_l1hdr_8x l1ch_gate (
2119// .l2clk (l2clk),
2120// .pce (pce),
2121// .l1clk (l1clk_gate),
2122// .se (tcu_scan_en),
2123// .pce_ov (tcu_pce_ov),
2124// .stop (1'b0)
2125// );
2126
2127
2128///////////////////////////////////
2129// decomposed l1hdr for l1clk_in
2130///////////////////////////////////
2131
2132cl_mc1_l1enable_12x l1ch_in_l1en (
2133 .l2clk (l2clk),
2134 .pce (pce),
2135 .pce_ov (tcu_pce_ov),
2136 .l1en (l1clk_in_en)
2137 );
2138
2139cl_mc1_l1driver_12x l1ch_in_l1drvr (
2140 .se (tcu_se_scancollar_in),
2141 .l1en (l1clk_in_en),
2142 .l1clk (l1clk_in),
2143 .l2clk(l2clk)
2144 );
2145///////////////////////////////////
2146// decomposed l1hdr for l1clk_in
2147///////////////////////////////////
2148
2149cl_mc1_l1enable_12x l1ch_out_l1en (
2150 .l2clk (l2clk),
2151 .pce (pce),
2152 .pce_ov (tcu_pce_ov),
2153 .l1en (l1clk_out_en)
2154 );
2155
2156cl_mc1_l1driver_12x l1ch_out_l1drvr (
2157 .se (tcu_se_scancollar_out),
2158 .l1en (l1clk_out_en),
2159 .l1clk (l1clk_out),
2160 .l2clk(l2clk)
2161 );
2162
2163///////////////////////////////////
2164// decomposed l1hdr for l1clk_gate
2165///////////////////////////////////
2166
2167cl_mc1_l1enable_12x l1ch_gate_l1en (
2168 .l2clk (l2clk),
2169 .pce (pce),
2170 .pce_ov (tcu_pce_ov),
2171 .l1en (l1clk_gate_en)
2172 );
2173
2174cl_mc1_l1driver_12x l1ch_gate_l1drvr (
2175 .se (tcu_scan_en),
2176 .l1en (l1clk_gate_en),
2177 .l1clk (l1clk_gate),
2178 .l2clk(l2clk)
2179 );
2180
2181
2182//================================================
2183// l2 clock Domain: Input flops
2184//================================================
2185
2186/****************************************************/
2187wire [5:0] fuse_niu_repair_value;
2188wire fuse_niu_repair_en;
2189wire [2:0] fuse_niu_rid;
2190wire fuse_niu_wen;
2191wire fuse_red_reset;
2192
2193wire dff_rvalue_m_scanin;
2194wire dff_rvalue_m_scanout;
2195wire dff_rid_m_scanin;
2196wire dff_rid_m_scanout;
2197wire dff_wr_en_m_scanin;
2198wire dff_wr_en_m_scanout;
2199wire dff_red_clr_m_scanin;
2200wire dff_red_clr_m_scanout;
2201
2202wire sr10;
2203wire hdr_wr_en;
2204wire hdr_red_clr;
2205
2206 niu1024_msff_ctl_macro__width_7 srhdr_rvalue (
2207 .scan_in (dff_rvalue_m_scanin),
2208 .scan_out (dff_rvalue_m_scanout),
2209 .l1clk (l1clk_in),
2210 .din (hdr_sram_rvalue[6:0]),
2211 .dout ({fuse_niu_repair_value[5:0],fuse_niu_repair_en}),
2212 .siclk(siclk),
2213 .soclk(soclk) );
2214
2215 niu1024_msff_ctl_macro__width_3 srhdr_rid (
2216 .scan_in (dff_rid_m_scanin),
2217 .scan_out (dff_rid_m_scanout),
2218 .l1clk (l1clk_in),
2219 .din (hdr_sram_rid[2:0]),
2220 .dout (fuse_niu_rid[2:0]),
2221 .siclk(siclk),
2222 .soclk(soclk) );
2223
2224 niu1024_msff_ctl_macro__width_1 srhdr_wr_en (
2225 .scan_in (dff_wr_en_m_scanin),
2226 .scan_out (dff_wr_en_m_scanout),
2227 .l1clk (l1clk_in),
2228 .din (hdr_sram_wr_en),
2229 .dout (hdr_wr_en),
2230 .siclk(siclk),
2231 .soclk(soclk) );
2232
2233 niu1024_msff_ctl_macro__width_1 srhdr_red_clr (
2234 .scan_in (dff_red_clr_m_scanin),
2235 .scan_out (dff_red_clr_m_scanout),
2236 .l1clk (l1clk_in),
2237 .din (hdr_sram_red_clr),
2238 .dout (hdr_red_clr),
2239 .siclk(siclk),
2240 .soclk(soclk) );
2241
2242// assign fuse_niu_wen = hdr_wr_en && !tcu_array_wr_inhibit;
2243// assign fuse_red_reset = hdr_red_clr && !tcu_array_wr_inhibit;
2244
2245 niu1024_inv_macro__width_1 r1 (.dout(sr10), .din(tcu_array_wr_inhibit) );
2246 niu1024_and_macro__width_1 r2 (.dout(fuse_niu_wen), .din0(hdr_wr_en), .din1(sr10) );
2247 niu1024_and_macro__width_1 r3 (.dout(fuse_red_reset), .din0(hdr_red_clr), .din1(sr10) );
2248
2249//================================================
2250// l2 clock Domain: output flops
2251//================================================
2252
2253// ------------ repair_ph.a register ----------------
2254wire [5:0] niu_fuse_repair_value;
2255wire niu_fuse_repair_en;
2256
2257wire dff_read_data_m_scanin;
2258wire dff_read_data_m_scanout;
2259
2260 niu1024_msff_ctl_macro__width_7 sram_read_data (
2261 .scan_in (dff_read_data_m_scanin),
2262 .scan_out (dff_read_data_m_scanout),
2263 .l1clk (l1clk_out),
2264 .din ({niu_fuse_repair_value[5:0],niu_fuse_repair_en}),
2265 .dout (sram_hdr_read_data[6:0]),
2266 .siclk(siclk),
2267 .soclk(soclk) );
2268
2269//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2270//////////////////////////////
2271// Redundancy Register //
2272//////////////////////////////
2273 assign red_id[0] = !fuse_niu_rid[2] && !fuse_niu_rid[1] && !fuse_niu_rid[0];
2274 assign red_id[1] = !fuse_niu_rid[2] && !fuse_niu_rid[1] && fuse_niu_rid[0];
2275 assign red_id[2] = !fuse_niu_rid[2] && fuse_niu_rid[1] && !fuse_niu_rid[0];
2276 assign red_id[3] = !fuse_niu_rid[2] && fuse_niu_rid[1] && fuse_niu_rid[0];
2277 assign red_id[4] = fuse_niu_rid[2] && !fuse_niu_rid[1] && !fuse_niu_rid[0];
2278 assign red_id[5] = fuse_niu_rid[2] && !fuse_niu_rid[1] && fuse_niu_rid[0];
2279 assign red_id[6] = fuse_niu_rid[2] && fuse_niu_rid[1] && !fuse_niu_rid[0];
2280 assign red_id[7] = fuse_niu_rid[2] && fuse_niu_rid[1] && fuse_niu_rid[0];
2281
2282 assign red_reg_clk_p[0] = (!l1clk_gate && (red_id[0] && fuse_niu_wen || fuse_red_reset));
2283 assign red_reg_clk_p[1] = (!l1clk_gate && (red_id[1] && fuse_niu_wen || fuse_red_reset));
2284 assign red_reg_clk_p[2] = (!l1clk_gate && (red_id[2] && fuse_niu_wen || fuse_red_reset));
2285 assign red_reg_clk_p[3] = (!l1clk_gate && (red_id[3] && fuse_niu_wen || fuse_red_reset));
2286 assign red_reg_clk_p[4] = (!l1clk_gate && (red_id[4] && fuse_niu_wen || fuse_red_reset));
2287 assign red_reg_clk_p[5] = (!l1clk_gate && (red_id[5] && fuse_niu_wen || fuse_red_reset));
2288 assign red_reg_clk_p[6] = (!l1clk_gate && (red_id[6] && fuse_niu_wen || fuse_red_reset));
2289 assign red_reg_clk_p[7] = (!l1clk_gate && (red_id[7] && fuse_niu_wen || fuse_red_reset));
2290
2291 assign fuse_red_data = fuse_niu_repair_value & {6{!fuse_red_reset}};
2292 assign fuse_red_enable = fuse_niu_repair_en && !fuse_red_reset;
2293
2294//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2295 n2_niu_dp_1024x152s_redreg redreg_brr (
2296 .fuse_red_data (fuse_red_data),
2297 .fuse_red_enable (fuse_red_enable),
2298 .red_reg_clk_p (red_reg_clk_p[0]),
2299 .red_data_reg (red_data_reg_b0),
2300 .red_en_reg (red_en_reg_bk[0]),
2301 .red_value (red_v_brr),
2302 .repair_en (red_en_brr)
2303 );
2304
2305 n2_niu_dp_1024x152s_redreg redreg_brm (
2306 .fuse_red_data (fuse_red_data),
2307 .fuse_red_enable (fuse_red_enable),
2308 .red_reg_clk_p (red_reg_clk_p[1]),
2309 .red_data_reg (red_data_reg_b1),
2310 .red_en_reg (red_en_reg_bk[1]),
2311 .red_value (red_v_brm),
2312 .repair_en (red_en_brm)
2313 );
2314
2315 n2_niu_dp_1024x152s_redreg redreg_bml (
2316 .fuse_red_data (fuse_red_data),
2317 .fuse_red_enable (fuse_red_enable),
2318 .red_reg_clk_p (red_reg_clk_p[2]),
2319 .red_data_reg (red_data_reg_b2),
2320 .red_en_reg (red_en_reg_bk[2]),
2321 .red_value (red_v_blm),
2322 .repair_en (red_en_blm)
2323 );
2324
2325 n2_niu_dp_1024x152s_redreg redreg_bll (
2326 .fuse_red_data (fuse_red_data),
2327 .fuse_red_enable (fuse_red_enable),
2328 .red_reg_clk_p (red_reg_clk_p[3]),
2329 .red_data_reg (red_data_reg_b3),
2330 .red_en_reg (red_en_reg_bk[3]),
2331 .red_value (red_v_bll),
2332 .repair_en (red_en_bll)
2333 );
2334 n2_niu_dp_1024x152s_redreg redreg_trr (
2335 .fuse_red_data (fuse_red_data),
2336 .fuse_red_enable (fuse_red_enable),
2337 .red_reg_clk_p (red_reg_clk_p[4]),
2338 .red_data_reg (red_data_reg_b4),
2339 .red_en_reg (red_en_reg_bk[4]),
2340 .red_value (red_v_trr),
2341 .repair_en (red_en_trr)
2342 );
2343
2344 n2_niu_dp_1024x152s_redreg redreg_tmr (
2345 .fuse_red_data (fuse_red_data),
2346 .fuse_red_enable (fuse_red_enable),
2347 .red_reg_clk_p (red_reg_clk_p[5]),
2348 .red_data_reg (red_data_reg_b5),
2349 .red_en_reg (red_en_reg_bk[5]),
2350 .red_value (red_v_trm),
2351 .repair_en (red_en_trm)
2352 );
2353
2354 n2_niu_dp_1024x152s_redreg redreg_tml (
2355 .fuse_red_data (fuse_red_data),
2356 .fuse_red_enable (fuse_red_enable),
2357 .red_reg_clk_p (red_reg_clk_p[6]),
2358 .red_data_reg (red_data_reg_b6),
2359 .red_en_reg (red_en_reg_bk[6]),
2360 .red_value (red_v_tlm),
2361 .repair_en (red_en_tlm)
2362 );
2363
2364 n2_niu_dp_1024x152s_redreg redreg_tll (
2365 .fuse_red_data (fuse_red_data),
2366 .fuse_red_enable (fuse_red_enable),
2367 .red_reg_clk_p (red_reg_clk_p[7]),
2368 .red_data_reg (red_data_reg_b7),
2369 .red_en_reg (red_en_reg_bk[7]),
2370 .red_value (red_v_tll),
2371 .repair_en (red_en_tll)
2372 );
2373
2374//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2375wire [5:0] niu_fuse_repair_value_b0;
2376wire [5:0] niu_fuse_repair_value_b1;
2377wire [5:0] niu_fuse_repair_value_b2;
2378wire [5:0] niu_fuse_repair_value_b3;
2379wire [5:0] niu_fuse_repair_value_b4;
2380wire [5:0] niu_fuse_repair_value_b5;
2381wire [5:0] niu_fuse_repair_value_b6;
2382wire [5:0] niu_fuse_repair_value_b7;
2383wire [5:0] or_val_b0;
2384wire [5:0] or_val_b1;
2385wire [5:0] or_val_b2;
2386wire [5:0] or_val_b3;
2387wire [5:0] or_val_b4;
2388wire [5:0] or_val_b5;
2389
2390 // assign niu_fuse_repair_value = (red_data_reg_b0 & {6{red_id[0]}}) |
2391 // (red_data_reg_b1 & {6{red_id[1]}}) |
2392 // (red_data_reg_b2 & {6{red_id[2]}}) |
2393 // (red_data_reg_b3 & {6{red_id[3]}}) |
2394 // (red_data_reg_b4 & {6{red_id[4]}}) |
2395 // (red_data_reg_b5 & {6{red_id[5]}}) |
2396 // (red_data_reg_b6 & {6{red_id[6]}}) |
2397 // (red_data_reg_b7 & {6{red_id[7]}});
2398
2399 niu1024_and_macro__width_6 ava0 (.dout(niu_fuse_repair_value_b0), .din0(red_data_reg_b0), .din1({6{red_id[0]}}));
2400 niu1024_and_macro__width_6 ava1 (.dout(niu_fuse_repair_value_b1), .din0(red_data_reg_b1), .din1({6{red_id[1]}}));
2401 niu1024_and_macro__width_6 ava2 (.dout(niu_fuse_repair_value_b2), .din0(red_data_reg_b2), .din1({6{red_id[2]}}));
2402 niu1024_and_macro__width_6 ava3 (.dout(niu_fuse_repair_value_b3), .din0(red_data_reg_b3), .din1({6{red_id[3]}}));
2403 niu1024_and_macro__width_6 ava4 (.dout(niu_fuse_repair_value_b4), .din0(red_data_reg_b4), .din1({6{red_id[4]}}));
2404 niu1024_and_macro__width_6 ava5 (.dout(niu_fuse_repair_value_b5), .din0(red_data_reg_b5), .din1({6{red_id[5]}}));
2405 niu1024_and_macro__width_6 ava6 (.dout(niu_fuse_repair_value_b6), .din0(red_data_reg_b6), .din1({6{red_id[6]}}));
2406 niu1024_and_macro__width_6 ava7 (.dout(niu_fuse_repair_value_b7), .din0(red_data_reg_b7), .din1({6{red_id[7]}}));
2407
2408 niu1024_or_macro__width_6 ova0 (.dout(or_val_b0), .din0(niu_fuse_repair_value_b0), .din1(niu_fuse_repair_value_b1));
2409 niu1024_or_macro__width_6 ova1 (.dout(or_val_b1), .din0(or_val_b0), .din1(niu_fuse_repair_value_b2));
2410 niu1024_or_macro__width_6 ova2 (.dout(or_val_b2), .din0(or_val_b1), .din1(niu_fuse_repair_value_b3));
2411 niu1024_or_macro__width_6 ova3 (.dout(or_val_b3), .din0(or_val_b2), .din1(niu_fuse_repair_value_b4));
2412 niu1024_or_macro__width_6 ova4 (.dout(or_val_b4), .din0(or_val_b3), .din1(niu_fuse_repair_value_b5));
2413 niu1024_or_macro__width_6 ova5 (.dout(or_val_b5), .din0(or_val_b4), .din1(niu_fuse_repair_value_b6));
2414 niu1024_or_macro__width_6 ova6 (.dout(niu_fuse_repair_value), .din0(or_val_b5), .din1(niu_fuse_repair_value_b7));
2415
2416wire [7:0] niu_fuse_repair_en_bk;
2417wire [5:0] or_ena;
2418
2419 // assign niu_fuse_repair_en = (red_en_reg_bk[0] && red_id[0]) ||
2420 // (red_en_reg_bk[1] && red_id[1]) ||
2421 // (red_en_reg_bk[2] && red_id[2]) ||
2422 // (red_en_reg_bk[3] && red_id[3]) ||
2423 // (red_en_reg_bk[4] && red_id[4]) ||
2424 // (red_en_reg_bk[5] && red_id[5]) ||
2425 // (red_en_reg_bk[6] && red_id[6]) ||
2426 // (red_en_reg_bk[7] && red_id[7]);
2427
2428 niu1024_and_macro__width_8 aen0 (.dout(niu_fuse_repair_en_bk), .din0(red_en_reg_bk[7:0]), .din1(red_id[7:0]) );
2429
2430 niu1024_or_macro__width_1 oen0 (.dout(or_ena[0]), .din0(niu_fuse_repair_en_bk[0]),.din1(niu_fuse_repair_en_bk[1]));
2431 niu1024_or_macro__width_1 oen1 (.dout(or_ena[1]), .din0(or_ena[0]), .din1(niu_fuse_repair_en_bk[2]));
2432 niu1024_or_macro__width_1 oen2 (.dout(or_ena[2]), .din0(or_ena[1]), .din1(niu_fuse_repair_en_bk[3]));
2433 niu1024_or_macro__width_1 oen3 (.dout(or_ena[3]), .din0(or_ena[2]), .din1(niu_fuse_repair_en_bk[4]));
2434 niu1024_or_macro__width_1 oen4 (.dout(or_ena[4]), .din0(or_ena[3]), .din1(niu_fuse_repair_en_bk[5]));
2435 niu1024_or_macro__width_1 oen5 (.dout(or_ena[5]), .din0(or_ena[4]), .din1(niu_fuse_repair_en_bk[6]));
2436 niu1024_or_macro__width_1 oen6 (.dout(niu_fuse_repair_en),.din0(or_ena[5]), .din1(niu_fuse_repair_en_bk[7]));
2437
2438// fixscan start:
2439
2440 assign dff_red_clr_m_scanin = scan_in ;
2441 assign dff_wr_en_m_scanin = dff_red_clr_m_scanout ;
2442 assign dff_rid_m_scanin = dff_wr_en_m_scanout ;
2443 assign dff_rvalue_m_scanin = dff_rid_m_scanout ;
2444 assign dff_read_data_m_scanin = dff_rvalue_m_scanout ;
2445 assign scan_out = dff_read_data_m_scanout ;
2446
2447// fixscan end
2448
2449endmodule
2450
2451
2452
2453
2454
2455
2456
2457// any PARAMS parms go into naming of macro
2458
2459module niu1024_msff_ctl_macro__width_7 (
2460 din,
2461 l1clk,
2462 scan_in,
2463 siclk,
2464 soclk,
2465 dout,
2466 scan_out);
2467wire [6:0] fdin;
2468wire [6:1] sout;
2469
2470 input [6:0] din;
2471 input l1clk;
2472 input scan_in;
2473
2474
2475 input siclk;
2476 input soclk;
2477
2478 output [6:0] dout;
2479 output scan_out;
2480assign fdin[6:0] = din[6:0];
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498cl_sc1_msff_4x d0_0 (
2499.l1clk(l1clk),
2500.siclk(siclk),
2501.soclk(soclk),
2502.d(fdin[0]),
2503.si(sout[1]),
2504.so(scan_out),
2505.q(dout[0])
2506);
2507cl_sc1_msff_4x d0_1 (
2508.l1clk(l1clk),
2509.siclk(siclk),
2510.soclk(soclk),
2511.d(fdin[1]),
2512.si(sout[2]),
2513.so(sout[1]),
2514.q(dout[1])
2515);
2516cl_sc1_msff_4x d0_2 (
2517.l1clk(l1clk),
2518.siclk(siclk),
2519.soclk(soclk),
2520.d(fdin[2]),
2521.si(sout[3]),
2522.so(sout[2]),
2523.q(dout[2])
2524);
2525cl_sc1_msff_4x d0_3 (
2526.l1clk(l1clk),
2527.siclk(siclk),
2528.soclk(soclk),
2529.d(fdin[3]),
2530.si(sout[4]),
2531.so(sout[3]),
2532.q(dout[3])
2533);
2534cl_sc1_msff_4x d0_4 (
2535.l1clk(l1clk),
2536.siclk(siclk),
2537.soclk(soclk),
2538.d(fdin[4]),
2539.si(sout[5]),
2540.so(sout[4]),
2541.q(dout[4])
2542);
2543cl_sc1_msff_4x d0_5 (
2544.l1clk(l1clk),
2545.siclk(siclk),
2546.soclk(soclk),
2547.d(fdin[5]),
2548.si(sout[6]),
2549.so(sout[5]),
2550.q(dout[5])
2551);
2552cl_sc1_msff_4x d0_6 (
2553.l1clk(l1clk),
2554.siclk(siclk),
2555.soclk(soclk),
2556.d(fdin[6]),
2557.si(scan_in),
2558.so(sout[6]),
2559.q(dout[6])
2560);
2561
2562
2563
2564
2565endmodule
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579// any PARAMS parms go into naming of macro
2580
2581module niu1024_msff_ctl_macro__width_3 (
2582 din,
2583 l1clk,
2584 scan_in,
2585 siclk,
2586 soclk,
2587 dout,
2588 scan_out);
2589wire [2:0] fdin;
2590wire [2:1] sout;
2591
2592 input [2:0] din;
2593 input l1clk;
2594 input scan_in;
2595
2596
2597 input siclk;
2598 input soclk;
2599
2600 output [2:0] dout;
2601 output scan_out;
2602assign fdin[2:0] = din[2:0];
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620cl_sc1_msff_4x d0_0 (
2621.l1clk(l1clk),
2622.siclk(siclk),
2623.soclk(soclk),
2624.d(fdin[0]),
2625.si(sout[1]),
2626.so(scan_out),
2627.q(dout[0])
2628);
2629cl_sc1_msff_4x d0_1 (
2630.l1clk(l1clk),
2631.siclk(siclk),
2632.soclk(soclk),
2633.d(fdin[1]),
2634.si(sout[2]),
2635.so(sout[1]),
2636.q(dout[1])
2637);
2638cl_sc1_msff_4x d0_2 (
2639.l1clk(l1clk),
2640.siclk(siclk),
2641.soclk(soclk),
2642.d(fdin[2]),
2643.si(scan_in),
2644.so(sout[2]),
2645.q(dout[2])
2646);
2647
2648
2649
2650
2651endmodule
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665// any PARAMS parms go into naming of macro
2666
2667module niu1024_msff_ctl_macro__width_1 (
2668 din,
2669 l1clk,
2670 scan_in,
2671 siclk,
2672 soclk,
2673 dout,
2674 scan_out);
2675wire [0:0] fdin;
2676
2677 input [0:0] din;
2678 input l1clk;
2679 input scan_in;
2680
2681
2682 input siclk;
2683 input soclk;
2684
2685 output [0:0] dout;
2686 output scan_out;
2687assign fdin[0:0] = din[0:0];
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705cl_sc1_msff_4x d0_0 (
2706.l1clk(l1clk),
2707.siclk(siclk),
2708.soclk(soclk),
2709.d(fdin[0]),
2710.si(scan_in),
2711.so(scan_out),
2712.q(dout[0])
2713);
2714
2715
2716
2717
2718endmodule
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729module n2_niu_dp_1024x152s_redreg (
2730 fuse_red_data,
2731 fuse_red_enable,
2732 red_reg_clk_p,
2733 red_data_reg,
2734 red_en_reg,
2735 red_value,
2736 repair_en);
2737
2738input [5:0] fuse_red_data;
2739input fuse_red_enable;
2740input red_reg_clk_p;
2741
2742output [5:0] red_data_reg; // to repair output
2743output red_en_reg;
2744output [5:0] red_value; // to subbank
2745output repair_en;
2746
2747wire [5:0] red_value;
2748wire repair_en;
2749
2750wire [5:0] red_data_reg;
2751wire red_en_reg;
2752
2753wire red_en_reg1;
2754
2755
2756//////////////////////////////
2757// Redundancy Register //
2758//////////////////////////////
2759
2760// `ifdef NOINITMEM
2761// `else
2762// // Initialize the arrays.
2763// initial begin
2764// red_data_reg = {6{1'h0}};
2765// red_en_reg = 1'h0;
2766// end
2767// `endif
2768
2769// always @(posedge red_reg_clk_p) begin
2770// red_data_reg <= fuse_red_data;
2771// red_en_reg <= fuse_red_enable;
2772// end
2773
2774cl_sc1_msff_4x e_r0 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_enable), .q(red_en_reg));
2775cl_sc1_msff_4x e_r1 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_enable), .q(red_en_reg1));
2776
2777cl_sc1_msff_4x d_r0 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[0]),.q(red_data_reg[0]));
2778cl_sc1_msff_4x d_r1 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[1]),.q(red_data_reg[1]));
2779cl_sc1_msff_4x d_r2 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[2]),.q(red_data_reg[2]));
2780cl_sc1_msff_4x d_r3 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[3]),.q(red_data_reg[3]));
2781cl_sc1_msff_4x d_r4 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[4]),.q(red_data_reg[4]));
2782cl_sc1_msff_4x d_r5 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[5]),.q(red_data_reg[5]));
2783
2784// assign repair_en = red_en_reg;
2785
2786 niu1024_and_macro__width_1 a0 (.dout(repair_en), .din0(red_en_reg), .din1(red_en_reg1));
2787
2788 assign red_value = red_data_reg[5:0];
2789
2790endmodule
2791
2792
2793
2794//
2795// and macro for ports = 2,3,4
2796//
2797//
2798
2799
2800
2801
2802
2803module niu1024_and_macro__width_6 (
2804 din0,
2805 din1,
2806 dout);
2807wire [5:0] nandout;
2808
2809 input [5:0] din0;
2810 input [5:0] din1;
2811 output [5:0] dout;
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821cl_u1_nand2_1x d0_0 (
2822.in0(din0[0]),
2823.in1(din1[0]),
2824.out(nandout[0])
2825);
2826
2827cl_u1_nand2_1x d0_1 (
2828.in0(din0[1]),
2829.in1(din1[1]),
2830.out(nandout[1])
2831);
2832
2833cl_u1_nand2_1x d0_2 (
2834.in0(din0[2]),
2835.in1(din1[2]),
2836.out(nandout[2])
2837);
2838
2839cl_u1_nand2_1x d0_3 (
2840.in0(din0[3]),
2841.in1(din1[3]),
2842.out(nandout[3])
2843);
2844
2845cl_u1_nand2_1x d0_4 (
2846.in0(din0[4]),
2847.in1(din1[4]),
2848.out(nandout[4])
2849);
2850
2851cl_u1_nand2_1x d0_5 (
2852.in0(din0[5]),
2853.in1(din1[5]),
2854.out(nandout[5])
2855);
2856
2857cl_u1_inv_1x d1_0 (
2858.in(nandout[0]),
2859.out(dout[0])
2860);
2861cl_u1_inv_1x d1_1 (
2862.in(nandout[1]),
2863.out(dout[1])
2864);
2865cl_u1_inv_1x d1_2 (
2866.in(nandout[2]),
2867.out(dout[2])
2868);
2869cl_u1_inv_1x d1_3 (
2870.in(nandout[3]),
2871.out(dout[3])
2872);
2873cl_u1_inv_1x d1_4 (
2874.in(nandout[4]),
2875.out(dout[4])
2876);
2877cl_u1_inv_1x d1_5 (
2878.in(nandout[5]),
2879.out(dout[5])
2880);
2881
2882
2883
2884
2885endmodule
2886
2887
2888
2889
2890
2891//
2892// or macro for ports = 2,3
2893//
2894//
2895
2896
2897
2898
2899
2900module niu1024_or_macro__width_6 (
2901 din0,
2902 din1,
2903 dout);
2904wire [5:0] norout;
2905
2906 input [5:0] din0;
2907 input [5:0] din1;
2908 output [5:0] dout;
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918cl_u1_nor2_1x d0_0 (
2919.in0(din0[0]),
2920.in1(din1[0]),
2921.out(norout[0])
2922);
2923
2924cl_u1_nor2_1x d0_1 (
2925.in0(din0[1]),
2926.in1(din1[1]),
2927.out(norout[1])
2928);
2929
2930cl_u1_nor2_1x d0_2 (
2931.in0(din0[2]),
2932.in1(din1[2]),
2933.out(norout[2])
2934);
2935
2936cl_u1_nor2_1x d0_3 (
2937.in0(din0[3]),
2938.in1(din1[3]),
2939.out(norout[3])
2940);
2941
2942cl_u1_nor2_1x d0_4 (
2943.in0(din0[4]),
2944.in1(din1[4]),
2945.out(norout[4])
2946);
2947
2948cl_u1_nor2_1x d0_5 (
2949.in0(din0[5]),
2950.in1(din1[5]),
2951.out(norout[5])
2952);
2953
2954cl_u1_inv_1x d1_0 (
2955.in(norout[0]),
2956.out(dout[0])
2957);
2958cl_u1_inv_1x d1_1 (
2959.in(norout[1]),
2960.out(dout[1])
2961);
2962cl_u1_inv_1x d1_2 (
2963.in(norout[2]),
2964.out(dout[2])
2965);
2966cl_u1_inv_1x d1_3 (
2967.in(norout[3]),
2968.out(dout[3])
2969);
2970cl_u1_inv_1x d1_4 (
2971.in(norout[4]),
2972.out(dout[4])
2973);
2974cl_u1_inv_1x d1_5 (
2975.in(norout[5]),
2976.out(dout[5])
2977);
2978
2979
2980
2981
2982endmodule
2983
2984
2985
2986
2987
2988//
2989// and macro for ports = 2,3,4
2990//
2991//
2992
2993
2994
2995
2996
2997module niu1024_and_macro__width_8 (
2998 din0,
2999 din1,
3000 dout);
3001wire [7:0] nandout;
3002
3003 input [7:0] din0;
3004 input [7:0] din1;
3005 output [7:0] dout;
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015cl_u1_nand2_1x d0_0 (
3016.in0(din0[0]),
3017.in1(din1[0]),
3018.out(nandout[0])
3019);
3020
3021cl_u1_nand2_1x d0_1 (
3022.in0(din0[1]),
3023.in1(din1[1]),
3024.out(nandout[1])
3025);
3026
3027cl_u1_nand2_1x d0_2 (
3028.in0(din0[2]),
3029.in1(din1[2]),
3030.out(nandout[2])
3031);
3032
3033cl_u1_nand2_1x d0_3 (
3034.in0(din0[3]),
3035.in1(din1[3]),
3036.out(nandout[3])
3037);
3038
3039cl_u1_nand2_1x d0_4 (
3040.in0(din0[4]),
3041.in1(din1[4]),
3042.out(nandout[4])
3043);
3044
3045cl_u1_nand2_1x d0_5 (
3046.in0(din0[5]),
3047.in1(din1[5]),
3048.out(nandout[5])
3049);
3050
3051cl_u1_nand2_1x d0_6 (
3052.in0(din0[6]),
3053.in1(din1[6]),
3054.out(nandout[6])
3055);
3056
3057cl_u1_nand2_1x d0_7 (
3058.in0(din0[7]),
3059.in1(din1[7]),
3060.out(nandout[7])
3061);
3062
3063cl_u1_inv_1x d1_0 (
3064.in(nandout[0]),
3065.out(dout[0])
3066);
3067cl_u1_inv_1x d1_1 (
3068.in(nandout[1]),
3069.out(dout[1])
3070);
3071cl_u1_inv_1x d1_2 (
3072.in(nandout[2]),
3073.out(dout[2])
3074);
3075cl_u1_inv_1x d1_3 (
3076.in(nandout[3]),
3077.out(dout[3])
3078);
3079cl_u1_inv_1x d1_4 (
3080.in(nandout[4]),
3081.out(dout[4])
3082);
3083cl_u1_inv_1x d1_5 (
3084.in(nandout[5]),
3085.out(dout[5])
3086);
3087cl_u1_inv_1x d1_6 (
3088.in(nandout[6]),
3089.out(dout[6])
3090);
3091cl_u1_inv_1x d1_7 (
3092.in(nandout[7]),
3093.out(dout[7])
3094);
3095
3096
3097
3098
3099endmodule
3100
3101
3102
3103
3104
3105//
3106// or macro for ports = 2,3
3107//
3108//
3109
3110
3111
3112
3113
3114module niu1024_or_macro__width_1 (
3115 din0,
3116 din1,
3117 dout);
3118wire [0:0] norout;
3119
3120 input [0:0] din0;
3121 input [0:0] din1;
3122 output [0:0] dout;
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132cl_u1_nor2_1x d0_0 (
3133.in0(din0[0]),
3134.in1(din1[0]),
3135.out(norout[0])
3136);
3137
3138cl_u1_inv_1x d1_0 (
3139.in(norout[0]),
3140.out(dout[0])
3141);
3142
3143
3144
3145
3146endmodule
3147
3148
3149
3150
Full OpenSPARC design & verification tarball including full HDL.