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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / libs / n2sram / dp / n2_niu_dp_512x152s_cust_l / n2_niu_dp_512x152s_cust / rtl / n2_niu_dp_512x152s_cust.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: n2_niu_dp_512x152s_cust.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module n2_niu_dp_512x152s_cust (
36 reset,
37 tcu_aclk,
38 tcu_bclk,
39 tcu_scan_en,
40 tcu_se_scancollar_in,
41 tcu_se_scancollar_out,
42 tcu_pce_ov,
43 pce,
44 tcu_array_wr_inhibit,
45 scan_in,
46 scan_out,
47 hdr_sram_rvalue,
48 hdr_sram_rid,
49 hdr_sram_wr_en,
50 hdr_sram_red_clr,
51 sram_hdr_read_data,
52 wr_adr,
53 wr_en,
54 rd_adr,
55 rd_en,
56 din,
57 dout,
58 l2clk_2x,
59 l2clk);
60wire array_scan_out;
61
62
63input reset;
64input tcu_aclk;
65input tcu_bclk;
66input tcu_scan_en;
67input tcu_se_scancollar_in;
68input tcu_se_scancollar_out;
69input tcu_pce_ov;
70input pce;
71input tcu_array_wr_inhibit;
72input scan_in;
73output scan_out;
74
75input [6:0] hdr_sram_rvalue;
76input [1:0] hdr_sram_rid;
77input hdr_sram_wr_en;
78input hdr_sram_red_clr;
79output [6:0] sram_hdr_read_data;
80
81input [8:0] wr_adr;
82input wr_en;
83input [8:0] rd_adr;
84input rd_en;
85input [151:0] din;
86output [151:0] dout;
87input l2clk_2x;
88input l2clk;
89
90wire [151:0] dout;
91wire [6:0] sram_hdr_read_data;
92wire [6:0] hdr_sram_rvalue;
93wire [1:0] hdr_sram_rid;
94wire [8:0] wr_adr;
95wire [8:0] rd_adr;
96wire [151:0] din;
97
98
99
100
101
102
103
104wire [5:0] red_value_b0; // to subbank
105wire [5:0] red_value_b1;
106wire [5:0] red_value_b2;
107wire [5:0] red_value_b3;
108wire repair_en_b0;
109wire repair_en_b1;
110wire repair_en_b2;
111wire repair_en_b3;
112
113wire scan_in_repair;
114wire scan_out_repair;
115
116 n2_niu_dp_512x152s_bank niu_dp_512x152s_bank_0 (
117 .reset (reset),
118 .tcu_aclk (tcu_aclk),
119 .tcu_bclk (tcu_bclk),
120 .pce (pce),
121 .tcu_pce_ov (tcu_pce_ov),
122 .tcu_scan_en (tcu_scan_en),
123 .tcu_se_scancollar_in (tcu_se_scancollar_in),
124 .tcu_array_wr_inhibit (tcu_array_wr_inhibit),
125 .l2clk (l2clk),
126 .l2clk_2x (l2clk_2x),
127 .wr_adr (wr_adr),
128 .wr_en (wr_en),
129 .rd_adr (rd_adr),
130 .rd_en (rd_en),
131 .din (din),
132 .scan_in (scan_in),
133 .scan_out (array_scan_out),
134 .red_v_br (red_value_b0),
135 .red_v_bl (red_value_b1),
136 .red_v_tr (red_value_b2),
137 .red_v_tl (red_value_b3),
138 .red_en_br (repair_en_b0),
139 .red_en_bl (repair_en_b1),
140 .red_en_tr (repair_en_b2),
141 .red_en_tl (repair_en_b3),
142 .dout (dout)
143 );
144
145
146 n2_niu_dp_512x152s_repair niu_dp_512x152s_repair_0 (
147 .aclk (tcu_aclk),
148 .bclk (tcu_bclk),
149 .pce (pce),
150 .tcu_pce_ov (tcu_pce_ov),
151 .tcu_scan_en (tcu_scan_en),
152 .tcu_se_scancollar_in (tcu_se_scancollar_in),
153 .tcu_se_scancollar_out (tcu_se_scancollar_out),
154 .tcu_array_wr_inhibit (tcu_array_wr_inhibit),
155 .scanin_red (array_scan_out),
156 .hdr_sram_rvalue (hdr_sram_rvalue),
157 .hdr_sram_rid (hdr_sram_rid),
158 .hdr_sram_wr_en (hdr_sram_wr_en),
159 .hdr_sram_red_clr (hdr_sram_red_clr),
160 .l2clk (l2clk),
161 .sram_hdr_read_data (sram_hdr_read_data),
162 .red_v_br (red_value_b0), // to subbank
163 .red_v_bl (red_value_b1),
164 .red_v_tr (red_value_b2),
165 .red_v_tl (red_value_b3),
166 .red_en_br (repair_en_b0),
167 .red_en_bl (repair_en_b1),
168 .red_en_tr (repair_en_b2),
169 .red_en_tl (repair_en_b3),
170 .scanout_red (scan_out)
171 );
172
173
174
175
176endmodule
177
178
179
180
181module n2_niu_dp_512x152s_bank (
182 reset,
183 din,
184 wr_adr,
185 rd_adr,
186 rd_en,
187 wr_en,
188 tcu_aclk,
189 tcu_bclk,
190 pce,
191 tcu_pce_ov,
192 tcu_scan_en,
193 tcu_se_scancollar_in,
194 tcu_array_wr_inhibit,
195 l2clk,
196 l2clk_2x,
197 scan_in,
198 red_v_br,
199 red_v_bl,
200 red_v_tr,
201 red_v_tl,
202 red_en_br,
203 red_en_bl,
204 red_en_tr,
205 red_en_tl,
206 dout,
207 scan_out);
208wire l1clk_in_en;
209wire l1clk_in;
210wire l1clk_gate_en;
211wire l1clk_gate;
212wire [8:0] dff_wr_adr_m_scanout;
213wire [8:0] dff_rd_adr_m_scanout;
214wire dff_rd_en_m_scanin;
215wire dff_rd_en_m_scanout;
216wire dff_wr_en_m_scanin;
217wire dff_wr_en_m_scanout;
218wire test_mode;
219wire dff_test_mode_scanin;
220wire dff_test_mode_scanout;
221wire test_clk;
222wire dff_test_clk_scanin;
223wire dff_test_clk_scanout;
224wire do_A_read_2x_a;
225wire do_B_write_2x_a;
226wire [151:0] wdata_2x_b;
227
228
229input reset;
230input [151:0] din;
231input [8:0] wr_adr;
232input [8:0] rd_adr;
233input rd_en;
234input wr_en;
235input tcu_aclk;
236input tcu_bclk;
237input pce;
238input tcu_pce_ov;
239input tcu_scan_en;
240input tcu_se_scancollar_in;
241input tcu_array_wr_inhibit;
242input l2clk;
243input l2clk_2x;
244input scan_in;
245
246input [5:0] red_v_br;
247input [5:0] red_v_bl;
248input [5:0] red_v_tr;
249input [5:0] red_v_tl;
250input red_en_br;
251input red_en_bl;
252input red_en_tr;
253input red_en_tl;
254
255output [151:0] dout;
256output scan_out;
257
258
259
260wire [5:0] red_value_b0;
261wire [5:0] red_value_b1;
262wire [5:0] red_value_b2;
263wire [5:0] red_value_b3;
264wire [3:0] repair_en_bk;
265wire [151:0] dout; //
266
267
268// scan renames
269// end scan
270
271wire rd_en_a;
272wire wr_en_a;
273wire [151:0] wdata_b;
274wire [8:0] addr_a;
275
276wire wcs_a;
277
278wire [37:0] din_br;
279wire [37:0] din_tr;
280wire [37:0] din_bl;
281wire [37:0] din_tl;
282
283wire [151:0] rd_dout;
284
285wire [3:0] rd_en_column;
286wire [3:0] wt_en_column;
287
288wire [37:0] ary_rdout_br;
289wire [37:0] ary_rdout_tr;
290wire [37:0] ary_rdout_bl;
291wire [37:0] ary_rdout_tl;
292
293wire siclk, soclk;
294assign siclk = tcu_aclk;
295assign soclk = tcu_bclk;
296
297
298//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
299//================================================
300// l2 clock Domain: Clock headers
301//================================================
302//cl_sc1_l1hdr_8x l1ch_in (
303// .l1clk (l1clk_in),
304// .l2clk (l2clk),
305// .se (tcu_se_scancollar_in),
306// .pce (pce),
307// .pce_ov (tcu_pce_ov),
308// .stop (1'b0)
309// );
310
311//cl_sc1_l1hdr_8x l1ch_gate (
312// .l1clk (l1clk_gate),
313// .l2clk (l2clk),
314// .se (tcu_scan_en),
315// .pce (pce),
316// .pce_ov (tcu_pce_ov),
317// .stop (1'b0)
318// );
319
320///////////////////////////////////
321// decomposed l1hdr for l1clk_in
322///////////////////////////////////
323
324cl_mc1_l1enable_12x l1ch_in_l1en (
325 .l2clk (l2clk),
326 .pce (pce),
327 .pce_ov (tcu_pce_ov),
328 .l1en (l1clk_in_en)
329 );
330
331cl_mc1_l1driver_12x l1ch_in_l1drvr (
332 .se (tcu_se_scancollar_in),
333 .l1en (l1clk_in_en),
334 .l1clk (l1clk_in),
335 .l2clk(l2clk)
336 );
337
338///////////////////////////////////
339// decomposed l1hdr for l1clk_gate
340///////////////////////////////////
341
342cl_mc1_l1enable_12x l1ch_gate_l1en (
343 .l2clk (l2clk),
344 .pce (pce),
345 .pce_ov (tcu_pce_ov),
346 .l1en (l1clk_gate_en)
347 );
348
349cl_mc1_l1driver_12x l1ch_gate_l1drvr (
350 .se (tcu_scan_en),
351 .l1en (l1clk_gate_en),
352 .l1clk (l1clk_gate),
353 .l2clk(l2clk)
354 );
355
356
357
358//================================================
359// l2 clock Domain: Input flops
360//================================================
361
362// ------------ controls_ph.a register --------------
363/****************************************************
364//reg [8:0] rd_adr_m;
365//reg [8:0] wr_adr_m;
366//reg rd_en_m;
367//reg wr_en_m;
368//
369// always @(posedge l1clk_in) begin
370// rd_adr_m <= rd_adr;
371// wr_adr_m <= wr_adr;
372// rd_en_m <= rd_en;
373// wr_en_m <= wr_en;
374// end
375
376*****************************************************/
377wire [8:0] rd_adr_m;
378wire [8:0] wr_adr_m;
379wire rd_en_m;
380wire wr_en_m;
381wire reset_l;
382wire [151:0] din_m;
383wire [8:0] dff_wr_adr_m_scanin;
384wire [8:0] dff_rd_adr_m_scanin;
385
386assign reset_l = ~reset;
387
388// msff_ctl_macro dff_ctrls_m (width=(9*2+2), clr_=1) (
389// .scan_in (scan_in),
390// .scan_out (dff_ctrls_m_scanout),
391// .clr_ (reset_l),
392// .l1clk (l1clk_in),
393// .din ({rd_en, wr_en, rd_adr[8:0], wr_adr[8:0]}),
394// .dout ({rd_en_m,wr_en_m,rd_adr_m[8:0],wr_adr_m[8:0]}) );
395
396
397 cl_sc1_msff_syrst_4x wr_adr_m00 (.d(wr_adr[0]), .si(dff_wr_adr_m_scanin[0]), .q(wr_adr_m[0]), .so(dff_wr_adr_m_scanout[0]),
398 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
399 cl_sc1_msff_syrst_4x wr_adr_m01 (.d(wr_adr[1]), .si(dff_wr_adr_m_scanin[1]), .q(wr_adr_m[1]), .so(dff_wr_adr_m_scanout[1]),
400 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
401 cl_sc1_msff_syrst_4x wr_adr_m02 (.d(wr_adr[2]), .si(dff_wr_adr_m_scanin[2]), .q(wr_adr_m[2]), .so(dff_wr_adr_m_scanout[2]),
402 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
403 cl_sc1_msff_syrst_4x wr_adr_m03 (.d(wr_adr[3]), .si(dff_wr_adr_m_scanin[3]), .q(wr_adr_m[3]), .so(dff_wr_adr_m_scanout[3]),
404 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
405 cl_sc1_msff_syrst_4x wr_adr_m04 (.d(wr_adr[4]), .si(dff_wr_adr_m_scanin[4]), .q(wr_adr_m[4]), .so(dff_wr_adr_m_scanout[4]),
406 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
407 cl_sc1_msff_syrst_4x wr_adr_m05 (.d(wr_adr[5]), .si(dff_wr_adr_m_scanin[5]), .q(wr_adr_m[5]), .so(dff_wr_adr_m_scanout[5]),
408 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
409 cl_sc1_msff_syrst_4x wr_adr_m06 (.d(wr_adr[6]), .si(dff_wr_adr_m_scanin[6]), .q(wr_adr_m[6]), .so(dff_wr_adr_m_scanout[6]),
410 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
411 cl_sc1_msff_syrst_4x wr_adr_m07 (.d(wr_adr[7]), .si(dff_wr_adr_m_scanin[7]), .q(wr_adr_m[7]), .so(dff_wr_adr_m_scanout[7]),
412 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
413 cl_sc1_msff_syrst_4x wr_adr_m08 (.d(wr_adr[8]), .si(dff_wr_adr_m_scanin[8]), .q(wr_adr_m[8]), .so(dff_wr_adr_m_scanout[8]),
414 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
415
416 cl_sc1_msff_syrst_4x rd_adr_m00 (.d(rd_adr[0]), .si(dff_rd_adr_m_scanin[0]), .q(rd_adr_m[0]), .so(dff_rd_adr_m_scanout[0]),
417 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
418 cl_sc1_msff_syrst_4x rd_adr_m01 (.d(rd_adr[1]), .si(dff_rd_adr_m_scanin[1]), .q(rd_adr_m[1]), .so(dff_rd_adr_m_scanout[1]),
419 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
420 cl_sc1_msff_syrst_4x rd_adr_m02 (.d(rd_adr[2]), .si(dff_rd_adr_m_scanin[2]), .q(rd_adr_m[2]), .so(dff_rd_adr_m_scanout[2]),
421 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
422 cl_sc1_msff_syrst_4x rd_adr_m03 (.d(rd_adr[3]), .si(dff_rd_adr_m_scanin[3]), .q(rd_adr_m[3]), .so(dff_rd_adr_m_scanout[3]),
423 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
424 cl_sc1_msff_syrst_4x rd_adr_m04 (.d(rd_adr[4]), .si(dff_rd_adr_m_scanin[4]), .q(rd_adr_m[4]), .so(dff_rd_adr_m_scanout[4]),
425 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
426 cl_sc1_msff_syrst_4x rd_adr_m05 (.d(rd_adr[5]), .si(dff_rd_adr_m_scanin[5]), .q(rd_adr_m[5]), .so(dff_rd_adr_m_scanout[5]),
427 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
428 cl_sc1_msff_syrst_4x rd_adr_m06 (.d(rd_adr[6]), .si(dff_rd_adr_m_scanin[6]), .q(rd_adr_m[6]), .so(dff_rd_adr_m_scanout[6]),
429 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
430 cl_sc1_msff_syrst_4x rd_adr_m07 (.d(rd_adr[7]), .si(dff_rd_adr_m_scanin[7]), .q(rd_adr_m[7]), .so(dff_rd_adr_m_scanout[7]),
431 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
432 cl_sc1_msff_syrst_4x rd_adr_m08 (.d(rd_adr[8]), .si(dff_rd_adr_m_scanin[8]), .q(rd_adr_m[8]), .so(dff_rd_adr_m_scanout[8]),
433 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
434
435 cl_sc1_msff_syrst_4x rd_en_m0 (.d(rd_en), .si(dff_rd_en_m_scanin), .q(rd_en_m), .so(dff_rd_en_m_scanout),
436 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
437 cl_sc1_msff_syrst_4x wr_en_m0 (.d(wr_en), .si(dff_wr_en_m_scanin), .q(wr_en_m), .so(dff_wr_en_m_scanout),
438 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
439
440// ------------ write_data_ph.a register ------------
441//
442//reg [151:0] din_m;
443//
444//
445// always @(posedge l1clk_in) begin
446// din_m <= din;
447// end
448
449// msff_ctl_macro dff_wdata_m (width=152, clr_=1) (
450// .scan_in (dff_ctrls_m_scanout),
451// .scan_out (dff_wdata_m_scanout),
452// .clr_ (reset_l),
453// .l1clk (l1clk_in),
454// .din (din[151:0]),
455// .dout (din_m[151:0]) );
456
457
458wire [151:0] dff_wdata_m_scanin, dff_wdata_m_scanout;
459
460 cl_sc1_msff_syrst_4x din_m000 (.d(din[0]), .si(dff_wdata_m_scanin[0]), .q(din_m[0]), .so(dff_wdata_m_scanout[0]),
461 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
462 cl_sc1_msff_syrst_4x din_m001 (.d(din[1]), .si(dff_wdata_m_scanin[1]), .q(din_m[1]), .so(dff_wdata_m_scanout[1]),
463 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
464 cl_sc1_msff_syrst_4x din_m002 (.d(din[2]), .si(dff_wdata_m_scanin[2]), .q(din_m[2]), .so(dff_wdata_m_scanout[2]),
465 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
466 cl_sc1_msff_syrst_4x din_m003 (.d(din[3]), .si(dff_wdata_m_scanin[3]), .q(din_m[3]), .so(dff_wdata_m_scanout[3]),
467 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
468 cl_sc1_msff_syrst_4x din_m004 (.d(din[4]), .si(dff_wdata_m_scanin[4]), .q(din_m[4]), .so(dff_wdata_m_scanout[4]),
469 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
470 cl_sc1_msff_syrst_4x din_m005 (.d(din[5]), .si(dff_wdata_m_scanin[5]), .q(din_m[5]), .so(dff_wdata_m_scanout[5]),
471 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
472 cl_sc1_msff_syrst_4x din_m006 (.d(din[6]), .si(dff_wdata_m_scanin[6]), .q(din_m[6]), .so(dff_wdata_m_scanout[6]),
473 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
474 cl_sc1_msff_syrst_4x din_m007 (.d(din[7]), .si(dff_wdata_m_scanin[7]), .q(din_m[7]), .so(dff_wdata_m_scanout[7]),
475 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
476 cl_sc1_msff_syrst_4x din_m008 (.d(din[8]), .si(dff_wdata_m_scanin[8]), .q(din_m[8]), .so(dff_wdata_m_scanout[8]),
477 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
478 cl_sc1_msff_syrst_4x din_m009 (.d(din[9]), .si(dff_wdata_m_scanin[9]), .q(din_m[9]), .so(dff_wdata_m_scanout[9]),
479 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
480
481 cl_sc1_msff_syrst_4x din_m010 (.d(din[10]), .si(dff_wdata_m_scanin[10]), .q(din_m[10]), .so(dff_wdata_m_scanout[10]),
482 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
483 cl_sc1_msff_syrst_4x din_m011 (.d(din[11]), .si(dff_wdata_m_scanin[11]), .q(din_m[11]), .so(dff_wdata_m_scanout[11]),
484 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
485 cl_sc1_msff_syrst_4x din_m012 (.d(din[12]), .si(dff_wdata_m_scanin[12]), .q(din_m[12]), .so(dff_wdata_m_scanout[12]),
486 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
487 cl_sc1_msff_syrst_4x din_m013 (.d(din[13]), .si(dff_wdata_m_scanin[13]), .q(din_m[13]), .so(dff_wdata_m_scanout[13]),
488 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
489 cl_sc1_msff_syrst_4x din_m014 (.d(din[14]), .si(dff_wdata_m_scanin[14]), .q(din_m[14]), .so(dff_wdata_m_scanout[14]),
490 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
491 cl_sc1_msff_syrst_4x din_m015 (.d(din[15]), .si(dff_wdata_m_scanin[15]), .q(din_m[15]), .so(dff_wdata_m_scanout[15]),
492 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
493 cl_sc1_msff_syrst_4x din_m016 (.d(din[16]), .si(dff_wdata_m_scanin[16]), .q(din_m[16]), .so(dff_wdata_m_scanout[16]),
494 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
495 cl_sc1_msff_syrst_4x din_m017 (.d(din[17]), .si(dff_wdata_m_scanin[17]), .q(din_m[17]), .so(dff_wdata_m_scanout[17]),
496 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
497 cl_sc1_msff_syrst_4x din_m018 (.d(din[18]), .si(dff_wdata_m_scanin[18]), .q(din_m[18]), .so(dff_wdata_m_scanout[18]),
498 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
499 cl_sc1_msff_syrst_4x din_m019 (.d(din[19]), .si(dff_wdata_m_scanin[19]), .q(din_m[19]), .so(dff_wdata_m_scanout[19]),
500 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
501
502 cl_sc1_msff_syrst_4x din_m020 (.d(din[20]), .si(dff_wdata_m_scanin[20]), .q(din_m[20]), .so(dff_wdata_m_scanout[20]),
503 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
504 cl_sc1_msff_syrst_4x din_m021 (.d(din[21]), .si(dff_wdata_m_scanin[21]), .q(din_m[21]), .so(dff_wdata_m_scanout[21]),
505 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
506 cl_sc1_msff_syrst_4x din_m022 (.d(din[22]), .si(dff_wdata_m_scanin[22]), .q(din_m[22]), .so(dff_wdata_m_scanout[22]),
507 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
508 cl_sc1_msff_syrst_4x din_m023 (.d(din[23]), .si(dff_wdata_m_scanin[23]), .q(din_m[23]), .so(dff_wdata_m_scanout[23]),
509 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
510 cl_sc1_msff_syrst_4x din_m024 (.d(din[24]), .si(dff_wdata_m_scanin[24]), .q(din_m[24]), .so(dff_wdata_m_scanout[24]),
511 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
512 cl_sc1_msff_syrst_4x din_m025 (.d(din[25]), .si(dff_wdata_m_scanin[25]), .q(din_m[25]), .so(dff_wdata_m_scanout[25]),
513 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
514 cl_sc1_msff_syrst_4x din_m026 (.d(din[26]), .si(dff_wdata_m_scanin[26]), .q(din_m[26]), .so(dff_wdata_m_scanout[26]),
515 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
516 cl_sc1_msff_syrst_4x din_m027 (.d(din[27]), .si(dff_wdata_m_scanin[27]), .q(din_m[27]), .so(dff_wdata_m_scanout[27]),
517 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
518 cl_sc1_msff_syrst_4x din_m028 (.d(din[28]), .si(dff_wdata_m_scanin[28]), .q(din_m[28]), .so(dff_wdata_m_scanout[28]),
519 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
520 cl_sc1_msff_syrst_4x din_m029 (.d(din[29]), .si(dff_wdata_m_scanin[29]), .q(din_m[29]), .so(dff_wdata_m_scanout[29]),
521 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
522
523 cl_sc1_msff_syrst_4x din_m030 (.d(din[30]), .si(dff_wdata_m_scanin[30]), .q(din_m[30]), .so(dff_wdata_m_scanout[30]),
524 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
525 cl_sc1_msff_syrst_4x din_m031 (.d(din[31]), .si(dff_wdata_m_scanin[31]), .q(din_m[31]), .so(dff_wdata_m_scanout[31]),
526 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
527 cl_sc1_msff_syrst_4x din_m032 (.d(din[32]), .si(dff_wdata_m_scanin[32]), .q(din_m[32]), .so(dff_wdata_m_scanout[32]),
528 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
529 cl_sc1_msff_syrst_4x din_m033 (.d(din[33]), .si(dff_wdata_m_scanin[33]), .q(din_m[33]), .so(dff_wdata_m_scanout[33]),
530 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
531 cl_sc1_msff_syrst_4x din_m034 (.d(din[34]), .si(dff_wdata_m_scanin[34]), .q(din_m[34]), .so(dff_wdata_m_scanout[34]),
532 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
533 cl_sc1_msff_syrst_4x din_m035 (.d(din[35]), .si(dff_wdata_m_scanin[35]), .q(din_m[35]), .so(dff_wdata_m_scanout[35]),
534 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
535 cl_sc1_msff_syrst_4x din_m036 (.d(din[36]), .si(dff_wdata_m_scanin[36]), .q(din_m[36]), .so(dff_wdata_m_scanout[36]),
536 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
537 cl_sc1_msff_syrst_4x din_m037 (.d(din[37]), .si(dff_wdata_m_scanin[37]), .q(din_m[37]), .so(dff_wdata_m_scanout[37]),
538 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
539 cl_sc1_msff_syrst_4x din_m038 (.d(din[38]), .si(dff_wdata_m_scanin[38]), .q(din_m[38]), .so(dff_wdata_m_scanout[38]),
540 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
541 cl_sc1_msff_syrst_4x din_m039 (.d(din[39]), .si(dff_wdata_m_scanin[39]), .q(din_m[39]), .so(dff_wdata_m_scanout[39]),
542 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
543
544 cl_sc1_msff_syrst_4x din_m040 (.d(din[40]), .si(dff_wdata_m_scanin[40]), .q(din_m[40]), .so(dff_wdata_m_scanout[40]),
545 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
546 cl_sc1_msff_syrst_4x din_m041 (.d(din[41]), .si(dff_wdata_m_scanin[41]), .q(din_m[41]), .so(dff_wdata_m_scanout[41]),
547 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
548 cl_sc1_msff_syrst_4x din_m042 (.d(din[42]), .si(dff_wdata_m_scanin[42]), .q(din_m[42]), .so(dff_wdata_m_scanout[42]),
549 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
550 cl_sc1_msff_syrst_4x din_m043 (.d(din[43]), .si(dff_wdata_m_scanin[43]), .q(din_m[43]), .so(dff_wdata_m_scanout[43]),
551 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
552 cl_sc1_msff_syrst_4x din_m044 (.d(din[44]), .si(dff_wdata_m_scanin[44]), .q(din_m[44]), .so(dff_wdata_m_scanout[44]),
553 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
554 cl_sc1_msff_syrst_4x din_m045 (.d(din[45]), .si(dff_wdata_m_scanin[45]), .q(din_m[45]), .so(dff_wdata_m_scanout[45]),
555 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
556 cl_sc1_msff_syrst_4x din_m046 (.d(din[46]), .si(dff_wdata_m_scanin[46]), .q(din_m[46]), .so(dff_wdata_m_scanout[46]),
557 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
558 cl_sc1_msff_syrst_4x din_m047 (.d(din[47]), .si(dff_wdata_m_scanin[47]), .q(din_m[47]), .so(dff_wdata_m_scanout[47]),
559 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
560 cl_sc1_msff_syrst_4x din_m048 (.d(din[48]), .si(dff_wdata_m_scanin[48]), .q(din_m[48]), .so(dff_wdata_m_scanout[48]),
561 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
562 cl_sc1_msff_syrst_4x din_m049 (.d(din[49]), .si(dff_wdata_m_scanin[49]), .q(din_m[49]), .so(dff_wdata_m_scanout[49]),
563 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
564
565 cl_sc1_msff_syrst_4x din_m050 (.d(din[50]), .si(dff_wdata_m_scanin[50]), .q(din_m[50]), .so(dff_wdata_m_scanout[50]),
566 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
567 cl_sc1_msff_syrst_4x din_m051 (.d(din[51]), .si(dff_wdata_m_scanin[51]), .q(din_m[51]), .so(dff_wdata_m_scanout[51]),
568 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
569 cl_sc1_msff_syrst_4x din_m052 (.d(din[52]), .si(dff_wdata_m_scanin[52]), .q(din_m[52]), .so(dff_wdata_m_scanout[52]),
570 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
571 cl_sc1_msff_syrst_4x din_m053 (.d(din[53]), .si(dff_wdata_m_scanin[53]), .q(din_m[53]), .so(dff_wdata_m_scanout[53]),
572 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
573 cl_sc1_msff_syrst_4x din_m054 (.d(din[54]), .si(dff_wdata_m_scanin[54]), .q(din_m[54]), .so(dff_wdata_m_scanout[54]),
574 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
575 cl_sc1_msff_syrst_4x din_m055 (.d(din[55]), .si(dff_wdata_m_scanin[55]), .q(din_m[55]), .so(dff_wdata_m_scanout[55]),
576 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
577 cl_sc1_msff_syrst_4x din_m056 (.d(din[56]), .si(dff_wdata_m_scanin[56]), .q(din_m[56]), .so(dff_wdata_m_scanout[56]),
578 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
579 cl_sc1_msff_syrst_4x din_m057 (.d(din[57]), .si(dff_wdata_m_scanin[57]), .q(din_m[57]), .so(dff_wdata_m_scanout[57]),
580 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
581 cl_sc1_msff_syrst_4x din_m058 (.d(din[58]), .si(dff_wdata_m_scanin[58]), .q(din_m[58]), .so(dff_wdata_m_scanout[58]),
582 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
583 cl_sc1_msff_syrst_4x din_m059 (.d(din[59]), .si(dff_wdata_m_scanin[59]), .q(din_m[59]), .so(dff_wdata_m_scanout[59]),
584 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
585
586 cl_sc1_msff_syrst_4x din_m060 (.d(din[60]), .si(dff_wdata_m_scanin[60]), .q(din_m[60]), .so(dff_wdata_m_scanout[60]),
587 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
588 cl_sc1_msff_syrst_4x din_m061 (.d(din[61]), .si(dff_wdata_m_scanin[61]), .q(din_m[61]), .so(dff_wdata_m_scanout[61]),
589 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
590 cl_sc1_msff_syrst_4x din_m062 (.d(din[62]), .si(dff_wdata_m_scanin[62]), .q(din_m[62]), .so(dff_wdata_m_scanout[62]),
591 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
592 cl_sc1_msff_syrst_4x din_m063 (.d(din[63]), .si(dff_wdata_m_scanin[63]), .q(din_m[63]), .so(dff_wdata_m_scanout[63]),
593 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
594 cl_sc1_msff_syrst_4x din_m064 (.d(din[64]), .si(dff_wdata_m_scanin[64]), .q(din_m[64]), .so(dff_wdata_m_scanout[64]),
595 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
596 cl_sc1_msff_syrst_4x din_m065 (.d(din[65]), .si(dff_wdata_m_scanin[65]), .q(din_m[65]), .so(dff_wdata_m_scanout[65]),
597 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
598 cl_sc1_msff_syrst_4x din_m066 (.d(din[66]), .si(dff_wdata_m_scanin[66]), .q(din_m[66]), .so(dff_wdata_m_scanout[66]),
599 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
600 cl_sc1_msff_syrst_4x din_m067 (.d(din[67]), .si(dff_wdata_m_scanin[67]), .q(din_m[67]), .so(dff_wdata_m_scanout[67]),
601 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
602 cl_sc1_msff_syrst_4x din_m068 (.d(din[68]), .si(dff_wdata_m_scanin[68]), .q(din_m[68]), .so(dff_wdata_m_scanout[68]),
603 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
604 cl_sc1_msff_syrst_4x din_m069 (.d(din[69]), .si(dff_wdata_m_scanin[69]), .q(din_m[69]), .so(dff_wdata_m_scanout[69]),
605 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
606
607 cl_sc1_msff_syrst_4x din_m070 (.d(din[70]), .si(dff_wdata_m_scanin[70]), .q(din_m[70]), .so(dff_wdata_m_scanout[70]),
608 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
609 cl_sc1_msff_syrst_4x din_m071 (.d(din[71]), .si(dff_wdata_m_scanin[71]), .q(din_m[71]), .so(dff_wdata_m_scanout[71]),
610 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
611 cl_sc1_msff_syrst_4x din_m072 (.d(din[72]), .si(dff_wdata_m_scanin[72]), .q(din_m[72]), .so(dff_wdata_m_scanout[72]),
612 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
613 cl_sc1_msff_syrst_4x din_m073 (.d(din[73]), .si(dff_wdata_m_scanin[73]), .q(din_m[73]), .so(dff_wdata_m_scanout[73]),
614 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
615 cl_sc1_msff_syrst_4x din_m074 (.d(din[74]), .si(dff_wdata_m_scanin[74]), .q(din_m[74]), .so(dff_wdata_m_scanout[74]),
616 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
617 cl_sc1_msff_syrst_4x din_m075 (.d(din[75]), .si(dff_wdata_m_scanin[75]), .q(din_m[75]), .so(dff_wdata_m_scanout[75]),
618 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
619 cl_sc1_msff_syrst_4x din_m076 (.d(din[76]), .si(dff_wdata_m_scanin[76]), .q(din_m[76]), .so(dff_wdata_m_scanout[76]),
620 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
621 cl_sc1_msff_syrst_4x din_m077 (.d(din[77]), .si(dff_wdata_m_scanin[77]), .q(din_m[77]), .so(dff_wdata_m_scanout[77]),
622 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
623 cl_sc1_msff_syrst_4x din_m078 (.d(din[78]), .si(dff_wdata_m_scanin[78]), .q(din_m[78]), .so(dff_wdata_m_scanout[78]),
624 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
625 cl_sc1_msff_syrst_4x din_m079 (.d(din[79]), .si(dff_wdata_m_scanin[79]), .q(din_m[79]), .so(dff_wdata_m_scanout[79]),
626 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
627
628 cl_sc1_msff_syrst_4x din_m080 (.d(din[80]), .si(dff_wdata_m_scanin[80]), .q(din_m[80]), .so(dff_wdata_m_scanout[80]),
629 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
630 cl_sc1_msff_syrst_4x din_m081 (.d(din[81]), .si(dff_wdata_m_scanin[81]), .q(din_m[81]), .so(dff_wdata_m_scanout[81]),
631 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
632 cl_sc1_msff_syrst_4x din_m082 (.d(din[82]), .si(dff_wdata_m_scanin[82]), .q(din_m[82]), .so(dff_wdata_m_scanout[82]),
633 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
634 cl_sc1_msff_syrst_4x din_m083 (.d(din[83]), .si(dff_wdata_m_scanin[83]), .q(din_m[83]), .so(dff_wdata_m_scanout[83]),
635 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
636 cl_sc1_msff_syrst_4x din_m084 (.d(din[84]), .si(dff_wdata_m_scanin[84]), .q(din_m[84]), .so(dff_wdata_m_scanout[84]),
637 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
638 cl_sc1_msff_syrst_4x din_m085 (.d(din[85]), .si(dff_wdata_m_scanin[85]), .q(din_m[85]), .so(dff_wdata_m_scanout[85]),
639 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
640 cl_sc1_msff_syrst_4x din_m086 (.d(din[86]), .si(dff_wdata_m_scanin[86]), .q(din_m[86]), .so(dff_wdata_m_scanout[86]),
641 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
642 cl_sc1_msff_syrst_4x din_m087 (.d(din[87]), .si(dff_wdata_m_scanin[87]), .q(din_m[87]), .so(dff_wdata_m_scanout[87]),
643 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
644 cl_sc1_msff_syrst_4x din_m088 (.d(din[88]), .si(dff_wdata_m_scanin[88]), .q(din_m[88]), .so(dff_wdata_m_scanout[88]),
645 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
646 cl_sc1_msff_syrst_4x din_m089 (.d(din[89]), .si(dff_wdata_m_scanin[89]), .q(din_m[89]), .so(dff_wdata_m_scanout[89]),
647 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
648
649 cl_sc1_msff_syrst_4x din_m090 (.d(din[90]), .si(dff_wdata_m_scanin[90]), .q(din_m[90]), .so(dff_wdata_m_scanout[90]),
650 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
651 cl_sc1_msff_syrst_4x din_m091 (.d(din[91]), .si(dff_wdata_m_scanin[91]), .q(din_m[91]), .so(dff_wdata_m_scanout[91]),
652 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
653 cl_sc1_msff_syrst_4x din_m092 (.d(din[92]), .si(dff_wdata_m_scanin[92]), .q(din_m[92]), .so(dff_wdata_m_scanout[92]),
654 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
655 cl_sc1_msff_syrst_4x din_m093 (.d(din[93]), .si(dff_wdata_m_scanin[93]), .q(din_m[93]), .so(dff_wdata_m_scanout[93]),
656 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
657 cl_sc1_msff_syrst_4x din_m094 (.d(din[94]), .si(dff_wdata_m_scanin[94]), .q(din_m[94]), .so(dff_wdata_m_scanout[94]),
658 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
659 cl_sc1_msff_syrst_4x din_m095 (.d(din[95]), .si(dff_wdata_m_scanin[95]), .q(din_m[95]), .so(dff_wdata_m_scanout[95]),
660 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
661 cl_sc1_msff_syrst_4x din_m096 (.d(din[96]), .si(dff_wdata_m_scanin[96]), .q(din_m[96]), .so(dff_wdata_m_scanout[96]),
662 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
663 cl_sc1_msff_syrst_4x din_m097 (.d(din[97]), .si(dff_wdata_m_scanin[97]), .q(din_m[97]), .so(dff_wdata_m_scanout[97]),
664 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
665 cl_sc1_msff_syrst_4x din_m098 (.d(din[98]), .si(dff_wdata_m_scanin[98]), .q(din_m[98]), .so(dff_wdata_m_scanout[98]),
666 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
667 cl_sc1_msff_syrst_4x din_m099 (.d(din[99]), .si(dff_wdata_m_scanin[99]), .q(din_m[99]), .so(dff_wdata_m_scanout[99]),
668 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
669
670 cl_sc1_msff_syrst_4x din_m100 (.d(din[100]), .si(dff_wdata_m_scanin[100]), .q(din_m[100]), .so(dff_wdata_m_scanout[100]),
671 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
672 cl_sc1_msff_syrst_4x din_m101 (.d(din[101]), .si(dff_wdata_m_scanin[101]), .q(din_m[101]), .so(dff_wdata_m_scanout[101]),
673 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
674 cl_sc1_msff_syrst_4x din_m102 (.d(din[102]), .si(dff_wdata_m_scanin[102]), .q(din_m[102]), .so(dff_wdata_m_scanout[102]),
675 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
676 cl_sc1_msff_syrst_4x din_m103 (.d(din[103]), .si(dff_wdata_m_scanin[103]), .q(din_m[103]), .so(dff_wdata_m_scanout[103]),
677 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
678 cl_sc1_msff_syrst_4x din_m104 (.d(din[104]), .si(dff_wdata_m_scanin[104]), .q(din_m[104]), .so(dff_wdata_m_scanout[104]),
679 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
680 cl_sc1_msff_syrst_4x din_m105 (.d(din[105]), .si(dff_wdata_m_scanin[105]), .q(din_m[105]), .so(dff_wdata_m_scanout[105]),
681 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
682 cl_sc1_msff_syrst_4x din_m106 (.d(din[106]), .si(dff_wdata_m_scanin[106]), .q(din_m[106]), .so(dff_wdata_m_scanout[106]),
683 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
684 cl_sc1_msff_syrst_4x din_m107 (.d(din[107]), .si(dff_wdata_m_scanin[107]), .q(din_m[107]), .so(dff_wdata_m_scanout[107]),
685 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
686 cl_sc1_msff_syrst_4x din_m108 (.d(din[108]), .si(dff_wdata_m_scanin[108]), .q(din_m[108]), .so(dff_wdata_m_scanout[108]),
687 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
688 cl_sc1_msff_syrst_4x din_m109 (.d(din[109]), .si(dff_wdata_m_scanin[109]), .q(din_m[109]), .so(dff_wdata_m_scanout[109]),
689 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
690
691 cl_sc1_msff_syrst_4x din_m110 (.d(din[110]), .si(dff_wdata_m_scanin[110]), .q(din_m[110]), .so(dff_wdata_m_scanout[110]),
692 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
693 cl_sc1_msff_syrst_4x din_m111 (.d(din[111]), .si(dff_wdata_m_scanin[111]), .q(din_m[111]), .so(dff_wdata_m_scanout[111]),
694 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
695 cl_sc1_msff_syrst_4x din_m112 (.d(din[112]), .si(dff_wdata_m_scanin[112]), .q(din_m[112]), .so(dff_wdata_m_scanout[112]),
696 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
697 cl_sc1_msff_syrst_4x din_m113 (.d(din[113]), .si(dff_wdata_m_scanin[113]), .q(din_m[113]), .so(dff_wdata_m_scanout[113]),
698 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
699 cl_sc1_msff_syrst_4x din_m114 (.d(din[114]), .si(dff_wdata_m_scanin[114]), .q(din_m[114]), .so(dff_wdata_m_scanout[114]),
700 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
701 cl_sc1_msff_syrst_4x din_m115 (.d(din[115]), .si(dff_wdata_m_scanin[115]), .q(din_m[115]), .so(dff_wdata_m_scanout[115]),
702 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
703 cl_sc1_msff_syrst_4x din_m116 (.d(din[116]), .si(dff_wdata_m_scanin[116]), .q(din_m[116]), .so(dff_wdata_m_scanout[116]),
704 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
705 cl_sc1_msff_syrst_4x din_m117 (.d(din[117]), .si(dff_wdata_m_scanin[117]), .q(din_m[117]), .so(dff_wdata_m_scanout[117]),
706 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
707 cl_sc1_msff_syrst_4x din_m118 (.d(din[118]), .si(dff_wdata_m_scanin[118]), .q(din_m[118]), .so(dff_wdata_m_scanout[118]),
708 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
709 cl_sc1_msff_syrst_4x din_m119 (.d(din[119]), .si(dff_wdata_m_scanin[119]), .q(din_m[119]), .so(dff_wdata_m_scanout[119]),
710 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
711
712 cl_sc1_msff_syrst_4x din_m120 (.d(din[120]), .si(dff_wdata_m_scanin[120]), .q(din_m[120]), .so(dff_wdata_m_scanout[120]),
713 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
714 cl_sc1_msff_syrst_4x din_m121 (.d(din[121]), .si(dff_wdata_m_scanin[121]), .q(din_m[121]), .so(dff_wdata_m_scanout[121]),
715 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
716 cl_sc1_msff_syrst_4x din_m122 (.d(din[122]), .si(dff_wdata_m_scanin[122]), .q(din_m[122]), .so(dff_wdata_m_scanout[122]),
717 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
718 cl_sc1_msff_syrst_4x din_m123 (.d(din[123]), .si(dff_wdata_m_scanin[123]), .q(din_m[123]), .so(dff_wdata_m_scanout[123]),
719 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
720 cl_sc1_msff_syrst_4x din_m124 (.d(din[124]), .si(dff_wdata_m_scanin[124]), .q(din_m[124]), .so(dff_wdata_m_scanout[124]),
721 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
722 cl_sc1_msff_syrst_4x din_m125 (.d(din[125]), .si(dff_wdata_m_scanin[125]), .q(din_m[125]), .so(dff_wdata_m_scanout[125]),
723 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
724 cl_sc1_msff_syrst_4x din_m126 (.d(din[126]), .si(dff_wdata_m_scanin[126]), .q(din_m[126]), .so(dff_wdata_m_scanout[126]),
725 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
726 cl_sc1_msff_syrst_4x din_m127 (.d(din[127]), .si(dff_wdata_m_scanin[127]), .q(din_m[127]), .so(dff_wdata_m_scanout[127]),
727 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
728 cl_sc1_msff_syrst_4x din_m128 (.d(din[128]), .si(dff_wdata_m_scanin[128]), .q(din_m[128]), .so(dff_wdata_m_scanout[128]),
729 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
730 cl_sc1_msff_syrst_4x din_m129 (.d(din[129]), .si(dff_wdata_m_scanin[129]), .q(din_m[129]), .so(dff_wdata_m_scanout[129]),
731 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
732
733 cl_sc1_msff_syrst_4x din_m130 (.d(din[130]), .si(dff_wdata_m_scanin[130]), .q(din_m[130]), .so(dff_wdata_m_scanout[130]),
734 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
735 cl_sc1_msff_syrst_4x din_m131 (.d(din[131]), .si(dff_wdata_m_scanin[131]), .q(din_m[131]), .so(dff_wdata_m_scanout[131]),
736 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
737 cl_sc1_msff_syrst_4x din_m132 (.d(din[132]), .si(dff_wdata_m_scanin[132]), .q(din_m[132]), .so(dff_wdata_m_scanout[132]),
738 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
739 cl_sc1_msff_syrst_4x din_m133 (.d(din[133]), .si(dff_wdata_m_scanin[133]), .q(din_m[133]), .so(dff_wdata_m_scanout[133]),
740 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
741 cl_sc1_msff_syrst_4x din_m134 (.d(din[134]), .si(dff_wdata_m_scanin[134]), .q(din_m[134]), .so(dff_wdata_m_scanout[134]),
742 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
743 cl_sc1_msff_syrst_4x din_m135 (.d(din[135]), .si(dff_wdata_m_scanin[135]), .q(din_m[135]), .so(dff_wdata_m_scanout[135]),
744 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
745 cl_sc1_msff_syrst_4x din_m136 (.d(din[136]), .si(dff_wdata_m_scanin[136]), .q(din_m[136]), .so(dff_wdata_m_scanout[136]),
746 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
747 cl_sc1_msff_syrst_4x din_m137 (.d(din[137]), .si(dff_wdata_m_scanin[137]), .q(din_m[137]), .so(dff_wdata_m_scanout[137]),
748 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
749 cl_sc1_msff_syrst_4x din_m138 (.d(din[138]), .si(dff_wdata_m_scanin[138]), .q(din_m[138]), .so(dff_wdata_m_scanout[138]),
750 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
751 cl_sc1_msff_syrst_4x din_m139 (.d(din[139]), .si(dff_wdata_m_scanin[139]), .q(din_m[139]), .so(dff_wdata_m_scanout[139]),
752 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
753
754 cl_sc1_msff_syrst_4x din_m140 (.d(din[140]), .si(dff_wdata_m_scanin[140]), .q(din_m[140]), .so(dff_wdata_m_scanout[140]),
755 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
756 cl_sc1_msff_syrst_4x din_m141 (.d(din[141]), .si(dff_wdata_m_scanin[141]), .q(din_m[141]), .so(dff_wdata_m_scanout[141]),
757 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
758 cl_sc1_msff_syrst_4x din_m142 (.d(din[142]), .si(dff_wdata_m_scanin[142]), .q(din_m[142]), .so(dff_wdata_m_scanout[142]),
759 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
760 cl_sc1_msff_syrst_4x din_m143 (.d(din[143]), .si(dff_wdata_m_scanin[143]), .q(din_m[143]), .so(dff_wdata_m_scanout[143]),
761 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
762 cl_sc1_msff_syrst_4x din_m144 (.d(din[144]), .si(dff_wdata_m_scanin[144]), .q(din_m[144]), .so(dff_wdata_m_scanout[144]),
763 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
764 cl_sc1_msff_syrst_4x din_m145 (.d(din[145]), .si(dff_wdata_m_scanin[145]), .q(din_m[145]), .so(dff_wdata_m_scanout[145]),
765 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
766 cl_sc1_msff_syrst_4x din_m146 (.d(din[146]), .si(dff_wdata_m_scanin[146]), .q(din_m[146]), .so(dff_wdata_m_scanout[146]),
767 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
768 cl_sc1_msff_syrst_4x din_m147 (.d(din[147]), .si(dff_wdata_m_scanin[147]), .q(din_m[147]), .so(dff_wdata_m_scanout[147]),
769 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
770 cl_sc1_msff_syrst_4x din_m148 (.d(din[148]), .si(dff_wdata_m_scanin[148]), .q(din_m[148]), .so(dff_wdata_m_scanout[148]),
771 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
772 cl_sc1_msff_syrst_4x din_m149 (.d(din[149]), .si(dff_wdata_m_scanin[149]), .q(din_m[149]), .so(dff_wdata_m_scanout[149]),
773 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
774
775 cl_sc1_msff_syrst_4x din_m150 (.d(din[150]), .si(dff_wdata_m_scanin[150]), .q(din_m[150]), .so(dff_wdata_m_scanout[150]),
776 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
777 cl_sc1_msff_syrst_4x din_m151 (.d(din[151]), .si(dff_wdata_m_scanin[151]), .q(din_m[151]), .so(dff_wdata_m_scanout[151]),
778 .reset(reset_l), .l1clk(l1clk_in), .siclk(siclk), .soclk(soclk) );
779
780// ------------ test registers ------------
781
782 cl_sc1_msff_syrst_4x test_mode_reg (
783 .d (test_mode),
784 .reset (reset_l),
785 .si (dff_test_mode_scanin),
786 .q (test_mode),
787 .so (dff_test_mode_scanout),
788 .l1clk (l1clk_in),
789 .siclk (tcu_aclk),
790 .soclk (tcu_bclk) );
791
792 cl_sc1_msff_syrst_4x test_clk_reg (
793 .d (test_clk),
794 .reset (reset_l),
795 .si (dff_test_clk_scanin),
796 .q (test_clk),
797 .so (dff_test_clk_scanout),
798 .l1clk (l1clk_in),
799 .siclk (tcu_aclk),
800 .soclk (tcu_bclk) );
801
802wire l1clk_testclk;
803
804 assign l1clk_testclk = test_mode ? test_clk : l1clk_gate;
805
806
807//================================================
808// l2 clock Domain: Control signals
809//================================================
810wire do_B_write_m, l1clk_testclk_not, wr_inhibit_not, wr_en_and_clk;
811wire do_A_read_m, do_A_read_temp;
812wire [8:0] rw_addr_m, sc11, sc12;
813
814// assign do_B_write_m = wr_en_m && !l1clk_gate && !tcu_array_wr_inhibit;
815// assign do_A_read_m = rd_en_m && l1clk_gate && !tcu_array_wr_inhibit;
816// assign rw_addr_m = {9{do_B_write_m}} & wr_adr_m |
817// {9{do_A_read_m}} & rd_adr_m;
818
819 niu512_inv_macro__width_1 a1 (.dout(l1clk_testclk_not), .din(l1clk_testclk) );
820 niu512_inv_macro__width_1 a2 (.dout(wr_inhibit_not), .din(tcu_array_wr_inhibit) );
821 niu512_and_macro__width_1 a3 (.dout(wr_en_and_clk), .din0(wr_en_m), .din1(l1clk_testclk_not) );
822 niu512_and_macro__width_1 a4 (.dout(do_B_write_m), .din0(wr_en_and_clk), .din1(wr_inhibit_not) );
823
824 niu512_and_macro__width_1 b1 (.dout(do_A_read_temp), .din0(rd_en_m), .din1(l1clk_testclk) );
825 niu512_and_macro__width_1 b2 (.dout(do_A_read_m), .din0(wr_inhibit_not), .din1(do_A_read_temp) );
826
827 niu512_and_macro__width_9 c1 (.dout(sc11[8:0]), .din0({9{do_B_write_m}}),.din1(wr_adr_m[8:0]));
828 niu512_and_macro__width_9 c2 (.dout(sc12[8:0]), .din0({9{do_A_read_m}}), .din1(rd_adr_m[8:0]));
829 niu512_or_macro__width_9 c3 (.dout(rw_addr_m[8:0]),.din0(sc11[8:0]), .din1(sc12[8:0]));
830
831//================================================
832// l2x2 clock Domain: Clock headers
833//================================================
834
835wire l1clk_2x_free;
836
837cl_sc1_l1hdr_8x l1ch_2x_free (
838 .l2clk (l2clk_2x),
839 .pce (pce),
840 .pce_ov (tcu_pce_ov),
841 .l1clk (l1clk_2x_free),
842 .se (tcu_scan_en),
843 .stop (1'b0)
844 );
845
846
847
848//================================================
849// l2x2 clock Domain: Input Logic
850//================================================
851// ------------ controls_ph.a Latch @ posedge -------
852//reg do_B_write_2x_a;
853//reg do_A_read_2x_a;
854//reg [8:0] rw_addr_2x_a;
855//
856// always @(l1clk_2x_free or rw_addr_m or do_A_read_m or do_B_write_m) begin
857// if (l1clk_2x_free)
858// begin
859// rw_addr_2x_a = rw_addr_m;
860// do_A_read_2x_a = do_A_read_m;
861// do_B_write_2x_a = do_B_write_m;
862// end
863// else
864// begin
865// rw_addr_2x_a = rw_addr_2x_a;
866// do_A_read_2x_a = do_A_read_2x_a;
867// do_B_write_2x_a = do_B_write_2x_a;
868// end
869// end
870// ------------ controls_ph.b Latch @ negedge -------
871//reg [1:0] rd_addr_column_b;
872//reg [1:0] rd_addr_column_b1;
873//
874// always @(l1clk_2x_free or rd_en_a or rw_addr_2x_a) begin
875// if (!l1clk_2x_free && rd_en_a)
876// begin
877// rd_addr_column_b1 = rw_addr_2x_a[1:0];
878// end
879// else
880// begin
881// rd_addr_column_b1 = rd_addr_column_b1;
882// end
883// end
884//
885// always @(l1clk_2x_free) begin
886// rd_addr_column_b <= rd_addr_column_b1;
887// end
888
889// ------------ write_data_ph.b Flop @ negedge -----
890//reg [151:0] wdata_2x_b;
891//
892// always @(negedge l1clk_2x_free) begin
893// wdata_2x_b <= din_m;
894// end
895//
896
897wire [8:0] rw_addr_2x_a;
898wire [1:0] rd_addr_column_b;
899wire [1:0] rd_addr_column_b1;
900
901cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat0 (.latout(rw_addr_2x_a[0]), .d(rw_addr_m[0]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
902cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat1 (.latout(rw_addr_2x_a[1]), .d(rw_addr_m[1]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
903cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat2 (.latout(rw_addr_2x_a[2]), .d(rw_addr_m[2]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
904cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat3 (.latout(rw_addr_2x_a[3]), .d(rw_addr_m[3]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
905cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat4 (.latout(rw_addr_2x_a[4]), .d(rw_addr_m[4]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
906cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat5 (.latout(rw_addr_2x_a[5]), .d(rw_addr_m[5]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
907cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat6 (.latout(rw_addr_2x_a[6]), .d(rw_addr_m[6]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
908cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat7 (.latout(rw_addr_2x_a[7]), .d(rw_addr_m[7]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
909cl_mc1_scm_msff_lat_4x rw_addr_2x_a_lat8 (.latout(rw_addr_2x_a[8]), .d(rw_addr_m[8]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
910
911cl_mc1_scm_msff_lat_4x do_A_read_2x_a_lat (.latout(do_A_read_2x_a), .d(do_A_read_m), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l(), .so() );
912cl_mc1_scm_msff_lat_4x do_B_write_2x_a_lat (.latout(do_B_write_2x_a), .d(do_B_write_m), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
913
914
915cl_mc1_scm_msff_lat_4x rd_addr_column_b1_lat0 (.latout(rd_addr_column_b1[0]), .d(rw_addr_2x_a[0]), .l1clk(~(!l1clk_2x_free && rd_en_a)), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
916cl_mc1_scm_msff_lat_4x rd_addr_column_b1_lat1 (.latout(rd_addr_column_b1[1]), .d(rw_addr_2x_a[1]), .l1clk(~(!l1clk_2x_free && rd_en_a)), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
917
918cl_mc1_scm_msff_lat_4x rd_addr_column_b_lat0 (.latout(rd_addr_column_b[0]), .d(rd_addr_column_b1[0]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
919cl_mc1_scm_msff_lat_4x rd_addr_column_b_lat1 (.latout(rd_addr_column_b[1]), .d(rd_addr_column_b1[1]), .l1clk(~l1clk_2x_free), .si(1'b0), .siclk(1'b0), .soclk(1'b0), .q(),.q_l() , .so());
920
921
922cl_sc1_msff_4x wdata_2x_b_reg0 (.d(din_m[0]), .si(1'b0), .q(wdata_2x_b[0]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
923cl_sc1_msff_4x wdata_2x_b_reg1 (.d(din_m[1]), .si(1'b0), .q(wdata_2x_b[1]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
924cl_sc1_msff_4x wdata_2x_b_reg2 (.d(din_m[2]), .si(1'b0), .q(wdata_2x_b[2]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
925cl_sc1_msff_4x wdata_2x_b_reg3 (.d(din_m[3]), .si(1'b0), .q(wdata_2x_b[3]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
926cl_sc1_msff_4x wdata_2x_b_reg4 (.d(din_m[4]), .si(1'b0), .q(wdata_2x_b[4]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
927cl_sc1_msff_4x wdata_2x_b_reg5 (.d(din_m[5]), .si(1'b0), .q(wdata_2x_b[5]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
928cl_sc1_msff_4x wdata_2x_b_reg6 (.d(din_m[6]), .si(1'b0), .q(wdata_2x_b[6]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
929cl_sc1_msff_4x wdata_2x_b_reg7 (.d(din_m[7]), .si(1'b0), .q(wdata_2x_b[7]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
930cl_sc1_msff_4x wdata_2x_b_reg8 (.d(din_m[8]), .si(1'b0), .q(wdata_2x_b[8]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
931cl_sc1_msff_4x wdata_2x_b_reg9 (.d(din_m[9]), .si(1'b0), .q(wdata_2x_b[9]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
932cl_sc1_msff_4x wdata_2x_b_reg10 (.d(din_m[10]), .si(1'b0), .q(wdata_2x_b[10]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
933cl_sc1_msff_4x wdata_2x_b_reg11 (.d(din_m[11]), .si(1'b0), .q(wdata_2x_b[11]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
934cl_sc1_msff_4x wdata_2x_b_reg12 (.d(din_m[12]), .si(1'b0), .q(wdata_2x_b[12]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
935cl_sc1_msff_4x wdata_2x_b_reg13 (.d(din_m[13]), .si(1'b0), .q(wdata_2x_b[13]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
936cl_sc1_msff_4x wdata_2x_b_reg14 (.d(din_m[14]), .si(1'b0), .q(wdata_2x_b[14]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
937cl_sc1_msff_4x wdata_2x_b_reg15 (.d(din_m[15]), .si(1'b0), .q(wdata_2x_b[15]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
938cl_sc1_msff_4x wdata_2x_b_reg16 (.d(din_m[16]), .si(1'b0), .q(wdata_2x_b[16]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
939cl_sc1_msff_4x wdata_2x_b_reg17 (.d(din_m[17]), .si(1'b0), .q(wdata_2x_b[17]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
940cl_sc1_msff_4x wdata_2x_b_reg18 (.d(din_m[18]), .si(1'b0), .q(wdata_2x_b[18]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
941cl_sc1_msff_4x wdata_2x_b_reg19 (.d(din_m[19]), .si(1'b0), .q(wdata_2x_b[19]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
942cl_sc1_msff_4x wdata_2x_b_reg20 (.d(din_m[20]), .si(1'b0), .q(wdata_2x_b[20]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
943cl_sc1_msff_4x wdata_2x_b_reg21 (.d(din_m[21]), .si(1'b0), .q(wdata_2x_b[21]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
944cl_sc1_msff_4x wdata_2x_b_reg22 (.d(din_m[22]), .si(1'b0), .q(wdata_2x_b[22]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
945cl_sc1_msff_4x wdata_2x_b_reg23 (.d(din_m[23]), .si(1'b0), .q(wdata_2x_b[23]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
946cl_sc1_msff_4x wdata_2x_b_reg24 (.d(din_m[24]), .si(1'b0), .q(wdata_2x_b[24]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
947cl_sc1_msff_4x wdata_2x_b_reg25 (.d(din_m[25]), .si(1'b0), .q(wdata_2x_b[25]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
948cl_sc1_msff_4x wdata_2x_b_reg26 (.d(din_m[26]), .si(1'b0), .q(wdata_2x_b[26]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
949cl_sc1_msff_4x wdata_2x_b_reg27 (.d(din_m[27]), .si(1'b0), .q(wdata_2x_b[27]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
950cl_sc1_msff_4x wdata_2x_b_reg28 (.d(din_m[28]), .si(1'b0), .q(wdata_2x_b[28]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
951cl_sc1_msff_4x wdata_2x_b_reg29 (.d(din_m[29]), .si(1'b0), .q(wdata_2x_b[29]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
952cl_sc1_msff_4x wdata_2x_b_reg30 (.d(din_m[30]), .si(1'b0), .q(wdata_2x_b[30]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
953cl_sc1_msff_4x wdata_2x_b_reg31 (.d(din_m[31]), .si(1'b0), .q(wdata_2x_b[31]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
954cl_sc1_msff_4x wdata_2x_b_reg32 (.d(din_m[32]), .si(1'b0), .q(wdata_2x_b[32]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
955cl_sc1_msff_4x wdata_2x_b_reg33 (.d(din_m[33]), .si(1'b0), .q(wdata_2x_b[33]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
956cl_sc1_msff_4x wdata_2x_b_reg34 (.d(din_m[34]), .si(1'b0), .q(wdata_2x_b[34]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
957cl_sc1_msff_4x wdata_2x_b_reg35 (.d(din_m[35]), .si(1'b0), .q(wdata_2x_b[35]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
958cl_sc1_msff_4x wdata_2x_b_reg36 (.d(din_m[36]), .si(1'b0), .q(wdata_2x_b[36]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
959cl_sc1_msff_4x wdata_2x_b_reg37 (.d(din_m[37]), .si(1'b0), .q(wdata_2x_b[37]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
960cl_sc1_msff_4x wdata_2x_b_reg38 (.d(din_m[38]), .si(1'b0), .q(wdata_2x_b[38]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
961cl_sc1_msff_4x wdata_2x_b_reg39 (.d(din_m[39]), .si(1'b0), .q(wdata_2x_b[39]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
962cl_sc1_msff_4x wdata_2x_b_reg40 (.d(din_m[40]), .si(1'b0), .q(wdata_2x_b[40]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
963cl_sc1_msff_4x wdata_2x_b_reg41 (.d(din_m[41]), .si(1'b0), .q(wdata_2x_b[41]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
964cl_sc1_msff_4x wdata_2x_b_reg42 (.d(din_m[42]), .si(1'b0), .q(wdata_2x_b[42]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
965cl_sc1_msff_4x wdata_2x_b_reg43 (.d(din_m[43]), .si(1'b0), .q(wdata_2x_b[43]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
966cl_sc1_msff_4x wdata_2x_b_reg44 (.d(din_m[44]), .si(1'b0), .q(wdata_2x_b[44]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
967cl_sc1_msff_4x wdata_2x_b_reg45 (.d(din_m[45]), .si(1'b0), .q(wdata_2x_b[45]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
968cl_sc1_msff_4x wdata_2x_b_reg46 (.d(din_m[46]), .si(1'b0), .q(wdata_2x_b[46]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
969cl_sc1_msff_4x wdata_2x_b_reg47 (.d(din_m[47]), .si(1'b0), .q(wdata_2x_b[47]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
970cl_sc1_msff_4x wdata_2x_b_reg48 (.d(din_m[48]), .si(1'b0), .q(wdata_2x_b[48]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
971cl_sc1_msff_4x wdata_2x_b_reg49 (.d(din_m[49]), .si(1'b0), .q(wdata_2x_b[49]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
972cl_sc1_msff_4x wdata_2x_b_reg50 (.d(din_m[50]), .si(1'b0), .q(wdata_2x_b[50]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
973cl_sc1_msff_4x wdata_2x_b_reg51 (.d(din_m[51]), .si(1'b0), .q(wdata_2x_b[51]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
974cl_sc1_msff_4x wdata_2x_b_reg52 (.d(din_m[52]), .si(1'b0), .q(wdata_2x_b[52]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
975cl_sc1_msff_4x wdata_2x_b_reg53 (.d(din_m[53]), .si(1'b0), .q(wdata_2x_b[53]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
976cl_sc1_msff_4x wdata_2x_b_reg54 (.d(din_m[54]), .si(1'b0), .q(wdata_2x_b[54]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
977cl_sc1_msff_4x wdata_2x_b_reg55 (.d(din_m[55]), .si(1'b0), .q(wdata_2x_b[55]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
978cl_sc1_msff_4x wdata_2x_b_reg56 (.d(din_m[56]), .si(1'b0), .q(wdata_2x_b[56]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
979cl_sc1_msff_4x wdata_2x_b_reg57 (.d(din_m[57]), .si(1'b0), .q(wdata_2x_b[57]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
980cl_sc1_msff_4x wdata_2x_b_reg58 (.d(din_m[58]), .si(1'b0), .q(wdata_2x_b[58]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
981cl_sc1_msff_4x wdata_2x_b_reg59 (.d(din_m[59]), .si(1'b0), .q(wdata_2x_b[59]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
982cl_sc1_msff_4x wdata_2x_b_reg60 (.d(din_m[60]), .si(1'b0), .q(wdata_2x_b[60]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
983cl_sc1_msff_4x wdata_2x_b_reg61 (.d(din_m[61]), .si(1'b0), .q(wdata_2x_b[61]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
984cl_sc1_msff_4x wdata_2x_b_reg62 (.d(din_m[62]), .si(1'b0), .q(wdata_2x_b[62]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
985cl_sc1_msff_4x wdata_2x_b_reg63 (.d(din_m[63]), .si(1'b0), .q(wdata_2x_b[63]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
986cl_sc1_msff_4x wdata_2x_b_reg64 (.d(din_m[64]), .si(1'b0), .q(wdata_2x_b[64]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
987cl_sc1_msff_4x wdata_2x_b_reg65 (.d(din_m[65]), .si(1'b0), .q(wdata_2x_b[65]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
988cl_sc1_msff_4x wdata_2x_b_reg66 (.d(din_m[66]), .si(1'b0), .q(wdata_2x_b[66]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
989cl_sc1_msff_4x wdata_2x_b_reg67 (.d(din_m[67]), .si(1'b0), .q(wdata_2x_b[67]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
990cl_sc1_msff_4x wdata_2x_b_reg68 (.d(din_m[68]), .si(1'b0), .q(wdata_2x_b[68]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
991cl_sc1_msff_4x wdata_2x_b_reg69 (.d(din_m[69]), .si(1'b0), .q(wdata_2x_b[69]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
992cl_sc1_msff_4x wdata_2x_b_reg70 (.d(din_m[70]), .si(1'b0), .q(wdata_2x_b[70]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
993cl_sc1_msff_4x wdata_2x_b_reg71 (.d(din_m[71]), .si(1'b0), .q(wdata_2x_b[71]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
994cl_sc1_msff_4x wdata_2x_b_reg72 (.d(din_m[72]), .si(1'b0), .q(wdata_2x_b[72]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
995cl_sc1_msff_4x wdata_2x_b_reg73 (.d(din_m[73]), .si(1'b0), .q(wdata_2x_b[73]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
996cl_sc1_msff_4x wdata_2x_b_reg74 (.d(din_m[74]), .si(1'b0), .q(wdata_2x_b[74]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
997cl_sc1_msff_4x wdata_2x_b_reg75 (.d(din_m[75]), .si(1'b0), .q(wdata_2x_b[75]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
998cl_sc1_msff_4x wdata_2x_b_reg76 (.d(din_m[76]), .si(1'b0), .q(wdata_2x_b[76]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
999cl_sc1_msff_4x wdata_2x_b_reg77 (.d(din_m[77]), .si(1'b0), .q(wdata_2x_b[77]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1000cl_sc1_msff_4x wdata_2x_b_reg78 (.d(din_m[78]), .si(1'b0), .q(wdata_2x_b[78]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1001cl_sc1_msff_4x wdata_2x_b_reg79 (.d(din_m[79]), .si(1'b0), .q(wdata_2x_b[79]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1002cl_sc1_msff_4x wdata_2x_b_reg80 (.d(din_m[80]), .si(1'b0), .q(wdata_2x_b[80]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1003cl_sc1_msff_4x wdata_2x_b_reg81 (.d(din_m[81]), .si(1'b0), .q(wdata_2x_b[81]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1004cl_sc1_msff_4x wdata_2x_b_reg82 (.d(din_m[82]), .si(1'b0), .q(wdata_2x_b[82]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1005cl_sc1_msff_4x wdata_2x_b_reg83 (.d(din_m[83]), .si(1'b0), .q(wdata_2x_b[83]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1006cl_sc1_msff_4x wdata_2x_b_reg84 (.d(din_m[84]), .si(1'b0), .q(wdata_2x_b[84]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1007cl_sc1_msff_4x wdata_2x_b_reg85 (.d(din_m[85]), .si(1'b0), .q(wdata_2x_b[85]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1008cl_sc1_msff_4x wdata_2x_b_reg86 (.d(din_m[86]), .si(1'b0), .q(wdata_2x_b[86]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1009cl_sc1_msff_4x wdata_2x_b_reg87 (.d(din_m[87]), .si(1'b0), .q(wdata_2x_b[87]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1010cl_sc1_msff_4x wdata_2x_b_reg88 (.d(din_m[88]), .si(1'b0), .q(wdata_2x_b[88]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1011cl_sc1_msff_4x wdata_2x_b_reg89 (.d(din_m[89]), .si(1'b0), .q(wdata_2x_b[89]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1012cl_sc1_msff_4x wdata_2x_b_reg90 (.d(din_m[90]), .si(1'b0), .q(wdata_2x_b[90]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1013cl_sc1_msff_4x wdata_2x_b_reg91 (.d(din_m[91]), .si(1'b0), .q(wdata_2x_b[91]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1014cl_sc1_msff_4x wdata_2x_b_reg92 (.d(din_m[92]), .si(1'b0), .q(wdata_2x_b[92]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1015cl_sc1_msff_4x wdata_2x_b_reg93 (.d(din_m[93]), .si(1'b0), .q(wdata_2x_b[93]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1016cl_sc1_msff_4x wdata_2x_b_reg94 (.d(din_m[94]), .si(1'b0), .q(wdata_2x_b[94]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1017cl_sc1_msff_4x wdata_2x_b_reg95 (.d(din_m[95]), .si(1'b0), .q(wdata_2x_b[95]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1018cl_sc1_msff_4x wdata_2x_b_reg96 (.d(din_m[96]), .si(1'b0), .q(wdata_2x_b[96]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1019cl_sc1_msff_4x wdata_2x_b_reg97 (.d(din_m[97]), .si(1'b0), .q(wdata_2x_b[97]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1020cl_sc1_msff_4x wdata_2x_b_reg98 (.d(din_m[98]), .si(1'b0), .q(wdata_2x_b[98]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1021cl_sc1_msff_4x wdata_2x_b_reg99 (.d(din_m[99]), .si(1'b0), .q(wdata_2x_b[99]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1022cl_sc1_msff_4x wdata_2x_b_reg100 (.d(din_m[100]), .si(1'b0), .q(wdata_2x_b[100]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1023cl_sc1_msff_4x wdata_2x_b_reg101 (.d(din_m[101]), .si(1'b0), .q(wdata_2x_b[101]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1024cl_sc1_msff_4x wdata_2x_b_reg102 (.d(din_m[102]), .si(1'b0), .q(wdata_2x_b[102]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1025cl_sc1_msff_4x wdata_2x_b_reg103 (.d(din_m[103]), .si(1'b0), .q(wdata_2x_b[103]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1026cl_sc1_msff_4x wdata_2x_b_reg104 (.d(din_m[104]), .si(1'b0), .q(wdata_2x_b[104]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1027cl_sc1_msff_4x wdata_2x_b_reg105 (.d(din_m[105]), .si(1'b0), .q(wdata_2x_b[105]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1028cl_sc1_msff_4x wdata_2x_b_reg106 (.d(din_m[106]), .si(1'b0), .q(wdata_2x_b[106]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1029cl_sc1_msff_4x wdata_2x_b_reg107 (.d(din_m[107]), .si(1'b0), .q(wdata_2x_b[107]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1030cl_sc1_msff_4x wdata_2x_b_reg108 (.d(din_m[108]), .si(1'b0), .q(wdata_2x_b[108]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1031cl_sc1_msff_4x wdata_2x_b_reg109 (.d(din_m[109]), .si(1'b0), .q(wdata_2x_b[109]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1032cl_sc1_msff_4x wdata_2x_b_reg110 (.d(din_m[110]), .si(1'b0), .q(wdata_2x_b[110]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1033cl_sc1_msff_4x wdata_2x_b_reg111 (.d(din_m[111]), .si(1'b0), .q(wdata_2x_b[111]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1034cl_sc1_msff_4x wdata_2x_b_reg112 (.d(din_m[112]), .si(1'b0), .q(wdata_2x_b[112]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1035cl_sc1_msff_4x wdata_2x_b_reg113 (.d(din_m[113]), .si(1'b0), .q(wdata_2x_b[113]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1036cl_sc1_msff_4x wdata_2x_b_reg114 (.d(din_m[114]), .si(1'b0), .q(wdata_2x_b[114]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1037cl_sc1_msff_4x wdata_2x_b_reg115 (.d(din_m[115]), .si(1'b0), .q(wdata_2x_b[115]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1038cl_sc1_msff_4x wdata_2x_b_reg116 (.d(din_m[116]), .si(1'b0), .q(wdata_2x_b[116]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1039cl_sc1_msff_4x wdata_2x_b_reg117 (.d(din_m[117]), .si(1'b0), .q(wdata_2x_b[117]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1040cl_sc1_msff_4x wdata_2x_b_reg118 (.d(din_m[118]), .si(1'b0), .q(wdata_2x_b[118]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1041cl_sc1_msff_4x wdata_2x_b_reg119 (.d(din_m[119]), .si(1'b0), .q(wdata_2x_b[119]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1042cl_sc1_msff_4x wdata_2x_b_reg120 (.d(din_m[120]), .si(1'b0), .q(wdata_2x_b[120]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1043cl_sc1_msff_4x wdata_2x_b_reg121 (.d(din_m[121]), .si(1'b0), .q(wdata_2x_b[121]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1044cl_sc1_msff_4x wdata_2x_b_reg122 (.d(din_m[122]), .si(1'b0), .q(wdata_2x_b[122]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1045cl_sc1_msff_4x wdata_2x_b_reg123 (.d(din_m[123]), .si(1'b0), .q(wdata_2x_b[123]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1046cl_sc1_msff_4x wdata_2x_b_reg124 (.d(din_m[124]), .si(1'b0), .q(wdata_2x_b[124]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1047cl_sc1_msff_4x wdata_2x_b_reg125 (.d(din_m[125]), .si(1'b0), .q(wdata_2x_b[125]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1048cl_sc1_msff_4x wdata_2x_b_reg126 (.d(din_m[126]), .si(1'b0), .q(wdata_2x_b[126]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1049cl_sc1_msff_4x wdata_2x_b_reg127 (.d(din_m[127]), .si(1'b0), .q(wdata_2x_b[127]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1050cl_sc1_msff_4x wdata_2x_b_reg128 (.d(din_m[128]), .si(1'b0), .q(wdata_2x_b[128]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1051cl_sc1_msff_4x wdata_2x_b_reg129 (.d(din_m[129]), .si(1'b0), .q(wdata_2x_b[129]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1052cl_sc1_msff_4x wdata_2x_b_reg130 (.d(din_m[130]), .si(1'b0), .q(wdata_2x_b[130]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1053cl_sc1_msff_4x wdata_2x_b_reg131 (.d(din_m[131]), .si(1'b0), .q(wdata_2x_b[131]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1054cl_sc1_msff_4x wdata_2x_b_reg132 (.d(din_m[132]), .si(1'b0), .q(wdata_2x_b[132]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1055cl_sc1_msff_4x wdata_2x_b_reg133 (.d(din_m[133]), .si(1'b0), .q(wdata_2x_b[133]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1056cl_sc1_msff_4x wdata_2x_b_reg134 (.d(din_m[134]), .si(1'b0), .q(wdata_2x_b[134]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1057cl_sc1_msff_4x wdata_2x_b_reg135 (.d(din_m[135]), .si(1'b0), .q(wdata_2x_b[135]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1058cl_sc1_msff_4x wdata_2x_b_reg136 (.d(din_m[136]), .si(1'b0), .q(wdata_2x_b[136]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1059cl_sc1_msff_4x wdata_2x_b_reg137 (.d(din_m[137]), .si(1'b0), .q(wdata_2x_b[137]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1060cl_sc1_msff_4x wdata_2x_b_reg138 (.d(din_m[138]), .si(1'b0), .q(wdata_2x_b[138]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1061cl_sc1_msff_4x wdata_2x_b_reg139 (.d(din_m[139]), .si(1'b0), .q(wdata_2x_b[139]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1062cl_sc1_msff_4x wdata_2x_b_reg140 (.d(din_m[140]), .si(1'b0), .q(wdata_2x_b[140]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1063cl_sc1_msff_4x wdata_2x_b_reg141 (.d(din_m[141]), .si(1'b0), .q(wdata_2x_b[141]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1064cl_sc1_msff_4x wdata_2x_b_reg142 (.d(din_m[142]), .si(1'b0), .q(wdata_2x_b[142]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1065cl_sc1_msff_4x wdata_2x_b_reg143 (.d(din_m[143]), .si(1'b0), .q(wdata_2x_b[143]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1066cl_sc1_msff_4x wdata_2x_b_reg144 (.d(din_m[144]), .si(1'b0), .q(wdata_2x_b[144]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1067cl_sc1_msff_4x wdata_2x_b_reg145 (.d(din_m[145]), .si(1'b0), .q(wdata_2x_b[145]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1068cl_sc1_msff_4x wdata_2x_b_reg146 (.d(din_m[146]), .si(1'b0), .q(wdata_2x_b[146]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1069cl_sc1_msff_4x wdata_2x_b_reg147 (.d(din_m[147]), .si(1'b0), .q(wdata_2x_b[147]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1070cl_sc1_msff_4x wdata_2x_b_reg148 (.d(din_m[148]), .si(1'b0), .q(wdata_2x_b[148]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1071cl_sc1_msff_4x wdata_2x_b_reg149 (.d(din_m[149]), .si(1'b0), .q(wdata_2x_b[149]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1072cl_sc1_msff_4x wdata_2x_b_reg150 (.d(din_m[150]), .si(1'b0), .q(wdata_2x_b[150]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1073cl_sc1_msff_4x wdata_2x_b_reg151 (.d(din_m[151]), .si(1'b0), .q(wdata_2x_b[151]), .l1clk(~l1clk_2x_free), .siclk(1'b0), .soclk(1'b0),.so() );
1074//================================================
1075 assign wdata_b = wdata_2x_b;
1076 assign addr_a = rw_addr_2x_a;
1077 assign rd_en_a = do_A_read_2x_a && !do_B_write_2x_a;
1078 assign wr_en_a = do_B_write_2x_a;
1079
1080// geo: assign wcs_a = wr_en_a & ~tcu_array_wr_inhibit & ~rd_en_a ;
1081 assign wcs_a = wr_en_a & ~tcu_array_wr_inhibit;
1082
1083 assign rd_en_column[0] = rd_en_a && !addr_a[1] && !addr_a[0];
1084 assign rd_en_column[1] = rd_en_a && !addr_a[1] && addr_a[0];
1085 assign rd_en_column[2] = rd_en_a && addr_a[1] && !addr_a[0];
1086 assign rd_en_column[3] = rd_en_a && addr_a[1] && addr_a[0];
1087
1088 assign wt_en_column[0] = wcs_a && !addr_a[1] && !addr_a[0];
1089 assign wt_en_column[1] = wcs_a && !addr_a[1] && addr_a[0];
1090 assign wt_en_column[2] = wcs_a && addr_a[1] && !addr_a[0];
1091 assign wt_en_column[3] = wcs_a && addr_a[1] && addr_a[0];
1092
1093//================================================
1094 assign din_tr = { wdata_b[74],wdata_b[72],wdata_b[70],wdata_b[68],wdata_b[66],wdata_b[64],
1095 wdata_b[62],wdata_b[60],wdata_b[58],wdata_b[56],wdata_b[54],wdata_b[52],wdata_b[50],wdata_b[48],
1096 wdata_b[46],wdata_b[44],wdata_b[42],wdata_b[40],wdata_b[38],wdata_b[36],wdata_b[34],wdata_b[32],
1097 wdata_b[30],wdata_b[28],wdata_b[26],wdata_b[24],wdata_b[22],wdata_b[20],wdata_b[18],wdata_b[16],
1098 wdata_b[14],wdata_b[12],wdata_b[10],wdata_b[8],wdata_b[6],wdata_b[4],wdata_b[2],wdata_b[0]};
1099
1100 assign din_br = { wdata_b[75],wdata_b[73],wdata_b[71],wdata_b[69],wdata_b[67],wdata_b[65],
1101 wdata_b[63],wdata_b[61],wdata_b[59],wdata_b[57],wdata_b[55],wdata_b[53],wdata_b[51],wdata_b[49],
1102 wdata_b[47],wdata_b[45],wdata_b[43],wdata_b[41],wdata_b[39],wdata_b[37],wdata_b[35],wdata_b[33],
1103 wdata_b[31],wdata_b[29],wdata_b[27],wdata_b[25],wdata_b[23],wdata_b[21],wdata_b[19],wdata_b[17],
1104 wdata_b[15],wdata_b[13],wdata_b[11],wdata_b[9],wdata_b[7],wdata_b[5],wdata_b[3],wdata_b[1]};
1105
1106 assign din_tl = { wdata_b[150],wdata_b[148],wdata_b[146],wdata_b[144],wdata_b[142],wdata_b[140],
1107 wdata_b[138],wdata_b[136],wdata_b[134],wdata_b[132],wdata_b[130],wdata_b[128],wdata_b[126],wdata_b[124],
1108 wdata_b[122],wdata_b[120],wdata_b[118],wdata_b[116],wdata_b[114],wdata_b[112],wdata_b[110],wdata_b[108],
1109 wdata_b[106],wdata_b[104],wdata_b[102],wdata_b[100],wdata_b[98],wdata_b[96],wdata_b[94],wdata_b[92],
1110 wdata_b[90],wdata_b[88],wdata_b[86],wdata_b[84],wdata_b[82],wdata_b[80],wdata_b[78],wdata_b[76]};
1111
1112 assign din_bl = { wdata_b[151],wdata_b[149],wdata_b[147],wdata_b[145],wdata_b[143],wdata_b[141],
1113 wdata_b[139],wdata_b[137],wdata_b[135],wdata_b[133],wdata_b[131],wdata_b[129],wdata_b[127],wdata_b[125],
1114 wdata_b[123],wdata_b[121],wdata_b[119],wdata_b[117],wdata_b[115],wdata_b[113],wdata_b[111],wdata_b[109],
1115 wdata_b[107],wdata_b[105],wdata_b[103],wdata_b[101],wdata_b[99],wdata_b[97],wdata_b[95],wdata_b[93],
1116 wdata_b[91],wdata_b[89],wdata_b[87],wdata_b[85],wdata_b[83],wdata_b[81],wdata_b[79],wdata_b[77]};
1117
1118 assign { rd_dout[74],rd_dout[72],rd_dout[70],rd_dout[68],rd_dout[66],rd_dout[64],
1119 rd_dout[62],rd_dout[60],rd_dout[58],rd_dout[56],rd_dout[54],rd_dout[52],rd_dout[50],rd_dout[48],
1120 rd_dout[46],rd_dout[44],rd_dout[42],rd_dout[40],rd_dout[38],rd_dout[36],rd_dout[34],rd_dout[32],
1121 rd_dout[30],rd_dout[28],rd_dout[26],rd_dout[24],rd_dout[22],rd_dout[20],rd_dout[18],rd_dout[16],
1122 rd_dout[14],rd_dout[12],rd_dout[10],rd_dout[8],rd_dout[6],rd_dout[4],rd_dout[2],rd_dout[0]}
1123 = ary_rdout_tr;
1124
1125 assign { rd_dout[75],rd_dout[73],rd_dout[71],rd_dout[69],rd_dout[67],rd_dout[65],
1126 rd_dout[63],rd_dout[61],rd_dout[59],rd_dout[57],rd_dout[55],rd_dout[53],rd_dout[51],rd_dout[49],
1127 rd_dout[47],rd_dout[45],rd_dout[43],rd_dout[41],rd_dout[39],rd_dout[37],rd_dout[35],rd_dout[33],
1128 rd_dout[31],rd_dout[29],rd_dout[27],rd_dout[25],rd_dout[23],rd_dout[21],rd_dout[19],rd_dout[17],
1129 rd_dout[15],rd_dout[13],rd_dout[11],rd_dout[9],rd_dout[7],rd_dout[5],rd_dout[3],rd_dout[1]}
1130 = ary_rdout_br;
1131
1132 assign { rd_dout[150],rd_dout[148],rd_dout[146],rd_dout[144],rd_dout[142],rd_dout[140],
1133 rd_dout[138],rd_dout[136],rd_dout[134],rd_dout[132],rd_dout[130],rd_dout[128],rd_dout[126],rd_dout[124],
1134 rd_dout[122],rd_dout[120],rd_dout[118],rd_dout[116],rd_dout[114],rd_dout[112],rd_dout[110],rd_dout[108],
1135 rd_dout[106],rd_dout[104],rd_dout[102],rd_dout[100],rd_dout[98],rd_dout[96],rd_dout[94],rd_dout[92],
1136 rd_dout[90],rd_dout[88],rd_dout[86],rd_dout[84],rd_dout[82],rd_dout[80],rd_dout[78],rd_dout[76]}
1137 = ary_rdout_tl;
1138
1139 assign { rd_dout[151],rd_dout[149],rd_dout[147],rd_dout[145],rd_dout[143],rd_dout[141],
1140 rd_dout[139],rd_dout[137],rd_dout[135],rd_dout[133],rd_dout[131],rd_dout[129],rd_dout[127],rd_dout[125],
1141 rd_dout[123],rd_dout[121],rd_dout[119],rd_dout[117],rd_dout[115],rd_dout[113],rd_dout[111],rd_dout[109],
1142 rd_dout[107],rd_dout[105],rd_dout[103],rd_dout[101],rd_dout[99],rd_dout[97],rd_dout[95],rd_dout[93],
1143 rd_dout[91],rd_dout[89],rd_dout[87],rd_dout[85],rd_dout[83],rd_dout[81],rd_dout[79],rd_dout[77]}
1144 = ary_rdout_bl;
1145
1146//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
1147 n2_niu_sp_512x152s_array niu_sp_512x152s_array_br (
1148 .din (din_br[37:0]),
1149 .rw_addr_subbank (addr_a[8:2]),
1150 .rd_addr_column (rd_addr_column_b[1:0]),
1151 .rd_en_column (rd_en_column[3:0]),
1152 .wt_en_column (wt_en_column[3:0]),
1153 .red_value (red_v_br),
1154 .repair_en (red_en_br),
1155 .l1clk (l1clk_2x_free),
1156 .ary_rdout (ary_rdout_br)
1157 );
1158
1159 n2_niu_sp_512x152s_array niu_sp_512x152s_array_tr (
1160 .din (din_tr[37:0]),
1161 .rw_addr_subbank (addr_a[8:2]),
1162 .rd_addr_column (rd_addr_column_b[1:0]),
1163 .rd_en_column (rd_en_column[3:0]),
1164 .wt_en_column (wt_en_column[3:0]),
1165 .red_value (red_v_tr),
1166 .repair_en (red_en_tr),
1167 .l1clk (l1clk_2x_free),
1168 .ary_rdout (ary_rdout_tr)
1169 );
1170
1171 n2_niu_sp_512x152s_array niu_sp_512x152s_array_bl (
1172 .din (din_bl[37:0]),
1173 .rw_addr_subbank (addr_a[8:2]),
1174 .rd_addr_column (rd_addr_column_b[1:0]),
1175 .rd_en_column (rd_en_column[3:0]),
1176 .wt_en_column (wt_en_column[3:0]),
1177 .red_value (red_v_bl),
1178 .repair_en (red_en_bl),
1179 .l1clk (l1clk_2x_free),
1180 .ary_rdout (ary_rdout_bl)
1181 );
1182
1183 n2_niu_sp_512x152s_array niu_sp_512x152s_array_tl (
1184 .din (din_tl[37:0]),
1185 .rw_addr_subbank (addr_a[8:2]),
1186 .rd_addr_column (rd_addr_column_b[1:0]),
1187 .rd_en_column (rd_en_column[3:0]),
1188 .wt_en_column (wt_en_column[3:0]),
1189 .red_value (red_v_tl),
1190 .repair_en (red_en_tl),
1191 .l1clk (l1clk_2x_free),
1192 .ary_rdout (ary_rdout_tl)
1193 );
1194
1195 assign dout = rd_dout[151:0];
1196
1197// fixscan start:
1198 assign dff_wdata_m_scanin[151] = scan_in ;
1199 assign dff_wdata_m_scanin[150] = dff_wdata_m_scanout[151] ;
1200 assign dff_wdata_m_scanin[149] = dff_wdata_m_scanout[150] ;
1201 assign dff_wdata_m_scanin[148] = dff_wdata_m_scanout[149] ;
1202 assign dff_wdata_m_scanin[147] = dff_wdata_m_scanout[148] ;
1203 assign dff_wdata_m_scanin[146] = dff_wdata_m_scanout[147] ;
1204 assign dff_wdata_m_scanin[145] = dff_wdata_m_scanout[146] ;
1205 assign dff_wdata_m_scanin[144] = dff_wdata_m_scanout[145] ;
1206 assign dff_wdata_m_scanin[143] = dff_wdata_m_scanout[144] ;
1207 assign dff_wdata_m_scanin[142] = dff_wdata_m_scanout[143] ;
1208 assign dff_wdata_m_scanin[141] = dff_wdata_m_scanout[142] ;
1209 assign dff_wdata_m_scanin[140] = dff_wdata_m_scanout[141] ;
1210 assign dff_wdata_m_scanin[139] = dff_wdata_m_scanout[140] ;
1211 assign dff_wdata_m_scanin[138] = dff_wdata_m_scanout[139] ;
1212 assign dff_wdata_m_scanin[137] = dff_wdata_m_scanout[138] ;
1213 assign dff_wdata_m_scanin[136] = dff_wdata_m_scanout[137] ;
1214 assign dff_wdata_m_scanin[135] = dff_wdata_m_scanout[136] ;
1215 assign dff_wdata_m_scanin[134] = dff_wdata_m_scanout[135] ;
1216 assign dff_wdata_m_scanin[133] = dff_wdata_m_scanout[134] ;
1217 assign dff_wdata_m_scanin[132] = dff_wdata_m_scanout[133] ;
1218 assign dff_wdata_m_scanin[131] = dff_wdata_m_scanout[132] ;
1219 assign dff_wdata_m_scanin[130] = dff_wdata_m_scanout[131] ;
1220 assign dff_wdata_m_scanin[129] = dff_wdata_m_scanout[130] ;
1221 assign dff_wdata_m_scanin[128] = dff_wdata_m_scanout[129] ;
1222 assign dff_wdata_m_scanin[127] = dff_wdata_m_scanout[128] ;
1223 assign dff_wdata_m_scanin[126] = dff_wdata_m_scanout[127] ;
1224 assign dff_wdata_m_scanin[125] = dff_wdata_m_scanout[126] ;
1225 assign dff_wdata_m_scanin[124] = dff_wdata_m_scanout[125] ;
1226 assign dff_wdata_m_scanin[123] = dff_wdata_m_scanout[124] ;
1227 assign dff_wdata_m_scanin[122] = dff_wdata_m_scanout[123] ;
1228 assign dff_wdata_m_scanin[121] = dff_wdata_m_scanout[122] ;
1229 assign dff_wdata_m_scanin[120] = dff_wdata_m_scanout[121] ;
1230 assign dff_wdata_m_scanin[119] = dff_wdata_m_scanout[120] ;
1231 assign dff_wdata_m_scanin[118] = dff_wdata_m_scanout[119] ;
1232 assign dff_wdata_m_scanin[117] = dff_wdata_m_scanout[118] ;
1233 assign dff_wdata_m_scanin[116] = dff_wdata_m_scanout[117] ;
1234 assign dff_wdata_m_scanin[115] = dff_wdata_m_scanout[116] ;
1235 assign dff_wdata_m_scanin[114] = dff_wdata_m_scanout[115] ;
1236 assign dff_wdata_m_scanin[113] = dff_wdata_m_scanout[114] ;
1237 assign dff_wdata_m_scanin[112] = dff_wdata_m_scanout[113] ;
1238 assign dff_wdata_m_scanin[111] = dff_wdata_m_scanout[112] ;
1239 assign dff_wdata_m_scanin[110] = dff_wdata_m_scanout[111] ;
1240 assign dff_wdata_m_scanin[109] = dff_wdata_m_scanout[110] ;
1241 assign dff_wdata_m_scanin[108] = dff_wdata_m_scanout[109] ;
1242 assign dff_wdata_m_scanin[107] = dff_wdata_m_scanout[108] ;
1243 assign dff_wdata_m_scanin[106] = dff_wdata_m_scanout[107] ;
1244 assign dff_wdata_m_scanin[105] = dff_wdata_m_scanout[106] ;
1245 assign dff_wdata_m_scanin[104] = dff_wdata_m_scanout[105] ;
1246 assign dff_wdata_m_scanin[103] = dff_wdata_m_scanout[104] ;
1247 assign dff_wdata_m_scanin[102] = dff_wdata_m_scanout[103] ;
1248 assign dff_wdata_m_scanin[101] = dff_wdata_m_scanout[102] ;
1249 assign dff_wdata_m_scanin[100] = dff_wdata_m_scanout[101] ;
1250 assign dff_wdata_m_scanin[99] = dff_wdata_m_scanout[100] ;
1251 assign dff_wdata_m_scanin[98] = dff_wdata_m_scanout[99] ;
1252 assign dff_wdata_m_scanin[97] = dff_wdata_m_scanout[98] ;
1253 assign dff_wdata_m_scanin[96] = dff_wdata_m_scanout[97] ;
1254 assign dff_wdata_m_scanin[95] = dff_wdata_m_scanout[96] ;
1255 assign dff_wdata_m_scanin[94] = dff_wdata_m_scanout[95] ;
1256 assign dff_wdata_m_scanin[93] = dff_wdata_m_scanout[94] ;
1257 assign dff_wdata_m_scanin[92] = dff_wdata_m_scanout[93] ;
1258 assign dff_wdata_m_scanin[91] = dff_wdata_m_scanout[92] ;
1259 assign dff_wdata_m_scanin[90] = dff_wdata_m_scanout[91] ;
1260 assign dff_wdata_m_scanin[89] = dff_wdata_m_scanout[90] ;
1261 assign dff_wdata_m_scanin[88] = dff_wdata_m_scanout[89] ;
1262 assign dff_wdata_m_scanin[87] = dff_wdata_m_scanout[88] ;
1263 assign dff_wdata_m_scanin[86] = dff_wdata_m_scanout[87] ;
1264 assign dff_wdata_m_scanin[85] = dff_wdata_m_scanout[86] ;
1265 assign dff_wdata_m_scanin[84] = dff_wdata_m_scanout[85] ;
1266 assign dff_wdata_m_scanin[83] = dff_wdata_m_scanout[84] ;
1267 assign dff_wdata_m_scanin[82] = dff_wdata_m_scanout[83] ;
1268 assign dff_wdata_m_scanin[81] = dff_wdata_m_scanout[82] ;
1269 assign dff_wdata_m_scanin[80] = dff_wdata_m_scanout[81] ;
1270 assign dff_wdata_m_scanin[79] = dff_wdata_m_scanout[80] ;
1271 assign dff_wdata_m_scanin[78] = dff_wdata_m_scanout[79] ;
1272 assign dff_wdata_m_scanin[77] = dff_wdata_m_scanout[78] ;
1273 assign dff_wdata_m_scanin[76] = dff_wdata_m_scanout[77] ;
1274
1275 assign dff_wr_adr_m_scanin[0] = dff_wdata_m_scanout[76] ;
1276 assign dff_rd_adr_m_scanin[0] = dff_wr_adr_m_scanout[0] ;
1277 assign dff_wr_adr_m_scanin[1] = dff_rd_adr_m_scanout[0] ;
1278 assign dff_rd_adr_m_scanin[1] = dff_wr_adr_m_scanout[1] ;
1279 assign dff_wr_adr_m_scanin[2] = dff_rd_adr_m_scanout[1] ;
1280 assign dff_rd_adr_m_scanin[2] = dff_wr_adr_m_scanout[2] ;
1281 assign dff_wr_adr_m_scanin[3] = dff_rd_adr_m_scanout[2] ;
1282 assign dff_rd_adr_m_scanin[3] = dff_wr_adr_m_scanout[3] ;
1283 assign dff_wr_adr_m_scanin[4] = dff_rd_adr_m_scanout[3] ;
1284 assign dff_rd_adr_m_scanin[4] = dff_wr_adr_m_scanout[4] ;
1285 assign dff_wr_adr_m_scanin[5] = dff_rd_adr_m_scanout[4] ;
1286 assign dff_rd_adr_m_scanin[5] = dff_wr_adr_m_scanout[5] ;
1287 assign dff_wr_adr_m_scanin[6] = dff_rd_adr_m_scanout[5] ;
1288 assign dff_rd_adr_m_scanin[6] = dff_wr_adr_m_scanout[6] ;
1289 assign dff_wr_adr_m_scanin[7] = dff_rd_adr_m_scanout[6] ;
1290 assign dff_rd_adr_m_scanin[7] = dff_wr_adr_m_scanout[7] ;
1291 assign dff_wr_adr_m_scanin[8] = dff_rd_adr_m_scanout[7] ;
1292 assign dff_rd_adr_m_scanin[8] = dff_wr_adr_m_scanout[8] ;
1293 assign dff_wr_en_m_scanin = dff_rd_adr_m_scanout[8] ;
1294 assign dff_rd_en_m_scanin = dff_wr_en_m_scanout ;
1295 assign dff_test_clk_scanin = dff_rd_en_m_scanout ;
1296 assign dff_test_mode_scanin = dff_test_clk_scanout ;
1297 assign dff_wdata_m_scanin[75] = dff_test_mode_scanout ;
1298 assign dff_wdata_m_scanin[74] = dff_wdata_m_scanout[75] ;
1299 assign dff_wdata_m_scanin[73] = dff_wdata_m_scanout[74] ;
1300 assign dff_wdata_m_scanin[72] = dff_wdata_m_scanout[73] ;
1301 assign dff_wdata_m_scanin[71] = dff_wdata_m_scanout[72] ;
1302 assign dff_wdata_m_scanin[70] = dff_wdata_m_scanout[71] ;
1303 assign dff_wdata_m_scanin[69] = dff_wdata_m_scanout[70] ;
1304 assign dff_wdata_m_scanin[68] = dff_wdata_m_scanout[69] ;
1305 assign dff_wdata_m_scanin[67] = dff_wdata_m_scanout[68] ;
1306 assign dff_wdata_m_scanin[66] = dff_wdata_m_scanout[67] ;
1307 assign dff_wdata_m_scanin[65] = dff_wdata_m_scanout[66] ;
1308 assign dff_wdata_m_scanin[64] = dff_wdata_m_scanout[65] ;
1309 assign dff_wdata_m_scanin[63] = dff_wdata_m_scanout[64] ;
1310 assign dff_wdata_m_scanin[62] = dff_wdata_m_scanout[63] ;
1311 assign dff_wdata_m_scanin[61] = dff_wdata_m_scanout[62] ;
1312 assign dff_wdata_m_scanin[60] = dff_wdata_m_scanout[61] ;
1313 assign dff_wdata_m_scanin[59] = dff_wdata_m_scanout[60] ;
1314 assign dff_wdata_m_scanin[58] = dff_wdata_m_scanout[59] ;
1315 assign dff_wdata_m_scanin[57] = dff_wdata_m_scanout[58] ;
1316 assign dff_wdata_m_scanin[56] = dff_wdata_m_scanout[57] ;
1317 assign dff_wdata_m_scanin[55] = dff_wdata_m_scanout[56] ;
1318 assign dff_wdata_m_scanin[54] = dff_wdata_m_scanout[55] ;
1319 assign dff_wdata_m_scanin[53] = dff_wdata_m_scanout[54] ;
1320 assign dff_wdata_m_scanin[52] = dff_wdata_m_scanout[53] ;
1321 assign dff_wdata_m_scanin[51] = dff_wdata_m_scanout[52] ;
1322 assign dff_wdata_m_scanin[50] = dff_wdata_m_scanout[51] ;
1323 assign dff_wdata_m_scanin[49] = dff_wdata_m_scanout[50] ;
1324 assign dff_wdata_m_scanin[48] = dff_wdata_m_scanout[49] ;
1325 assign dff_wdata_m_scanin[47] = dff_wdata_m_scanout[48] ;
1326 assign dff_wdata_m_scanin[46] = dff_wdata_m_scanout[47] ;
1327 assign dff_wdata_m_scanin[45] = dff_wdata_m_scanout[46] ;
1328 assign dff_wdata_m_scanin[44] = dff_wdata_m_scanout[45] ;
1329 assign dff_wdata_m_scanin[43] = dff_wdata_m_scanout[44] ;
1330 assign dff_wdata_m_scanin[42] = dff_wdata_m_scanout[43] ;
1331 assign dff_wdata_m_scanin[41] = dff_wdata_m_scanout[42] ;
1332 assign dff_wdata_m_scanin[40] = dff_wdata_m_scanout[41] ;
1333 assign dff_wdata_m_scanin[39] = dff_wdata_m_scanout[40] ;
1334 assign dff_wdata_m_scanin[38] = dff_wdata_m_scanout[39] ;
1335 assign dff_wdata_m_scanin[37] = dff_wdata_m_scanout[38] ;
1336 assign dff_wdata_m_scanin[36] = dff_wdata_m_scanout[37] ;
1337 assign dff_wdata_m_scanin[35] = dff_wdata_m_scanout[36] ;
1338 assign dff_wdata_m_scanin[34] = dff_wdata_m_scanout[35] ;
1339 assign dff_wdata_m_scanin[33] = dff_wdata_m_scanout[34] ;
1340 assign dff_wdata_m_scanin[32] = dff_wdata_m_scanout[33] ;
1341 assign dff_wdata_m_scanin[31] = dff_wdata_m_scanout[32] ;
1342 assign dff_wdata_m_scanin[30] = dff_wdata_m_scanout[31] ;
1343 assign dff_wdata_m_scanin[29] = dff_wdata_m_scanout[30] ;
1344 assign dff_wdata_m_scanin[28] = dff_wdata_m_scanout[29] ;
1345 assign dff_wdata_m_scanin[27] = dff_wdata_m_scanout[28] ;
1346 assign dff_wdata_m_scanin[26] = dff_wdata_m_scanout[27] ;
1347 assign dff_wdata_m_scanin[25] = dff_wdata_m_scanout[26] ;
1348 assign dff_wdata_m_scanin[24] = dff_wdata_m_scanout[25] ;
1349 assign dff_wdata_m_scanin[23] = dff_wdata_m_scanout[24] ;
1350 assign dff_wdata_m_scanin[22] = dff_wdata_m_scanout[23] ;
1351 assign dff_wdata_m_scanin[21] = dff_wdata_m_scanout[22] ;
1352 assign dff_wdata_m_scanin[20] = dff_wdata_m_scanout[21] ;
1353 assign dff_wdata_m_scanin[19] = dff_wdata_m_scanout[20] ;
1354 assign dff_wdata_m_scanin[18] = dff_wdata_m_scanout[19] ;
1355 assign dff_wdata_m_scanin[17] = dff_wdata_m_scanout[18] ;
1356 assign dff_wdata_m_scanin[16] = dff_wdata_m_scanout[17] ;
1357 assign dff_wdata_m_scanin[15] = dff_wdata_m_scanout[16] ;
1358 assign dff_wdata_m_scanin[14] = dff_wdata_m_scanout[15] ;
1359 assign dff_wdata_m_scanin[13] = dff_wdata_m_scanout[14] ;
1360 assign dff_wdata_m_scanin[12] = dff_wdata_m_scanout[13] ;
1361 assign dff_wdata_m_scanin[11] = dff_wdata_m_scanout[12] ;
1362 assign dff_wdata_m_scanin[10] = dff_wdata_m_scanout[11] ;
1363 assign dff_wdata_m_scanin[9] = dff_wdata_m_scanout[10] ;
1364 assign dff_wdata_m_scanin[8] = dff_wdata_m_scanout[9] ;
1365 assign dff_wdata_m_scanin[7] = dff_wdata_m_scanout[8] ;
1366 assign dff_wdata_m_scanin[6] = dff_wdata_m_scanout[7] ;
1367 assign dff_wdata_m_scanin[5] = dff_wdata_m_scanout[6] ;
1368 assign dff_wdata_m_scanin[4] = dff_wdata_m_scanout[5] ;
1369 assign dff_wdata_m_scanin[3] = dff_wdata_m_scanout[4] ;
1370 assign dff_wdata_m_scanin[2] = dff_wdata_m_scanout[3] ;
1371 assign dff_wdata_m_scanin[1] = dff_wdata_m_scanout[2] ;
1372 assign dff_wdata_m_scanin[0] = dff_wdata_m_scanout[1] ;
1373 assign scan_out = dff_wdata_m_scanout[0] ;
1374
1375// fixscan end:
1376
1377endmodule
1378
1379
1380
1381//
1382// invert macro
1383//
1384//
1385
1386
1387
1388
1389
1390module niu512_inv_macro__width_1 (
1391 din,
1392 dout);
1393 input [0:0] din;
1394 output [0:0] dout;
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404cl_u1_inv_1x d0_0 (
1405.in(din[0]),
1406.out(dout[0])
1407);
1408
1409
1410
1411
1412
1413endmodule
1414
1415
1416
1417
1418
1419//
1420// and macro for ports = 2,3,4
1421//
1422//
1423
1424
1425
1426
1427
1428module niu512_and_macro__width_1 (
1429 din0,
1430 din1,
1431 dout);
1432wire [0:0] nandout;
1433
1434 input [0:0] din0;
1435 input [0:0] din1;
1436 output [0:0] dout;
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446cl_u1_nand2_1x d0_0 (
1447.in0(din0[0]),
1448.in1(din1[0]),
1449.out(nandout[0])
1450);
1451
1452cl_u1_inv_1x d1_0 (
1453.in(nandout[0]),
1454.out(dout[0])
1455);
1456
1457
1458
1459
1460endmodule
1461
1462
1463
1464
1465
1466//
1467// and macro for ports = 2,3,4
1468//
1469//
1470
1471
1472
1473
1474
1475module niu512_and_macro__width_9 (
1476 din0,
1477 din1,
1478 dout);
1479wire [8:0] nandout;
1480
1481 input [8:0] din0;
1482 input [8:0] din1;
1483 output [8:0] dout;
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493cl_u1_nand2_1x d0_0 (
1494.in0(din0[0]),
1495.in1(din1[0]),
1496.out(nandout[0])
1497);
1498
1499cl_u1_nand2_1x d0_1 (
1500.in0(din0[1]),
1501.in1(din1[1]),
1502.out(nandout[1])
1503);
1504
1505cl_u1_nand2_1x d0_2 (
1506.in0(din0[2]),
1507.in1(din1[2]),
1508.out(nandout[2])
1509);
1510
1511cl_u1_nand2_1x d0_3 (
1512.in0(din0[3]),
1513.in1(din1[3]),
1514.out(nandout[3])
1515);
1516
1517cl_u1_nand2_1x d0_4 (
1518.in0(din0[4]),
1519.in1(din1[4]),
1520.out(nandout[4])
1521);
1522
1523cl_u1_nand2_1x d0_5 (
1524.in0(din0[5]),
1525.in1(din1[5]),
1526.out(nandout[5])
1527);
1528
1529cl_u1_nand2_1x d0_6 (
1530.in0(din0[6]),
1531.in1(din1[6]),
1532.out(nandout[6])
1533);
1534
1535cl_u1_nand2_1x d0_7 (
1536.in0(din0[7]),
1537.in1(din1[7]),
1538.out(nandout[7])
1539);
1540
1541cl_u1_nand2_1x d0_8 (
1542.in0(din0[8]),
1543.in1(din1[8]),
1544.out(nandout[8])
1545);
1546
1547cl_u1_inv_1x d1_0 (
1548.in(nandout[0]),
1549.out(dout[0])
1550);
1551cl_u1_inv_1x d1_1 (
1552.in(nandout[1]),
1553.out(dout[1])
1554);
1555cl_u1_inv_1x d1_2 (
1556.in(nandout[2]),
1557.out(dout[2])
1558);
1559cl_u1_inv_1x d1_3 (
1560.in(nandout[3]),
1561.out(dout[3])
1562);
1563cl_u1_inv_1x d1_4 (
1564.in(nandout[4]),
1565.out(dout[4])
1566);
1567cl_u1_inv_1x d1_5 (
1568.in(nandout[5]),
1569.out(dout[5])
1570);
1571cl_u1_inv_1x d1_6 (
1572.in(nandout[6]),
1573.out(dout[6])
1574);
1575cl_u1_inv_1x d1_7 (
1576.in(nandout[7]),
1577.out(dout[7])
1578);
1579cl_u1_inv_1x d1_8 (
1580.in(nandout[8]),
1581.out(dout[8])
1582);
1583
1584
1585
1586
1587endmodule
1588
1589
1590
1591
1592
1593//
1594// or macro for ports = 2,3
1595//
1596//
1597
1598
1599
1600
1601
1602module niu512_or_macro__width_9 (
1603 din0,
1604 din1,
1605 dout);
1606wire [8:0] norout;
1607
1608 input [8:0] din0;
1609 input [8:0] din1;
1610 output [8:0] dout;
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620cl_u1_nor2_1x d0_0 (
1621.in0(din0[0]),
1622.in1(din1[0]),
1623.out(norout[0])
1624);
1625
1626cl_u1_nor2_1x d0_1 (
1627.in0(din0[1]),
1628.in1(din1[1]),
1629.out(norout[1])
1630);
1631
1632cl_u1_nor2_1x d0_2 (
1633.in0(din0[2]),
1634.in1(din1[2]),
1635.out(norout[2])
1636);
1637
1638cl_u1_nor2_1x d0_3 (
1639.in0(din0[3]),
1640.in1(din1[3]),
1641.out(norout[3])
1642);
1643
1644cl_u1_nor2_1x d0_4 (
1645.in0(din0[4]),
1646.in1(din1[4]),
1647.out(norout[4])
1648);
1649
1650cl_u1_nor2_1x d0_5 (
1651.in0(din0[5]),
1652.in1(din1[5]),
1653.out(norout[5])
1654);
1655
1656cl_u1_nor2_1x d0_6 (
1657.in0(din0[6]),
1658.in1(din1[6]),
1659.out(norout[6])
1660);
1661
1662cl_u1_nor2_1x d0_7 (
1663.in0(din0[7]),
1664.in1(din1[7]),
1665.out(norout[7])
1666);
1667
1668cl_u1_nor2_1x d0_8 (
1669.in0(din0[8]),
1670.in1(din1[8]),
1671.out(norout[8])
1672);
1673
1674cl_u1_inv_1x d1_0 (
1675.in(norout[0]),
1676.out(dout[0])
1677);
1678cl_u1_inv_1x d1_1 (
1679.in(norout[1]),
1680.out(dout[1])
1681);
1682cl_u1_inv_1x d1_2 (
1683.in(norout[2]),
1684.out(dout[2])
1685);
1686cl_u1_inv_1x d1_3 (
1687.in(norout[3]),
1688.out(dout[3])
1689);
1690cl_u1_inv_1x d1_4 (
1691.in(norout[4]),
1692.out(dout[4])
1693);
1694cl_u1_inv_1x d1_5 (
1695.in(norout[5]),
1696.out(dout[5])
1697);
1698cl_u1_inv_1x d1_6 (
1699.in(norout[6]),
1700.out(dout[6])
1701);
1702cl_u1_inv_1x d1_7 (
1703.in(norout[7]),
1704.out(dout[7])
1705);
1706cl_u1_inv_1x d1_8 (
1707.in(norout[8]),
1708.out(dout[8])
1709);
1710
1711
1712
1713
1714endmodule
1715
1716
1717
1718
1719
1720module n2_niu_sp_512x152s_array (
1721 din,
1722 rw_addr_subbank,
1723 rd_addr_column,
1724 rd_en_column,
1725 wt_en_column,
1726 red_value,
1727 repair_en,
1728 l1clk,
1729 ary_rdout);
1730
1731input [37:0] din;
1732input [6:0] rw_addr_subbank;
1733input [1:0] rd_addr_column;
1734input [3:0] rd_en_column;
1735input [3:0] wt_en_column;
1736input [5:0] red_value;
1737input repair_en;
1738input l1clk;
1739
1740output [37:0] ary_rdout;
1741
1742wire [37:0] ary_rdout;
1743
1744wire [37:0] ary_rdout_c0;
1745wire [37:0] ary_rdout_c1;
1746wire [37:0] ary_rdout_c2;
1747wire [37:0] ary_rdout_c3;
1748
1749 n2_niu_sp_512x152s_subbank niu_sp_512x152s_subbank_c0 (
1750 .din (din),
1751 .rw_addr (rw_addr_subbank),
1752 .rd_en (rd_en_column[0]),
1753 .wt_en (wt_en_column[0]),
1754 .red_value (red_value),
1755 .repair_en (repair_en),
1756 .l1clk (l1clk),
1757 .ary_rdout (ary_rdout_c0)
1758 );
1759
1760 n2_niu_sp_512x152s_subbank niu_sp_512x152s_subbank_c1 (
1761 .din (din),
1762 .rw_addr (rw_addr_subbank),
1763 .rd_en (rd_en_column[1]),
1764 .wt_en (wt_en_column[1]),
1765 .red_value (red_value),
1766 .repair_en (repair_en),
1767 .l1clk (l1clk),
1768 .ary_rdout (ary_rdout_c1)
1769 );
1770
1771 n2_niu_sp_512x152s_subbank niu_sp_512x152s_subbank_c2 (
1772 .din (din),
1773 .rw_addr (rw_addr_subbank),
1774 .rd_en (rd_en_column[2]),
1775 .wt_en (wt_en_column[2]),
1776 .red_value (red_value),
1777 .repair_en (repair_en),
1778 .l1clk (l1clk),
1779 .ary_rdout (ary_rdout_c2)
1780 );
1781
1782 n2_niu_sp_512x152s_subbank niu_sp_512x152s_subbank_c3 (
1783 .din (din),
1784 .rw_addr (rw_addr_subbank),
1785 .rd_en (rd_en_column[3]),
1786 .wt_en (wt_en_column[3]),
1787 .red_value (red_value),
1788 .repair_en (repair_en),
1789 .l1clk (l1clk),
1790 .ary_rdout (ary_rdout_c3)
1791 );
1792
1793
1794assign ary_rdout = rd_addr_column[1]? ( rd_addr_column[0]? ary_rdout_c3: ary_rdout_c2 ) :
1795 ( rd_addr_column[0]? ary_rdout_c1: ary_rdout_c0);
1796
1797
1798endmodule
1799
1800
1801
1802module n2_niu_sp_512x152s_subbank (
1803 din,
1804 rw_addr,
1805 rd_en,
1806 wt_en,
1807 red_value,
1808 repair_en,
1809 l1clk,
1810 ary_rdout);
1811// din,
1812// rw_addr,
1813// rd_en,
1814// wt_en,
1815// red_value,
1816// repair_en,
1817// l1clk,
1818// ary_rdout
1819// );
1820
1821input [37:0] din;
1822input [6:0] rw_addr;
1823input rd_en;
1824input wt_en;
1825input [5:0] red_value;
1826input repair_en;
1827input l1clk;
1828
1829output [37:0] ary_rdout;
1830
1831// ----------------------------------------------------------------------------
1832// Zero In Checkers
1833// ----------------------------------------------------------------------------
1834// checker to verify on accesses's that no bits are x
1835// 0in kndr -var rw_addr
1836// 0in kndr -var rd_en
1837// 0in kndr -var wt_en
1838// 0in kndr -var red_value
1839// 0in kndr -var repair_en
1840
1841wire [37:0] ary_rdout;
1842
1843wire [38:0] wr_data;
1844
1845reg [38:0] mem_ary_dout;
1846
1847integer n;
1848
1849//`ifndef INNOLOGIC
1850//// Emulate reset
1851//integer i;
1852//initial begin
1853// for (i=0; i<128; i=i+1) begin
1854// mem[i] = {39{1'b0}};
1855// end
1856// mem_ary_dout = {39{1'b0}};
1857//end
1858//`endif
1859
1860//////////////////////////////
1861// Redundancy write shifter //
1862//////////////////////////////
1863reg [38:0] wr_data_rep;
1864
1865wire [31:0] red_value_32bit = {{(32-6){1'h0}},red_value}; // 0in < max 37 -active ( (repair_en==1'b1) && (l1clk==1'b1) ) -group mbist_mode
1866
1867
1868wire [38:0] shift_col_en = {39{~repair_en}} |
1869 ( { {37{1'b1}}, {2'b00} } << red_value[5:0] ) ;
1870
1871assign wr_data[38:0] = (~shift_col_en & {{1'b0}, din}) | (shift_col_en & {din, {din[0]}}) ;
1872
1873
1874//////////////////////////////
1875// Read/write array //
1876//////////////////////////////
1877reg rd_en_blat;
1878
1879 always @ (l1clk or rd_en)
1880 if (!l1clk)
1881 rd_en_blat = rd_en;
1882 else
1883 rd_en_blat = rd_en_blat;
1884
1885`ifdef AXIS_SMEM_BAD
1886
1887// internal variable
1888integer k, l;
1889
1890reg [38:0] write_mask;
1891
1892wire [38:0] axis_dout ;
1893wire [38:0] axis_din = wr_data ;
1894wire [6:0] axis_waddr = rw_addr ;
1895wire [6:0] axis_raddr = rw_addr ;
1896wire axis_wen = wt_en ;
1897wire axis_ren = rd_en ;
1898wire axis_clk = l1clk ;
1899
1900axis_smem #(7, 39, 2, 1'b0) mem // addr_width,data_width,num_ports,init_value
1901( {axis_dout , {39{1'bz}} }, // Output Port (1,2)
1902 {{39{1'bz}} , axis_din }, // Input Port (1,2)
1903 {axis_raddr , axis_waddr }, // Address Port (1,2)
1904 {1'b0 , axis_wen }, // Write Enable (1,2)
1905 {1'b1 , 1'b1 }, // Chip Enable (1,2)
1906 {axis_clk , axis_clk }, // Port Clocks (1,2)
1907 {{39{1'bz}} , {39{1'bz}}} ); // Write Mask (1,2)
1908
1909always @(posedge l1clk) begin
1910 if (rd_en_blat) begin
1911 if (axis_wen)
1912 mem_ary_dout <= 39'hx;
1913 else
1914 mem_ary_dout <= axis_dout;
1915 end
1916end
1917
1918`else
1919
1920reg [38:0] mem[0:128-1];
1921
1922 always @ (negedge l1clk) begin
1923 if (wt_en) begin
1924 if(rd_en)
1925 mem[rw_addr[6:0]] <= {39{1'hx}}; // 0in < fire -severity 1 -message "Detected rd/wr collision in NIU 512x152s RAM, dout driven as X's" -group mbist_mode
1926 else
1927 mem[rw_addr[6:0]] <= wr_data;
1928 end
1929 end
1930
1931
1932 always @(posedge l1clk) begin
1933 if (rd_en_blat) begin
1934 if (wt_en)
1935 mem_ary_dout <= {39{1'hx}}; // 0in < fire -severity 1 -message "Detected rd/wr collision in NIU 512x152s RAM, dout driven as X's" -group mbist_mode
1936
1937
1938 else
1939 mem_ary_dout <= mem[rw_addr[6:0]] ;
1940 end
1941 end
1942
1943// Initialize the arrays.
1944`ifndef NOINITMEM
1945integer j;
1946initial begin
1947 for (j=0;j<128;j=j+1) begin
1948 mem[j] = 39'd0;
1949 end
1950 mem_ary_dout[38:0] = 39'h0;
1951end
1952
1953`endif // NOINITMEM
1954
1955`endif // AXIS_SMEM
1956
1957//////////////////////////////
1958// Redundancy read shifter //
1959//////////////////////////////
1960reg [37:0] mem_ary_dout_rep;
1961
1962 always @(red_value_32bit or mem_ary_dout ) begin
1963 for (n = 0; n < 38; n = n + 1) begin
1964 if ( n <= (red_value_32bit))
1965 mem_ary_dout_rep[n] = mem_ary_dout[n];
1966 else
1967 mem_ary_dout_rep[n] = mem_ary_dout[n+1];
1968 end
1969 end
1970
1971 assign ary_rdout = repair_en ? mem_ary_dout_rep : mem_ary_dout[38:1];
1972
1973
1974
1975
1976supply0 vss;
1977supply1 vdd;
1978
1979endmodule
1980
1981
1982
1983
1984module n2_niu_dp_512x152s_repair (
1985 aclk,
1986 bclk,
1987 tcu_se_scancollar_in,
1988 tcu_se_scancollar_out,
1989 pce,
1990 tcu_pce_ov,
1991 tcu_scan_en,
1992 tcu_array_wr_inhibit,
1993 scanin_red,
1994 hdr_sram_rvalue,
1995 hdr_sram_rid,
1996 hdr_sram_wr_en,
1997 hdr_sram_red_clr,
1998 l2clk,
1999 sram_hdr_read_data,
2000 red_v_br,
2001 red_v_bl,
2002 red_v_tr,
2003 red_v_tl,
2004 red_en_br,
2005 red_en_bl,
2006 red_en_tr,
2007 red_en_tl,
2008 scanout_red);
2009wire l1clk_in_en;
2010wire l1clk_out_en;
2011wire l1clk_gate_en;
2012
2013
2014input aclk;
2015input bclk;
2016input tcu_se_scancollar_in;
2017input tcu_se_scancollar_out;
2018input pce;
2019input tcu_pce_ov;
2020input tcu_scan_en;
2021input tcu_array_wr_inhibit; // direct input, not flopped
2022input scanin_red;
2023input [6:0] hdr_sram_rvalue;
2024input [1:0] hdr_sram_rid;
2025input hdr_sram_wr_en;
2026input hdr_sram_red_clr;
2027
2028input l2clk;
2029
2030output [6:0] sram_hdr_read_data;
2031
2032output [5:0] red_v_br; // to subbank
2033output [5:0] red_v_bl;
2034output [5:0] red_v_tr;
2035output [5:0] red_v_tl;
2036output red_en_br;
2037output red_en_bl;
2038output red_en_tr;
2039output red_en_tl;
2040
2041output scanout_red;
2042
2043wire [6:0] sram_hdr_read_data;
2044
2045wire [5:0] red_v_br; // to subbank
2046wire [5:0] red_v_bl;
2047wire [5:0] red_v_tr;
2048wire [5:0] red_v_tl;
2049wire red_en_br;
2050wire red_en_bl;
2051wire red_en_tr;
2052wire red_en_tl;
2053
2054wire [5:0] red_value_b0; // to subbank
2055wire [5:0] red_value_b1;
2056wire [5:0] red_value_b2;
2057wire [5:0] red_value_b3;
2058wire [3:0] repair_en_bk; // to subbank
2059
2060wire scanout_red;
2061
2062assign red_v_bl = red_value_b0;
2063assign red_v_br = red_value_b1;
2064assign red_v_tl = red_value_b2;
2065assign red_v_tr = red_value_b3;
2066
2067assign red_en_bl = repair_en_bk[0];
2068assign red_en_br = repair_en_bk[1];
2069assign red_en_tl = repair_en_bk[2];
2070assign red_en_tr = repair_en_bk[3];
2071
2072
2073// scan renames
2074wire siclk = aclk;
2075wire soclk = bclk;
2076// end scan
2077
2078wire [3:0] red_id;
2079wire [3:0] red_reg_clk_p;
2080wire [5:0] fuse_red_data;
2081wire fuse_red_enable;
2082
2083wire [5:0] red_data_reg_b0;
2084wire [5:0] red_data_reg_b1;
2085wire [5:0] red_data_reg_b2;
2086wire [5:0] red_data_reg_b3;
2087wire [3:0] red_en_reg_bk;
2088
2089wire [3:0] scan_input_bk;
2090wire [3:0] scan_output_bk;
2091
2092//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2093//================================================
2094// l2 clock Domain: Clock headers
2095//================================================
2096wire l1clk_in;
2097wire l1clk_gate;
2098wire l1clk_out;
2099
2100//cl_sc1_l1hdr_8x l1ch_in (
2101// .l2clk (l2clk),
2102// .pce (pce),
2103// .l1clk (l1clk_in),
2104// .se (tcu_se_scancollar_in),
2105// .pce_ov (tcu_pce_ov),
2106// .stop (1'b0)
2107// );
2108
2109
2110//cl_sc1_l1hdr_8x l1ch_out (
2111// .l2clk (l2clk),
2112// .pce (pce),
2113// .l1clk (l1clk_out),
2114// .se (tcu_se_scancollar_out),
2115// .pce_ov (tcu_pce_ov),
2116// .stop (1'b0)
2117// );
2118
2119//cl_sc1_l1hdr_8x l1ch_gate (
2120// .l2clk (l2clk),
2121// .pce (pce),
2122// .l1clk (l1clk_gate),
2123// .se (tcu_scan_en),
2124// .pce_ov (tcu_pce_ov),
2125// .stop (1'b0)
2126// );
2127
2128///////////////////////////////////
2129// decomposed l1hdr for l1clk_in
2130///////////////////////////////////
2131
2132cl_mc1_l1enable_12x l1ch_in_l1en (
2133 .l2clk (l2clk),
2134 .pce (pce),
2135 .pce_ov (tcu_pce_ov),
2136 .l1en (l1clk_in_en)
2137 );
2138
2139cl_mc1_l1driver_12x l1ch_in_l1drvr (
2140 .se (tcu_se_scancollar_in),
2141 .l1en (l1clk_in_en),
2142 .l1clk (l1clk_in),
2143 .l2clk(l2clk)
2144 );
2145
2146///////////////////////////////////
2147// decomposed l1hdr for l1clk_out
2148///////////////////////////////////
2149
2150cl_mc1_l1enable_12x l1ch_out_l1en (
2151 .l2clk (l2clk),
2152 .pce (pce),
2153 .pce_ov (tcu_pce_ov),
2154 .l1en (l1clk_out_en)
2155 );
2156
2157cl_mc1_l1driver_12x l1ch_out_l1drvr (
2158 .se (tcu_se_scancollar_out),
2159 .l1en (l1clk_out_en),
2160 .l1clk (l1clk_out),
2161 .l2clk(l2clk)
2162 );
2163
2164
2165///////////////////////////////////
2166// decomposed l1hdr for l1clk_gate
2167///////////////////////////////////
2168
2169cl_mc1_l1enable_12x l1ch_gate_l1en (
2170 .l2clk (l2clk),
2171 .pce (pce),
2172 .pce_ov (tcu_pce_ov),
2173 .l1en (l1clk_gate_en)
2174 );
2175
2176cl_mc1_l1driver_12x l1ch_gate_l1drvr (
2177 .se (tcu_scan_en),
2178 .l1en (l1clk_gate_en),
2179 .l1clk (l1clk_gate),
2180 .l2clk(l2clk)
2181 );
2182
2183
2184
2185//================================================
2186// l2 clock Domain: Input flops
2187//================================================
2188
2189/****************************************************/
2190wire [5:0] fuse_niu_repair_value;
2191wire fuse_niu_repair_en;
2192wire [1:0] fuse_niu_rid;
2193wire fuse_niu_wen;
2194wire fuse_red_reset;
2195
2196wire dff_rvalue_m_scanin;
2197wire dff_rvalue_m_scanout;
2198wire dff_rid_m_scanin;
2199wire dff_rid_m_scanout;
2200wire dff_wr_en_m_scanin;
2201wire dff_wr_en_m_scanout;
2202wire dff_red_clr_m_scanin;
2203wire dff_red_clr_m_scanout;
2204
2205wire sr10;
2206wire hdr_wr_en;
2207wire hdr_red_clr;
2208
2209 niu512_msff_ctl_macro__width_7 srhdr_rvalue (
2210 .scan_in (dff_rvalue_m_scanin),
2211 .scan_out (dff_rvalue_m_scanout),
2212 .l1clk (l1clk_in),
2213 .din (hdr_sram_rvalue[6:0]),
2214 .dout ({fuse_niu_repair_value[5:0],fuse_niu_repair_en}),
2215 .siclk(siclk),
2216 .soclk(soclk) );
2217
2218 niu512_msff_ctl_macro__width_2 srhdr_rid (
2219 .scan_in (dff_rid_m_scanin),
2220 .scan_out (dff_rid_m_scanout),
2221 .l1clk (l1clk_in),
2222 .din (hdr_sram_rid[1:0]),
2223 .dout (fuse_niu_rid[1:0]),
2224 .siclk(siclk),
2225 .soclk(soclk) );
2226
2227 niu512_msff_ctl_macro__width_1 srhdr_wr_en (
2228 .scan_in (dff_wr_en_m_scanin),
2229 .scan_out (dff_wr_en_m_scanout),
2230 .l1clk (l1clk_in),
2231 .din (hdr_sram_wr_en),
2232 .dout (hdr_wr_en),
2233 .siclk(siclk),
2234 .soclk(soclk) );
2235
2236 niu512_msff_ctl_macro__width_1 srhdr_red_clr (
2237 .scan_in (dff_red_clr_m_scanin),
2238 .scan_out (dff_red_clr_m_scanout),
2239 .l1clk (l1clk_in),
2240 .din (hdr_sram_red_clr),
2241 .dout (hdr_red_clr),
2242 .siclk(siclk),
2243 .soclk(soclk) );
2244
2245// assign fuse_niu_wen = hdr_wr_en && !tcu_array_wr_inhibit;
2246// assign fuse_red_reset = hdr_red_clr && !tcu_array_wr_inhibit;
2247
2248 niu512_inv_macro__width_1 r1 (.dout(sr10), .din(tcu_array_wr_inhibit) );
2249 niu512_and_macro__width_1 r2 (.dout(fuse_niu_wen), .din0(hdr_wr_en), .din1(sr10) );
2250 niu512_and_macro__width_1 r3 (.dout(fuse_red_reset), .din0(hdr_red_clr), .din1(sr10) );
2251
2252//================================================
2253// l2 clock Domain: output flops
2254//================================================
2255
2256// ------------ repair_ph.a register ----------------
2257wire [5:0] niu_fuse_repair_value;
2258wire niu_fuse_repair_en;
2259
2260wire dff_read_data_m_scanin;
2261wire dff_read_data_m_scanout;
2262
2263 niu512_msff_ctl_macro__width_7 sram_read_data (
2264 .scan_in (dff_read_data_m_scanin),
2265 .scan_out (dff_read_data_m_scanout),
2266 .l1clk (l1clk_out),
2267 .din ({niu_fuse_repair_value[5:0],niu_fuse_repair_en}),
2268 .dout (sram_hdr_read_data[6:0]),
2269 .siclk(siclk),
2270 .soclk(soclk) );
2271
2272//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2273//////////////////////////////
2274// Redundancy Register //
2275//////////////////////////////
2276 assign red_id[0] = !fuse_niu_rid[1] && !fuse_niu_rid[0];
2277 assign red_id[1] = !fuse_niu_rid[1] && fuse_niu_rid[0];
2278 assign red_id[2] = fuse_niu_rid[1] && !fuse_niu_rid[0];
2279 assign red_id[3] = fuse_niu_rid[1] && fuse_niu_rid[0];
2280
2281 assign red_reg_clk_p[0] = (!l1clk_gate && (red_id[0] && fuse_niu_wen || fuse_red_reset));
2282 assign red_reg_clk_p[1] = (!l1clk_gate && (red_id[1] && fuse_niu_wen || fuse_red_reset));
2283 assign red_reg_clk_p[2] = (!l1clk_gate && (red_id[2] && fuse_niu_wen || fuse_red_reset));
2284 assign red_reg_clk_p[3] = (!l1clk_gate && (red_id[3] && fuse_niu_wen || fuse_red_reset));
2285
2286 assign fuse_red_data = fuse_niu_repair_value & {6{!fuse_red_reset}};
2287 assign fuse_red_enable = fuse_niu_repair_en && !fuse_red_reset;
2288
2289//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2290 n2_niu_dp_512x152s_redreg redreg_0 (
2291 .fuse_red_data (fuse_red_data),
2292 .fuse_red_enable (fuse_red_enable),
2293 .red_reg_clk_p (red_reg_clk_p[0]),
2294 .red_data_reg (red_data_reg_b0),
2295 .red_en_reg (red_en_reg_bk[0]),
2296 .red_value (red_value_b0),
2297 .repair_en (repair_en_bk[0])
2298 );
2299
2300 n2_niu_dp_512x152s_redreg redreg_1 (
2301 .fuse_red_data (fuse_red_data),
2302 .fuse_red_enable (fuse_red_enable),
2303 .red_reg_clk_p (red_reg_clk_p[1]),
2304 .red_data_reg (red_data_reg_b1),
2305 .red_en_reg (red_en_reg_bk[1]),
2306 .red_value (red_value_b1),
2307 .repair_en (repair_en_bk[1])
2308 );
2309
2310 n2_niu_dp_512x152s_redreg redreg_2 (
2311 .fuse_red_data (fuse_red_data),
2312 .fuse_red_enable (fuse_red_enable),
2313 .red_reg_clk_p (red_reg_clk_p[2]),
2314 .red_data_reg (red_data_reg_b2),
2315 .red_en_reg (red_en_reg_bk[2]),
2316 .red_value (red_value_b2),
2317 .repair_en (repair_en_bk[2])
2318 );
2319
2320 n2_niu_dp_512x152s_redreg redreg_3 (
2321 .fuse_red_data (fuse_red_data),
2322 .fuse_red_enable (fuse_red_enable),
2323 .red_reg_clk_p (red_reg_clk_p[3]),
2324 .red_data_reg (red_data_reg_b3),
2325 .red_en_reg (red_en_reg_bk[3]),
2326 .red_value (red_value_b3),
2327 .repair_en (repair_en_bk[3])
2328 );
2329
2330//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2331wire [5:0] niu_fuse_repair_value_b0;
2332wire [5:0] niu_fuse_repair_value_b1;
2333wire [5:0] niu_fuse_repair_value_b2;
2334wire [5:0] niu_fuse_repair_value_b3;
2335wire [5:0] or_val_b0;
2336wire [5:0] or_val_b1;
2337
2338 // assign niu_fuse_repair_value = (red_data_reg_b0 & {6{red_id[0]}}) |
2339 // (red_data_reg_b1 & {6{red_id[1]}}) |
2340 // (red_data_reg_b2 & {6{red_id[2]}}) |
2341 // (red_data_reg_b3 & {6{red_id[3]}});
2342
2343 niu512_and_macro__width_6 ava0 (.dout(niu_fuse_repair_value_b0), .din0(red_data_reg_b0), .din1({6{red_id[0]}}));
2344 niu512_and_macro__width_6 ava1 (.dout(niu_fuse_repair_value_b1), .din0(red_data_reg_b1), .din1({6{red_id[1]}}));
2345 niu512_and_macro__width_6 ava2 (.dout(niu_fuse_repair_value_b2), .din0(red_data_reg_b2), .din1({6{red_id[2]}}));
2346 niu512_and_macro__width_6 ava3 (.dout(niu_fuse_repair_value_b3), .din0(red_data_reg_b3), .din1({6{red_id[3]}}));
2347
2348 niu512_or_macro__width_6 ova0 (.dout(or_val_b0), .din0(niu_fuse_repair_value_b0), .din1(niu_fuse_repair_value_b1));
2349 niu512_or_macro__width_6 ova1 (.dout(or_val_b1), .din0(or_val_b0), .din1(niu_fuse_repair_value_b2));
2350 niu512_or_macro__width_6 ova2 (.dout(niu_fuse_repair_value), .din0(or_val_b1), .din1(niu_fuse_repair_value_b3));
2351
2352wire [3:0] niu_fuse_repair_en_bk;
2353wire [1:0] or_ena;
2354
2355 // assign niu_fuse_repair_en = (red_en_reg_bk[0] && red_id[0]) ||
2356 // (red_en_reg_bk[1] && red_id[1]) ||
2357 // (red_en_reg_bk[2] && red_id[2]) ||
2358 // (red_en_reg_bk[3] && red_id[3]);
2359
2360 niu512_and_macro__width_4 aen0 (.dout(niu_fuse_repair_en_bk), .din0(red_en_reg_bk[3:0]), .din1(red_id[3:0]) );
2361
2362 niu512_or_macro__width_1 oen0 (.dout(or_ena[0]), .din0(niu_fuse_repair_en_bk[0]),.din1(niu_fuse_repair_en_bk[1]));
2363 niu512_or_macro__width_1 oen1 (.dout(or_ena[1]), .din0(or_ena[0]), .din1(niu_fuse_repair_en_bk[2]));
2364 niu512_or_macro__width_1 oen2 (.dout(niu_fuse_repair_en),.din0(or_ena[1]), .din1(niu_fuse_repair_en_bk[3]));
2365
2366//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
2367// fixscan start:
2368
2369 assign dff_red_clr_m_scanin = scanin_red ;
2370 assign dff_wr_en_m_scanin = dff_red_clr_m_scanout ;
2371 assign dff_rid_m_scanin = dff_wr_en_m_scanout ;
2372 assign dff_rvalue_m_scanin = dff_rid_m_scanout ;
2373 assign dff_read_data_m_scanin = dff_rvalue_m_scanout ;
2374 assign scanout_red = dff_read_data_m_scanout ;
2375
2376// fixscan end
2377
2378endmodule
2379
2380
2381
2382
2383
2384
2385
2386// any PARAMS parms go into naming of macro
2387
2388module niu512_msff_ctl_macro__width_7 (
2389 din,
2390 l1clk,
2391 scan_in,
2392 siclk,
2393 soclk,
2394 dout,
2395 scan_out);
2396wire [6:0] fdin;
2397wire [6:1] sout;
2398
2399 input [6:0] din;
2400 input l1clk;
2401 input scan_in;
2402
2403
2404 input siclk;
2405 input soclk;
2406
2407 output [6:0] dout;
2408 output scan_out;
2409assign fdin[6:0] = din[6:0];
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427cl_sc1_msff_4x d0_0 (
2428.l1clk(l1clk),
2429.siclk(siclk),
2430.soclk(soclk),
2431.d(fdin[0]),
2432.si(sout[1]),
2433.so(scan_out),
2434.q(dout[0])
2435);
2436cl_sc1_msff_4x d0_1 (
2437.l1clk(l1clk),
2438.siclk(siclk),
2439.soclk(soclk),
2440.d(fdin[1]),
2441.si(sout[2]),
2442.so(sout[1]),
2443.q(dout[1])
2444);
2445cl_sc1_msff_4x d0_2 (
2446.l1clk(l1clk),
2447.siclk(siclk),
2448.soclk(soclk),
2449.d(fdin[2]),
2450.si(sout[3]),
2451.so(sout[2]),
2452.q(dout[2])
2453);
2454cl_sc1_msff_4x d0_3 (
2455.l1clk(l1clk),
2456.siclk(siclk),
2457.soclk(soclk),
2458.d(fdin[3]),
2459.si(sout[4]),
2460.so(sout[3]),
2461.q(dout[3])
2462);
2463cl_sc1_msff_4x d0_4 (
2464.l1clk(l1clk),
2465.siclk(siclk),
2466.soclk(soclk),
2467.d(fdin[4]),
2468.si(sout[5]),
2469.so(sout[4]),
2470.q(dout[4])
2471);
2472cl_sc1_msff_4x d0_5 (
2473.l1clk(l1clk),
2474.siclk(siclk),
2475.soclk(soclk),
2476.d(fdin[5]),
2477.si(sout[6]),
2478.so(sout[5]),
2479.q(dout[5])
2480);
2481cl_sc1_msff_4x d0_6 (
2482.l1clk(l1clk),
2483.siclk(siclk),
2484.soclk(soclk),
2485.d(fdin[6]),
2486.si(scan_in),
2487.so(sout[6]),
2488.q(dout[6])
2489);
2490
2491
2492
2493
2494endmodule
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508// any PARAMS parms go into naming of macro
2509
2510module niu512_msff_ctl_macro__width_2 (
2511 din,
2512 l1clk,
2513 scan_in,
2514 siclk,
2515 soclk,
2516 dout,
2517 scan_out);
2518wire [1:0] fdin;
2519wire [1:1] sout;
2520
2521 input [1:0] din;
2522 input l1clk;
2523 input scan_in;
2524
2525
2526 input siclk;
2527 input soclk;
2528
2529 output [1:0] dout;
2530 output scan_out;
2531assign fdin[1:0] = din[1:0];
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549cl_sc1_msff_4x d0_0 (
2550.l1clk(l1clk),
2551.siclk(siclk),
2552.soclk(soclk),
2553.d(fdin[0]),
2554.si(sout[1]),
2555.so(scan_out),
2556.q(dout[0])
2557);
2558cl_sc1_msff_4x d0_1 (
2559.l1clk(l1clk),
2560.siclk(siclk),
2561.soclk(soclk),
2562.d(fdin[1]),
2563.si(scan_in),
2564.so(sout[1]),
2565.q(dout[1])
2566);
2567
2568
2569
2570
2571endmodule
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585// any PARAMS parms go into naming of macro
2586
2587module niu512_msff_ctl_macro__width_1 (
2588 din,
2589 l1clk,
2590 scan_in,
2591 siclk,
2592 soclk,
2593 dout,
2594 scan_out);
2595wire [0:0] fdin;
2596
2597 input [0:0] din;
2598 input l1clk;
2599 input scan_in;
2600
2601
2602 input siclk;
2603 input soclk;
2604
2605 output [0:0] dout;
2606 output scan_out;
2607assign fdin[0:0] = din[0:0];
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625cl_sc1_msff_4x d0_0 (
2626.l1clk(l1clk),
2627.siclk(siclk),
2628.soclk(soclk),
2629.d(fdin[0]),
2630.si(scan_in),
2631.so(scan_out),
2632.q(dout[0])
2633);
2634
2635
2636
2637
2638endmodule
2639
2640
2641
2642
2643
2644
2645
2646
2647module n2_niu_dp_512x152s_redreg (
2648 fuse_red_data,
2649 fuse_red_enable,
2650 red_reg_clk_p,
2651 red_data_reg,
2652 red_en_reg,
2653 red_value,
2654 repair_en);
2655
2656input [5:0] fuse_red_data;
2657input fuse_red_enable;
2658input red_reg_clk_p;
2659
2660output [5:0] red_data_reg; // to repair output
2661output red_en_reg;
2662output [5:0] red_value; // to subbank
2663output repair_en;
2664
2665wire [5:0] red_value;
2666wire repair_en;
2667
2668wire [5:0] red_data_reg;
2669wire red_en_reg;
2670
2671wire red_en_reg1;
2672
2673
2674//////////////////////////////
2675// Redundancy Register //
2676//////////////////////////////
2677
2678// `ifdef NOINITMEM
2679// `else
2680// // Initialize the arrays.
2681// initial begin
2682// red_data_reg = {6{1'h0}};
2683// red_en_reg = 1'h0;
2684// end
2685// `endif
2686
2687// always @(posedge red_reg_clk_p) begin
2688// red_data_reg <= fuse_red_data;
2689// red_en_reg <= fuse_red_enable;
2690// end
2691
2692cl_sc1_msff_4x e_r0 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_enable), .q(red_en_reg));
2693cl_sc1_msff_4x e_r1 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_enable), .q(red_en_reg1));
2694
2695cl_sc1_msff_4x d_r0 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[0]),.q(red_data_reg[0]));
2696cl_sc1_msff_4x d_r1 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[1]),.q(red_data_reg[1]));
2697cl_sc1_msff_4x d_r2 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[2]),.q(red_data_reg[2]));
2698cl_sc1_msff_4x d_r3 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[3]),.q(red_data_reg[3]));
2699cl_sc1_msff_4x d_r4 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[4]),.q(red_data_reg[4]));
2700cl_sc1_msff_4x d_r5 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[5]),.q(red_data_reg[5]));
2701
2702// assign repair_en = red_en_reg;
2703
2704 niu512_and_macro__width_1 a0 (.dout(repair_en), .din0(red_en_reg), .din1(red_en_reg1));
2705 assign red_value = red_data_reg;
2706
2707endmodule
2708
2709
2710
2711//
2712// and macro for ports = 2,3,4
2713//
2714//
2715
2716
2717
2718
2719
2720module niu512_and_macro__width_6 (
2721 din0,
2722 din1,
2723 dout);
2724wire [5:0] nandout;
2725
2726 input [5:0] din0;
2727 input [5:0] din1;
2728 output [5:0] dout;
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738cl_u1_nand2_1x d0_0 (
2739.in0(din0[0]),
2740.in1(din1[0]),
2741.out(nandout[0])
2742);
2743
2744cl_u1_nand2_1x d0_1 (
2745.in0(din0[1]),
2746.in1(din1[1]),
2747.out(nandout[1])
2748);
2749
2750cl_u1_nand2_1x d0_2 (
2751.in0(din0[2]),
2752.in1(din1[2]),
2753.out(nandout[2])
2754);
2755
2756cl_u1_nand2_1x d0_3 (
2757.in0(din0[3]),
2758.in1(din1[3]),
2759.out(nandout[3])
2760);
2761
2762cl_u1_nand2_1x d0_4 (
2763.in0(din0[4]),
2764.in1(din1[4]),
2765.out(nandout[4])
2766);
2767
2768cl_u1_nand2_1x d0_5 (
2769.in0(din0[5]),
2770.in1(din1[5]),
2771.out(nandout[5])
2772);
2773
2774cl_u1_inv_1x d1_0 (
2775.in(nandout[0]),
2776.out(dout[0])
2777);
2778cl_u1_inv_1x d1_1 (
2779.in(nandout[1]),
2780.out(dout[1])
2781);
2782cl_u1_inv_1x d1_2 (
2783.in(nandout[2]),
2784.out(dout[2])
2785);
2786cl_u1_inv_1x d1_3 (
2787.in(nandout[3]),
2788.out(dout[3])
2789);
2790cl_u1_inv_1x d1_4 (
2791.in(nandout[4]),
2792.out(dout[4])
2793);
2794cl_u1_inv_1x d1_5 (
2795.in(nandout[5]),
2796.out(dout[5])
2797);
2798
2799
2800
2801
2802endmodule
2803
2804
2805
2806
2807
2808//
2809// or macro for ports = 2,3
2810//
2811//
2812
2813
2814
2815
2816
2817module niu512_or_macro__width_6 (
2818 din0,
2819 din1,
2820 dout);
2821wire [5:0] norout;
2822
2823 input [5:0] din0;
2824 input [5:0] din1;
2825 output [5:0] dout;
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835cl_u1_nor2_1x d0_0 (
2836.in0(din0[0]),
2837.in1(din1[0]),
2838.out(norout[0])
2839);
2840
2841cl_u1_nor2_1x d0_1 (
2842.in0(din0[1]),
2843.in1(din1[1]),
2844.out(norout[1])
2845);
2846
2847cl_u1_nor2_1x d0_2 (
2848.in0(din0[2]),
2849.in1(din1[2]),
2850.out(norout[2])
2851);
2852
2853cl_u1_nor2_1x d0_3 (
2854.in0(din0[3]),
2855.in1(din1[3]),
2856.out(norout[3])
2857);
2858
2859cl_u1_nor2_1x d0_4 (
2860.in0(din0[4]),
2861.in1(din1[4]),
2862.out(norout[4])
2863);
2864
2865cl_u1_nor2_1x d0_5 (
2866.in0(din0[5]),
2867.in1(din1[5]),
2868.out(norout[5])
2869);
2870
2871cl_u1_inv_1x d1_0 (
2872.in(norout[0]),
2873.out(dout[0])
2874);
2875cl_u1_inv_1x d1_1 (
2876.in(norout[1]),
2877.out(dout[1])
2878);
2879cl_u1_inv_1x d1_2 (
2880.in(norout[2]),
2881.out(dout[2])
2882);
2883cl_u1_inv_1x d1_3 (
2884.in(norout[3]),
2885.out(dout[3])
2886);
2887cl_u1_inv_1x d1_4 (
2888.in(norout[4]),
2889.out(dout[4])
2890);
2891cl_u1_inv_1x d1_5 (
2892.in(norout[5]),
2893.out(dout[5])
2894);
2895
2896
2897
2898
2899endmodule
2900
2901
2902
2903
2904
2905//
2906// and macro for ports = 2,3,4
2907//
2908//
2909
2910
2911
2912
2913
2914module niu512_and_macro__width_4 (
2915 din0,
2916 din1,
2917 dout);
2918wire [3:0] nandout;
2919
2920 input [3:0] din0;
2921 input [3:0] din1;
2922 output [3:0] dout;
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932cl_u1_nand2_1x d0_0 (
2933.in0(din0[0]),
2934.in1(din1[0]),
2935.out(nandout[0])
2936);
2937
2938cl_u1_nand2_1x d0_1 (
2939.in0(din0[1]),
2940.in1(din1[1]),
2941.out(nandout[1])
2942);
2943
2944cl_u1_nand2_1x d0_2 (
2945.in0(din0[2]),
2946.in1(din1[2]),
2947.out(nandout[2])
2948);
2949
2950cl_u1_nand2_1x d0_3 (
2951.in0(din0[3]),
2952.in1(din1[3]),
2953.out(nandout[3])
2954);
2955
2956cl_u1_inv_1x d1_0 (
2957.in(nandout[0]),
2958.out(dout[0])
2959);
2960cl_u1_inv_1x d1_1 (
2961.in(nandout[1]),
2962.out(dout[1])
2963);
2964cl_u1_inv_1x d1_2 (
2965.in(nandout[2]),
2966.out(dout[2])
2967);
2968cl_u1_inv_1x d1_3 (
2969.in(nandout[3]),
2970.out(dout[3])
2971);
2972
2973
2974
2975
2976endmodule
2977
2978
2979
2980
2981
2982//
2983// or macro for ports = 2,3
2984//
2985//
2986
2987
2988
2989
2990
2991module niu512_or_macro__width_1 (
2992 din0,
2993 din1,
2994 dout);
2995wire [0:0] norout;
2996
2997 input [0:0] din0;
2998 input [0:0] din1;
2999 output [0:0] dout;
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009cl_u1_nor2_1x d0_0 (
3010.in0(din0[0]),
3011.in1(din1[0]),
3012.out(norout[0])
3013);
3014
3015cl_u1_inv_1x d1_0 (
3016.in(norout[0]),
3017.out(dout[0])
3018);
3019
3020
3021
3022
3023endmodule
3024
3025
3026
3027
Full OpenSPARC design & verification tarball including full HDL.