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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / libs / n2sram / sp / n2_niu_sp_4096x9s_cust_l / n2_niu_sp_4096x9s_cust / rtl / n2_niu_sp_4096x9s_cust.v
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86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: n2_niu_sp_4096x9s_cust.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module n2_niu_sp_4096x9s_cust (
36 reset,
37 tcu_aclk,
38 tcu_bclk,
39 pce,
40 tcu_pce_ov,
41 tcu_scan_en,
42 tcu_se_scancollar_in,
43 tcu_se_scancollar_out,
44 tcu_array_wr_inhibit,
45 scan_in,
46 scan_out,
47 hdr_sram_rvalue,
48 hdr_sram_rid,
49 hdr_sram_wr_en,
50 hdr_sram_red_clr,
51 sram_hdr_read_data,
52 rw_adr,
53 wr_en,
54 rd_en,
55 din,
56 dout,
57 l2clk);
58wire repair_scanout;
59
60
61input reset;
62input tcu_aclk;
63input tcu_bclk;
64input pce;
65input tcu_pce_ov;
66input tcu_scan_en;
67input tcu_se_scancollar_in;
68input tcu_se_scancollar_out;
69input tcu_array_wr_inhibit;
70input scan_in;
71output scan_out;
72
73input [5:0] hdr_sram_rvalue;
74input hdr_sram_rid;
75input hdr_sram_wr_en;
76input hdr_sram_red_clr;
77output [5:0] sram_hdr_read_data;
78
79input [11:0] rw_adr;
80input wr_en;
81input rd_en;
82input [8:0] din;
83output [8:0] dout;
84input l2clk;
85
86// 0in set_clock l2clk
87// 0in bits_on -var {rd_en,wr_en} -max 1 -message "niu_sp_4096x9: Attempt to read AND write on same cycle" -group mbist_mode
88
89wire [5:0] hdr_sram_rvalue;
90wire [5:0] sram_hdr_read_data;
91wire [11:0] rw_adr;
92wire [8:0] din;
93wire [8:0] dout;
94wire [1:0] repair_en_bk;
95wire [4:0] red_value_b0, red_value_b1;
96
97n2_niu_sp_4096x9s_bank niu_sp_4096x9s_bank (
98 .reset (reset),
99 .tcu_aclk (tcu_aclk),
100 .tcu_bclk (tcu_bclk),
101 .pce (pce),
102 .tcu_pce_ov (tcu_pce_ov),
103 .tcu_scan_en (tcu_scan_en),
104 .tcu_se_scancollar_in (tcu_se_scancollar_in),
105 .tcu_array_wr_inhibit (tcu_array_wr_inhibit),
106 .l2clk (l2clk),
107 .wr_en (wr_en),
108 .rw_adr (rw_adr),
109 .rd_en (rd_en),
110 .din (din),
111 .scan_in (repair_scanout),
112 .scan_out (scan_out),
113 .red_value_b0 (red_value_b0),
114 .red_value_b1 (red_value_b1),
115 .repair_en_bk (repair_en_bk),
116 .dout (dout));
117
118n2_niu_sp_4096x9s_repair repair (
119 .tcu_aclk (tcu_aclk),
120 .tcu_bclk (tcu_bclk),
121 .pce (pce),
122 .tcu_pce_ov (tcu_pce_ov),
123 .tcu_scan_en (tcu_scan_en),
124 .tcu_se_scancollar_in (tcu_se_scancollar_in),
125 .tcu_se_scancollar_out (tcu_se_scancollar_out),
126 .tcu_array_wr_inhibit (tcu_array_wr_inhibit),
127 .scan_in (scan_in),
128 .hdr_sram_rvalue (hdr_sram_rvalue),
129 .hdr_sram_rid (hdr_sram_rid),
130 .hdr_sram_wr_en (hdr_sram_wr_en),
131 .hdr_sram_red_clr (hdr_sram_red_clr),
132 .l2clk (l2clk),
133 .sram_hdr_read_data (sram_hdr_read_data),
134 .red_value_b0 (red_value_b0),
135 .red_value_b1 (red_value_b1),
136 .repair_en_bk (repair_en_bk),
137 .scan_out (repair_scanout));
138
139endmodule
140
141
142
143
144
145module n2_niu_sp_4096x9s_bank (
146 reset,
147 din,
148 rw_adr,
149 rd_en,
150 wr_en,
151 tcu_aclk,
152 tcu_bclk,
153 pce,
154 tcu_pce_ov,
155 tcu_scan_en,
156 tcu_se_scancollar_in,
157 tcu_array_wr_inhibit,
158 l2clk,
159 scan_in,
160 red_value_b0,
161 red_value_b1,
162 repair_en_bk,
163 dout,
164 scan_out);
165wire l1clk_in_en;
166wire l1clk_in;
167wire l1clk_andclk_in_en;
168wire andclk;
169wire dff_rd_en_m_scanin;
170wire dff_rd_en_m_scanout;
171wire rd_en_m_noinhi;
172wire dff_wr_en_m_scanin;
173wire dff_wr_en_m_scanout;
174wire wr_en_m_noinhi;
175wire [3:0] spare_f;
176wire [3:0] spare_scanin;
177wire [3:0] spare_scanout;
178
179
180
181input reset;
182input [8:0] din;
183input [11:0] rw_adr;
184input rd_en;
185input wr_en;
186input tcu_aclk;
187input tcu_bclk;
188input pce;
189input tcu_pce_ov;
190input tcu_scan_en;
191input tcu_se_scancollar_in;
192input tcu_array_wr_inhibit;
193input l2clk;
194input scan_in;
195
196input [4:0] red_value_b0; // to subbank
197input [4:0] red_value_b1;
198input [1:0] repair_en_bk;
199
200output [8:0] dout;
201output scan_out;
202
203wire [8:0] din;
204wire [11:0] rw_adr;
205wire [4:0] red_value_b0; // to subbank
206wire [4:0] red_value_b1;
207wire [1:0] repair_en_bk;
208wire [8:0] dout;
209
210wire [11:0] rw_adr_f;
211wire [11:0] dff_rw_adr_f_scanin;
212wire [11:0] dff_rw_adr_f_scanout;
213wire [8:0] din_f;
214wire [8:0] din_scanin;
215wire [8:0] din_scanout;
216wire [8:0] dout_up, dout_dn;
217wire siclk;
218wire soclk;
219
220assign siclk=tcu_aclk;
221assign soclk=tcu_bclk;
222
223//cl_sc1_l1hdr_8x l1ch_in (
224// .l2clk (l2clk),
225// .pce (pce),
226// .l1clk (l1clk_in),
227// .se (tcu_se_scancollar_in),
228// .pce_ov (tcu_pce_ov),
229// .stop (1'b0) );
230
231//cl_sc1_l1hdr_8x andclk_in ( .l2clk (l2clk),
232// .pce (pce),
233// .l1clk (andclk),
234// .se (tcu_scan_en),
235// .pce_ov (tcu_pce_ov),
236// .stop (1'b0) );
237
238///////////////////////////////////
239// decomposed l1hdr for l1clk_in
240///////////////////////////////////
241
242cl_mc1_l1enable_12x l1ch_in_l1en (
243 .l2clk (l2clk),
244 .pce (pce),
245 .pce_ov (tcu_pce_ov),
246 .l1en (l1clk_in_en)
247 );
248
249cl_mc1_l1driver_12x l1ch_in_l1drvr (
250 .se (tcu_se_scancollar_in),
251 .l1en (l1clk_in_en),
252 .l1clk (l1clk_in),
253 .l2clk(l2clk)
254 );
255
256///////////////////////////////////
257// decomposed l1hdr for andclk_in
258///////////////////////////////////
259
260cl_mc1_l1enable_12x andclk_in_l1en (
261 .l2clk (l2clk),
262 .pce (pce),
263 .pce_ov (tcu_pce_ov),
264 .l1en (l1clk_andclk_in_en)
265 );
266
267cl_mc1_l1driver_12x andclk_in_l1drvr (
268 .se (tcu_scan_en),
269 .l1en (l1clk_andclk_in_en),
270 .l1clk (andclk),
271 .l2clk(l2clk)
272 );
273
274
275wire reset_l = ~reset;
276
277cl_sc1_msff_syrst_4x rw_adr_m00 (.d(rw_adr[0 ]),.si(dff_rw_adr_f_scanin[0 ]),.q(rw_adr_f[0 ]),.so(dff_rw_adr_f_scanout[0]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
278cl_sc1_msff_syrst_4x rw_adr_m01 (.d(rw_adr[1 ]),.si(dff_rw_adr_f_scanin[1 ]),.q(rw_adr_f[1 ]),.so(dff_rw_adr_f_scanout[1]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
279cl_sc1_msff_syrst_4x rw_adr_m02 (.d(rw_adr[2 ]),.si(dff_rw_adr_f_scanin[2 ]),.q(rw_adr_f[2 ]),.so(dff_rw_adr_f_scanout[2]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
280cl_sc1_msff_syrst_4x rw_adr_m03 (.d(rw_adr[3 ]),.si(dff_rw_adr_f_scanin[3 ]),.q(rw_adr_f[3 ]),.so(dff_rw_adr_f_scanout[3]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
281cl_sc1_msff_syrst_4x rw_adr_m04 (.d(rw_adr[4 ]),.si(dff_rw_adr_f_scanin[4 ]),.q(rw_adr_f[4 ]),.so(dff_rw_adr_f_scanout[4]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
282cl_sc1_msff_syrst_4x rw_adr_m05 (.d(rw_adr[5 ]),.si(dff_rw_adr_f_scanin[5 ]),.q(rw_adr_f[5 ]),.so(dff_rw_adr_f_scanout[5]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
283cl_sc1_msff_syrst_4x rw_adr_m06 (.d(rw_adr[6 ]),.si(dff_rw_adr_f_scanin[6 ]),.q(rw_adr_f[6 ]),.so(dff_rw_adr_f_scanout[6]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
284cl_sc1_msff_syrst_4x rw_adr_m07 (.d(rw_adr[7 ]),.si(dff_rw_adr_f_scanin[7 ]),.q(rw_adr_f[7 ]),.so(dff_rw_adr_f_scanout[7]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
285cl_sc1_msff_syrst_4x rw_adr_m08 (.d(rw_adr[8 ]),.si(dff_rw_adr_f_scanin[8 ]),.q(rw_adr_f[8 ]),.so(dff_rw_adr_f_scanout[8]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
286cl_sc1_msff_syrst_4x rw_adr_m09 (.d(rw_adr[9 ]),.si(dff_rw_adr_f_scanin[9 ]),.q(rw_adr_f[9 ]),.so(dff_rw_adr_f_scanout[9]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
287cl_sc1_msff_syrst_4x rw_adr_m10 (.d(rw_adr[10]),.si(dff_rw_adr_f_scanin[10]),.q(rw_adr_f[10]),.so(dff_rw_adr_f_scanout[10]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
288cl_sc1_msff_syrst_4x rw_adr_m11 (.d(rw_adr[11]),.si(dff_rw_adr_f_scanin[11]),.q(rw_adr_f[11]),.so(dff_rw_adr_f_scanout[11]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
289
290cl_mc1_sram_msff_mo_8x rd_en_m0 (.d(rd_en & reset_l),.si(dff_rd_en_m_scanin),.q(),.so(dff_rd_en_m_scanout),.and_clk(andclk),.q_l(),.mq(rd_en_m_noinhi),.mq_l(),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk) );
291cl_mc1_sram_msff_mo_8x wr_en_m0 (.d(wr_en & reset_l),.si(dff_wr_en_m_scanin),.q(),.so(dff_wr_en_m_scanout),.and_clk(andclk),.q_l(),.mq(wr_en_m_noinhi),.mq_l(),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk) );
292
293//cl_sc1_msff_syrst_4x rd_en_m0 (.d(rd_en),.si(dff_rd_en_m_scanin),.q(rd_en_m_noinhi),.so(dff_rd_en_m_scanout),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
294//cl_sc1_msff_syrst_4x wr_en_m0 (.d(wr_en),.si(dff_wr_en_m_scanin),.q(wr_en_m_noinhi),.so(dff_wr_en_m_scanout),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
295
296cl_sc1_msff_syrst_4x spare_0 (.d(spare_f[0] ),.si(spare_scanin[0]),.q(spare_f[0]),.so(spare_scanout[0]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
297cl_sc1_msff_syrst_4x spare_1 (.d(spare_f[1] ),.si(spare_scanin[1]),.q(spare_f[1]),.so(spare_scanout[1]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
298cl_sc1_msff_syrst_4x spare_2 (.d(spare_f[2] ),.si(spare_scanin[2]),.q(spare_f[2]),.so(spare_scanout[2]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
299cl_sc1_msff_syrst_4x spare_3 (.d(spare_f[3] ),.si(spare_scanin[3]),.q(spare_f[3]),.so(spare_scanout[3]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
300
301cl_sc1_msff_syrst_4x din_0 (.d(din[0]),.si(din_scanin[0]),.q(din_f[0]),.so(din_scanout[0]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
302cl_sc1_msff_syrst_4x din_1 (.d(din[1]),.si(din_scanin[1]),.q(din_f[1]),.so(din_scanout[1]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
303cl_sc1_msff_syrst_4x din_2 (.d(din[2]),.si(din_scanin[2]),.q(din_f[2]),.so(din_scanout[2]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
304cl_sc1_msff_syrst_4x din_3 (.d(din[3]),.si(din_scanin[3]),.q(din_f[3]),.so(din_scanout[3]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
305cl_sc1_msff_syrst_4x din_4 (.d(din[4]),.si(din_scanin[4]),.q(din_f[4]),.so(din_scanout[4]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
306cl_sc1_msff_syrst_4x din_5 (.d(din[5]),.si(din_scanin[5]),.q(din_f[5]),.so(din_scanout[5]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
307cl_sc1_msff_syrst_4x din_6 (.d(din[6]),.si(din_scanin[6]),.q(din_f[6]),.so(din_scanout[6]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
308cl_sc1_msff_syrst_4x din_7 (.d(din[7]),.si(din_scanin[7]),.q(din_f[7]),.so(din_scanout[7]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
309cl_sc1_msff_syrst_4x din_8 (.d(din[8]),.si(din_scanin[8]),.q(din_f[8]),.so(din_scanout[8]),.reset(reset_l),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk));
310
311
312wire rd_en_m = rd_en_m_noinhi && ~tcu_array_wr_inhibit;
313wire wr_en_m = wr_en_m_noinhi && ~tcu_array_wr_inhibit;
314
315wire wr_en_m_0 = wr_en_m && ~rw_adr_f[11];
316wire wr_en_m_1 = wr_en_m && rw_adr_f[11];
317
318n2_niu_sp_4096x9s_array array_dn (
319 .l1clk (l2clk),
320 .dout (dout_dn),
321 .din (din_f),
322 .addr (rw_adr_f[10:0]),
323 .rd_en (rd_en_m && ~rw_adr_f[11]),
324 .wr_en (wr_en_m_0),
325 .red_value_b (red_value_b1),
326 .repair_en_bk (repair_en_bk[1]) );
327
328n2_niu_sp_4096x9s_array array_up (
329 .l1clk (l2clk),
330 .dout (dout_up),
331 .din (din_f),
332 .addr (rw_adr_f[10:0]),
333 .rd_en (rd_en_m && rw_adr_f[11]),
334 .wr_en (wr_en_m_1),
335 .red_value_b (red_value_b0),
336 .repair_en_bk (repair_en_bk[0]) );
337
338// Final mux stage
339
340 assign dout[0] = rw_adr_f[11] && dout_up[0] || ~rw_adr_f[11] && dout_dn[0];
341 assign dout[1] = rw_adr_f[11] && dout_up[1] || ~rw_adr_f[11] && dout_dn[1];
342 assign dout[2] = rw_adr_f[11] && dout_up[2] || ~rw_adr_f[11] && dout_dn[2];
343 assign dout[3] = rw_adr_f[11] && dout_up[3] || ~rw_adr_f[11] && dout_dn[3];
344 assign dout[4] = rw_adr_f[11] && dout_up[4] || ~rw_adr_f[11] && dout_dn[4];
345 assign dout[5] = rw_adr_f[11] && dout_up[5] || ~rw_adr_f[11] && dout_dn[5];
346 assign dout[6] = rw_adr_f[11] && dout_up[6] || ~rw_adr_f[11] && dout_dn[6];
347 assign dout[7] = rw_adr_f[11] && dout_up[7] || ~rw_adr_f[11] && dout_dn[7];
348 assign dout[8] = rw_adr_f[11] && dout_up[8] || ~rw_adr_f[11] && dout_dn[8];
349
350// scanfix start
351
352assign din_scanin[8]= scan_in;
353assign din_scanin[7]= din_scanout[8] ;
354assign din_scanin[6]= din_scanout[7] ;
355assign din_scanin[5]= din_scanout[6] ;
356assign din_scanin[4]= din_scanout[5] ;
357assign din_scanin[3]= din_scanout[4] ;
358assign din_scanin[2]= din_scanout[3] ;
359assign din_scanin[1]= din_scanout[2] ;
360assign din_scanin[0]= din_scanout[1] ;
361assign dff_rw_adr_f_scanin[11]= din_scanout[0];
362assign dff_rw_adr_f_scanin[10]= dff_rw_adr_f_scanout[11];
363assign dff_rw_adr_f_scanin[9 ]= dff_rw_adr_f_scanout[10];
364assign dff_rw_adr_f_scanin[8 ]= dff_rw_adr_f_scanout[9 ];
365assign dff_rw_adr_f_scanin[7 ]= dff_rw_adr_f_scanout[8 ];
366assign dff_rw_adr_f_scanin[6 ]= dff_rw_adr_f_scanout[7 ];
367assign dff_rw_adr_f_scanin[5 ]= dff_rw_adr_f_scanout[6 ];
368assign dff_rw_adr_f_scanin[4 ]= dff_rw_adr_f_scanout[5 ];
369assign dff_rw_adr_f_scanin[3 ]= dff_rw_adr_f_scanout[4 ];
370assign dff_rw_adr_f_scanin[2 ]= dff_rw_adr_f_scanout[3 ];
371assign dff_rw_adr_f_scanin[1 ]= dff_rw_adr_f_scanout[2 ];
372assign dff_rw_adr_f_scanin[0 ]= dff_rw_adr_f_scanout[1 ];
373assign dff_rd_en_m_scanin= dff_rw_adr_f_scanout[0 ];
374assign dff_wr_en_m_scanin= dff_rd_en_m_scanout;
375assign spare_scanin[0] = dff_wr_en_m_scanout;
376assign spare_scanin[1] = spare_scanout[0];
377assign spare_scanin[2] = spare_scanout[1];
378assign spare_scanin[3] = spare_scanout[2];
379assign scan_out= spare_scanout[3];
380
381// scanfix end
382
383endmodule
384
385
386
387module n2_niu_sp_4096x9s_array (
388 l1clk,
389 din,
390 dout,
391 addr,
392 rd_en,
393 wr_en,
394 red_value_b,
395 repair_en_bk);
396
397
398input l1clk;
399input [8:0] din;
400output [8:0] dout;
401input [10:0] addr;
402input rd_en;
403input wr_en;
404input [4:0] red_value_b;
405input repair_en_bk;
406
407wire [18:0] dout_arr;
408wire [18:0] dout_repwrdmux;
409wire [18:0] wr_en_bit;
410wire [17:0] doutrdmux;
411wire [17:0] repair_out_chain;
412
413n2_niu_sp_4096x9s_128x152_mem array_2k ( l1clk,
414 dout_repwrdmux,
415 dout_arr,
416 addr[9:0],
417 {18{rd_en}},
418 wr_en_bit);
419
420repwrmux wrmux ( din,
421 dout_repwrdmux,
422 repair_out_chain[17:0]);
423
424repwrselmux wrselmux ( .wr_en (wr_en),
425 .wrseldout (wr_en_bit),
426 .addr10 (addr[10]),
427 .repsel (repair_out_chain[17:0]) );
428
429reprdmux rdselmux ( dout_arr,
430 doutrdmux,
431 repair_out_chain[17:0]);
432
433repdec_5_32 rep_dec ( red_value_b,
434 repair_en_bk,
435 repair_out_chain);
436
437assign dout[0] = addr[10] && doutrdmux[1 ] || ~addr[10] && doutrdmux[0 ];
438assign dout[1] = addr[10] && doutrdmux[3 ] || ~addr[10] && doutrdmux[2 ];
439assign dout[2] = addr[10] && doutrdmux[5 ] || ~addr[10] && doutrdmux[4 ];
440assign dout[3] = addr[10] && doutrdmux[7 ] || ~addr[10] && doutrdmux[6 ];
441assign dout[4] = addr[10] && doutrdmux[9 ] || ~addr[10] && doutrdmux[8 ];
442assign dout[5] = addr[10] && doutrdmux[11] || ~addr[10] && doutrdmux[10];
443assign dout[6] = addr[10] && doutrdmux[13] || ~addr[10] && doutrdmux[12];
444assign dout[7] = addr[10] && doutrdmux[15] || ~addr[10] && doutrdmux[14];
445assign dout[8] = addr[10] && doutrdmux[17] || ~addr[10] && doutrdmux[16];
446
447endmodule
448
449
450
451
452module n2_niu_sp_4096x9s_128x152_mem (
453 l1clk,
454 din,
455 dout,
456 addr,
457 rd_en,
458 wr_en
459);
460 input l1clk;
461 input [18:0] din;
462 output [18:0] dout;
463 input [9:0] addr;
464 input [17:0] rd_en;
465 input [18:0] wr_en;
466
467n2_niu_sp_4096x9s_128x8_halfbit b0 (l1clk,din[0 ],dout[0 ],addr,rd_en[0 ],wr_en[0 ]);
468n2_niu_sp_4096x9s_128x8_halfbit b1 (l1clk,din[1 ],dout[1 ],addr,rd_en[1 ],wr_en[1 ]);
469n2_niu_sp_4096x9s_128x8_halfbit b2 (l1clk,din[2 ],dout[2 ],addr,rd_en[2 ],wr_en[2 ]);
470n2_niu_sp_4096x9s_128x8_halfbit b3 (l1clk,din[3 ],dout[3 ],addr,rd_en[3 ],wr_en[3 ]);
471n2_niu_sp_4096x9s_128x8_halfbit b4 (l1clk,din[4 ],dout[4 ],addr,rd_en[4 ],wr_en[4 ]);
472n2_niu_sp_4096x9s_128x8_halfbit b5 (l1clk,din[5 ],dout[5 ],addr,rd_en[5 ],wr_en[5 ]);
473n2_niu_sp_4096x9s_128x8_halfbit b6 (l1clk,din[6 ],dout[6 ],addr,rd_en[6 ],wr_en[6 ]);
474n2_niu_sp_4096x9s_128x8_halfbit b7 (l1clk,din[7 ],dout[7 ],addr,rd_en[7 ],wr_en[7 ]);
475n2_niu_sp_4096x9s_128x8_halfbit b8 (l1clk,din[8 ],dout[8 ],addr,rd_en[8 ],wr_en[8 ]);
476n2_niu_sp_4096x9s_128x8_halfbit b9 (l1clk,din[9 ],dout[9 ],addr,rd_en[9 ],wr_en[9 ]);
477n2_niu_sp_4096x9s_128x8_halfbit b10 (l1clk,din[10],dout[10],addr,rd_en[10],wr_en[10]);
478n2_niu_sp_4096x9s_128x8_halfbit b11 (l1clk,din[11],dout[11],addr,rd_en[11],wr_en[11]);
479n2_niu_sp_4096x9s_128x8_halfbit b12 (l1clk,din[12],dout[12],addr,rd_en[12],wr_en[12]);
480n2_niu_sp_4096x9s_128x8_halfbit b13 (l1clk,din[13],dout[13],addr,rd_en[13],wr_en[13]);
481n2_niu_sp_4096x9s_128x8_halfbit b14 (l1clk,din[14],dout[14],addr,rd_en[14],wr_en[14]);
482n2_niu_sp_4096x9s_128x8_halfbit b15 (l1clk,din[15],dout[15],addr,rd_en[15],wr_en[15]);
483n2_niu_sp_4096x9s_128x8_halfbit b16 (l1clk,din[16],dout[16],addr,rd_en[16],wr_en[16]);
484n2_niu_sp_4096x9s_128x8_halfbit b17 (l1clk,din[17],dout[17],addr,rd_en[17],wr_en[17]);
485n2_niu_sp_4096x9s_128x8_halfbit rep (l1clk,din[18],dout[18],addr,rd_en[17],wr_en[18]);
486
487endmodule
488
489
490
491module n2_niu_sp_4096x9s_128x8_halfbit (
492 l1clk,
493 din,
494 dout,
495 addr,
496 rd_en,
497 wr_en);
498
499input l1clk;
500input din;
501output dout;
502input [9:0] addr;
503input rd_en;
504input wr_en;
505
506reg dout;
507reg dout1;
508reg [7:0] din_mem;
509reg [7:0] rd_en_col;
510reg [7:0] wr_en_col;
511wire din;
512wire [7:0] dout_mem;
513
514n2_niu_sp_4096x9s_128x8_memory mem ( .l1clk (l1clk),
515 .din (din_mem),
516 .dout (dout_mem),
517 .rw_addr(addr[6:0]),
518 .rd_en (rd_en_col),
519 .wr_en (wr_en_col));
520always @ (addr[9:7] or rd_en)
521 begin
522 if(!rd_en)
523 rd_en_col=8'b00000000;
524 else if(rd_en)
525 case(addr[9:7])
526 3'h0: rd_en_col=8'b00000001;
527 3'h1: rd_en_col=8'b00000010;
528 3'h2: rd_en_col=8'b00000100;
529 3'h3: rd_en_col=8'b00001000;
530 3'h4: rd_en_col=8'b00010000;
531 3'h5: rd_en_col=8'b00100000;
532 3'h6: rd_en_col=8'b01000000;
533 3'h7: rd_en_col=8'b10000000;
534 endcase
535
536 end
537
538always @ (addr[9:7] or wr_en)
539 begin
540 if(!wr_en)
541 wr_en_col=8'b00000000;
542 else if(wr_en)
543 case(addr[9:7])
544 3'h0: wr_en_col=8'b00000001;
545 3'h1: wr_en_col=8'b00000010;
546 3'h2: wr_en_col=8'b00000100;
547 3'h3: wr_en_col=8'b00001000;
548 3'h4: wr_en_col=8'b00010000;
549 3'h5: wr_en_col=8'b00100000;
550 3'h6: wr_en_col=8'b01000000;
551 3'h7: wr_en_col=8'b10000000;
552 endcase
553
554 end
555
556
557always @ (addr or dout_mem)
558 begin
559 case (addr[9:7])
560 3'h0: dout1=dout_mem[0];
561 3'h1: dout1=dout_mem[1];
562 3'h2: dout1=dout_mem[2];
563 3'h3: dout1=dout_mem[3];
564 3'h4: dout1=dout_mem[4];
565 3'h5: dout1=dout_mem[5];
566 3'h6: dout1=dout_mem[6];
567 3'h7: dout1=dout_mem[7];
568 endcase
569 end
570
571always @ (addr or din)
572 begin
573 case (addr[9:7])
574 3'h0: din_mem=8'b00000001 & {8{din}};
575 3'h1: din_mem=8'b00000010 & {8{din}};
576 3'h2: din_mem=8'b00000100 & {8{din}};
577 3'h3: din_mem=8'b00001000 & {8{din}};
578 3'h4: din_mem=8'b00010000 & {8{din}};
579 3'h5: din_mem=8'b00100000 & {8{din}};
580 3'h6: din_mem=8'b01000000 & {8{din}};
581 3'h7: din_mem=8'b10000000 & {8{din}};
582 endcase
583 end
584// sa and latch
585always @(rd_en or addr or l1clk or dout1) begin
586 if(rd_en & l1clk)
587 dout = dout1;
588end
589
590// Initialize latches
591
592`ifndef NOINITMEM
593initial begin
594 dout=1'b0;
595end
596`endif // NOINITMEM
597
598endmodule
599
600
601module n2_niu_sp_4096x9s_128x8_memory (
602 l1clk,
603 din,
604 dout,
605 rw_addr,
606 rd_en,
607 wr_en
608);
609input l1clk;
610input [7:0] din;
611input [6:0] rw_addr;
612input [7:0] rd_en;
613input [7:0] wr_en;
614output [7:0] dout;
615
616n2_niu_sp_4096x9s_128x1_memory b0 (l1clk,din[0],dout[0],rw_addr,rd_en[0],wr_en[0]);
617n2_niu_sp_4096x9s_128x1_memory b1 (l1clk,din[1],dout[1],rw_addr,rd_en[1],wr_en[1]);
618n2_niu_sp_4096x9s_128x1_memory b2 (l1clk,din[2],dout[2],rw_addr,rd_en[2],wr_en[2]);
619n2_niu_sp_4096x9s_128x1_memory b3 (l1clk,din[3],dout[3],rw_addr,rd_en[3],wr_en[3]);
620n2_niu_sp_4096x9s_128x1_memory b4 (l1clk,din[4],dout[4],rw_addr,rd_en[4],wr_en[4]);
621n2_niu_sp_4096x9s_128x1_memory b5 (l1clk,din[5],dout[5],rw_addr,rd_en[5],wr_en[5]);
622n2_niu_sp_4096x9s_128x1_memory b6 (l1clk,din[6],dout[6],rw_addr,rd_en[6],wr_en[6]);
623n2_niu_sp_4096x9s_128x1_memory b7 (l1clk,din[7],dout[7],rw_addr,rd_en[7],wr_en[7]);
624
625endmodule
626
627
628
629
630
631module n2_niu_sp_4096x9s_128x1_memory (
632 l1clk,
633 din,
634 dout,
635 rw_addr,
636 rd_en,
637 wr_en
638);
639
640input l1clk;
641input din;
642input [6:0] rw_addr;
643input rd_en;
644input wr_en;
645output dout;
646
647
648wire [6:0] rw_addr;
649
650`ifdef AXIS_SMEM_BAD
651
652// internal variable
653integer k, l;
654reg dout;
655
656reg write_mask;
657
658wire axis_dout ;
659wire axis_din = din ;
660wire [6:0] axis_waddr = rw_addr ;
661wire [6:0] axis_raddr = rw_addr ;
662wire axis_wen = wr_en ;
663wire axis_ren = rd_en ;
664wire axis_clk = ~l1clk ;
665
666axis_smem #(7, 1, 2, 1'b0) mem // addr_width,data_width,num_ports,init_value
667( {axis_dout , {1'bz} }, // Output Port (1,2)
668 {{1'bz} , axis_din }, // Input Port (1,2)
669 {axis_raddr , axis_waddr }, // Address Port (1,2)
670 {1'b0 , axis_wen }, // Write Enable (1,2)
671 {1'b1 , 1'b1 }, // Chip Enable (1,2)
672 {axis_clk , axis_clk }, // Port Clocks (1,2)
673 {{1'bz} , {1'bz}} ); // Write Mask (1,2)
674
675
676always @(axis_dout or axis_ren or axis_wen or l1clk) begin
677 if (axis_ren & ~l1clk) begin
678 if (axis_wen)
679 dout <= 1'bx;
680 else
681 dout <= axis_dout;
682 end
683end
684
685`else
686
687reg dout;
688reg mem[127:0];
689
690always @(wr_en or rd_en or din or rw_addr or l1clk)
691`ifndef AXIS_SMEM
692 #1.01
693`else
694`endif
695 if(l1clk & wr_en)
696 if (rd_en)
697 mem[rw_addr] = 1'bx;
698 else
699 mem[rw_addr[6:0]] = din;
700
701always @(rd_en or rw_addr or l1clk)
702`ifndef AXIS_SMEM
703 #1.01
704`else
705`endif
706 if(rd_en & l1clk)
707 if(wr_en)
708 dout = 1'bx;
709 else
710 dout= rd_en & mem[rw_addr[6:0]];
711
712// Initialize the arrays.
713`ifndef NOINITMEM
714integer j;
715initial begin
716 for (j=0;j<128;j=j+1) begin
717 mem[j] = 1'd0;
718 end
719 dout=1'b0;
720end
721`endif // NOINITMEM
722
723`endif // AXIS_SMEM
724
725
726
727endmodule
728
729
730module repwrmux (
731 din,
732 dout,
733 sel
734);
735 input [8:0] din;
736 output [18:0] dout;
737 input [17:0] sel;
738 wire [17:0] din_replicate;
739
740 assign din_replicate={ {2{din[8]}},{2{din[7]}},{2{din[6]}},{2{din[5]}},
741 {2{din[4]}},{2{din[3]}},{2{din[2]}},{2{din[1]}},{2{din[0]}}};
742
743 assign dout[0 ]=~sel[0 ]&&din_replicate[0 ] || sel[0 ]&&din_replicate[0 ];
744 assign dout[1 ]=~sel[1 ]&&din_replicate[1 ] || sel[1 ]&&din_replicate[0 ];
745 assign dout[2 ]=~sel[2 ]&&din_replicate[2 ] || sel[2 ]&&din_replicate[1 ];
746 assign dout[3 ]=~sel[3 ]&&din_replicate[3 ] || sel[3 ]&&din_replicate[2 ];
747 assign dout[4 ]=~sel[4 ]&&din_replicate[4 ] || sel[4 ]&&din_replicate[3 ];
748 assign dout[5 ]=~sel[5 ]&&din_replicate[5 ] || sel[5 ]&&din_replicate[4 ];
749 assign dout[6 ]=~sel[6 ]&&din_replicate[6 ] || sel[6 ]&&din_replicate[5 ];
750 assign dout[7 ]=~sel[7 ]&&din_replicate[7 ] || sel[7 ]&&din_replicate[6 ];
751 assign dout[8 ]=~sel[8 ]&&din_replicate[8 ] || sel[8 ]&&din_replicate[7 ];
752 assign dout[9 ]=~sel[9 ]&&din_replicate[9 ] || sel[9 ]&&din_replicate[8 ];
753 assign dout[10]=~sel[10]&&din_replicate[10] || sel[10]&&din_replicate[9 ];
754 assign dout[11]=~sel[11]&&din_replicate[11] || sel[11]&&din_replicate[10];
755 assign dout[12]=~sel[12]&&din_replicate[12] || sel[12]&&din_replicate[11];
756 assign dout[13]=~sel[13]&&din_replicate[13] || sel[13]&&din_replicate[12];
757 assign dout[14]=~sel[14]&&din_replicate[14] || sel[14]&&din_replicate[13];
758 assign dout[15]=~sel[15]&&din_replicate[15] || sel[15]&&din_replicate[14];
759 assign dout[16]=~sel[16]&&din_replicate[16] || sel[16]&&din_replicate[15];
760 assign dout[17]=~sel[17]&&din_replicate[17] || sel[17]&&din_replicate[16];
761 assign dout[18]= din_replicate[17];
762
763endmodule
764
765
766
767
768module repwrselmux (
769 wr_en,
770 wrseldout,
771 addr10,
772 repsel
773);
774 input wr_en;
775 output [18:0] wrseldout;
776 input addr10;
777 input [17:0] repsel;
778 assign wrseldout[0 ]= wr_en && (~addr10 && ~repsel[0 ]|| addr10 && repsel[0 ]);
779 assign wrseldout[1 ]= wr_en && ( addr10 && ~repsel[1 ]||~addr10 && repsel[1 ]);
780 assign wrseldout[2 ]= wr_en && (~addr10 && ~repsel[2 ]|| addr10 && repsel[2 ]);
781 assign wrseldout[3 ]= wr_en && ( addr10 && ~repsel[3 ]||~addr10 && repsel[3 ]);
782 assign wrseldout[4 ]= wr_en && (~addr10 && ~repsel[4 ]|| addr10 && repsel[4 ]);
783 assign wrseldout[5 ]= wr_en && ( addr10 && ~repsel[5 ]||~addr10 && repsel[5 ]);
784 assign wrseldout[6 ]= wr_en && (~addr10 && ~repsel[6 ]|| addr10 && repsel[6 ]);
785 assign wrseldout[7 ]= wr_en && ( addr10 && ~repsel[7 ]||~addr10 && repsel[7 ]);
786 assign wrseldout[8 ]= wr_en && (~addr10 && ~repsel[8 ]|| addr10 && repsel[8 ]);
787 assign wrseldout[9 ]= wr_en && ( addr10 && ~repsel[9 ]||~addr10 && repsel[9 ]);
788 assign wrseldout[10]= wr_en && (~addr10 && ~repsel[10]|| addr10 && repsel[10]);
789 assign wrseldout[11]= wr_en && ( addr10 && ~repsel[11]||~addr10 && repsel[11]);
790 assign wrseldout[12]= wr_en && (~addr10 && ~repsel[12]|| addr10 && repsel[12]);
791 assign wrseldout[13]= wr_en && ( addr10 && ~repsel[13]||~addr10 && repsel[13]);
792 assign wrseldout[14]= wr_en && (~addr10 && ~repsel[14]|| addr10 && repsel[14]);
793 assign wrseldout[15]= wr_en && ( addr10 && ~repsel[15]||~addr10 && repsel[15]);
794 assign wrseldout[16]= wr_en && (~addr10 && ~repsel[16]|| addr10 && repsel[16]);
795 assign wrseldout[17]= wr_en && ( addr10 && ~repsel[17]||~addr10 && repsel[17]);
796 assign wrseldout[18]= wr_en && addr10 ;
797
798endmodule
799
800
801
802module reprdmux (
803 din,
804 dout,
805 sel
806);
807 input [18:0] din;
808 output [17:0] dout;
809 input [17:0] sel;
810 assign dout[0 ]=~sel[0 ]&&din[0 ] || sel[0 ]&&din[1 ];
811 assign dout[1 ]=~sel[1 ]&&din[1 ] || sel[1 ]&&din[2 ];
812 assign dout[2 ]=~sel[2 ]&&din[2 ] || sel[2 ]&&din[3 ];
813 assign dout[3 ]=~sel[3 ]&&din[3 ] || sel[3 ]&&din[4 ];
814 assign dout[4 ]=~sel[4 ]&&din[4 ] || sel[4 ]&&din[5 ];
815 assign dout[5 ]=~sel[5 ]&&din[5 ] || sel[5 ]&&din[6 ];
816 assign dout[6 ]=~sel[6 ]&&din[6 ] || sel[6 ]&&din[7 ];
817 assign dout[7 ]=~sel[7 ]&&din[7 ] || sel[7 ]&&din[8 ];
818 assign dout[8 ]=~sel[8 ]&&din[8 ] || sel[8 ]&&din[9 ];
819 assign dout[9 ]=~sel[9 ]&&din[9 ] || sel[9 ]&&din[10];
820 assign dout[10]=~sel[10]&&din[10] || sel[10]&&din[11];
821 assign dout[11]=~sel[11]&&din[11] || sel[11]&&din[12];
822 assign dout[12]=~sel[12]&&din[12] || sel[12]&&din[13];
823 assign dout[13]=~sel[13]&&din[13] || sel[13]&&din[14];
824 assign dout[14]=~sel[14]&&din[14] || sel[14]&&din[15];
825 assign dout[15]=~sel[15]&&din[15] || sel[15]&&din[16];
826 assign dout[16]=~sel[16]&&din[16] || sel[16]&&din[17];
827 assign dout[17]=~sel[17]&&din[17] || sel[17]&&din[18];
828endmodule
829
830
831
832
833module repdec_5_32 (
834 addr,
835 en,
836 dout_chain
837);
838 input [4:0] addr;
839 input en;
840 output [17:0] dout_chain;
841
842wire [17:0] dout_chain;
843wire [31:0] dout;
844
845coldec_3_8 ad34_00 (addr[2:0],en & ~addr[4] & ~addr[3],dout[7:0]);
846coldec_3_8 ad34_01 (addr[2:0],en & ~addr[4] & addr[3],dout[15:8]);
847coldec_3_8 ad34_10 (addr[2:0],en & addr[4] & ~addr[3],dout[23:16]);
848coldec_3_8 ad34_11 (addr[2:0],en & addr[4] & addr[3],dout[31:24]);
849
850assign dout_chain = { |dout[17:0],|dout[16:0],
851 |dout[15:0],|dout[14:0], |dout[13:0],|dout[12:0],
852 |dout[11:0],|dout[10:0], |dout[9:0],|dout[8:0],
853 |dout[7:0],|dout[6:0], |dout[5:0],|dout[4:0],
854 |dout[3:0],|dout[2:0],|dout[1:0],|dout[0]};
855
856
857endmodule
858
859
860
861
862module coldec_3_8 (
863 addr,
864 en,
865 dout
866);
867 input [2:0] addr;
868 input en;
869 output [7:0] dout;
870
871 reg [7:0] dout;
872 wire [2:0] addr;
873
874always @ (addr or en)
875 begin
876 if(!en)
877 dout=8'b00000000;
878 if(en)
879 case(addr)
880 3'h0: dout=8'b00000001;
881 3'h1: dout=8'b00000010;
882 3'h2: dout=8'b00000100;
883 3'h3: dout=8'b00001000;
884 3'h4: dout=8'b00010000;
885 3'h5: dout=8'b00100000;
886 3'h6: dout=8'b01000000;
887 3'h7: dout=8'b10000000;
888 endcase
889
890 end
891endmodule
892
893
894
895
896
897module n2_niu_sp_4096x9s_repair (
898 tcu_aclk,
899 tcu_bclk,
900 tcu_pce_ov,
901 pce,
902 tcu_scan_en,
903 tcu_se_scancollar_in,
904 tcu_se_scancollar_out,
905 tcu_array_wr_inhibit,
906 scan_in,
907 hdr_sram_rvalue,
908 hdr_sram_rid,
909 hdr_sram_wr_en,
910 hdr_sram_red_clr,
911 l2clk,
912 sram_hdr_read_data,
913 red_value_b0,
914 red_value_b1,
915 repair_en_bk,
916 scan_out);
917wire l1clk_in_en;
918wire l1clk_out_en;
919wire l1clk_gate_en;
920wire hdr_sram_rid_reg_scanout;
921wire hdr_sram_wr_en_reg_scanout;
922wire hdr_sram_red_clr_reg_scanout;
923
924
925input tcu_aclk;
926input tcu_bclk;
927input tcu_pce_ov;
928input pce;
929input tcu_scan_en;
930input tcu_se_scancollar_in;
931input tcu_se_scancollar_out;
932input tcu_array_wr_inhibit; // direct input, not flopped
933input scan_in;
934input [5:0] hdr_sram_rvalue;
935input hdr_sram_rid;
936input hdr_sram_wr_en;
937input hdr_sram_red_clr;
938
939input l2clk;
940
941output [5:0] sram_hdr_read_data;
942
943output [4:0] red_value_b0; // to subbank
944output [4:0] red_value_b1;
945output [1:0] repair_en_bk;
946
947output scan_out;
948
949wire [5:0] sram_hdr_read_data;
950
951wire [4:0] red_value_b0; // to subbank
952wire [4:0] red_value_b1;
953wire [1:0] repair_en_bk; // to subbank
954
955wire scan_out;
956
957// scan renames
958wire siclk = tcu_aclk;
959wire soclk = tcu_bclk;
960// end scan
961
962wire [1:0] red_id;
963wire [1:0] red_reg_clk_p;
964wire [4:0] fuse_red_data;
965wire fuse_red_enable;
966
967wire [4:0] red_data_reg_b0;
968wire [4:0] red_data_reg_b1;
969wire [1:0] red_en_reg_bk;
970
971wire [1:0] scan_input_bk;
972wire [1:0] scan_output_bk;
973
974//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
975//================================================
976// l2 clock Domain: Clock headers
977//================================================
978wire l1clk_in;
979wire l1clk_gate;
980wire l1clk_out;
981
982//cl_sc1_l1hdr_8x l1ch_in (
983// .l2clk (l2clk),
984// .pce (pce),
985// .l1clk (l1clk_in),
986// .se (tcu_se_scancollar_in),
987// .pce_ov (tcu_pce_ov),
988// .stop (1'b0)
989// );
990
991
992//cl_sc1_l1hdr_8x l1ch_out (
993// .l2clk (l2clk),
994// .pce (pce),
995// .l1clk (l1clk_out),
996// .se (tcu_se_scancollar_out),
997// .pce_ov (tcu_pce_ov),
998// .stop (1'b0)
999// );
1000
1001//cl_sc1_l1hdr_8x l1ch_gate (
1002// .l2clk (l2clk),
1003// .pce (pce),
1004// .l1clk (l1clk_gate),
1005// .se (tcu_scan_en),
1006// .pce_ov (tcu_pce_ov),
1007// .stop (1'b0)
1008// );
1009
1010///////////////////////////////////
1011// decomposed l1hdr for l1clk_in
1012///////////////////////////////////
1013
1014cl_mc1_l1enable_12x l1ch_in_l1en (
1015 .l2clk (l2clk),
1016 .pce (pce),
1017 .pce_ov (tcu_pce_ov),
1018 .l1en (l1clk_in_en)
1019 );
1020
1021cl_mc1_l1driver_12x l1ch_in_l1drvr (
1022 .se (tcu_se_scancollar_in),
1023 .l1en (l1clk_in_en),
1024 .l1clk (l1clk_in),
1025 .l2clk(l2clk)
1026 );
1027
1028///////////////////////////////////
1029// decomposed l1hdr for l1clk_out
1030///////////////////////////////////
1031
1032cl_mc1_l1enable_12x l1ch_out_l1en (
1033 .l2clk (l2clk),
1034 .pce (pce),
1035 .pce_ov (tcu_pce_ov),
1036 .l1en (l1clk_out_en)
1037 );
1038
1039cl_mc1_l1driver_12x l1ch_out_l1drvr (
1040 .se (tcu_se_scancollar_out),
1041 .l1en (l1clk_out_en),
1042 .l1clk (l1clk_out),
1043 .l2clk(l2clk)
1044 );
1045
1046///////////////////////////////////
1047// decomposed l1hdr for l1clk_gate
1048///////////////////////////////////
1049
1050cl_mc1_l1enable_12x l1ch_gate_l1en (
1051 .l2clk (l2clk),
1052 .pce (pce),
1053 .pce_ov (tcu_pce_ov),
1054 .l1en (l1clk_gate_en)
1055 );
1056
1057cl_mc1_l1driver_12x l1ch_gate_l1drvr (
1058 .se (tcu_scan_en),
1059 .l1en (l1clk_gate_en),
1060 .l1clk (l1clk_gate),
1061 .l2clk(l2clk)
1062 );
1063
1064
1065
1066//================================================
1067// l2 clock Domain: Input flops
1068//================================================
1069
1070/****************************************************/
1071wire [4:0] fuse_niu_repair_value;
1072wire fuse_niu_repair_en;
1073wire fuse_niu_rid;
1074wire fuse_niu_wen;
1075wire fuse_red_reset;
1076
1077wire sr10;
1078wire hdr_wr_en;
1079wire hdr_red_clr;
1080wire hdr_sram_rid_reg_scanin;
1081wire hdr_sram_wr_en_reg_scanin;
1082wire hdr_sram_red_clr_reg_scanin;
1083
1084wire [5:0] hdr_rvalue_reg_scanin;
1085wire [5:0] hdr_rvalue_reg_scanout;
1086wire [5:0] sram_read_data_reg_scanin;
1087wire [5:0] sram_read_data_reg_scanout;
1088
1089// msff_ctl_macro srhdr_rvalue (width=6) (
1090// .scan_in (dff_rvalue_m_scanin),
1091// .scan_out (dff_rvalue_m_scanout),
1092// .l1clk (l1clk_in),
1093// .din (hdr_sram_rvalue[5:0]),
1094// .dout ({fuse_niu_repair_value[4:0],fuse_niu_repair_en}) );
1095
1096// msff_ctl_macro srhdr_rid (width=1) (
1097// .scan_in (dff_rid_m_scanin),
1098// .scan_out (dff_rid_m_scanout),
1099// .l1clk (l1clk_in),
1100// .din (hdr_sram_rid),
1101// .dout (fuse_niu_rid) );
1102
1103// msff_ctl_macro srhdr_wr_en (width=1) (
1104// .scan_in (dff_wr_en_m_scanin),
1105// .scan_out (dff_wr_en_m_scanout),
1106// .l1clk (l1clk_in),
1107// .din (hdr_sram_wr_en),
1108// .dout (hdr_wr_en) );
1109
1110// msff_ctl_macro srhdr_red_clr (width=1) (
1111// .scan_in (dff_red_clr_m_scanin),
1112// .scan_out (dff_red_clr_m_scanout),
1113// .l1clk (l1clk_in),
1114// .din (hdr_sram_red_clr),
1115// .dout (hdr_red_clr) );
1116
1117
1118cl_sc1_msff_4x srhdr_rvalue_reg_0 (.d(hdr_sram_rvalue[0]),.si(hdr_rvalue_reg_scanin[0]),.q(fuse_niu_repair_en),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[0]));
1119cl_sc1_msff_4x srhdr_rvalue_reg_1 (.d(hdr_sram_rvalue[1]),.si(hdr_rvalue_reg_scanin[1]),.q(fuse_niu_repair_value[0]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[1]));
1120cl_sc1_msff_4x srhdr_rvalue_reg_2 (.d(hdr_sram_rvalue[2]),.si(hdr_rvalue_reg_scanin[2]),.q(fuse_niu_repair_value[1]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[2]));
1121cl_sc1_msff_4x srhdr_rvalue_reg_3 (.d(hdr_sram_rvalue[3]),.si(hdr_rvalue_reg_scanin[3]),.q(fuse_niu_repair_value[2]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[3]));
1122cl_sc1_msff_4x srhdr_rvalue_reg_4 (.d(hdr_sram_rvalue[4]),.si(hdr_rvalue_reg_scanin[4]),.q(fuse_niu_repair_value[3]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[4]));
1123cl_sc1_msff_4x srhdr_rvalue_reg_5 (.d(hdr_sram_rvalue[5]),.si(hdr_rvalue_reg_scanin[5]),.q(fuse_niu_repair_value[4]),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_rvalue_reg_scanout[5]));
1124
1125cl_sc1_msff_4x hdr_sram_rid_reg_0 (.d(hdr_sram_rid),.si(hdr_sram_rid_reg_scanin),.q(fuse_niu_rid),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_sram_rid_reg_scanout));
1126
1127cl_sc1_msff_4x hdr_sram_wr_en_reg (.d(hdr_sram_wr_en),.si(hdr_sram_wr_en_reg_scanin),.q(hdr_wr_en),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_sram_wr_en_reg_scanout));
1128
1129cl_sc1_msff_4x hdr_sram_red_clr_reg (.d(hdr_sram_red_clr),.si(hdr_sram_red_clr_reg_scanin),.q(hdr_red_clr),.l1clk(l1clk_in),.siclk(siclk),.soclk(soclk),.so(hdr_sram_red_clr_reg_scanout));
1130
1131// assign fuse_niu_wen = hdr_wr_en && !tcu_array_wr_inhibit;
1132// assign fuse_red_reset = hdr_red_clr && !tcu_array_wr_inhibit;
1133
1134 niu4k_inv_macro__width_1 r1 (.dout(sr10), .din(tcu_array_wr_inhibit) );
1135 niu4k_and_macro__width_1 r2 (.dout(fuse_niu_wen), .din0(hdr_wr_en), .din1(sr10) );
1136 niu4k_and_macro__width_1 r3 (.dout(fuse_red_reset), .din0(hdr_red_clr), .din1(sr10) );
1137
1138//================================================
1139// l2 clock Domain: output flops
1140//================================================
1141
1142// ------------ repair_ph.a register ----------------
1143wire [4:0] niu_fuse_repair_value;
1144wire niu_fuse_repair_en;
1145
1146
1147
1148
1149// msff_ctl_macro sram_read_data (width=6) (
1150// .scan_in (dff_read_data_m_scanin),
1151// .scan_out (dff_read_data_m_scanout),
1152// .l1clk (l1clk_out),
1153// .din ({niu_fuse_repair_value[4:0],niu_fuse_repair_en}),
1154// .dout (sram_hdr_read_data[5:0]) );
1155
1156cl_sc1_msff_4x sram_read_data_reg_0 (.d(niu_fuse_repair_en),.si(sram_read_data_reg_scanin[0]),.q(sram_hdr_read_data[0]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[0]));
1157cl_sc1_msff_4x sram_read_data_reg_1 (.d(niu_fuse_repair_value[0]),.si(sram_read_data_reg_scanin[1]),.q(sram_hdr_read_data[1]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[1]));
1158cl_sc1_msff_4x sram_read_data_reg_2 (.d(niu_fuse_repair_value[1]),.si(sram_read_data_reg_scanin[2]),.q(sram_hdr_read_data[2]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[2]));
1159cl_sc1_msff_4x sram_read_data_reg_3 (.d(niu_fuse_repair_value[2]),.si(sram_read_data_reg_scanin[3]),.q(sram_hdr_read_data[3]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[3]));
1160cl_sc1_msff_4x sram_read_data_reg_4 (.d(niu_fuse_repair_value[3]),.si(sram_read_data_reg_scanin[4]),.q(sram_hdr_read_data[4]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[4]));
1161cl_sc1_msff_4x sram_read_data_reg_5 (.d(niu_fuse_repair_value[4]),.si(sram_read_data_reg_scanin[5]),.q(sram_hdr_read_data[5]),.l1clk(l1clk_out),.siclk(siclk),.soclk(soclk),.so(sram_read_data_reg_scanout[5]));
1162
1163//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
1164//////////////////////////////
1165// Redundancy Register //
1166//////////////////////////////
1167 assign red_id[0] = !fuse_niu_rid;
1168 assign red_id[1] = fuse_niu_rid;
1169
1170 assign red_reg_clk_p[0] = (!l1clk_gate && (red_id[0] && fuse_niu_wen || fuse_red_reset));
1171 assign red_reg_clk_p[1] = (!l1clk_gate && (red_id[1] && fuse_niu_wen || fuse_red_reset));
1172
1173 assign fuse_red_data = fuse_niu_repair_value & {5{!fuse_red_reset}};
1174 assign fuse_red_enable = fuse_niu_repair_en && !fuse_red_reset;
1175
1176//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
1177 n2_niu_sp_4096x9s_redreg redreg_0 (
1178 .fuse_red_data (fuse_red_data),
1179 .fuse_red_enable (fuse_red_enable),
1180 .red_reg_clk_p (red_reg_clk_p[0]),
1181 .red_data_reg (red_data_reg_b0),
1182 .red_en_reg (red_en_reg_bk[0]),
1183 .red_value (red_value_b0),
1184 .repair_en (repair_en_bk[0])
1185 );
1186
1187 n2_niu_sp_4096x9s_redreg redreg_1 (
1188 .fuse_red_data (fuse_red_data),
1189 .fuse_red_enable (fuse_red_enable),
1190 .red_reg_clk_p (red_reg_clk_p[1]),
1191 .red_data_reg (red_data_reg_b1),
1192 .red_en_reg (red_en_reg_bk[1]),
1193 .red_value (red_value_b1),
1194 .repair_en (repair_en_bk[1])
1195 );
1196
1197//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
1198wire [4:0] niu_fuse_repair_value_b0;
1199wire [4:0] niu_fuse_repair_value_b1;
1200
1201 // assign niu_fuse_repair_value = (red_data_reg_b0 & {5{red_id[0]}}) |
1202 // (red_data_reg_b1 & {5{red_id[1]}});
1203
1204 niu4k_and_macro__width_5 ava0 (.dout(niu_fuse_repair_value_b0), .din0(red_data_reg_b0), .din1({5{red_id[0]}}));
1205 niu4k_and_macro__width_5 ava1 (.dout(niu_fuse_repair_value_b1), .din0(red_data_reg_b1), .din1({5{red_id[1]}}));
1206
1207 niu4k_or_macro__width_5 ova0 (.dout(niu_fuse_repair_value), .din0(niu_fuse_repair_value_b0), .din1(niu_fuse_repair_value_b1));
1208
1209wire [1:0] niu_fuse_repair_en_bk;
1210
1211 // assign niu_fuse_repair_en = (red_en_reg_bk[0] && red_id[0]) ||
1212 // (red_en_reg_bk[1] && red_id[1]);
1213
1214 niu4k_and_macro__width_2 aen0 (.dout(niu_fuse_repair_en_bk), .din0(red_en_reg_bk[1:0]), .din1(red_id[1:0]) );
1215
1216 niu4k_or_macro__width_1 oen0 (.dout(niu_fuse_repair_en),.din0(niu_fuse_repair_en_bk[0]),.din1(niu_fuse_repair_en_bk[1]));
1217
1218//=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=#=
1219// fixscan start:
1220
1221
1222assign hdr_rvalue_reg_scanin[5] = scan_in;
1223assign sram_read_data_reg_scanin[5] = hdr_rvalue_reg_scanout[5];
1224assign hdr_rvalue_reg_scanin[4] = sram_read_data_reg_scanout[5];
1225assign sram_read_data_reg_scanin[4] = hdr_rvalue_reg_scanout[4];
1226assign hdr_rvalue_reg_scanin[3] = sram_read_data_reg_scanout[4];
1227assign sram_read_data_reg_scanin[3] = hdr_rvalue_reg_scanout[3];
1228assign hdr_rvalue_reg_scanin[2] = sram_read_data_reg_scanout[3];
1229assign sram_read_data_reg_scanin[2] = hdr_rvalue_reg_scanout[2];
1230assign hdr_rvalue_reg_scanin[1] = sram_read_data_reg_scanout[2];
1231assign sram_read_data_reg_scanin[1] = hdr_rvalue_reg_scanout[1];
1232assign hdr_rvalue_reg_scanin[0] = sram_read_data_reg_scanout[1];
1233assign sram_read_data_reg_scanin[0] = hdr_rvalue_reg_scanout[0];
1234assign hdr_sram_rid_reg_scanin = sram_read_data_reg_scanout[0];
1235assign hdr_sram_wr_en_reg_scanin = hdr_sram_rid_reg_scanout;
1236assign hdr_sram_red_clr_reg_scanin = hdr_sram_wr_en_reg_scanout;
1237assign scan_out = hdr_sram_red_clr_reg_scanout;
1238
1239
1240// fixscan end
1241
1242endmodule
1243
1244
1245
1246//
1247// invert macro
1248//
1249//
1250
1251
1252
1253
1254
1255module niu4k_inv_macro__width_1 (
1256 din,
1257 dout);
1258 input [0:0] din;
1259 output [0:0] dout;
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269cl_u1_inv_1x d0_0 (
1270.in(din[0]),
1271.out(dout[0])
1272);
1273
1274
1275
1276
1277
1278endmodule
1279
1280
1281
1282
1283
1284//
1285// and macro for ports = 2,3,4
1286//
1287//
1288
1289
1290
1291
1292
1293module niu4k_and_macro__width_1 (
1294 din0,
1295 din1,
1296 dout);
1297wire [0:0] nandout;
1298
1299 input [0:0] din0;
1300 input [0:0] din1;
1301 output [0:0] dout;
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311cl_u1_nand2_1x d0_0 (
1312.in0(din0[0]),
1313.in1(din1[0]),
1314.out(nandout[0])
1315);
1316
1317cl_u1_inv_1x d1_0 (
1318.in(nandout[0]),
1319.out(dout[0])
1320);
1321
1322
1323
1324
1325endmodule
1326
1327
1328
1329
1330
1331
1332module n2_niu_sp_4096x9s_redreg (
1333 fuse_red_data,
1334 fuse_red_enable,
1335 red_reg_clk_p,
1336 red_data_reg,
1337 red_en_reg,
1338 red_value,
1339 repair_en);
1340
1341input [4:0] fuse_red_data;
1342input fuse_red_enable;
1343input red_reg_clk_p;
1344
1345output [4:0] red_data_reg; // to repair output
1346output red_en_reg;
1347output [4:0] red_value; // to subbank
1348output repair_en;
1349
1350wire [4:0] red_value;
1351wire repair_en;
1352
1353wire [4:0] red_data_reg;
1354wire red_en_reg;
1355
1356wire red_en_reg1;
1357
1358
1359//////////////////////////////
1360// Redundancy Register //
1361//////////////////////////////
1362
1363// `ifdef NOINITMEM
1364// `else
1365// // Initialize the arrays.
1366// initial begin
1367// red_data_reg = {5{1'h0}};
1368// red_en_reg = 1'h0;
1369// end
1370// `endif
1371
1372// always @(posedge red_reg_clk_p) begin
1373// red_data_reg <= fuse_red_data;
1374// red_en_reg <= fuse_red_enable;
1375// end
1376
1377cl_sc1_msff_4x e_r0 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_enable), .q(red_en_reg));
1378cl_sc1_msff_4x e_r1 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_enable), .q(red_en_reg1));
1379
1380cl_sc1_msff_4x d_r0 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[0]),.q(red_data_reg[0]));
1381cl_sc1_msff_4x d_r1 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[1]),.q(red_data_reg[1]));
1382cl_sc1_msff_4x d_r2 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[2]),.q(red_data_reg[2]));
1383cl_sc1_msff_4x d_r3 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[3]),.q(red_data_reg[3]));
1384cl_sc1_msff_4x d_r4 (.si(1'b0),.so(),.l1clk(red_reg_clk_p),.siclk(1'b0),.soclk(1'b0),.d(fuse_red_data[4]),.q(red_data_reg[4]));
1385
1386// assign repair_en = red_en_reg;
1387// assign red_value = red_data_reg[4:0] & {5{repair_en}};
1388
1389 niu4k_and_macro__width_1 a0 (.dout(repair_en), .din0(red_en_reg), .din1(red_en_reg1));
1390 niu4k_and_macro__width_5 a1 (.dout(red_value), .din0(red_data_reg[4:0]), .din1({5{repair_en}}));
1391
1392
1393endmodule
1394
1395
1396
1397//
1398// and macro for ports = 2,3,4
1399//
1400//
1401
1402
1403
1404
1405
1406module niu4k_and_macro__width_5 (
1407 din0,
1408 din1,
1409 dout);
1410wire [4:0] nandout;
1411
1412 input [4:0] din0;
1413 input [4:0] din1;
1414 output [4:0] dout;
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424cl_u1_nand2_1x d0_0 (
1425.in0(din0[0]),
1426.in1(din1[0]),
1427.out(nandout[0])
1428);
1429
1430cl_u1_nand2_1x d0_1 (
1431.in0(din0[1]),
1432.in1(din1[1]),
1433.out(nandout[1])
1434);
1435
1436cl_u1_nand2_1x d0_2 (
1437.in0(din0[2]),
1438.in1(din1[2]),
1439.out(nandout[2])
1440);
1441
1442cl_u1_nand2_1x d0_3 (
1443.in0(din0[3]),
1444.in1(din1[3]),
1445.out(nandout[3])
1446);
1447
1448cl_u1_nand2_1x d0_4 (
1449.in0(din0[4]),
1450.in1(din1[4]),
1451.out(nandout[4])
1452);
1453
1454cl_u1_inv_1x d1_0 (
1455.in(nandout[0]),
1456.out(dout[0])
1457);
1458cl_u1_inv_1x d1_1 (
1459.in(nandout[1]),
1460.out(dout[1])
1461);
1462cl_u1_inv_1x d1_2 (
1463.in(nandout[2]),
1464.out(dout[2])
1465);
1466cl_u1_inv_1x d1_3 (
1467.in(nandout[3]),
1468.out(dout[3])
1469);
1470cl_u1_inv_1x d1_4 (
1471.in(nandout[4]),
1472.out(dout[4])
1473);
1474
1475
1476
1477
1478endmodule
1479
1480
1481
1482
1483
1484//
1485// or macro for ports = 2,3
1486//
1487//
1488
1489
1490
1491
1492
1493module niu4k_or_macro__width_5 (
1494 din0,
1495 din1,
1496 dout);
1497wire [4:0] norout;
1498
1499 input [4:0] din0;
1500 input [4:0] din1;
1501 output [4:0] dout;
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511cl_u1_nor2_1x d0_0 (
1512.in0(din0[0]),
1513.in1(din1[0]),
1514.out(norout[0])
1515);
1516
1517cl_u1_nor2_1x d0_1 (
1518.in0(din0[1]),
1519.in1(din1[1]),
1520.out(norout[1])
1521);
1522
1523cl_u1_nor2_1x d0_2 (
1524.in0(din0[2]),
1525.in1(din1[2]),
1526.out(norout[2])
1527);
1528
1529cl_u1_nor2_1x d0_3 (
1530.in0(din0[3]),
1531.in1(din1[3]),
1532.out(norout[3])
1533);
1534
1535cl_u1_nor2_1x d0_4 (
1536.in0(din0[4]),
1537.in1(din1[4]),
1538.out(norout[4])
1539);
1540
1541cl_u1_inv_1x d1_0 (
1542.in(norout[0]),
1543.out(dout[0])
1544);
1545cl_u1_inv_1x d1_1 (
1546.in(norout[1]),
1547.out(dout[1])
1548);
1549cl_u1_inv_1x d1_2 (
1550.in(norout[2]),
1551.out(dout[2])
1552);
1553cl_u1_inv_1x d1_3 (
1554.in(norout[3]),
1555.out(dout[3])
1556);
1557cl_u1_inv_1x d1_4 (
1558.in(norout[4]),
1559.out(dout[4])
1560);
1561
1562
1563
1564
1565endmodule
1566
1567
1568
1569
1570
1571//
1572// and macro for ports = 2,3,4
1573//
1574//
1575
1576
1577
1578
1579
1580module niu4k_and_macro__width_2 (
1581 din0,
1582 din1,
1583 dout);
1584wire [1:0] nandout;
1585
1586 input [1:0] din0;
1587 input [1:0] din1;
1588 output [1:0] dout;
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598cl_u1_nand2_1x d0_0 (
1599.in0(din0[0]),
1600.in1(din1[0]),
1601.out(nandout[0])
1602);
1603
1604cl_u1_nand2_1x d0_1 (
1605.in0(din0[1]),
1606.in1(din1[1]),
1607.out(nandout[1])
1608);
1609
1610cl_u1_inv_1x d1_0 (
1611.in(nandout[0]),
1612.out(dout[0])
1613);
1614cl_u1_inv_1x d1_1 (
1615.in(nandout[1]),
1616.out(dout[1])
1617);
1618
1619
1620
1621
1622endmodule
1623
1624
1625
1626
1627
1628//
1629// or macro for ports = 2,3
1630//
1631//
1632
1633
1634
1635
1636
1637module niu4k_or_macro__width_1 (
1638 din0,
1639 din1,
1640 dout);
1641wire [0:0] norout;
1642
1643 input [0:0] din0;
1644 input [0:0] din1;
1645 output [0:0] dout;
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655cl_u1_nor2_1x d0_0 (
1656.in0(din0[0]),
1657.in1(din1[0]),
1658.out(norout[0])
1659);
1660
1661cl_u1_inv_1x d1_0 (
1662.in(norout[0]),
1663.out(dout[0])
1664);
1665
1666
1667
1668
1669endmodule
1670
1671
1672
1673
Full OpenSPARC design & verification tarball including full HDL.