projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: n2_efuhdr1_ctl.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module n2_efuhdr1_ctl ( | |
| 36 | efu_hdr_write_data, | |
| 37 | efu_hdr_xfer_en, | |
| 38 | efu_hdr_clr, | |
| 39 | hdr_efu_read_data, | |
| 40 | hdr_efu_xfer_en, | |
| 41 | hdr_sram_rvalue, | |
| 42 | hdr_sram_rid, | |
| 43 | hdr_sram_wr_en, | |
| 44 | hdr_sram_red_clr, | |
| 45 | sram_hdr_read_data, | |
| 46 | l2clk, | |
| 47 | io_cmp_sync_en, | |
| 48 | cmp_io_sync_en, | |
| 49 | tcu_pce_ov, | |
| 50 | tcu_aclk, | |
| 51 | tcu_bclk, | |
| 52 | tcu_scan_en, | |
| 53 | tcu_clk_stop, | |
| 54 | scan_in, | |
| 55 | scan_out) ; | |
| 56 | wire stop; | |
| 57 | wire se; | |
| 58 | wire l1clk_cmp; | |
| 59 | wire ff_cmp_io_sync_en_scanin; | |
| 60 | wire ff_cmp_io_sync_en_scanout; | |
| 61 | wire cmp_io_sync_en_r1; | |
| 62 | wire ff_io_cmp_sync_en_scanin; | |
| 63 | wire ff_io_cmp_sync_en_scanout; | |
| 64 | wire io_cmp_sync_en_r1; | |
| 65 | wire ff_input_all_enable_scanin; | |
| 66 | wire ff_input_all_enable_scanout; | |
| 67 | wire efu_hdr_xfer_en_r1; | |
| 68 | wire efu_hdr_write_data_r1; | |
| 69 | wire efu_hdr_clr_r1; | |
| 70 | wire efu_hdr_xfer_en_r2; | |
| 71 | wire [21:0] efu_instr; | |
| 72 | wire [21:0] instr; | |
| 73 | wire [21:0] sram_read_data; | |
| 74 | wire [21:0] received_instr; | |
| 75 | wire [4:0] rdcount; | |
| 76 | wire [21:0] sync_read; | |
| 77 | wire dispatch_read_data; | |
| 78 | wire load_shift_reg; | |
| 79 | wire ff_receiver_instr_slice_scanin; | |
| 80 | wire ff_receiver_instr_slice_scanout; | |
| 81 | wire data_en_io_cmp; | |
| 82 | wire [4:0] count; | |
| 83 | wire wr_en; | |
| 84 | wire [21:0] sync_instr; | |
| 85 | wire read_en_io_cmp; | |
| 86 | wire ff_sync_sram_data_scanin; | |
| 87 | wire ff_sync_sram_data_scanout; | |
| 88 | wire ff_sync_read_data_scanin; | |
| 89 | wire ff_sync_read_data_scanout; | |
| 90 | wire ff_sync_sram_clr_scanin; | |
| 91 | wire ff_sync_sram_clr_scanout; | |
| 92 | wire sync_clr; | |
| 93 | wire ff_sync_sram_wr_scanin; | |
| 94 | wire ff_sync_sram_wr_scanout; | |
| 95 | wire sync_wr; | |
| 96 | wire load_en; | |
| 97 | wire ld_rd_en; | |
| 98 | wire reset_count; | |
| 99 | wire rdreset_count; | |
| 100 | wire [4:0] count_in; | |
| 101 | wire [4:0] rdcount_in; | |
| 102 | wire ff_counter_slice_scanin; | |
| 103 | wire ff_counter_slice_scanout; | |
| 104 | wire ff_rd_counter_scanin; | |
| 105 | wire ff_rd_counter_scanout; | |
| 106 | wire spares_cmp_scanin; | |
| 107 | wire spares_cmp_scanout; | |
| 108 | ||
| 109 | ||
| 110 | // EFU to SRAM header | |
| 111 | input efu_hdr_write_data; | |
| 112 | input efu_hdr_xfer_en; | |
| 113 | input efu_hdr_clr; | |
| 114 | ||
| 115 | // SRAM header to EFU | |
| 116 | output hdr_efu_read_data; | |
| 117 | output hdr_efu_xfer_en; | |
| 118 | ||
| 119 | // SRAM header to SRAM | |
| 120 | output [ 10 : 0 ] hdr_sram_rvalue; | |
| 121 | output [ 10 : 0 ] hdr_sram_rid; | |
| 122 | output hdr_sram_wr_en; | |
| 123 | output hdr_sram_red_clr; | |
| 124 | ||
| 125 | // SRAM to SRAM header | |
| 126 | input [ 10 : 0 ] sram_hdr_read_data; | |
| 127 | ||
| 128 | ||
| 129 | // other common signals | |
| 130 | ||
| 131 | input l2clk; | |
| 132 | input io_cmp_sync_en; | |
| 133 | input cmp_io_sync_en; | |
| 134 | input tcu_pce_ov; | |
| 135 | input tcu_aclk; | |
| 136 | input tcu_bclk; | |
| 137 | input tcu_scan_en; | |
| 138 | input tcu_clk_stop; | |
| 139 | input scan_in; | |
| 140 | output scan_out; | |
| 141 | ||
| 142 | ||
| 143 | ||
| 144 | // scan renames | |
| 145 | wire pce_ov; | |
| 146 | wire siclk; | |
| 147 | wire soclk; | |
| 148 | ||
| 149 | assign pce_ov = tcu_pce_ov; | |
| 150 | assign stop = tcu_clk_stop; | |
| 151 | assign siclk = tcu_aclk; | |
| 152 | assign soclk = tcu_bclk; | |
| 153 | assign se = tcu_scan_en; | |
| 154 | // end scan renames | |
| 155 | ||
| 156 | ||
| 157 | l1clkhdr_ctl_macro clkgen_l1clk | |
| 158 | ( | |
| 159 | .l2clk( l2clk ), | |
| 160 | .l1en ( 1'b1 ), | |
| 161 | .l1clk( l1clk_cmp ), | |
| 162 | .pce_ov(pce_ov), | |
| 163 | .stop(stop), | |
| 164 | .se(se) | |
| 165 | ); | |
| 166 | ||
| 167 | ||
| 168 | msff_ctl_macro__width_1 ff_cmp_io_sync_en | |
| 169 | ( | |
| 170 | .scan_in(ff_cmp_io_sync_en_scanin), | |
| 171 | .scan_out(ff_cmp_io_sync_en_scanout), | |
| 172 | .dout (cmp_io_sync_en_r1), | |
| 173 | .din (cmp_io_sync_en), | |
| 174 | .l1clk (l1clk_cmp), | |
| 175 | .siclk(siclk), | |
| 176 | .soclk(soclk) | |
| 177 | ); | |
| 178 | ||
| 179 | msff_ctl_macro__width_1 ff_io_cmp_sync_en | |
| 180 | ( | |
| 181 | .scan_in(ff_io_cmp_sync_en_scanin), | |
| 182 | .scan_out(ff_io_cmp_sync_en_scanout), | |
| 183 | .dout (io_cmp_sync_en_r1), | |
| 184 | .din (io_cmp_sync_en), | |
| 185 | .l1clk (l1clk_cmp), | |
| 186 | .siclk(siclk), | |
| 187 | .soclk(soclk) | |
| 188 | ); | |
| 189 | ||
| 190 | msff_ctl_macro__en_1__width_4 ff_input_all_enable | |
| 191 | ( | |
| 192 | .scan_in(ff_input_all_enable_scanin), | |
| 193 | .scan_out(ff_input_all_enable_scanout), | |
| 194 | .dout ({efu_hdr_xfer_en_r1,efu_hdr_write_data_r1,efu_hdr_clr_r1,efu_hdr_xfer_en_r2}), | |
| 195 | .din ({efu_hdr_xfer_en, efu_hdr_write_data ,efu_hdr_clr, efu_hdr_xfer_en_r1}), | |
| 196 | .en (io_cmp_sync_en_r1), | |
| 197 | .l1clk (l1clk_cmp), | |
| 198 | .siclk(siclk), | |
| 199 | .soclk(soclk) | |
| 200 | ); | |
| 201 | ||
| 202 | ||
| 203 | assign efu_instr[ 21 : 0 ] = {instr[ 20 : 0 ],efu_hdr_write_data_r1}; | |
| 204 | ||
| 205 | assign sram_read_data[ 21 : 0 ] = {instr[ 21 : 11 ],sram_hdr_read_data[ 10 : 0 ]}; | |
| 206 | ||
| 207 | //assign received_instr[21:0] = efu_hdr_xfer_en_r1 ? efu_instr[21:0] : | |
| 208 | // (count==5'd6) ? sram_read_data[21:0] : | |
| 209 | // dispatch_read_data ? ({instr[20:0],1'b0}) : 22'b0; | |
| 210 | ||
| 211 | assign received_instr[ 21 : 0 ] = efu_hdr_xfer_en_r1 ? efu_instr[ 21 : 0 ] | |
| 212 | : rdcount == 5'd23 ? sync_read | |
| 213 | : dispatch_read_data ? ({instr[ 20 : 0 ],1'b0}) : 22'b0; | |
| 214 | ||
| 215 | ||
| 216 | //assign load_shift_reg = efu_hdr_xfer_en_r1 | dispatch_read_data; | |
| 217 | assign load_shift_reg = efu_hdr_xfer_en_r1 | dispatch_read_data | rdcount == 5'd23; | |
| 218 | ||
| 219 | msff_ctl_macro__en_1__width_22 ff_receiver_instr_slice | |
| 220 | ( | |
| 221 | .scan_in(ff_receiver_instr_slice_scanin), | |
| 222 | .scan_out(ff_receiver_instr_slice_scanout), | |
| 223 | .dout (instr[ 21 : 0 ]), | |
| 224 | .din (load_shift_reg ? received_instr[ 21 : 0 ] : instr[ 21 : 0 ]), | |
| 225 | .en (io_cmp_sync_en_r1), | |
| 226 | .l1clk (l1clk_cmp), | |
| 227 | .siclk(siclk), | |
| 228 | .soclk(soclk) | |
| 229 | ); | |
| 230 | ||
| 231 | //data available at 5'd8 (completely shifted in) | |
| 232 | assign data_en_io_cmp = (count==5'd8) & io_cmp_sync_en_r1; | |
| 233 | // generate wr_en after 1 cycle of setup and enable bits are valid | |
| 234 | //assign wr_en = (count==5'd7) & sync_instr[11] & sync_instr[0]; | |
| 235 | assign wr_en = (count==5'd7) & ~sync_instr[ 21 ]; | |
| 236 | //get data back from sram after 4 ioclk cycles wait | |
| 237 | assign read_en_io_cmp = (count==5'd1) & cmp_io_sync_en_r1; | |
| 238 | ||
| 239 | msff_ctl_macro__en_1__width_22 ff_sync_sram_data | |
| 240 | ( | |
| 241 | .scan_in(ff_sync_sram_data_scanin), | |
| 242 | .scan_out(ff_sync_sram_data_scanout), | |
| 243 | .dout (sync_instr[ 21 : 0 ]), | |
| 244 | .din ((count==5'd8) ? instr[ 21 : 0 ] : sync_instr[ 21 : 0 ]), | |
| 245 | .en (io_cmp_sync_en_r1), | |
| 246 | .l1clk (l1clk_cmp), | |
| 247 | .siclk(siclk), | |
| 248 | .soclk(soclk) | |
| 249 | ); | |
| 250 | ||
| 251 | msff_ctl_macro__en_1__width_22 ff_sync_read_data | |
| 252 | ( | |
| 253 | .scan_in(ff_sync_read_data_scanin), | |
| 254 | .scan_out(ff_sync_read_data_scanout), | |
| 255 | .dout (sync_read[ 21 : 0 ]), | |
| 256 | .din ((count==5'd1) ? sram_read_data[ 21 : 0 ] : sync_read[ 21 : 0 ]), | |
| 257 | .en (cmp_io_sync_en_r1), | |
| 258 | .l1clk (l1clk_cmp), | |
| 259 | .siclk(siclk), | |
| 260 | .soclk(soclk) | |
| 261 | ); | |
| 262 | ||
| 263 | msff_ctl_macro__en_1__width_1 ff_sync_sram_clr | |
| 264 | ( | |
| 265 | .scan_in(ff_sync_sram_clr_scanin), | |
| 266 | .scan_out(ff_sync_sram_clr_scanout), | |
| 267 | .dout (sync_clr), | |
| 268 | .din (efu_hdr_clr_r1), | |
| 269 | .en (io_cmp_sync_en_r1), | |
| 270 | .l1clk (l1clk_cmp), | |
| 271 | .siclk(siclk), | |
| 272 | .soclk(soclk) | |
| 273 | ); | |
| 274 | ||
| 275 | msff_ctl_macro__en_1__width_1 ff_sync_sram_wr | |
| 276 | ( | |
| 277 | .scan_in(ff_sync_sram_wr_scanin), | |
| 278 | .scan_out(ff_sync_sram_wr_scanout), | |
| 279 | .dout (sync_wr), | |
| 280 | .din (wr_en), | |
| 281 | .en (io_cmp_sync_en_r1), | |
| 282 | .l1clk (l1clk_cmp), | |
| 283 | .siclk(siclk), | |
| 284 | .soclk(soclk) | |
| 285 | ); | |
| 286 | ||
| 287 | ||
| 288 | ||
| 289 | assign load_en = (~efu_hdr_xfer_en_r2 & efu_hdr_xfer_en_r1); | |
| 290 | assign ld_rd_en = (count==5'd1); | |
| 291 | ||
| 292 | assign reset_count = ( count == 5'd0 ); | |
| 293 | assign rdreset_count = ( rdcount == 5'd0 ); | |
| 294 | ||
| 295 | assign count_in = load_en ? 5'd29 : reset_count ? 5'b0 : ( count - 5'b1); | |
| 296 | assign rdcount_in = ld_rd_en ? 5'd23 : rdreset_count ? 5'b0 : (rdcount - 5'b1); | |
| 297 | ||
| 298 | msff_ctl_macro__en_1__width_5 ff_counter_slice | |
| 299 | ( | |
| 300 | .scan_in(ff_counter_slice_scanin), | |
| 301 | .scan_out(ff_counter_slice_scanout), | |
| 302 | .dout (count[ 4 : 0 ]), | |
| 303 | .din (count_in[ 4 : 0 ]), | |
| 304 | .en (io_cmp_sync_en_r1), | |
| 305 | .l1clk (l1clk_cmp), | |
| 306 | .siclk(siclk), | |
| 307 | .soclk(soclk) | |
| 308 | ); | |
| 309 | ||
| 310 | msff_ctl_macro__en_1__width_5 ff_rd_counter | |
| 311 | ( | |
| 312 | .scan_in(ff_rd_counter_scanin), | |
| 313 | .scan_out(ff_rd_counter_scanout), | |
| 314 | .dout (rdcount[ 4 : 0 ]), | |
| 315 | .din (rdcount_in[ 4 : 0 ]), | |
| 316 | .en (io_cmp_sync_en_r1), | |
| 317 | .l1clk (l1clk_cmp), | |
| 318 | .siclk(siclk), | |
| 319 | .soclk(soclk) | |
| 320 | ); | |
| 321 | ||
| 322 | spare_ctl_macro__num_4 spares_cmp ( | |
| 323 | .scan_in(spares_cmp_scanin), | |
| 324 | .scan_out(spares_cmp_scanout), | |
| 325 | .l1clk (l1clk_cmp), | |
| 326 | .siclk(siclk), | |
| 327 | .soclk(soclk) | |
| 328 | ); | |
| 329 | ||
| 330 | //assign hdr_sram_rvalue[10:0] = instr[10:0]; | |
| 331 | //assign hdr_sram_rid[10:0] = instr[21:11]; | |
| 332 | //assign hdr_sram_red_clr = efu_hdr_clr_r1; | |
| 333 | //assign hdr_sram_wr_en = |(count[1:0]); | |
| 334 | assign hdr_sram_rvalue[ 10 : 0 ] = sync_instr[ 10 : 0 ]; | |
| 335 | assign hdr_sram_rid[ 10 : 0 ] = sync_instr[ 21 : 11 ]; | |
| 336 | assign hdr_sram_red_clr = sync_clr; | |
| 337 | assign hdr_sram_wr_en = sync_wr; | |
| 338 | ||
| 339 | ||
| 340 | assign dispatch_read_data = (rdcount[ 4 : 0 ] < 5'd23 & rdcount[ 4 : 0 ] != 5'd0); | |
| 341 | ||
| 342 | assign hdr_efu_read_data = instr[ 21 ]; | |
| 343 | assign hdr_efu_xfer_en = dispatch_read_data; | |
| 344 | ||
| 345 | // fixscan start: | |
| 346 | assign ff_cmp_io_sync_en_scanin = scan_in ; | |
| 347 | assign ff_io_cmp_sync_en_scanin = ff_cmp_io_sync_en_scanout; | |
| 348 | assign ff_input_all_enable_scanin = ff_io_cmp_sync_en_scanout; | |
| 349 | assign ff_receiver_instr_slice_scanin = ff_input_all_enable_scanout; | |
| 350 | assign ff_counter_slice_scanin = ff_receiver_instr_slice_scanout; | |
| 351 | assign ff_sync_sram_data_scanin = ff_counter_slice_scanout; | |
| 352 | assign ff_sync_read_data_scanin = ff_sync_sram_data_scanout; | |
| 353 | assign ff_sync_sram_clr_scanin = ff_sync_read_data_scanout; | |
| 354 | assign ff_sync_sram_wr_scanin = ff_sync_sram_clr_scanout; | |
| 355 | assign ff_rd_counter_scanin = ff_sync_sram_wr_scanout; | |
| 356 | assign spares_cmp_scanin = ff_rd_counter_scanout ; | |
| 357 | assign scan_out = spares_cmp_scanout ; | |
| 358 | // fixscan end: | |
| 359 | endmodule | |
| 360 | ||
| 361 | ||
| 362 | ||
| 363 | ||
| 364 | ||
| 365 | ||
| 366 | // any PARAMS parms go into naming of macro | |
| 367 | ||
| 368 | module l1clkhdr_ctl_macro ( | |
| 369 | l2clk, | |
| 370 | l1en, | |
| 371 | pce_ov, | |
| 372 | stop, | |
| 373 | se, | |
| 374 | l1clk); | |
| 375 | ||
| 376 | ||
| 377 | input l2clk; | |
| 378 | input l1en; | |
| 379 | input pce_ov; | |
| 380 | input stop; | |
| 381 | input se; | |
| 382 | output l1clk; | |
| 383 | ||
| 384 | ||
| 385 | ||
| 386 | ||
| 387 | ||
| 388 | cl_sc1_l1hdr_8x c_0 ( | |
| 389 | ||
| 390 | ||
| 391 | .l2clk(l2clk), | |
| 392 | .pce(l1en), | |
| 393 | .l1clk(l1clk), | |
| 394 | .se(se), | |
| 395 | .pce_ov(pce_ov), | |
| 396 | .stop(stop) | |
| 397 | ); | |
| 398 | ||
| 399 | ||
| 400 | ||
| 401 | endmodule | |
| 402 | ||
| 403 | ||
| 404 | ||
| 405 | ||
| 406 | ||
| 407 | ||
| 408 | ||
| 409 | ||
| 410 | ||
| 411 | ||
| 412 | ||
| 413 | ||
| 414 | ||
| 415 | // any PARAMS parms go into naming of macro | |
| 416 | ||
| 417 | module msff_ctl_macro__width_1 ( | |
| 418 | din, | |
| 419 | l1clk, | |
| 420 | scan_in, | |
| 421 | siclk, | |
| 422 | soclk, | |
| 423 | dout, | |
| 424 | scan_out); | |
| 425 | wire [0:0] fdin; | |
| 426 | ||
| 427 | input [ 0 : 0 ] din; | |
| 428 | input l1clk; | |
| 429 | input scan_in; | |
| 430 | ||
| 431 | ||
| 432 | input siclk; | |
| 433 | input soclk; | |
| 434 | ||
| 435 | output [ 0 : 0 ] dout; | |
| 436 | output scan_out; | |
| 437 | assign fdin[ 0 : 0 ] = din[ 0 : 0 ]; | |
| 438 | ||
| 439 | ||
| 440 | ||
| 441 | ||
| 442 | ||
| 443 | ||
| 444 | ||
| 445 | ||
| 446 | ||
| 447 | ||
| 448 | ||
| 449 | ||
| 450 | ||
| 451 | ||
| 452 | ||
| 453 | ||
| 454 | ||
| 455 | cl_sc1_msff_4x d0_0 ( | |
| 456 | .l1clk(l1clk), | |
| 457 | .siclk(siclk), | |
| 458 | .soclk(soclk), | |
| 459 | .d(fdin[ 0 ]), | |
| 460 | .si(scan_in), | |
| 461 | .so(scan_out), | |
| 462 | .q(dout[ 0 ]) | |
| 463 | ); | |
| 464 | ||
| 465 | ||
| 466 | ||
| 467 | ||
| 468 | endmodule | |
| 469 | ||
| 470 | ||
| 471 | ||
| 472 | ||
| 473 | ||
| 474 | ||
| 475 | ||
| 476 | ||
| 477 | ||
| 478 | ||
| 479 | ||
| 480 | ||
| 481 | ||
| 482 | // any PARAMS parms go into naming of macro | |
| 483 | ||
| 484 | module msff_ctl_macro__en_1__width_4 ( | |
| 485 | din, | |
| 486 | en, | |
| 487 | l1clk, | |
| 488 | scan_in, | |
| 489 | siclk, | |
| 490 | soclk, | |
| 491 | dout, | |
| 492 | scan_out); | |
| 493 | wire [3:0] fdin; | |
| 494 | wire [3:1] sout; | |
| 495 | ||
| 496 | input [ 3 : 0 ] din; | |
| 497 | input en; | |
| 498 | input l1clk; | |
| 499 | input scan_in; | |
| 500 | ||
| 501 | ||
| 502 | input siclk; | |
| 503 | input soclk; | |
| 504 | ||
| 505 | output [ 3 : 0 ] dout; | |
| 506 | output scan_out; | |
| 507 | assign fdin[ 3 : 0 ] = (din[ 3 : 0 ] & {4{en}}) | (dout[ 3 : 0 ] & ~{4{en}}); | |
| 508 | ||
| 509 | ||
| 510 | ||
| 511 | ||
| 512 | ||
| 513 | ||
| 514 | ||
| 515 | ||
| 516 | ||
| 517 | ||
| 518 | ||
| 519 | ||
| 520 | ||
| 521 | ||
| 522 | ||
| 523 | ||
| 524 | ||
| 525 | cl_sc1_msff_4x d0_0 ( | |
| 526 | .l1clk(l1clk), | |
| 527 | .siclk(siclk), | |
| 528 | .soclk(soclk), | |
| 529 | .d(fdin[ 0 ]), | |
| 530 | .si(sout[ 1 ]), | |
| 531 | .so(scan_out), | |
| 532 | .q(dout[ 0 ]) | |
| 533 | ); | |
| 534 | cl_sc1_msff_4x d0_1 ( | |
| 535 | .l1clk(l1clk), | |
| 536 | .siclk(siclk), | |
| 537 | .soclk(soclk), | |
| 538 | .d(fdin[ 1 ]), | |
| 539 | .si(sout[ 2 ]), | |
| 540 | .so(sout[ 1 ]), | |
| 541 | .q(dout[ 1 ]) | |
| 542 | ); | |
| 543 | cl_sc1_msff_4x d0_2 ( | |
| 544 | .l1clk(l1clk), | |
| 545 | .siclk(siclk), | |
| 546 | .soclk(soclk), | |
| 547 | .d(fdin[ 2 ]), | |
| 548 | .si(sout[ 3 ]), | |
| 549 | .so(sout[ 2 ]), | |
| 550 | .q(dout[ 2 ]) | |
| 551 | ); | |
| 552 | cl_sc1_msff_4x d0_3 ( | |
| 553 | .l1clk(l1clk), | |
| 554 | .siclk(siclk), | |
| 555 | .soclk(soclk), | |
| 556 | .d(fdin[ 3 ]), | |
| 557 | .si(scan_in), | |
| 558 | .so(sout[ 3 ]), | |
| 559 | .q(dout[ 3 ]) | |
| 560 | ); | |
| 561 | ||
| 562 | ||
| 563 | ||
| 564 | ||
| 565 | endmodule | |
| 566 | ||
| 567 | ||
| 568 | ||
| 569 | ||
| 570 | ||
| 571 | ||
| 572 | ||
| 573 | ||
| 574 | ||
| 575 | ||
| 576 | ||
| 577 | ||
| 578 | ||
| 579 | // any PARAMS parms go into naming of macro | |
| 580 | ||
| 581 | module msff_ctl_macro__en_1__width_22 ( | |
| 582 | din, | |
| 583 | en, | |
| 584 | l1clk, | |
| 585 | scan_in, | |
| 586 | siclk, | |
| 587 | soclk, | |
| 588 | dout, | |
| 589 | scan_out); | |
| 590 | wire [21:0] fdin; | |
| 591 | wire [21:1] sout; | |
| 592 | ||
| 593 | input [ 21 : 0 ] din; | |
| 594 | input en; | |
| 595 | input l1clk; | |
| 596 | input scan_in; | |
| 597 | ||
| 598 | ||
| 599 | input siclk; | |
| 600 | input soclk; | |
| 601 | ||
| 602 | output [ 21 : 0 ] dout; | |
| 603 | output scan_out; | |
| 604 | assign fdin[ 21 : 0 ] = (din[ 21 : 0 ] & {22{en}}) | (dout[ 21 : 0 ] & ~{22{en}}); | |
| 605 | ||
| 606 | ||
| 607 | ||
| 608 | ||
| 609 | ||
| 610 | ||
| 611 | ||
| 612 | ||
| 613 | ||
| 614 | ||
| 615 | ||
| 616 | ||
| 617 | ||
| 618 | ||
| 619 | ||
| 620 | ||
| 621 | ||
| 622 | cl_sc1_msff_4x d0_0 ( | |
| 623 | .l1clk(l1clk), | |
| 624 | .siclk(siclk), | |
| 625 | .soclk(soclk), | |
| 626 | .d(fdin[ 0 ]), | |
| 627 | .si(sout[ 1 ]), | |
| 628 | .so(scan_out), | |
| 629 | .q(dout[ 0 ]) | |
| 630 | ); | |
| 631 | cl_sc1_msff_4x d0_1 ( | |
| 632 | .l1clk(l1clk), | |
| 633 | .siclk(siclk), | |
| 634 | .soclk(soclk), | |
| 635 | .d(fdin[ 1 ]), | |
| 636 | .si(sout[ 2 ]), | |
| 637 | .so(sout[ 1 ]), | |
| 638 | .q(dout[ 1 ]) | |
| 639 | ); | |
| 640 | cl_sc1_msff_4x d0_2 ( | |
| 641 | .l1clk(l1clk), | |
| 642 | .siclk(siclk), | |
| 643 | .soclk(soclk), | |
| 644 | .d(fdin[ 2 ]), | |
| 645 | .si(sout[ 3 ]), | |
| 646 | .so(sout[ 2 ]), | |
| 647 | .q(dout[ 2 ]) | |
| 648 | ); | |
| 649 | cl_sc1_msff_4x d0_3 ( | |
| 650 | .l1clk(l1clk), | |
| 651 | .siclk(siclk), | |
| 652 | .soclk(soclk), | |
| 653 | .d(fdin[ 3 ]), | |
| 654 | .si(sout[ 4 ]), | |
| 655 | .so(sout[ 3 ]), | |
| 656 | .q(dout[ 3 ]) | |
| 657 | ); | |
| 658 | cl_sc1_msff_4x d0_4 ( | |
| 659 | .l1clk(l1clk), | |
| 660 | .siclk(siclk), | |
| 661 | .soclk(soclk), | |
| 662 | .d(fdin[ 4 ]), | |
| 663 | .si(sout[ 5 ]), | |
| 664 | .so(sout[ 4 ]), | |
| 665 | .q(dout[ 4 ]) | |
| 666 | ); | |
| 667 | cl_sc1_msff_4x d0_5 ( | |
| 668 | .l1clk(l1clk), | |
| 669 | .siclk(siclk), | |
| 670 | .soclk(soclk), | |
| 671 | .d(fdin[ 5 ]), | |
| 672 | .si(sout[ 6 ]), | |
| 673 | .so(sout[ 5 ]), | |
| 674 | .q(dout[ 5 ]) | |
| 675 | ); | |
| 676 | cl_sc1_msff_4x d0_6 ( | |
| 677 | .l1clk(l1clk), | |
| 678 | .siclk(siclk), | |
| 679 | .soclk(soclk), | |
| 680 | .d(fdin[ 6 ]), | |
| 681 | .si(sout[ 7 ]), | |
| 682 | .so(sout[ 6 ]), | |
| 683 | .q(dout[ 6 ]) | |
| 684 | ); | |
| 685 | cl_sc1_msff_4x d0_7 ( | |
| 686 | .l1clk(l1clk), | |
| 687 | .siclk(siclk), | |
| 688 | .soclk(soclk), | |
| 689 | .d(fdin[ 7 ]), | |
| 690 | .si(sout[ 8 ]), | |
| 691 | .so(sout[ 7 ]), | |
| 692 | .q(dout[ 7 ]) | |
| 693 | ); | |
| 694 | cl_sc1_msff_4x d0_8 ( | |
| 695 | .l1clk(l1clk), | |
| 696 | .siclk(siclk), | |
| 697 | .soclk(soclk), | |
| 698 | .d(fdin[ 8 ]), | |
| 699 | .si(sout[ 9 ]), | |
| 700 | .so(sout[ 8 ]), | |
| 701 | .q(dout[ 8 ]) | |
| 702 | ); | |
| 703 | cl_sc1_msff_4x d0_9 ( | |
| 704 | .l1clk(l1clk), | |
| 705 | .siclk(siclk), | |
| 706 | .soclk(soclk), | |
| 707 | .d(fdin[ 9 ]), | |
| 708 | .si(sout[ 10 ]), | |
| 709 | .so(sout[ 9 ]), | |
| 710 | .q(dout[ 9 ]) | |
| 711 | ); | |
| 712 | cl_sc1_msff_4x d0_10 ( | |
| 713 | .l1clk(l1clk), | |
| 714 | .siclk(siclk), | |
| 715 | .soclk(soclk), | |
| 716 | .d(fdin[ 10 ]), | |
| 717 | .si(sout[ 11 ]), | |
| 718 | .so(sout[ 10 ]), | |
| 719 | .q(dout[ 10 ]) | |
| 720 | ); | |
| 721 | cl_sc1_msff_4x d0_11 ( | |
| 722 | .l1clk(l1clk), | |
| 723 | .siclk(siclk), | |
| 724 | .soclk(soclk), | |
| 725 | .d(fdin[ 11 ]), | |
| 726 | .si(sout[ 12 ]), | |
| 727 | .so(sout[ 11 ]), | |
| 728 | .q(dout[ 11 ]) | |
| 729 | ); | |
| 730 | cl_sc1_msff_4x d0_12 ( | |
| 731 | .l1clk(l1clk), | |
| 732 | .siclk(siclk), | |
| 733 | .soclk(soclk), | |
| 734 | .d(fdin[ 12 ]), | |
| 735 | .si(sout[ 13 ]), | |
| 736 | .so(sout[ 12 ]), | |
| 737 | .q(dout[ 12 ]) | |
| 738 | ); | |
| 739 | cl_sc1_msff_4x d0_13 ( | |
| 740 | .l1clk(l1clk), | |
| 741 | .siclk(siclk), | |
| 742 | .soclk(soclk), | |
| 743 | .d(fdin[ 13 ]), | |
| 744 | .si(sout[ 14 ]), | |
| 745 | .so(sout[ 13 ]), | |
| 746 | .q(dout[ 13 ]) | |
| 747 | ); | |
| 748 | cl_sc1_msff_4x d0_14 ( | |
| 749 | .l1clk(l1clk), | |
| 750 | .siclk(siclk), | |
| 751 | .soclk(soclk), | |
| 752 | .d(fdin[ 14 ]), | |
| 753 | .si(sout[ 15 ]), | |
| 754 | .so(sout[ 14 ]), | |
| 755 | .q(dout[ 14 ]) | |
| 756 | ); | |
| 757 | cl_sc1_msff_4x d0_15 ( | |
| 758 | .l1clk(l1clk), | |
| 759 | .siclk(siclk), | |
| 760 | .soclk(soclk), | |
| 761 | .d(fdin[ 15 ]), | |
| 762 | .si(sout[ 16 ]), | |
| 763 | .so(sout[ 15 ]), | |
| 764 | .q(dout[ 15 ]) | |
| 765 | ); | |
| 766 | cl_sc1_msff_4x d0_16 ( | |
| 767 | .l1clk(l1clk), | |
| 768 | .siclk(siclk), | |
| 769 | .soclk(soclk), | |
| 770 | .d(fdin[ 16 ]), | |
| 771 | .si(sout[ 17 ]), | |
| 772 | .so(sout[ 16 ]), | |
| 773 | .q(dout[ 16 ]) | |
| 774 | ); | |
| 775 | cl_sc1_msff_4x d0_17 ( | |
| 776 | .l1clk(l1clk), | |
| 777 | .siclk(siclk), | |
| 778 | .soclk(soclk), | |
| 779 | .d(fdin[ 17 ]), | |
| 780 | .si(sout[ 18 ]), | |
| 781 | .so(sout[ 17 ]), | |
| 782 | .q(dout[ 17 ]) | |
| 783 | ); | |
| 784 | cl_sc1_msff_4x d0_18 ( | |
| 785 | .l1clk(l1clk), | |
| 786 | .siclk(siclk), | |
| 787 | .soclk(soclk), | |
| 788 | .d(fdin[ 18 ]), | |
| 789 | .si(sout[ 19 ]), | |
| 790 | .so(sout[ 18 ]), | |
| 791 | .q(dout[ 18 ]) | |
| 792 | ); | |
| 793 | cl_sc1_msff_4x d0_19 ( | |
| 794 | .l1clk(l1clk), | |
| 795 | .siclk(siclk), | |
| 796 | .soclk(soclk), | |
| 797 | .d(fdin[ 19 ]), | |
| 798 | .si(sout[ 20 ]), | |
| 799 | .so(sout[ 19 ]), | |
| 800 | .q(dout[ 19 ]) | |
| 801 | ); | |
| 802 | cl_sc1_msff_4x d0_20 ( | |
| 803 | .l1clk(l1clk), | |
| 804 | .siclk(siclk), | |
| 805 | .soclk(soclk), | |
| 806 | .d(fdin[ 20 ]), | |
| 807 | .si(sout[ 21 ]), | |
| 808 | .so(sout[ 20 ]), | |
| 809 | .q(dout[ 20 ]) | |
| 810 | ); | |
| 811 | cl_sc1_msff_4x d0_21 ( | |
| 812 | .l1clk(l1clk), | |
| 813 | .siclk(siclk), | |
| 814 | .soclk(soclk), | |
| 815 | .d(fdin[ 21 ]), | |
| 816 | .si(scan_in), | |
| 817 | .so(sout[ 21 ]), | |
| 818 | .q(dout[ 21 ]) | |
| 819 | ); | |
| 820 | ||
| 821 | ||
| 822 | ||
| 823 | ||
| 824 | endmodule | |
| 825 | ||
| 826 | ||
| 827 | ||
| 828 | ||
| 829 | ||
| 830 | ||
| 831 | ||
| 832 | ||
| 833 | ||
| 834 | ||
| 835 | ||
| 836 | ||
| 837 | ||
| 838 | // any PARAMS parms go into naming of macro | |
| 839 | ||
| 840 | module msff_ctl_macro__en_1__width_1 ( | |
| 841 | din, | |
| 842 | en, | |
| 843 | l1clk, | |
| 844 | scan_in, | |
| 845 | siclk, | |
| 846 | soclk, | |
| 847 | dout, | |
| 848 | scan_out); | |
| 849 | wire [0:0] fdin; | |
| 850 | ||
| 851 | input [ 0 : 0 ] din; | |
| 852 | input en; | |
| 853 | input l1clk; | |
| 854 | input scan_in; | |
| 855 | ||
| 856 | ||
| 857 | input siclk; | |
| 858 | input soclk; | |
| 859 | ||
| 860 | output [ 0 : 0 ] dout; | |
| 861 | output scan_out; | |
| 862 | assign fdin[ 0 : 0 ] = (din[ 0 : 0 ] & {1{en}}) | (dout[ 0 : 0 ] & ~{1{en}}); | |
| 863 | ||
| 864 | ||
| 865 | ||
| 866 | ||
| 867 | ||
| 868 | ||
| 869 | ||
| 870 | ||
| 871 | ||
| 872 | ||
| 873 | ||
| 874 | ||
| 875 | ||
| 876 | ||
| 877 | ||
| 878 | ||
| 879 | ||
| 880 | cl_sc1_msff_4x d0_0 ( | |
| 881 | .l1clk(l1clk), | |
| 882 | .siclk(siclk), | |
| 883 | .soclk(soclk), | |
| 884 | .d(fdin[ 0 ]), | |
| 885 | .si(scan_in), | |
| 886 | .so(scan_out), | |
| 887 | .q(dout[ 0 ]) | |
| 888 | ); | |
| 889 | ||
| 890 | ||
| 891 | ||
| 892 | ||
| 893 | endmodule | |
| 894 | ||
| 895 | ||
| 896 | ||
| 897 | ||
| 898 | ||
| 899 | ||
| 900 | ||
| 901 | ||
| 902 | ||
| 903 | ||
| 904 | ||
| 905 | ||
| 906 | ||
| 907 | // any PARAMS parms go into naming of macro | |
| 908 | ||
| 909 | module msff_ctl_macro__en_1__width_5 ( | |
| 910 | din, | |
| 911 | en, | |
| 912 | l1clk, | |
| 913 | scan_in, | |
| 914 | siclk, | |
| 915 | soclk, | |
| 916 | dout, | |
| 917 | scan_out); | |
| 918 | wire [4:0] fdin; | |
| 919 | wire [4:1] sout; | |
| 920 | ||
| 921 | input [ 4 : 0 ] din; | |
| 922 | input en; | |
| 923 | input l1clk; | |
| 924 | input scan_in; | |
| 925 | ||
| 926 | ||
| 927 | input siclk; | |
| 928 | input soclk; | |
| 929 | ||
| 930 | output [ 4 : 0 ] dout; | |
| 931 | output scan_out; | |
| 932 | assign fdin[ 4 : 0 ] = (din[ 4 : 0 ] & {5{en}}) | (dout[ 4 : 0 ] & ~{5{en}}); | |
| 933 | ||
| 934 | ||
| 935 | ||
| 936 | ||
| 937 | ||
| 938 | ||
| 939 | ||
| 940 | ||
| 941 | ||
| 942 | ||
| 943 | ||
| 944 | ||
| 945 | ||
| 946 | ||
| 947 | ||
| 948 | ||
| 949 | ||
| 950 | cl_sc1_msff_4x d0_0 ( | |
| 951 | .l1clk(l1clk), | |
| 952 | .siclk(siclk), | |
| 953 | .soclk(soclk), | |
| 954 | .d(fdin[ 0 ]), | |
| 955 | .si(sout[ 1 ]), | |
| 956 | .so(scan_out), | |
| 957 | .q(dout[ 0 ]) | |
| 958 | ); | |
| 959 | cl_sc1_msff_4x d0_1 ( | |
| 960 | .l1clk(l1clk), | |
| 961 | .siclk(siclk), | |
| 962 | .soclk(soclk), | |
| 963 | .d(fdin[ 1 ]), | |
| 964 | .si(sout[ 2 ]), | |
| 965 | .so(sout[ 1 ]), | |
| 966 | .q(dout[ 1 ]) | |
| 967 | ); | |
| 968 | cl_sc1_msff_4x d0_2 ( | |
| 969 | .l1clk(l1clk), | |
| 970 | .siclk(siclk), | |
| 971 | .soclk(soclk), | |
| 972 | .d(fdin[ 2 ]), | |
| 973 | .si(sout[ 3 ]), | |
| 974 | .so(sout[ 2 ]), | |
| 975 | .q(dout[ 2 ]) | |
| 976 | ); | |
| 977 | cl_sc1_msff_4x d0_3 ( | |
| 978 | .l1clk(l1clk), | |
| 979 | .siclk(siclk), | |
| 980 | .soclk(soclk), | |
| 981 | .d(fdin[ 3 ]), | |
| 982 | .si(sout[ 4 ]), | |
| 983 | .so(sout[ 3 ]), | |
| 984 | .q(dout[ 3 ]) | |
| 985 | ); | |
| 986 | cl_sc1_msff_4x d0_4 ( | |
| 987 | .l1clk(l1clk), | |
| 988 | .siclk(siclk), | |
| 989 | .soclk(soclk), | |
| 990 | .d(fdin[ 4 ]), | |
| 991 | .si(scan_in), | |
| 992 | .so(sout[ 4 ]), | |
| 993 | .q(dout[ 4 ]) | |
| 994 | ); | |
| 995 | ||
| 996 | ||
| 997 | ||
| 998 | ||
| 999 | endmodule | |
| 1000 | ||
| 1001 | ||
| 1002 | ||
| 1003 | ||
| 1004 | ||
| 1005 | ||
| 1006 | ||
| 1007 | ||
| 1008 | ||
| 1009 | // Description: Spare gate macro for control blocks | |
| 1010 | // | |
| 1011 | // Param num controls the number of times the macro is added | |
| 1012 | // flops=0 can be used to use only combination spare logic | |
| 1013 | ||
| 1014 | ||
| 1015 | module spare_ctl_macro__num_4 ( | |
| 1016 | l1clk, | |
| 1017 | scan_in, | |
| 1018 | siclk, | |
| 1019 | soclk, | |
| 1020 | scan_out); | |
| 1021 | wire si_0; | |
| 1022 | wire so_0; | |
| 1023 | wire spare0_flop_unused; | |
| 1024 | wire spare0_buf_32x_unused; | |
| 1025 | wire spare0_nand3_8x_unused; | |
| 1026 | wire spare0_inv_8x_unused; | |
| 1027 | wire spare0_aoi22_4x_unused; | |
| 1028 | wire spare0_buf_8x_unused; | |
| 1029 | wire spare0_oai22_4x_unused; | |
| 1030 | wire spare0_inv_16x_unused; | |
| 1031 | wire spare0_nand2_16x_unused; | |
| 1032 | wire spare0_nor3_4x_unused; | |
| 1033 | wire spare0_nand2_8x_unused; | |
| 1034 | wire spare0_buf_16x_unused; | |
| 1035 | wire spare0_nor2_16x_unused; | |
| 1036 | wire spare0_inv_32x_unused; | |
| 1037 | wire si_1; | |
| 1038 | wire so_1; | |
| 1039 | wire spare1_flop_unused; | |
| 1040 | wire spare1_buf_32x_unused; | |
| 1041 | wire spare1_nand3_8x_unused; | |
| 1042 | wire spare1_inv_8x_unused; | |
| 1043 | wire spare1_aoi22_4x_unused; | |
| 1044 | wire spare1_buf_8x_unused; | |
| 1045 | wire spare1_oai22_4x_unused; | |
| 1046 | wire spare1_inv_16x_unused; | |
| 1047 | wire spare1_nand2_16x_unused; | |
| 1048 | wire spare1_nor3_4x_unused; | |
| 1049 | wire spare1_nand2_8x_unused; | |
| 1050 | wire spare1_buf_16x_unused; | |
| 1051 | wire spare1_nor2_16x_unused; | |
| 1052 | wire spare1_inv_32x_unused; | |
| 1053 | wire si_2; | |
| 1054 | wire so_2; | |
| 1055 | wire spare2_flop_unused; | |
| 1056 | wire spare2_buf_32x_unused; | |
| 1057 | wire spare2_nand3_8x_unused; | |
| 1058 | wire spare2_inv_8x_unused; | |
| 1059 | wire spare2_aoi22_4x_unused; | |
| 1060 | wire spare2_buf_8x_unused; | |
| 1061 | wire spare2_oai22_4x_unused; | |
| 1062 | wire spare2_inv_16x_unused; | |
| 1063 | wire spare2_nand2_16x_unused; | |
| 1064 | wire spare2_nor3_4x_unused; | |
| 1065 | wire spare2_nand2_8x_unused; | |
| 1066 | wire spare2_buf_16x_unused; | |
| 1067 | wire spare2_nor2_16x_unused; | |
| 1068 | wire spare2_inv_32x_unused; | |
| 1069 | wire si_3; | |
| 1070 | wire so_3; | |
| 1071 | wire spare3_flop_unused; | |
| 1072 | wire spare3_buf_32x_unused; | |
| 1073 | wire spare3_nand3_8x_unused; | |
| 1074 | wire spare3_inv_8x_unused; | |
| 1075 | wire spare3_aoi22_4x_unused; | |
| 1076 | wire spare3_buf_8x_unused; | |
| 1077 | wire spare3_oai22_4x_unused; | |
| 1078 | wire spare3_inv_16x_unused; | |
| 1079 | wire spare3_nand2_16x_unused; | |
| 1080 | wire spare3_nor3_4x_unused; | |
| 1081 | wire spare3_nand2_8x_unused; | |
| 1082 | wire spare3_buf_16x_unused; | |
| 1083 | wire spare3_nor2_16x_unused; | |
| 1084 | wire spare3_inv_32x_unused; | |
| 1085 | ||
| 1086 | ||
| 1087 | input l1clk; | |
| 1088 | input scan_in; | |
| 1089 | input siclk; | |
| 1090 | input soclk; | |
| 1091 | output scan_out; | |
| 1092 | ||
| 1093 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
| 1094 | .siclk(siclk), | |
| 1095 | .soclk(soclk), | |
| 1096 | .si(si_0), | |
| 1097 | .so(so_0), | |
| 1098 | .d(1'b0), | |
| 1099 | .q(spare0_flop_unused)); | |
| 1100 | assign si_0 = scan_in; | |
| 1101 | ||
| 1102 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
| 1103 | .out(spare0_buf_32x_unused)); | |
| 1104 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
| 1105 | .in1(1'b1), | |
| 1106 | .in2(1'b1), | |
| 1107 | .out(spare0_nand3_8x_unused)); | |
| 1108 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
| 1109 | .out(spare0_inv_8x_unused)); | |
| 1110 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
| 1111 | .in01(1'b1), | |
| 1112 | .in10(1'b1), | |
| 1113 | .in11(1'b1), | |
| 1114 | .out(spare0_aoi22_4x_unused)); | |
| 1115 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
| 1116 | .out(spare0_buf_8x_unused)); | |
| 1117 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
| 1118 | .in01(1'b1), | |
| 1119 | .in10(1'b1), | |
| 1120 | .in11(1'b1), | |
| 1121 | .out(spare0_oai22_4x_unused)); | |
| 1122 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
| 1123 | .out(spare0_inv_16x_unused)); | |
| 1124 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
| 1125 | .in1(1'b1), | |
| 1126 | .out(spare0_nand2_16x_unused)); | |
| 1127 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
| 1128 | .in1(1'b0), | |
| 1129 | .in2(1'b0), | |
| 1130 | .out(spare0_nor3_4x_unused)); | |
| 1131 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
| 1132 | .in1(1'b1), | |
| 1133 | .out(spare0_nand2_8x_unused)); | |
| 1134 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
| 1135 | .out(spare0_buf_16x_unused)); | |
| 1136 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
| 1137 | .in1(1'b0), | |
| 1138 | .out(spare0_nor2_16x_unused)); | |
| 1139 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
| 1140 | .out(spare0_inv_32x_unused)); | |
| 1141 | ||
| 1142 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
| 1143 | .siclk(siclk), | |
| 1144 | .soclk(soclk), | |
| 1145 | .si(si_1), | |
| 1146 | .so(so_1), | |
| 1147 | .d(1'b0), | |
| 1148 | .q(spare1_flop_unused)); | |
| 1149 | assign si_1 = so_0; | |
| 1150 | ||
| 1151 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
| 1152 | .out(spare1_buf_32x_unused)); | |
| 1153 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
| 1154 | .in1(1'b1), | |
| 1155 | .in2(1'b1), | |
| 1156 | .out(spare1_nand3_8x_unused)); | |
| 1157 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
| 1158 | .out(spare1_inv_8x_unused)); | |
| 1159 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
| 1160 | .in01(1'b1), | |
| 1161 | .in10(1'b1), | |
| 1162 | .in11(1'b1), | |
| 1163 | .out(spare1_aoi22_4x_unused)); | |
| 1164 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
| 1165 | .out(spare1_buf_8x_unused)); | |
| 1166 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
| 1167 | .in01(1'b1), | |
| 1168 | .in10(1'b1), | |
| 1169 | .in11(1'b1), | |
| 1170 | .out(spare1_oai22_4x_unused)); | |
| 1171 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
| 1172 | .out(spare1_inv_16x_unused)); | |
| 1173 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
| 1174 | .in1(1'b1), | |
| 1175 | .out(spare1_nand2_16x_unused)); | |
| 1176 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
| 1177 | .in1(1'b0), | |
| 1178 | .in2(1'b0), | |
| 1179 | .out(spare1_nor3_4x_unused)); | |
| 1180 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
| 1181 | .in1(1'b1), | |
| 1182 | .out(spare1_nand2_8x_unused)); | |
| 1183 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
| 1184 | .out(spare1_buf_16x_unused)); | |
| 1185 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
| 1186 | .in1(1'b0), | |
| 1187 | .out(spare1_nor2_16x_unused)); | |
| 1188 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
| 1189 | .out(spare1_inv_32x_unused)); | |
| 1190 | ||
| 1191 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
| 1192 | .siclk(siclk), | |
| 1193 | .soclk(soclk), | |
| 1194 | .si(si_2), | |
| 1195 | .so(so_2), | |
| 1196 | .d(1'b0), | |
| 1197 | .q(spare2_flop_unused)); | |
| 1198 | assign si_2 = so_1; | |
| 1199 | ||
| 1200 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
| 1201 | .out(spare2_buf_32x_unused)); | |
| 1202 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
| 1203 | .in1(1'b1), | |
| 1204 | .in2(1'b1), | |
| 1205 | .out(spare2_nand3_8x_unused)); | |
| 1206 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
| 1207 | .out(spare2_inv_8x_unused)); | |
| 1208 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
| 1209 | .in01(1'b1), | |
| 1210 | .in10(1'b1), | |
| 1211 | .in11(1'b1), | |
| 1212 | .out(spare2_aoi22_4x_unused)); | |
| 1213 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
| 1214 | .out(spare2_buf_8x_unused)); | |
| 1215 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
| 1216 | .in01(1'b1), | |
| 1217 | .in10(1'b1), | |
| 1218 | .in11(1'b1), | |
| 1219 | .out(spare2_oai22_4x_unused)); | |
| 1220 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
| 1221 | .out(spare2_inv_16x_unused)); | |
| 1222 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
| 1223 | .in1(1'b1), | |
| 1224 | .out(spare2_nand2_16x_unused)); | |
| 1225 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
| 1226 | .in1(1'b0), | |
| 1227 | .in2(1'b0), | |
| 1228 | .out(spare2_nor3_4x_unused)); | |
| 1229 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
| 1230 | .in1(1'b1), | |
| 1231 | .out(spare2_nand2_8x_unused)); | |
| 1232 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
| 1233 | .out(spare2_buf_16x_unused)); | |
| 1234 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
| 1235 | .in1(1'b0), | |
| 1236 | .out(spare2_nor2_16x_unused)); | |
| 1237 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
| 1238 | .out(spare2_inv_32x_unused)); | |
| 1239 | ||
| 1240 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
| 1241 | .siclk(siclk), | |
| 1242 | .soclk(soclk), | |
| 1243 | .si(si_3), | |
| 1244 | .so(so_3), | |
| 1245 | .d(1'b0), | |
| 1246 | .q(spare3_flop_unused)); | |
| 1247 | assign si_3 = so_2; | |
| 1248 | ||
| 1249 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
| 1250 | .out(spare3_buf_32x_unused)); | |
| 1251 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
| 1252 | .in1(1'b1), | |
| 1253 | .in2(1'b1), | |
| 1254 | .out(spare3_nand3_8x_unused)); | |
| 1255 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
| 1256 | .out(spare3_inv_8x_unused)); | |
| 1257 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
| 1258 | .in01(1'b1), | |
| 1259 | .in10(1'b1), | |
| 1260 | .in11(1'b1), | |
| 1261 | .out(spare3_aoi22_4x_unused)); | |
| 1262 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
| 1263 | .out(spare3_buf_8x_unused)); | |
| 1264 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
| 1265 | .in01(1'b1), | |
| 1266 | .in10(1'b1), | |
| 1267 | .in11(1'b1), | |
| 1268 | .out(spare3_oai22_4x_unused)); | |
| 1269 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
| 1270 | .out(spare3_inv_16x_unused)); | |
| 1271 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
| 1272 | .in1(1'b1), | |
| 1273 | .out(spare3_nand2_16x_unused)); | |
| 1274 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
| 1275 | .in1(1'b0), | |
| 1276 | .in2(1'b0), | |
| 1277 | .out(spare3_nor3_4x_unused)); | |
| 1278 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
| 1279 | .in1(1'b1), | |
| 1280 | .out(spare3_nand2_8x_unused)); | |
| 1281 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
| 1282 | .out(spare3_buf_16x_unused)); | |
| 1283 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
| 1284 | .in1(1'b0), | |
| 1285 | .out(spare3_nor2_16x_unused)); | |
| 1286 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
| 1287 | .out(spare3_inv_32x_unused)); | |
| 1288 | assign scan_out = so_3; | |
| 1289 | ||
| 1290 | ||
| 1291 | ||
| 1292 | endmodule | |
| 1293 |