projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: n2_dca_sp_9kb_cust.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | `ifndef FPGA | |
| 36 | module n2_dca_sp_9kb_cust ( | |
| 37 | dcache_rd_addr_e, | |
| 38 | dcache_alt_addr_e, | |
| 39 | dcache_alt_addr_sel_e, | |
| 40 | dcache_rvld_e, | |
| 41 | dcache_wvld_e, | |
| 42 | dcache_clk_en_e, | |
| 43 | dcache_wclk_en_e, | |
| 44 | dcache_rclk_en_m, | |
| 45 | dcache_wdata_e, | |
| 46 | dcache_wr_way_e, | |
| 47 | dcache_byte_wr_en_e, | |
| 48 | dcache_alt_rsel_way_m, | |
| 49 | dcache_rsel_way_b, | |
| 50 | dcache_alt_way_sel_m, | |
| 51 | lsu_l2fill_or_byp_data_m, | |
| 52 | dcache_bypass_e_, | |
| 53 | dcache_rdata_b, | |
| 54 | dcache_rparity_b, | |
| 55 | dcache_perr_w0_b, | |
| 56 | dcache_perr_w1_b, | |
| 57 | dcache_perr_w2_b, | |
| 58 | dcache_perr_w3_b, | |
| 59 | dcache_rdata_msb_w0_b, | |
| 60 | dcache_rdata_msb_w1_b, | |
| 61 | dcache_rdata_msb_w2_b, | |
| 62 | dcache_rdata_msb_w3_b, | |
| 63 | l2clk, | |
| 64 | scan_in, | |
| 65 | tcu_pce_ov, | |
| 66 | tcu_aclk, | |
| 67 | tcu_bclk, | |
| 68 | tcu_array_wr_inhibit, | |
| 69 | tcu_scan_en, | |
| 70 | tcu_se_scancollar_in, | |
| 71 | tcu_se_scancollar_out, | |
| 72 | scan_out, | |
| 73 | fuse_dca_repair_value, | |
| 74 | fuse_dca_repair_en, | |
| 75 | fuse_dca_rid, | |
| 76 | fuse_dca_wen, | |
| 77 | fuse_red_reset, | |
| 78 | dca_fuse_repair_value, | |
| 79 | dca_fuse_repair_en, | |
| 80 | vnw_ary); | |
| 81 | wire l1clk_in; | |
| 82 | wire l1clk_in_pm; | |
| 83 | wire l1clk_out_pm; | |
| 84 | wire l1clk_out; | |
| 85 | wire l1clk_free; | |
| 86 | wire l1clk_free_wpm; | |
| 87 | wire l1clk_red; | |
| 88 | wire [10:3] dcache_rwaddr_e; | |
| 89 | wire [7:0] lat_addr_scanin; | |
| 90 | wire [7:0] lat_addr_scanout; | |
| 91 | wire [10:3] dcache_rwaddr_eb; | |
| 92 | wire [10:3] dcache_rwaddr_l_unused; | |
| 93 | wire [3:0] wr_way_dec_e; | |
| 94 | wire [6:0] lat_ctl_eb_scanin; | |
| 95 | wire [6:0] lat_ctl_eb_scanout; | |
| 96 | wire dcache_rvld_top_eb; | |
| 97 | wire dcache_rvld_bot_eb; | |
| 98 | wire dcache_wvld_eb; | |
| 99 | wire [3:0] wr_way_dec_eb; | |
| 100 | wire [6:0] lat_ctl_unused; | |
| 101 | wire [2:0] dff_ctl_m_0_scanin; | |
| 102 | wire [2:0] dff_ctl_m_0_scanout; | |
| 103 | wire dcache_rvld_m; | |
| 104 | wire dcache_wvld_m; | |
| 105 | wire dcache_bypass_m_; | |
| 106 | wire [15:0] dff_ctl_m_1_scanin; | |
| 107 | wire [15:0] dff_ctl_m_1_scanout; | |
| 108 | wire [15:0] byte_wr_en_eb; | |
| 109 | wire [15:0] dff_ctl_l_unused; | |
| 110 | wire [4:0] dff_ctl_b_scanin; | |
| 111 | wire [4:0] dff_ctl_b_scanout; | |
| 112 | wire dcache_alt_way_sel_b; | |
| 113 | wire [3:0] dcache_alt_rsel_way_b; | |
| 114 | wire [143:0] dff_wdata_m_scanin; | |
| 115 | wire [143:0] dff_wdata_m_scanout; | |
| 116 | wire [15:0] dcache_wparity_m; | |
| 117 | wire [127:0] dcache_wdata_m; | |
| 118 | wire [5:0] fuse_dca_repair_value_ff; | |
| 119 | wire [1:0] fuse_dca_repair_en_ff; | |
| 120 | wire [1:0] fuse_dca_rid_ff; | |
| 121 | wire fuse_dca_wen_ff; | |
| 122 | wire fuse_red_reset_ff; | |
| 123 | wire [5:0] dca_fuse_repair_value_pre; | |
| 124 | wire [1:0] dca_fuse_repair_en_pre; | |
| 125 | wire [63:0] dcache_rdata_w0_m; | |
| 126 | wire [63:0] rdata_w0_m; | |
| 127 | wire [63:0] rdata_w1_m; | |
| 128 | wire [63:0] dcache_rdata_w1_m; | |
| 129 | wire [63:0] rdata_w2_m; | |
| 130 | wire [63:0] dcache_rdata_w2_m; | |
| 131 | wire [63:0] rdata_w3_m; | |
| 132 | wire [63:0] dcache_rdata_w3_m; | |
| 133 | wire [7:0] dff_msb_w0_scanin; | |
| 134 | wire [7:0] dff_msb_w0_scanout; | |
| 135 | wire [7:0] dff_msb_w1_scanin; | |
| 136 | wire [7:0] dff_msb_w1_scanout; | |
| 137 | wire [7:0] dff_msb_w2_scanin; | |
| 138 | wire [7:0] dff_msb_w2_scanout; | |
| 139 | wire [7:0] dff_msb_w3_scanin; | |
| 140 | wire [7:0] dff_msb_w3_scanout; | |
| 141 | wire [63:0] dff_rdata_w0_m_scanin; | |
| 142 | wire [63:0] dff_rdata_w0_m_scanout; | |
| 143 | wire [63:0] rdata_w0_b; | |
| 144 | wire [7:0] dff_rparity_w0_m_scanin; | |
| 145 | wire [7:0] dff_rparity_w0_m_scanout; | |
| 146 | wire [7:0] rparity_w0_m; | |
| 147 | wire [7:0] rparity_w0_b; | |
| 148 | wire [63:0] dff_rdata_w1_m_scanin; | |
| 149 | wire [63:0] dff_rdata_w1_m_scanout; | |
| 150 | wire [63:0] rdata_w1_b; | |
| 151 | wire [7:0] dff_rparity_w1_m_scanin; | |
| 152 | wire [7:0] dff_rparity_w1_m_scanout; | |
| 153 | wire [7:0] rparity_w1_m; | |
| 154 | wire [7:0] rparity_w1_b; | |
| 155 | wire [63:0] dff_rdata_w2_m_scanin; | |
| 156 | wire [63:0] dff_rdata_w2_m_scanout; | |
| 157 | wire [63:0] rdata_w2_b; | |
| 158 | wire [7:0] dff_rparity_w2_m_scanin; | |
| 159 | wire [7:0] dff_rparity_w2_m_scanout; | |
| 160 | wire [7:0] rparity_w2_m; | |
| 161 | wire [7:0] rparity_w2_b; | |
| 162 | wire [63:0] dff_rdata_w3_m_scanin; | |
| 163 | wire [63:0] dff_rdata_w3_m_scanout; | |
| 164 | wire [63:0] rdata_w3_b; | |
| 165 | wire [7:0] dff_rparity_w3_m_scanin; | |
| 166 | wire [7:0] dff_rparity_w3_m_scanout; | |
| 167 | wire [7:0] rparity_w3_m; | |
| 168 | wire [7:0] rparity_w3_b; | |
| 169 | wire [3:0] dcache_rd_sel_way_b; | |
| 170 | wire w0_p0_0; | |
| 171 | wire w0_p0_1; | |
| 172 | wire w0_p0_2; | |
| 173 | wire [7:0] w0_parity_m; | |
| 174 | wire w0_p1_0; | |
| 175 | wire w0_p1_1; | |
| 176 | wire w0_p1_2; | |
| 177 | wire w0_p2_0; | |
| 178 | wire w0_p2_1; | |
| 179 | wire w0_p2_2; | |
| 180 | wire w0_p3_0; | |
| 181 | wire w0_p3_1; | |
| 182 | wire w0_p3_2; | |
| 183 | wire w0_p4_0; | |
| 184 | wire w0_p4_1; | |
| 185 | wire w0_p4_2; | |
| 186 | wire w0_p5_0; | |
| 187 | wire w0_p5_1; | |
| 188 | wire w0_p5_2; | |
| 189 | wire w0_p6_0; | |
| 190 | wire w0_p6_1; | |
| 191 | wire w0_p6_2; | |
| 192 | wire w0_p7_0; | |
| 193 | wire w0_p7_1; | |
| 194 | wire w0_p7_2; | |
| 195 | wire w1_p0_0; | |
| 196 | wire w1_p0_1; | |
| 197 | wire w1_p0_2; | |
| 198 | wire [7:0] w1_parity_m; | |
| 199 | wire w1_p1_0; | |
| 200 | wire w1_p1_1; | |
| 201 | wire w1_p1_2; | |
| 202 | wire w1_p2_0; | |
| 203 | wire w1_p2_1; | |
| 204 | wire w1_p2_2; | |
| 205 | wire w1_p3_0; | |
| 206 | wire w1_p3_1; | |
| 207 | wire w1_p3_2; | |
| 208 | wire w1_p4_0; | |
| 209 | wire w1_p4_1; | |
| 210 | wire w1_p4_2; | |
| 211 | wire w1_p5_0; | |
| 212 | wire w1_p5_1; | |
| 213 | wire w1_p5_2; | |
| 214 | wire w1_p6_0; | |
| 215 | wire w1_p6_1; | |
| 216 | wire w1_p6_2; | |
| 217 | wire w1_p7_0; | |
| 218 | wire w1_p7_1; | |
| 219 | wire w1_p7_2; | |
| 220 | wire w2_p0_0; | |
| 221 | wire w2_p0_1; | |
| 222 | wire w2_p0_2; | |
| 223 | wire [7:0] w2_parity_m; | |
| 224 | wire w2_p1_0; | |
| 225 | wire w2_p1_1; | |
| 226 | wire w2_p1_2; | |
| 227 | wire w2_p2_0; | |
| 228 | wire w2_p2_1; | |
| 229 | wire w2_p2_2; | |
| 230 | wire w2_p3_0; | |
| 231 | wire w2_p3_1; | |
| 232 | wire w2_p3_2; | |
| 233 | wire w2_p4_0; | |
| 234 | wire w2_p4_1; | |
| 235 | wire w2_p4_2; | |
| 236 | wire w2_p5_0; | |
| 237 | wire w2_p5_1; | |
| 238 | wire w2_p5_2; | |
| 239 | wire w2_p6_0; | |
| 240 | wire w2_p6_1; | |
| 241 | wire w2_p6_2; | |
| 242 | wire w2_p7_0; | |
| 243 | wire w2_p7_1; | |
| 244 | wire w2_p7_2; | |
| 245 | wire w3_p0_0; | |
| 246 | wire w3_p0_1; | |
| 247 | wire w3_p0_2; | |
| 248 | wire [7:0] w3_parity_m; | |
| 249 | wire w3_p1_0; | |
| 250 | wire w3_p1_1; | |
| 251 | wire w3_p1_2; | |
| 252 | wire w3_p2_0; | |
| 253 | wire w3_p2_1; | |
| 254 | wire w3_p2_2; | |
| 255 | wire w3_p3_0; | |
| 256 | wire w3_p3_1; | |
| 257 | wire w3_p3_2; | |
| 258 | wire w3_p4_0; | |
| 259 | wire w3_p4_1; | |
| 260 | wire w3_p4_2; | |
| 261 | wire w3_p5_0; | |
| 262 | wire w3_p5_1; | |
| 263 | wire w3_p5_2; | |
| 264 | wire w3_p6_0; | |
| 265 | wire w3_p6_1; | |
| 266 | wire w3_p6_2; | |
| 267 | wire w3_p7_0; | |
| 268 | wire w3_p7_1; | |
| 269 | wire w3_p7_2; | |
| 270 | wire [7:0] dff_byte_perr_w0_scanin; | |
| 271 | wire [7:0] dff_byte_perr_w0_scanout; | |
| 272 | wire [7:0] w0_parity_b; | |
| 273 | wire [7:0] dff_byte_perr_w1_scanin; | |
| 274 | wire [7:0] dff_byte_perr_w1_scanout; | |
| 275 | wire [7:0] w1_parity_b; | |
| 276 | wire [7:0] dff_byte_perr_w2_scanin; | |
| 277 | wire [7:0] dff_byte_perr_w2_scanout; | |
| 278 | wire [7:0] w2_parity_b; | |
| 279 | wire [7:0] dff_byte_perr_w3_scanin; | |
| 280 | wire [7:0] dff_byte_perr_w3_scanout; | |
| 281 | wire [7:0] w3_parity_b; | |
| 282 | wire w0_parity_err_b; | |
| 283 | wire w1_parity_err_b; | |
| 284 | wire w2_parity_err_b; | |
| 285 | wire w3_parity_err_b; | |
| 286 | wire [11:0] dff_red_in_scanin; | |
| 287 | wire [11:0] dff_red_in_scanout; | |
| 288 | wire [7:0] dff_red_out_scanin; | |
| 289 | wire [7:0] dff_red_out_scanout; | |
| 290 | ||
| 291 | ||
| 292 | input [10:3] dcache_rd_addr_e; // read cache index [10:4] + bit [3] offset | |
| 293 | input [10:3] dcache_alt_addr_e; // write/bist/diagnostic read cache index + offset | |
| 294 | input dcache_alt_addr_sel_e; | |
| 295 | ||
| 296 | input dcache_rvld_e; // read accesses d$. | |
| 297 | input dcache_wvld_e; // valid write setup to m-stage. | |
| 298 | // 0in bits_on -var {dcache_rvld_e,dcache_wvld_e} -max 1 -message "Attempt to read AND write dcache on same cycle" | |
| 299 | input dcache_clk_en_e; // array clock enable | |
| 300 | input dcache_wclk_en_e; // write data/byte_wr_en flops clock enable | |
| 301 | input dcache_rclk_en_m; // read flops clock enable | |
| 302 | ||
| 303 | input [143:0] dcache_wdata_e; // write data - 16Bx8 + 8b parity. | |
| 304 | input [1:0] dcache_wr_way_e; // replacement way for load miss/store (encoded). | |
| 305 | input [15:0] dcache_byte_wr_en_e; // 16b byte wr enable for stores. | |
| 306 | ||
| 307 | input [3:0] dcache_alt_rsel_way_m;// bist/diagnostic read way select | |
| 308 | input [3:0] dcache_rsel_way_b; // load way select, connect to cache_way_hit | |
| 309 | input dcache_alt_way_sel_m; | |
| 310 | ||
| 311 | input [63:0] lsu_l2fill_or_byp_data_m; | |
| 312 | input dcache_bypass_e_; | |
| 313 | ||
| 314 | output [63:0] dcache_rdata_b; | |
| 315 | output [7:0] dcache_rparity_b; | |
| 316 | ||
| 317 | output dcache_perr_w0_b; | |
| 318 | output dcache_perr_w1_b; | |
| 319 | output dcache_perr_w2_b; | |
| 320 | output dcache_perr_w3_b; | |
| 321 | ||
| 322 | output [7:0] dcache_rdata_msb_w0_b; | |
| 323 | output [7:0] dcache_rdata_msb_w1_b; | |
| 324 | output [7:0] dcache_rdata_msb_w2_b; | |
| 325 | output [7:0] dcache_rdata_msb_w3_b; | |
| 326 | ||
| 327 | input l2clk; | |
| 328 | input scan_in; | |
| 329 | input tcu_pce_ov; | |
| 330 | input tcu_aclk; | |
| 331 | input tcu_bclk; | |
| 332 | input tcu_array_wr_inhibit; | |
| 333 | input tcu_scan_en; | |
| 334 | input tcu_se_scancollar_in; | |
| 335 | input tcu_se_scancollar_out; | |
| 336 | output scan_out; | |
| 337 | ||
| 338 | input [5:0] fuse_dca_repair_value; | |
| 339 | input [1:0] fuse_dca_repair_en; | |
| 340 | input [1:0] fuse_dca_rid; | |
| 341 | input fuse_dca_wen; | |
| 342 | input fuse_red_reset; | |
| 343 | output [5:0] dca_fuse_repair_value; | |
| 344 | output [1:0] dca_fuse_repair_en; | |
| 345 | ||
| 346 | input vnw_ary; | |
| 347 | ||
| 348 | // synopsys translate_off | |
| 349 | ||
| 350 | // 0in bits_on -var {~dcache_clk_en_e,dcache_wvld_e} -max 1 -message "Attempt to write with clk_en disabled" | |
| 351 | // 0in bits_on -var {~dcache_clk_en_e,dcache_rvld_e} -max 1 -message "Attempt to read with clk_en disabled" | |
| 352 | // 0in bits_on -var {~dcache_wclk_en_e,dcache_wvld_e} -max 1 -message "Attempt to write with wclk_en disabled" | |
| 353 | // 0in bits_on -var {~dcache_rclk_en_m,dcache_rvld_m} -max 1 -message "Attempt to read with rclk_en disabled" | |
| 354 | // 0in bits_on -var {~dcache_bypass_e_,dcache_rvld_e} -max 1 -message "Read and bypass both active" | |
| 355 | ||
| 356 | wire pce_ov = tcu_pce_ov; | |
| 357 | wire stop = 1'b0; | |
| 358 | wire siclk = tcu_aclk ; | |
| 359 | wire soclk = tcu_bclk; | |
| 360 | ||
| 361 | //================================================ | |
| 362 | // Clock headers | |
| 363 | //================================================ | |
| 364 | n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_in ( | |
| 365 | .l2clk (l2clk), | |
| 366 | .l1en (1'b1), | |
| 367 | .pce_ov (1'b1), | |
| 368 | .se (tcu_se_scancollar_in), | |
| 369 | .l1clk (l1clk_in), | |
| 370 | .stop(stop) | |
| 371 | ); | |
| 372 | ||
| 373 | n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_in_pm ( | |
| 374 | .l2clk (l2clk), | |
| 375 | .l1en (dcache_wclk_en_e), | |
| 376 | .se (tcu_se_scancollar_in), | |
| 377 | .l1clk (l1clk_in_pm), | |
| 378 | .pce_ov(pce_ov), | |
| 379 | .stop(stop) | |
| 380 | ); | |
| 381 | ||
| 382 | n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_out_pm ( | |
| 383 | .l2clk (l2clk), | |
| 384 | .l1en (dcache_rclk_en_m), | |
| 385 | .se (tcu_se_scancollar_out), | |
| 386 | .l1clk (l1clk_out_pm), | |
| 387 | .pce_ov(pce_ov), | |
| 388 | .stop(stop) | |
| 389 | ); | |
| 390 | ||
| 391 | n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_out ( | |
| 392 | .l2clk (l2clk), | |
| 393 | .l1en (1'b1), | |
| 394 | .pce_ov (1'b1), | |
| 395 | .se (tcu_se_scancollar_out), | |
| 396 | .l1clk (l1clk_out), | |
| 397 | .stop(stop) | |
| 398 | ); | |
| 399 | ||
| 400 | n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_free ( | |
| 401 | .l2clk (l2clk), | |
| 402 | .l1en (dcache_clk_en_e), | |
| 403 | .se (tcu_scan_en), | |
| 404 | .l1clk (l1clk_free), | |
| 405 | .pce_ov(pce_ov), | |
| 406 | .stop(stop) | |
| 407 | ); | |
| 408 | ||
| 409 | n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_free_wpm ( | |
| 410 | .l2clk (l2clk), | |
| 411 | .l1en (dcache_wclk_en_e), | |
| 412 | .se (tcu_scan_en), | |
| 413 | .l1clk (l1clk_free_wpm), | |
| 414 | .pce_ov(pce_ov), | |
| 415 | .stop(stop) | |
| 416 | ); | |
| 417 | ||
| 418 | n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_red ( | |
| 419 | .l2clk (l2clk), | |
| 420 | .l1en (1'b1), | |
| 421 | .pce_ov (1'b1), | |
| 422 | .se (1'b0), | |
| 423 | .l1clk (l1clk_red), | |
| 424 | .stop(stop) | |
| 425 | ); | |
| 426 | ||
| 427 | //========================================================================================= | |
| 428 | // Input flops | |
| 429 | //========================================================================================= | |
| 430 | ||
| 431 | // BIST Rd used fill address port. | |
| 432 | n2_dca_sp_9kb_cust_mux_macro__mux_aope__ports_2__width_8 mx_addr_e ( | |
| 433 | .din0 (dcache_alt_addr_e[10:3]), | |
| 434 | .din1 (dcache_rd_addr_e[10:3]), | |
| 435 | .sel0 (dcache_alt_addr_sel_e), | |
| 436 | .dout (dcache_rwaddr_e[10:3]) | |
| 437 | ); | |
| 438 | ||
| 439 | n2_dca_sp_9kb_cust_tisram_msff_macro__fs_1__width_8 lat_addr ( | |
| 440 | .scan_in(lat_addr_scanin[7:0]), | |
| 441 | .scan_out(lat_addr_scanout[7:0]), | |
| 442 | .l1clk (l1clk_in), | |
| 443 | .d (dcache_rwaddr_e[10:3]), | |
| 444 | .latout (dcache_rwaddr_eb[10:3]), | |
| 445 | .latout_l (dcache_rwaddr_l_unused[10:3]), | |
| 446 | .siclk(siclk), | |
| 447 | .soclk(soclk) | |
| 448 | ); | |
| 449 | ||
| 450 | // This is just a 2:4 decoder | |
| 451 | n2_dca_sp_9kb_cust_mux_macro__mux_aodec__ports_4__width_4 wr_way_decode ( | |
| 452 | .din0 (4'b0001), | |
| 453 | .din1 (4'b0010), | |
| 454 | .din2 (4'b0100), | |
| 455 | .din3 (4'b1000), | |
| 456 | .sel (dcache_wr_way_e[1:0]), | |
| 457 | .dout (wr_way_dec_e[3:0]) | |
| 458 | ); | |
| 459 | ||
| 460 | n2_dca_sp_9kb_cust_tisram_msff_macro__fs_1__width_7 lat_ctl_eb ( | |
| 461 | .scan_in(lat_ctl_eb_scanin[6:0]), | |
| 462 | .scan_out(lat_ctl_eb_scanout[6:0]), | |
| 463 | .l1clk (l1clk_in), | |
| 464 | .d ({dcache_rvld_e, dcache_rvld_e, dcache_wvld_e, wr_way_dec_e[3:0]}), | |
| 465 | .latout ({dcache_rvld_top_eb,dcache_rvld_bot_eb,dcache_wvld_eb,wr_way_dec_eb[3:0]}), | |
| 466 | .latout_l (lat_ctl_unused[6:0]), | |
| 467 | .siclk(siclk), | |
| 468 | .soclk(soclk) | |
| 469 | ); | |
| 470 | ||
| 471 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_3 dff_ctl_m_0 ( | |
| 472 | .scan_in(dff_ctl_m_0_scanin[2:0]), | |
| 473 | .scan_out(dff_ctl_m_0_scanout[2:0]), | |
| 474 | .l1clk (l1clk_in), | |
| 475 | .din ({dcache_rvld_e,dcache_wvld_e,dcache_bypass_e_}), | |
| 476 | .dout ({dcache_rvld_m,dcache_wvld_m,dcache_bypass_m_}), | |
| 477 | .siclk(siclk), | |
| 478 | .soclk(soclk) | |
| 479 | ); | |
| 480 | ||
| 481 | n2_dca_sp_9kb_cust_tisram_msff_macro__fs_1__width_16 dff_ctl_m_1 ( | |
| 482 | .scan_in(dff_ctl_m_1_scanin[15:0]), | |
| 483 | .scan_out(dff_ctl_m_1_scanout[15:0]), | |
| 484 | .l1clk (l1clk_in_pm), | |
| 485 | .d (dcache_byte_wr_en_e[15:0]), | |
| 486 | .latout (byte_wr_en_eb[15:0]), | |
| 487 | .latout_l (dff_ctl_l_unused[15:0]), | |
| 488 | .siclk(siclk), | |
| 489 | .soclk(soclk) | |
| 490 | ); | |
| 491 | ||
| 492 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_5 dff_ctl_b ( | |
| 493 | .scan_in(dff_ctl_b_scanin[4:0]), | |
| 494 | .scan_out(dff_ctl_b_scanout[4:0]), | |
| 495 | .l1clk (l1clk_in), | |
| 496 | .din ({dcache_alt_way_sel_m,dcache_alt_rsel_way_m[3:0]}), | |
| 497 | .dout ({dcache_alt_way_sel_b,dcache_alt_rsel_way_b[3:0]}), | |
| 498 | .siclk(siclk), | |
| 499 | .soclk(soclk) | |
| 500 | ); | |
| 501 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_144 dff_wdata_m ( | |
| 502 | .scan_in(dff_wdata_m_scanin[143:0]), | |
| 503 | .scan_out(dff_wdata_m_scanout[143:0]), | |
| 504 | .l1clk (l1clk_in_pm), | |
| 505 | .din (dcache_wdata_e[143:0]), | |
| 506 | .dout ({dcache_wparity_m[15],dcache_wdata_m[127:120], | |
| 507 | dcache_wparity_m[14],dcache_wdata_m[119:112], | |
| 508 | dcache_wparity_m[13],dcache_wdata_m[111:104], | |
| 509 | dcache_wparity_m[12],dcache_wdata_m[103:96], | |
| 510 | dcache_wparity_m[11],dcache_wdata_m[95:88], | |
| 511 | dcache_wparity_m[10],dcache_wdata_m[87:80], | |
| 512 | dcache_wparity_m[9],dcache_wdata_m[79:72], | |
| 513 | dcache_wparity_m[8],dcache_wdata_m[71:64], | |
| 514 | dcache_wparity_m[7],dcache_wdata_m[63:56], | |
| 515 | dcache_wparity_m[6],dcache_wdata_m[55:48], | |
| 516 | dcache_wparity_m[5],dcache_wdata_m[47:40], | |
| 517 | dcache_wparity_m[4],dcache_wdata_m[39:32], | |
| 518 | dcache_wparity_m[3],dcache_wdata_m[31:24], | |
| 519 | dcache_wparity_m[2],dcache_wdata_m[23:16], | |
| 520 | dcache_wparity_m[1],dcache_wdata_m[15:8], | |
| 521 | dcache_wparity_m[0],dcache_wdata_m[7:0] }), | |
| 522 | .siclk(siclk), | |
| 523 | .soclk(soclk) | |
| 524 | ); | |
| 525 | ||
| 526 | ||
| 527 | ||
| 528 | ||
| 529 | ||
| 530 | ||
| 531 | ||
| 532 | ||
| 533 | ||
| 534 | ||
| 535 | ||
| 536 | n2_dca_sp_9kb_array array ( | |
| 537 | .l1clk (l1clk_free), | |
| 538 | .l1clk_wr (l1clk_free_wpm), | |
| 539 | .addr_b (dcache_rwaddr_eb[10:3]), | |
| 540 | .rd_en_top_b (dcache_rvld_top_eb), | |
| 541 | .rd_en_bot_b (dcache_rvld_bot_eb), | |
| 542 | .rd_en_a (dcache_rvld_m), | |
| 543 | .wr_en_b (dcache_wvld_eb), | |
| 544 | .wr_en_a (dcache_wvld_m), | |
| 545 | .wr_inh_b (tcu_array_wr_inhibit), | |
| 546 | .byte_wr_en_b (byte_wr_en_eb[15:0]), | |
| 547 | .wr_waysel_b (wr_way_dec_eb[3:0]), | |
| 548 | .fuse_dca_repair_value (fuse_dca_repair_value_ff[5:0]), | |
| 549 | .fuse_dca_repair_en (fuse_dca_repair_en_ff[1:0]), | |
| 550 | .fuse_dca_rid (fuse_dca_rid_ff[1:0]), | |
| 551 | .fuse_dca_wen (fuse_dca_wen_ff), | |
| 552 | .fuse_red_reset (fuse_red_reset_ff), | |
| 553 | .dca_fuse_repair_value (dca_fuse_repair_value_pre[5:0]), | |
| 554 | .dca_fuse_repair_en (dca_fuse_repair_en_pre[1:0]), | |
| 555 | .l1clk_red(l1clk_red), | |
| 556 | .dcache_wdata_m(dcache_wdata_m[127:0]), | |
| 557 | .dcache_wparity_m(dcache_wparity_m[15:0]), | |
| 558 | .dcache_rdata_w0_m(dcache_rdata_w0_m[63:0]), | |
| 559 | .rparity_w0_m(rparity_w0_m[7:0]), | |
| 560 | .dcache_rdata_w1_m(dcache_rdata_w1_m[63:0]), | |
| 561 | .rparity_w1_m(rparity_w1_m[7:0]), | |
| 562 | .dcache_rdata_w2_m(dcache_rdata_w2_m[63:0]), | |
| 563 | .rparity_w2_m(rparity_w2_m[7:0]), | |
| 564 | .dcache_rdata_w3_m(dcache_rdata_w3_m[63:0]), | |
| 565 | .rparity_w3_m(rparity_w3_m[7:0]), | |
| 566 | .vnw_ary(vnw_ary) | |
| 567 | ); | |
| 568 | ||
| 569 | ||
| 570 | ||
| 571 | // mux fill/bypass data into way0 here so that it's not in the critical B stage path | |
| 572 | n2_dca_sp_9kb_cust_mux_macro__mux_aope__ports_2__width_64 mx_way0_data ( | |
| 573 | .din0 (dcache_rdata_w0_m[63:0]), | |
| 574 | .din1 (lsu_l2fill_or_byp_data_m[63:0]), | |
| 575 | .sel0 (dcache_bypass_m_), | |
| 576 | .dout (rdata_w0_m[63:0]) | |
| 577 | ); | |
| 578 | assign rdata_w1_m[63:0] = dcache_rdata_w1_m[63:0]; | |
| 579 | assign rdata_w2_m[63:0] = dcache_rdata_w2_m[63:0]; | |
| 580 | assign rdata_w3_m[63:0] = dcache_rdata_w3_m[63:0]; | |
| 581 | ||
| 582 | //========================================================================================= | |
| 583 | // Output flops | |
| 584 | //========================================================================================= | |
| 585 | ||
| 586 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_msb_w0 ( | |
| 587 | .scan_in(dff_msb_w0_scanin[7:0]), | |
| 588 | .scan_out(dff_msb_w0_scanout[7:0]), | |
| 589 | .l1clk (l1clk_out_pm), | |
| 590 | .din ({dcache_rdata_w0_m[63],dcache_rdata_w0_m[55],dcache_rdata_w0_m[47],dcache_rdata_w0_m[39], | |
| 591 | dcache_rdata_w0_m[31],dcache_rdata_w0_m[23],dcache_rdata_w0_m[15],dcache_rdata_w0_m[7]}), | |
| 592 | .dout (dcache_rdata_msb_w0_b[7:0]), | |
| 593 | .siclk(siclk), | |
| 594 | .soclk(soclk) | |
| 595 | ); | |
| 596 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_msb_w1 ( | |
| 597 | .scan_in(dff_msb_w1_scanin[7:0]), | |
| 598 | .scan_out(dff_msb_w1_scanout[7:0]), | |
| 599 | .l1clk (l1clk_out_pm), | |
| 600 | .din ({dcache_rdata_w1_m[63],dcache_rdata_w1_m[55],dcache_rdata_w1_m[47],dcache_rdata_w1_m[39], | |
| 601 | dcache_rdata_w1_m[31],dcache_rdata_w1_m[23],dcache_rdata_w1_m[15],dcache_rdata_w1_m[7]}), | |
| 602 | .dout (dcache_rdata_msb_w1_b[7:0]), | |
| 603 | .siclk(siclk), | |
| 604 | .soclk(soclk) | |
| 605 | ); | |
| 606 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_msb_w2 ( | |
| 607 | .scan_in(dff_msb_w2_scanin[7:0]), | |
| 608 | .scan_out(dff_msb_w2_scanout[7:0]), | |
| 609 | .l1clk (l1clk_out_pm), | |
| 610 | .din ({dcache_rdata_w2_m[63],dcache_rdata_w2_m[55],dcache_rdata_w2_m[47],dcache_rdata_w2_m[39], | |
| 611 | dcache_rdata_w2_m[31],dcache_rdata_w2_m[23],dcache_rdata_w2_m[15],dcache_rdata_w2_m[7]}), | |
| 612 | .dout (dcache_rdata_msb_w2_b[7:0]), | |
| 613 | .siclk(siclk), | |
| 614 | .soclk(soclk) | |
| 615 | ); | |
| 616 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_msb_w3 ( | |
| 617 | .scan_in(dff_msb_w3_scanin[7:0]), | |
| 618 | .scan_out(dff_msb_w3_scanout[7:0]), | |
| 619 | .l1clk (l1clk_out_pm), | |
| 620 | .din ({dcache_rdata_w3_m[63],dcache_rdata_w3_m[55],dcache_rdata_w3_m[47],dcache_rdata_w3_m[39], | |
| 621 | dcache_rdata_w3_m[31],dcache_rdata_w3_m[23],dcache_rdata_w3_m[15],dcache_rdata_w3_m[7]}), | |
| 622 | .dout (dcache_rdata_msb_w3_b[7:0]), | |
| 623 | .siclk(siclk), | |
| 624 | .soclk(soclk) | |
| 625 | ); | |
| 626 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_64 dff_rdata_w0_m ( | |
| 627 | .scan_in(dff_rdata_w0_m_scanin[63:0]), | |
| 628 | .scan_out(dff_rdata_w0_m_scanout[63:0]), | |
| 629 | .l1clk (l1clk_out_pm), | |
| 630 | .din (rdata_w0_m[63:0]), | |
| 631 | .dout (rdata_w0_b[63:0]), | |
| 632 | .siclk(siclk), | |
| 633 | .soclk(soclk) | |
| 634 | ); | |
| 635 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_rparity_w0_m ( | |
| 636 | .scan_in(dff_rparity_w0_m_scanin[7:0]), | |
| 637 | .scan_out(dff_rparity_w0_m_scanout[7:0]), | |
| 638 | .l1clk (l1clk_out_pm), | |
| 639 | .din (rparity_w0_m[7:0]), | |
| 640 | .dout (rparity_w0_b[7:0]), | |
| 641 | .siclk(siclk), | |
| 642 | .soclk(soclk) | |
| 643 | ); | |
| 644 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_64 dff_rdata_w1_m ( | |
| 645 | .scan_in(dff_rdata_w1_m_scanin[63:0]), | |
| 646 | .scan_out(dff_rdata_w1_m_scanout[63:0]), | |
| 647 | .l1clk (l1clk_out_pm), | |
| 648 | .din (rdata_w1_m[63:0]), | |
| 649 | .dout (rdata_w1_b[63:0]), | |
| 650 | .siclk(siclk), | |
| 651 | .soclk(soclk) | |
| 652 | ); | |
| 653 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_rparity_w1_m ( | |
| 654 | .scan_in(dff_rparity_w1_m_scanin[7:0]), | |
| 655 | .scan_out(dff_rparity_w1_m_scanout[7:0]), | |
| 656 | .l1clk (l1clk_out_pm), | |
| 657 | .din (rparity_w1_m[7:0]), | |
| 658 | .dout (rparity_w1_b[7:0]), | |
| 659 | .siclk(siclk), | |
| 660 | .soclk(soclk) | |
| 661 | ); | |
| 662 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_64 dff_rdata_w2_m ( | |
| 663 | .scan_in(dff_rdata_w2_m_scanin[63:0]), | |
| 664 | .scan_out(dff_rdata_w2_m_scanout[63:0]), | |
| 665 | .l1clk (l1clk_out_pm), | |
| 666 | .din (rdata_w2_m[63:0]), | |
| 667 | .dout (rdata_w2_b[63:0]), | |
| 668 | .siclk(siclk), | |
| 669 | .soclk(soclk) | |
| 670 | ); | |
| 671 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_rparity_w2_m ( | |
| 672 | .scan_in(dff_rparity_w2_m_scanin[7:0]), | |
| 673 | .scan_out(dff_rparity_w2_m_scanout[7:0]), | |
| 674 | .l1clk (l1clk_out_pm), | |
| 675 | .din (rparity_w2_m[7:0]), | |
| 676 | .dout (rparity_w2_b[7:0]), | |
| 677 | .siclk(siclk), | |
| 678 | .soclk(soclk) | |
| 679 | ); | |
| 680 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_64 dff_rdata_w3_m ( | |
| 681 | .scan_in(dff_rdata_w3_m_scanin[63:0]), | |
| 682 | .scan_out(dff_rdata_w3_m_scanout[63:0]), | |
| 683 | .l1clk (l1clk_out_pm), | |
| 684 | .din (rdata_w3_m[63:0]), | |
| 685 | .dout (rdata_w3_b[63:0]), | |
| 686 | .siclk(siclk), | |
| 687 | .soclk(soclk) | |
| 688 | ); | |
| 689 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_rparity_w3_m ( | |
| 690 | .scan_in(dff_rparity_w3_m_scanin[7:0]), | |
| 691 | .scan_out(dff_rparity_w3_m_scanout[7:0]), | |
| 692 | .l1clk (l1clk_out_pm), | |
| 693 | .din (rparity_w3_m[7:0]), | |
| 694 | .dout (rparity_w3_b[7:0]), | |
| 695 | .siclk(siclk), | |
| 696 | .soclk(soclk) | |
| 697 | ); | |
| 698 | ||
| 699 | //========================================================================================= | |
| 700 | // Way select | |
| 701 | //========================================================================================= | |
| 702 | ||
| 703 | n2_dca_sp_9kb_cust_mux_macro__mux_aope__ports_2__width_4 mx_sel_way ( | |
| 704 | .din0 (dcache_alt_rsel_way_b[3:0]), | |
| 705 | .din1 (dcache_rsel_way_b[3:0]), | |
| 706 | .sel0 (dcache_alt_way_sel_b), | |
| 707 | .dout (dcache_rd_sel_way_b[3:0]) | |
| 708 | ); | |
| 709 | ||
| 710 | n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_4__width_64 mx_rdata_b ( | |
| 711 | .din0 (rdata_w0_b[63:0]), | |
| 712 | .din1 (rdata_w1_b[63:0]), | |
| 713 | .din2 (rdata_w2_b[63:0]), | |
| 714 | .din3 (rdata_w3_b[63:0]), | |
| 715 | .sel0 (dcache_rd_sel_way_b[0]), | |
| 716 | .sel1 (dcache_rd_sel_way_b[1]), | |
| 717 | .sel2 (dcache_rd_sel_way_b[2]), | |
| 718 | .sel3 (dcache_rd_sel_way_b[3]), | |
| 719 | .dout (dcache_rdata_b[63:0]) | |
| 720 | ); | |
| 721 | ||
| 722 | n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_4__width_8 mx_rparity_b ( | |
| 723 | .din0 (rparity_w0_b[7:0]), | |
| 724 | .din1 (rparity_w1_b[7:0]), | |
| 725 | .din2 (rparity_w2_b[7:0]), | |
| 726 | .din3 (rparity_w3_b[7:0]), | |
| 727 | .sel0 (dcache_rd_sel_way_b[0]), | |
| 728 | .sel1 (dcache_rd_sel_way_b[1]), | |
| 729 | .sel2 (dcache_rd_sel_way_b[2]), | |
| 730 | .sel3 (dcache_rd_sel_way_b[3]), | |
| 731 | .dout (dcache_rparity_b[7:0]) | |
| 732 | ); | |
| 733 | ||
| 734 | //========================================================================================= | |
| 735 | // Parity check. Parity for each byte is calculated in M. The result of all bytes is | |
| 736 | // flopped and OR'ed in B. | |
| 737 | //========================================================================================= | |
| 738 | ||
| 739 | // ***** Way 0 ***** | |
| 740 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par0 ( | |
| 741 | .din0({dcache_rdata_w0_m[0],dcache_rdata_w0_m[3],dcache_rdata_w0_m[6], w0_p0_0}), | |
| 742 | .din1({dcache_rdata_w0_m[1],dcache_rdata_w0_m[4],dcache_rdata_w0_m[7], w0_p0_1}), | |
| 743 | .din2({dcache_rdata_w0_m[2],dcache_rdata_w0_m[5],rparity_w0_m[0],w0_p0_2}), | |
| 744 | .dout({w0_p0_0,w0_p0_1,w0_p0_2,w0_parity_m[0]}) | |
| 745 | ); | |
| 746 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par1 ( | |
| 747 | .din0({dcache_rdata_w0_m[8],dcache_rdata_w0_m[11],dcache_rdata_w0_m[14], w0_p1_0}), | |
| 748 | .din1({dcache_rdata_w0_m[9],dcache_rdata_w0_m[12],dcache_rdata_w0_m[15], w0_p1_1}), | |
| 749 | .din2({dcache_rdata_w0_m[10],dcache_rdata_w0_m[13],rparity_w0_m[1],w0_p1_2}), | |
| 750 | .dout({w0_p1_0,w0_p1_1,w0_p1_2,w0_parity_m[1]}) | |
| 751 | ); | |
| 752 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par2 ( | |
| 753 | .din0({dcache_rdata_w0_m[16],dcache_rdata_w0_m[19],dcache_rdata_w0_m[22], w0_p2_0}), | |
| 754 | .din1({dcache_rdata_w0_m[17],dcache_rdata_w0_m[20],dcache_rdata_w0_m[23], w0_p2_1}), | |
| 755 | .din2({dcache_rdata_w0_m[18],dcache_rdata_w0_m[21],rparity_w0_m[2],w0_p2_2}), | |
| 756 | .dout({w0_p2_0,w0_p2_1,w0_p2_2,w0_parity_m[2]}) | |
| 757 | ); | |
| 758 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par3 ( | |
| 759 | .din0({dcache_rdata_w0_m[24],dcache_rdata_w0_m[27],dcache_rdata_w0_m[30], w0_p3_0}), | |
| 760 | .din1({dcache_rdata_w0_m[25],dcache_rdata_w0_m[28],dcache_rdata_w0_m[31], w0_p3_1}), | |
| 761 | .din2({dcache_rdata_w0_m[26],dcache_rdata_w0_m[29],rparity_w0_m[3],w0_p3_2}), | |
| 762 | .dout({w0_p3_0,w0_p3_1,w0_p3_2,w0_parity_m[3]}) | |
| 763 | ); | |
| 764 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par4 ( | |
| 765 | .din0({dcache_rdata_w0_m[32],dcache_rdata_w0_m[35],dcache_rdata_w0_m[38], w0_p4_0}), | |
| 766 | .din1({dcache_rdata_w0_m[33],dcache_rdata_w0_m[36],dcache_rdata_w0_m[39], w0_p4_1}), | |
| 767 | .din2({dcache_rdata_w0_m[34],dcache_rdata_w0_m[37],rparity_w0_m[4],w0_p4_2}), | |
| 768 | .dout({w0_p4_0,w0_p4_1,w0_p4_2,w0_parity_m[4]}) | |
| 769 | ); | |
| 770 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par5 ( | |
| 771 | .din0({dcache_rdata_w0_m[40],dcache_rdata_w0_m[43],dcache_rdata_w0_m[46], w0_p5_0}), | |
| 772 | .din1({dcache_rdata_w0_m[41],dcache_rdata_w0_m[44],dcache_rdata_w0_m[47], w0_p5_1}), | |
| 773 | .din2({dcache_rdata_w0_m[42],dcache_rdata_w0_m[45],rparity_w0_m[5],w0_p5_2}), | |
| 774 | .dout({w0_p5_0,w0_p5_1,w0_p5_2,w0_parity_m[5]}) | |
| 775 | ); | |
| 776 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par6 ( | |
| 777 | .din0({dcache_rdata_w0_m[48],dcache_rdata_w0_m[51],dcache_rdata_w0_m[54], w0_p6_0}), | |
| 778 | .din1({dcache_rdata_w0_m[49],dcache_rdata_w0_m[52],dcache_rdata_w0_m[55], w0_p6_1}), | |
| 779 | .din2({dcache_rdata_w0_m[50],dcache_rdata_w0_m[53],rparity_w0_m[6],w0_p6_2}), | |
| 780 | .dout({w0_p6_0,w0_p6_1,w0_p6_2,w0_parity_m[6]}) | |
| 781 | ); | |
| 782 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par7 ( | |
| 783 | .din0({dcache_rdata_w0_m[56],dcache_rdata_w0_m[59],dcache_rdata_w0_m[62], w0_p7_0}), | |
| 784 | .din1({dcache_rdata_w0_m[57],dcache_rdata_w0_m[60],dcache_rdata_w0_m[63], w0_p7_1}), | |
| 785 | .din2({dcache_rdata_w0_m[58],dcache_rdata_w0_m[61],rparity_w0_m[7],w0_p7_2}), | |
| 786 | .dout({w0_p7_0,w0_p7_1,w0_p7_2,w0_parity_m[7]}) | |
| 787 | ); | |
| 788 | ||
| 789 | // ***** Way 1 ***** | |
| 790 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par0 ( | |
| 791 | .din0({dcache_rdata_w1_m[0],dcache_rdata_w1_m[3],dcache_rdata_w1_m[6], w1_p0_0}), | |
| 792 | .din1({dcache_rdata_w1_m[1],dcache_rdata_w1_m[4],dcache_rdata_w1_m[7], w1_p0_1}), | |
| 793 | .din2({dcache_rdata_w1_m[2],dcache_rdata_w1_m[5],rparity_w1_m[0],w1_p0_2}), | |
| 794 | .dout({w1_p0_0,w1_p0_1,w1_p0_2,w1_parity_m[0]}) | |
| 795 | ); | |
| 796 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par1 ( | |
| 797 | .din0({dcache_rdata_w1_m[8],dcache_rdata_w1_m[11],dcache_rdata_w1_m[14], w1_p1_0}), | |
| 798 | .din1({dcache_rdata_w1_m[9],dcache_rdata_w1_m[12],dcache_rdata_w1_m[15], w1_p1_1}), | |
| 799 | .din2({dcache_rdata_w1_m[10],dcache_rdata_w1_m[13],rparity_w1_m[1],w1_p1_2}), | |
| 800 | .dout({w1_p1_0,w1_p1_1,w1_p1_2,w1_parity_m[1]}) | |
| 801 | ); | |
| 802 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par2 ( | |
| 803 | .din0({dcache_rdata_w1_m[16],dcache_rdata_w1_m[19],dcache_rdata_w1_m[22], w1_p2_0}), | |
| 804 | .din1({dcache_rdata_w1_m[17],dcache_rdata_w1_m[20],dcache_rdata_w1_m[23], w1_p2_1}), | |
| 805 | .din2({dcache_rdata_w1_m[18],dcache_rdata_w1_m[21],rparity_w1_m[2],w1_p2_2}), | |
| 806 | .dout({w1_p2_0,w1_p2_1,w1_p2_2,w1_parity_m[2]}) | |
| 807 | ); | |
| 808 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par3 ( | |
| 809 | .din0({dcache_rdata_w1_m[24],dcache_rdata_w1_m[27],dcache_rdata_w1_m[30], w1_p3_0}), | |
| 810 | .din1({dcache_rdata_w1_m[25],dcache_rdata_w1_m[28],dcache_rdata_w1_m[31], w1_p3_1}), | |
| 811 | .din2({dcache_rdata_w1_m[26],dcache_rdata_w1_m[29],rparity_w1_m[3],w1_p3_2}), | |
| 812 | .dout({w1_p3_0,w1_p3_1,w1_p3_2,w1_parity_m[3]}) | |
| 813 | ); | |
| 814 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par4 ( | |
| 815 | .din0({dcache_rdata_w1_m[32],dcache_rdata_w1_m[35],dcache_rdata_w1_m[38], w1_p4_0}), | |
| 816 | .din1({dcache_rdata_w1_m[33],dcache_rdata_w1_m[36],dcache_rdata_w1_m[39], w1_p4_1}), | |
| 817 | .din2({dcache_rdata_w1_m[34],dcache_rdata_w1_m[37],rparity_w1_m[4],w1_p4_2}), | |
| 818 | .dout({w1_p4_0,w1_p4_1,w1_p4_2,w1_parity_m[4]}) | |
| 819 | ); | |
| 820 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par5 ( | |
| 821 | .din0({dcache_rdata_w1_m[40],dcache_rdata_w1_m[43],dcache_rdata_w1_m[46], w1_p5_0}), | |
| 822 | .din1({dcache_rdata_w1_m[41],dcache_rdata_w1_m[44],dcache_rdata_w1_m[47], w1_p5_1}), | |
| 823 | .din2({dcache_rdata_w1_m[42],dcache_rdata_w1_m[45],rparity_w1_m[5],w1_p5_2}), | |
| 824 | .dout({w1_p5_0,w1_p5_1,w1_p5_2,w1_parity_m[5]}) | |
| 825 | ); | |
| 826 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par6 ( | |
| 827 | .din0({dcache_rdata_w1_m[48],dcache_rdata_w1_m[51],dcache_rdata_w1_m[54], w1_p6_0}), | |
| 828 | .din1({dcache_rdata_w1_m[49],dcache_rdata_w1_m[52],dcache_rdata_w1_m[55], w1_p6_1}), | |
| 829 | .din2({dcache_rdata_w1_m[50],dcache_rdata_w1_m[53],rparity_w1_m[6],w1_p6_2}), | |
| 830 | .dout({w1_p6_0,w1_p6_1,w1_p6_2,w1_parity_m[6]}) | |
| 831 | ); | |
| 832 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par7 ( | |
| 833 | .din0({dcache_rdata_w1_m[56],dcache_rdata_w1_m[59],dcache_rdata_w1_m[62], w1_p7_0}), | |
| 834 | .din1({dcache_rdata_w1_m[57],dcache_rdata_w1_m[60],dcache_rdata_w1_m[63], w1_p7_1}), | |
| 835 | .din2({dcache_rdata_w1_m[58],dcache_rdata_w1_m[61],rparity_w1_m[7],w1_p7_2}), | |
| 836 | .dout({w1_p7_0,w1_p7_1,w1_p7_2,w1_parity_m[7]}) | |
| 837 | ); | |
| 838 | ||
| 839 | // ***** Way 2 ***** | |
| 840 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par0 ( | |
| 841 | .din0({dcache_rdata_w2_m[0],dcache_rdata_w2_m[3],dcache_rdata_w2_m[6], w2_p0_0}), | |
| 842 | .din1({dcache_rdata_w2_m[1],dcache_rdata_w2_m[4],dcache_rdata_w2_m[7], w2_p0_1}), | |
| 843 | .din2({dcache_rdata_w2_m[2],dcache_rdata_w2_m[5],rparity_w2_m[0],w2_p0_2}), | |
| 844 | .dout({w2_p0_0,w2_p0_1,w2_p0_2,w2_parity_m[0]}) | |
| 845 | ); | |
| 846 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par1 ( | |
| 847 | .din0({dcache_rdata_w2_m[8],dcache_rdata_w2_m[11],dcache_rdata_w2_m[14], w2_p1_0}), | |
| 848 | .din1({dcache_rdata_w2_m[9],dcache_rdata_w2_m[12],dcache_rdata_w2_m[15], w2_p1_1}), | |
| 849 | .din2({dcache_rdata_w2_m[10],dcache_rdata_w2_m[13],rparity_w2_m[1],w2_p1_2}), | |
| 850 | .dout({w2_p1_0,w2_p1_1,w2_p1_2,w2_parity_m[1]}) | |
| 851 | ); | |
| 852 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par2 ( | |
| 853 | .din0({dcache_rdata_w2_m[16],dcache_rdata_w2_m[19],dcache_rdata_w2_m[22], w2_p2_0}), | |
| 854 | .din1({dcache_rdata_w2_m[17],dcache_rdata_w2_m[20],dcache_rdata_w2_m[23], w2_p2_1}), | |
| 855 | .din2({dcache_rdata_w2_m[18],dcache_rdata_w2_m[21],rparity_w2_m[2],w2_p2_2}), | |
| 856 | .dout({w2_p2_0,w2_p2_1,w2_p2_2,w2_parity_m[2]}) | |
| 857 | ); | |
| 858 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par3 ( | |
| 859 | .din0({dcache_rdata_w2_m[24],dcache_rdata_w2_m[27],dcache_rdata_w2_m[30], w2_p3_0}), | |
| 860 | .din1({dcache_rdata_w2_m[25],dcache_rdata_w2_m[28],dcache_rdata_w2_m[31], w2_p3_1}), | |
| 861 | .din2({dcache_rdata_w2_m[26],dcache_rdata_w2_m[29],rparity_w2_m[3],w2_p3_2}), | |
| 862 | .dout({w2_p3_0,w2_p3_1,w2_p3_2,w2_parity_m[3]}) | |
| 863 | ); | |
| 864 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par4 ( | |
| 865 | .din0({dcache_rdata_w2_m[32],dcache_rdata_w2_m[35],dcache_rdata_w2_m[38], w2_p4_0}), | |
| 866 | .din1({dcache_rdata_w2_m[33],dcache_rdata_w2_m[36],dcache_rdata_w2_m[39], w2_p4_1}), | |
| 867 | .din2({dcache_rdata_w2_m[34],dcache_rdata_w2_m[37],rparity_w2_m[4],w2_p4_2}), | |
| 868 | .dout({w2_p4_0,w2_p4_1,w2_p4_2,w2_parity_m[4]}) | |
| 869 | ); | |
| 870 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par5 ( | |
| 871 | .din0({dcache_rdata_w2_m[40],dcache_rdata_w2_m[43],dcache_rdata_w2_m[46], w2_p5_0}), | |
| 872 | .din1({dcache_rdata_w2_m[41],dcache_rdata_w2_m[44],dcache_rdata_w2_m[47], w2_p5_1}), | |
| 873 | .din2({dcache_rdata_w2_m[42],dcache_rdata_w2_m[45],rparity_w2_m[5],w2_p5_2}), | |
| 874 | .dout({w2_p5_0,w2_p5_1,w2_p5_2,w2_parity_m[5]}) | |
| 875 | ); | |
| 876 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par6 ( | |
| 877 | .din0({dcache_rdata_w2_m[48],dcache_rdata_w2_m[51],dcache_rdata_w2_m[54], w2_p6_0}), | |
| 878 | .din1({dcache_rdata_w2_m[49],dcache_rdata_w2_m[52],dcache_rdata_w2_m[55], w2_p6_1}), | |
| 879 | .din2({dcache_rdata_w2_m[50],dcache_rdata_w2_m[53],rparity_w2_m[6],w2_p6_2}), | |
| 880 | .dout({w2_p6_0,w2_p6_1,w2_p6_2,w2_parity_m[6]}) | |
| 881 | ); | |
| 882 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par7 ( | |
| 883 | .din0({dcache_rdata_w2_m[56],dcache_rdata_w2_m[59],dcache_rdata_w2_m[62], w2_p7_0}), | |
| 884 | .din1({dcache_rdata_w2_m[57],dcache_rdata_w2_m[60],dcache_rdata_w2_m[63], w2_p7_1}), | |
| 885 | .din2({dcache_rdata_w2_m[58],dcache_rdata_w2_m[61],rparity_w2_m[7],w2_p7_2}), | |
| 886 | .dout({w2_p7_0,w2_p7_1,w2_p7_2,w2_parity_m[7]}) | |
| 887 | ); | |
| 888 | ||
| 889 | // ***** Way 3 ***** | |
| 890 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par0 ( | |
| 891 | .din0({dcache_rdata_w3_m[0],dcache_rdata_w3_m[3],dcache_rdata_w3_m[6], w3_p0_0}), | |
| 892 | .din1({dcache_rdata_w3_m[1],dcache_rdata_w3_m[4],dcache_rdata_w3_m[7], w3_p0_1}), | |
| 893 | .din2({dcache_rdata_w3_m[2],dcache_rdata_w3_m[5],rparity_w3_m[0],w3_p0_2}), | |
| 894 | .dout({w3_p0_0,w3_p0_1,w3_p0_2,w3_parity_m[0]}) | |
| 895 | ); | |
| 896 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par1 ( | |
| 897 | .din0({dcache_rdata_w3_m[8],dcache_rdata_w3_m[11],dcache_rdata_w3_m[14], w3_p1_0}), | |
| 898 | .din1({dcache_rdata_w3_m[9],dcache_rdata_w3_m[12],dcache_rdata_w3_m[15], w3_p1_1}), | |
| 899 | .din2({dcache_rdata_w3_m[10],dcache_rdata_w3_m[13],rparity_w3_m[1],w3_p1_2}), | |
| 900 | .dout({w3_p1_0,w3_p1_1,w3_p1_2,w3_parity_m[1]}) | |
| 901 | ); | |
| 902 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par2 ( | |
| 903 | .din0({dcache_rdata_w3_m[16],dcache_rdata_w3_m[19],dcache_rdata_w3_m[22], w3_p2_0}), | |
| 904 | .din1({dcache_rdata_w3_m[17],dcache_rdata_w3_m[20],dcache_rdata_w3_m[23], w3_p2_1}), | |
| 905 | .din2({dcache_rdata_w3_m[18],dcache_rdata_w3_m[21],rparity_w3_m[2],w3_p2_2}), | |
| 906 | .dout({w3_p2_0,w3_p2_1,w3_p2_2,w3_parity_m[2]}) | |
| 907 | ); | |
| 908 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par3 ( | |
| 909 | .din0({dcache_rdata_w3_m[24],dcache_rdata_w3_m[27],dcache_rdata_w3_m[30], w3_p3_0}), | |
| 910 | .din1({dcache_rdata_w3_m[25],dcache_rdata_w3_m[28],dcache_rdata_w3_m[31], w3_p3_1}), | |
| 911 | .din2({dcache_rdata_w3_m[26],dcache_rdata_w3_m[29],rparity_w3_m[3],w3_p3_2}), | |
| 912 | .dout({w3_p3_0,w3_p3_1,w3_p3_2,w3_parity_m[3]}) | |
| 913 | ); | |
| 914 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par4 ( | |
| 915 | .din0({dcache_rdata_w3_m[32],dcache_rdata_w3_m[35],dcache_rdata_w3_m[38], w3_p4_0}), | |
| 916 | .din1({dcache_rdata_w3_m[33],dcache_rdata_w3_m[36],dcache_rdata_w3_m[39], w3_p4_1}), | |
| 917 | .din2({dcache_rdata_w3_m[34],dcache_rdata_w3_m[37],rparity_w3_m[4],w3_p4_2}), | |
| 918 | .dout({w3_p4_0,w3_p4_1,w3_p4_2,w3_parity_m[4]}) | |
| 919 | ); | |
| 920 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par5 ( | |
| 921 | .din0({dcache_rdata_w3_m[40],dcache_rdata_w3_m[43],dcache_rdata_w3_m[46], w3_p5_0}), | |
| 922 | .din1({dcache_rdata_w3_m[41],dcache_rdata_w3_m[44],dcache_rdata_w3_m[47], w3_p5_1}), | |
| 923 | .din2({dcache_rdata_w3_m[42],dcache_rdata_w3_m[45],rparity_w3_m[5],w3_p5_2}), | |
| 924 | .dout({w3_p5_0,w3_p5_1,w3_p5_2,w3_parity_m[5]}) | |
| 925 | ); | |
| 926 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par6 ( | |
| 927 | .din0({dcache_rdata_w3_m[48],dcache_rdata_w3_m[51],dcache_rdata_w3_m[54], w3_p6_0}), | |
| 928 | .din1({dcache_rdata_w3_m[49],dcache_rdata_w3_m[52],dcache_rdata_w3_m[55], w3_p6_1}), | |
| 929 | .din2({dcache_rdata_w3_m[50],dcache_rdata_w3_m[53],rparity_w3_m[6],w3_p6_2}), | |
| 930 | .dout({w3_p6_0,w3_p6_1,w3_p6_2,w3_parity_m[6]}) | |
| 931 | ); | |
| 932 | n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par7 ( | |
| 933 | .din0({dcache_rdata_w3_m[56],dcache_rdata_w3_m[59],dcache_rdata_w3_m[62], w3_p7_0}), | |
| 934 | .din1({dcache_rdata_w3_m[57],dcache_rdata_w3_m[60],dcache_rdata_w3_m[63], w3_p7_1}), | |
| 935 | .din2({dcache_rdata_w3_m[58],dcache_rdata_w3_m[61],rparity_w3_m[7],w3_p7_2}), | |
| 936 | .dout({w3_p7_0,w3_p7_1,w3_p7_2,w3_parity_m[7]}) | |
| 937 | ); | |
| 938 | ||
| 939 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_byte_perr_w0 ( | |
| 940 | .scan_in(dff_byte_perr_w0_scanin[7:0]), | |
| 941 | .scan_out(dff_byte_perr_w0_scanout[7:0]), | |
| 942 | .l1clk (l1clk_out_pm), | |
| 943 | .din (w0_parity_m[7:0]), | |
| 944 | .dout (w0_parity_b[7:0]), | |
| 945 | .siclk(siclk), | |
| 946 | .soclk(soclk) | |
| 947 | ); | |
| 948 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_byte_perr_w1 ( | |
| 949 | .scan_in(dff_byte_perr_w1_scanin[7:0]), | |
| 950 | .scan_out(dff_byte_perr_w1_scanout[7:0]), | |
| 951 | .l1clk (l1clk_out_pm), | |
| 952 | .din (w1_parity_m[7:0]), | |
| 953 | .dout (w1_parity_b[7:0]), | |
| 954 | .siclk(siclk), | |
| 955 | .soclk(soclk) | |
| 956 | ); | |
| 957 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_byte_perr_w2 ( | |
| 958 | .scan_in(dff_byte_perr_w2_scanin[7:0]), | |
| 959 | .scan_out(dff_byte_perr_w2_scanout[7:0]), | |
| 960 | .l1clk (l1clk_out_pm), | |
| 961 | .din (w2_parity_m[7:0]), | |
| 962 | .dout (w2_parity_b[7:0]), | |
| 963 | .siclk(siclk), | |
| 964 | .soclk(soclk) | |
| 965 | ); | |
| 966 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_byte_perr_w3 ( | |
| 967 | .scan_in(dff_byte_perr_w3_scanin[7:0]), | |
| 968 | .scan_out(dff_byte_perr_w3_scanout[7:0]), | |
| 969 | .l1clk (l1clk_out_pm), | |
| 970 | .din (w3_parity_m[7:0]), | |
| 971 | .dout (w3_parity_b[7:0]), | |
| 972 | .siclk(siclk), | |
| 973 | .soclk(soclk) | |
| 974 | ); | |
| 975 | ||
| 976 | // Funcionally this is just an OR gate. | |
| 977 | n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_8__width_1 parity_w0 ( | |
| 978 | .din0(1'b1), .din1(1'b1), .din2(1'b1), .din3(1'b1), .din4(1'b1), .din5(1'b1), .din6(1'b1), .din7(1'b1), | |
| 979 | .sel0(w0_parity_b[0]), .sel1(w0_parity_b[1]), .sel2(w0_parity_b[2]), .sel3(w0_parity_b[3]), | |
| 980 | .sel4(w0_parity_b[4]), .sel5(w0_parity_b[5]), .sel6(w0_parity_b[6]), .sel7(w0_parity_b[7]), | |
| 981 | .dout(w0_parity_err_b) | |
| 982 | ); | |
| 983 | // Funcionally this is just an OR gate. | |
| 984 | n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_8__width_1 parity_w1 ( | |
| 985 | .din0(1'b1), .din1(1'b1), .din2(1'b1), .din3(1'b1), .din4(1'b1), .din5(1'b1), .din6(1'b1), .din7(1'b1), | |
| 986 | .sel0(w1_parity_b[0]), .sel1(w1_parity_b[1]), .sel2(w1_parity_b[2]), .sel3(w1_parity_b[3]), | |
| 987 | .sel4(w1_parity_b[4]), .sel5(w1_parity_b[5]), .sel6(w1_parity_b[6]), .sel7(w1_parity_b[7]), | |
| 988 | .dout(w1_parity_err_b) | |
| 989 | ); | |
| 990 | // Funcionally this is just an OR gate. | |
| 991 | n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_8__width_1 parity_w2 ( | |
| 992 | .din0(1'b1), .din1(1'b1), .din2(1'b1), .din3(1'b1), .din4(1'b1), .din5(1'b1), .din6(1'b1), .din7(1'b1), | |
| 993 | .sel0(w2_parity_b[0]), .sel1(w2_parity_b[1]), .sel2(w2_parity_b[2]), .sel3(w2_parity_b[3]), | |
| 994 | .sel4(w2_parity_b[4]), .sel5(w2_parity_b[5]), .sel6(w2_parity_b[6]), .sel7(w2_parity_b[7]), | |
| 995 | .dout(w2_parity_err_b) | |
| 996 | ); | |
| 997 | // Funcionally this is just an OR gate. | |
| 998 | n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_8__width_1 parity_w3 ( | |
| 999 | .din0(1'b1), .din1(1'b1), .din2(1'b1), .din3(1'b1), .din4(1'b1), .din5(1'b1), .din6(1'b1), .din7(1'b1), | |
| 1000 | .sel0(w3_parity_b[0]), .sel1(w3_parity_b[1]), .sel2(w3_parity_b[2]), .sel3(w3_parity_b[3]), | |
| 1001 | .sel4(w3_parity_b[4]), .sel5(w3_parity_b[5]), .sel6(w3_parity_b[6]), .sel7(w3_parity_b[7]), | |
| 1002 | .dout(w3_parity_err_b) | |
| 1003 | ); | |
| 1004 | ||
| 1005 | assign dcache_perr_w0_b = w0_parity_err_b; | |
| 1006 | assign dcache_perr_w1_b = w1_parity_err_b; | |
| 1007 | assign dcache_perr_w2_b = w2_parity_err_b; | |
| 1008 | assign dcache_perr_w3_b = w3_parity_err_b; | |
| 1009 | ||
| 1010 | //========================================================================================= | |
| 1011 | // Redundancy flops | |
| 1012 | //========================================================================================= | |
| 1013 | ||
| 1014 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_12 dff_red_in ( | |
| 1015 | .scan_in(dff_red_in_scanin[11:0]), | |
| 1016 | .scan_out(dff_red_in_scanout[11:0]), | |
| 1017 | .l1clk (l1clk_in), | |
| 1018 | .din ({fuse_dca_repair_value[5:0], fuse_dca_repair_en[1:0], | |
| 1019 | fuse_dca_rid[1:0], fuse_dca_wen, fuse_red_reset}), | |
| 1020 | .dout ({fuse_dca_repair_value_ff[5:0],fuse_dca_repair_en_ff[1:0], | |
| 1021 | fuse_dca_rid_ff[1:0],fuse_dca_wen_ff,fuse_red_reset_ff}), | |
| 1022 | .siclk(siclk), | |
| 1023 | .soclk(soclk) | |
| 1024 | ); | |
| 1025 | ||
| 1026 | n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_red_out ( | |
| 1027 | .scan_in(dff_red_out_scanin[7:0]), | |
| 1028 | .scan_out(dff_red_out_scanout[7:0]), | |
| 1029 | .l1clk (l1clk_out), | |
| 1030 | .din ({dca_fuse_repair_value_pre[5:0],dca_fuse_repair_en_pre[1:0]}), | |
| 1031 | .dout ({dca_fuse_repair_value[5:0], dca_fuse_repair_en[1:0]}), | |
| 1032 | .siclk(siclk), | |
| 1033 | .soclk(soclk) | |
| 1034 | ); | |
| 1035 | ||
| 1036 | ||
| 1037 | supply0 vss; | |
| 1038 | supply1 vdd; | |
| 1039 | ||
| 1040 | // scanorder start | |
| 1041 | // dff_byte_perr_w0_scanin[7] | |
| 1042 | // dff_byte_perr_w1_scanin[7] | |
| 1043 | // dff_byte_perr_w1_scanin[6] | |
| 1044 | // dff_byte_perr_w0_scanin[6] | |
| 1045 | // dff_byte_perr_w0_scanin[5] | |
| 1046 | // dff_byte_perr_w1_scanin[5] | |
| 1047 | // dff_byte_perr_w1_scanin[4] | |
| 1048 | // dff_byte_perr_w0_scanin[4] | |
| 1049 | // dff_wdata_m_scanin[143] | |
| 1050 | // dff_wdata_m_scanin[71] | |
| 1051 | // dff_rparity_w3_m_scanin[7] | |
| 1052 | // dff_rparity_w2_m_scanin[7] | |
| 1053 | // dff_rparity_w1_m_scanin[7] | |
| 1054 | // dff_rparity_w0_m_scanin[7] | |
| 1055 | // dff_wdata_m_scanin[134] | |
| 1056 | // dff_wdata_m_scanin[62] | |
| 1057 | // dff_rparity_w3_m_scanin[6] | |
| 1058 | // dff_rparity_w2_m_scanin[6] | |
| 1059 | // dff_rparity_w1_m_scanin[6] | |
| 1060 | // dff_rparity_w0_m_scanin[6] | |
| 1061 | // dff_wdata_m_scanin[142] | |
| 1062 | // dff_wdata_m_scanin[70] | |
| 1063 | // dff_rdata_w3_m_scanin[63] | |
| 1064 | // dff_rdata_w2_m_scanin[63] | |
| 1065 | // dff_rdata_w1_m_scanin[63] | |
| 1066 | // dff_rdata_w0_m_scanin[63] | |
| 1067 | // dff_wdata_m_scanin[133] | |
| 1068 | // dff_wdata_m_scanin[61] | |
| 1069 | // dff_rdata_w3_m_scanin[55] | |
| 1070 | // dff_rdata_w2_m_scanin[55] | |
| 1071 | // dff_rdata_w1_m_scanin[55] | |
| 1072 | // dff_rdata_w0_m_scanin[55] | |
| 1073 | // dff_wdata_m_scanin[141] | |
| 1074 | // dff_wdata_m_scanin[69] | |
| 1075 | // dff_rdata_w3_m_scanin[62] | |
| 1076 | // dff_rdata_w2_m_scanin[62] | |
| 1077 | // dff_rdata_w1_m_scanin[62] | |
| 1078 | // dff_rdata_w0_m_scanin[62] | |
| 1079 | // dff_wdata_m_scanin[132] | |
| 1080 | // dff_wdata_m_scanin[60] | |
| 1081 | // dff_rdata_w3_m_scanin[54] | |
| 1082 | // dff_rdata_w2_m_scanin[54] | |
| 1083 | // dff_rdata_w1_m_scanin[54] | |
| 1084 | // dff_rdata_w0_m_scanin[54] | |
| 1085 | // dff_wdata_m_scanin[140] | |
| 1086 | // dff_wdata_m_scanin[68] | |
| 1087 | // dff_rdata_w3_m_scanin[61] | |
| 1088 | // dff_rdata_w2_m_scanin[61] | |
| 1089 | // dff_rdata_w1_m_scanin[61] | |
| 1090 | // dff_rdata_w0_m_scanin[61] | |
| 1091 | // dff_wdata_m_scanin[131] | |
| 1092 | // dff_wdata_m_scanin[59] | |
| 1093 | // dff_rdata_w3_m_scanin[53] | |
| 1094 | // dff_rdata_w2_m_scanin[53] | |
| 1095 | // dff_rdata_w1_m_scanin[53] | |
| 1096 | // dff_rdata_w0_m_scanin[53] | |
| 1097 | // dff_wdata_m_scanin[139] | |
| 1098 | // dff_wdata_m_scanin[67] | |
| 1099 | // dff_rdata_w3_m_scanin[60] | |
| 1100 | // dff_rdata_w2_m_scanin[60] | |
| 1101 | // dff_rdata_w1_m_scanin[60] | |
| 1102 | // dff_rdata_w0_m_scanin[60] | |
| 1103 | // dff_wdata_m_scanin[130] | |
| 1104 | // dff_wdata_m_scanin[58] | |
| 1105 | // dff_rdata_w3_m_scanin[52] | |
| 1106 | // dff_rdata_w2_m_scanin[52] | |
| 1107 | // dff_rdata_w1_m_scanin[52] | |
| 1108 | // dff_rdata_w0_m_scanin[52] | |
| 1109 | // dff_wdata_m_scanin[138] | |
| 1110 | // dff_wdata_m_scanin[66] | |
| 1111 | // dff_rdata_w3_m_scanin[59] | |
| 1112 | // dff_rdata_w2_m_scanin[59] | |
| 1113 | // dff_rdata_w1_m_scanin[59] | |
| 1114 | // dff_rdata_w0_m_scanin[59] | |
| 1115 | // dff_wdata_m_scanin[129] | |
| 1116 | // dff_wdata_m_scanin[57] | |
| 1117 | // dff_rdata_w3_m_scanin[51] | |
| 1118 | // dff_rdata_w2_m_scanin[51] | |
| 1119 | // dff_rdata_w1_m_scanin[51] | |
| 1120 | // dff_rdata_w0_m_scanin[51] | |
| 1121 | // dff_wdata_m_scanin[137] | |
| 1122 | // dff_wdata_m_scanin[65] | |
| 1123 | // dff_rdata_w3_m_scanin[58] | |
| 1124 | // dff_rdata_w2_m_scanin[58] | |
| 1125 | // dff_rdata_w1_m_scanin[58] | |
| 1126 | // dff_rdata_w0_m_scanin[58] | |
| 1127 | // dff_wdata_m_scanin[128] | |
| 1128 | // dff_wdata_m_scanin[56] | |
| 1129 | // dff_rdata_w3_m_scanin[50] | |
| 1130 | // dff_rdata_w2_m_scanin[50] | |
| 1131 | // dff_rdata_w1_m_scanin[50] | |
| 1132 | // dff_rdata_w0_m_scanin[50] | |
| 1133 | // dff_wdata_m_scanin[136] | |
| 1134 | // dff_wdata_m_scanin[64] | |
| 1135 | // dff_rdata_w3_m_scanin[57] | |
| 1136 | // dff_rdata_w2_m_scanin[57] | |
| 1137 | // dff_rdata_w1_m_scanin[57] | |
| 1138 | // dff_rdata_w0_m_scanin[57] | |
| 1139 | // dff_wdata_m_scanin[127] | |
| 1140 | // dff_wdata_m_scanin[55] | |
| 1141 | // dff_rdata_w3_m_scanin[49] | |
| 1142 | // dff_rdata_w2_m_scanin[49] | |
| 1143 | // dff_rdata_w1_m_scanin[49] | |
| 1144 | // dff_rdata_w0_m_scanin[49] | |
| 1145 | // dff_wdata_m_scanin[135] | |
| 1146 | // dff_wdata_m_scanin[63] | |
| 1147 | // dff_rdata_w3_m_scanin[56] | |
| 1148 | // dff_rdata_w2_m_scanin[56] | |
| 1149 | // dff_rdata_w1_m_scanin[56] | |
| 1150 | // dff_rdata_w0_m_scanin[56] | |
| 1151 | // dff_wdata_m_scanin[126] | |
| 1152 | // dff_wdata_m_scanin[54] | |
| 1153 | // dff_rdata_w3_m_scanin[48] | |
| 1154 | // dff_rdata_w2_m_scanin[48] | |
| 1155 | // dff_rdata_w1_m_scanin[48] | |
| 1156 | // dff_rdata_w0_m_scanin[48] | |
| 1157 | // dff_wdata_m_scanin[125] | |
| 1158 | // dff_wdata_m_scanin[53] | |
| 1159 | // dff_rparity_w3_m_scanin[5] | |
| 1160 | // dff_rparity_w2_m_scanin[5] | |
| 1161 | // dff_rparity_w1_m_scanin[5] | |
| 1162 | // dff_rparity_w0_m_scanin[5] | |
| 1163 | // dff_wdata_m_scanin[116] | |
| 1164 | // dff_wdata_m_scanin[44] | |
| 1165 | // dff_rparity_w3_m_scanin[4] | |
| 1166 | // dff_rparity_w2_m_scanin[4] | |
| 1167 | // dff_rparity_w1_m_scanin[4] | |
| 1168 | // dff_rparity_w0_m_scanin[4] | |
| 1169 | // dff_wdata_m_scanin[124] | |
| 1170 | // dff_wdata_m_scanin[52] | |
| 1171 | // dff_rdata_w3_m_scanin[47] | |
| 1172 | // dff_rdata_w2_m_scanin[47] | |
| 1173 | // dff_rdata_w1_m_scanin[47] | |
| 1174 | // dff_rdata_w0_m_scanin[47] | |
| 1175 | // dff_wdata_m_scanin[115] | |
| 1176 | // dff_wdata_m_scanin[43] | |
| 1177 | // dff_rdata_w3_m_scanin[39] | |
| 1178 | // dff_rdata_w2_m_scanin[39] | |
| 1179 | // dff_rdata_w1_m_scanin[39] | |
| 1180 | // dff_rdata_w0_m_scanin[39] | |
| 1181 | // dff_wdata_m_scanin[123] | |
| 1182 | // dff_wdata_m_scanin[51] | |
| 1183 | // dff_rdata_w3_m_scanin[46] | |
| 1184 | // dff_rdata_w2_m_scanin[46] | |
| 1185 | // dff_rdata_w1_m_scanin[46] | |
| 1186 | // dff_rdata_w0_m_scanin[46] | |
| 1187 | // dff_wdata_m_scanin[114] | |
| 1188 | // dff_wdata_m_scanin[42] | |
| 1189 | // dff_rdata_w3_m_scanin[38] | |
| 1190 | // dff_rdata_w2_m_scanin[38] | |
| 1191 | // dff_rdata_w1_m_scanin[38] | |
| 1192 | // dff_rdata_w0_m_scanin[38] | |
| 1193 | // dff_wdata_m_scanin[122] | |
| 1194 | // dff_wdata_m_scanin[50] | |
| 1195 | // dff_rdata_w3_m_scanin[45] | |
| 1196 | // dff_rdata_w2_m_scanin[45] | |
| 1197 | // dff_rdata_w1_m_scanin[45] | |
| 1198 | // dff_rdata_w0_m_scanin[45] | |
| 1199 | // dff_wdata_m_scanin[113] | |
| 1200 | // dff_wdata_m_scanin[41] | |
| 1201 | // dff_rdata_w3_m_scanin[37] | |
| 1202 | // dff_rdata_w2_m_scanin[37] | |
| 1203 | // dff_rdata_w1_m_scanin[37] | |
| 1204 | // dff_rdata_w0_m_scanin[37] | |
| 1205 | // dff_wdata_m_scanin[121] | |
| 1206 | // dff_wdata_m_scanin[49] | |
| 1207 | // dff_rdata_w3_m_scanin[44] | |
| 1208 | // dff_rdata_w2_m_scanin[44] | |
| 1209 | // dff_rdata_w1_m_scanin[44] | |
| 1210 | // dff_rdata_w0_m_scanin[44] | |
| 1211 | // dff_wdata_m_scanin[112] | |
| 1212 | // dff_wdata_m_scanin[40] | |
| 1213 | // dff_rdata_w3_m_scanin[36] | |
| 1214 | // dff_rdata_w2_m_scanin[36] | |
| 1215 | // dff_rdata_w1_m_scanin[36] | |
| 1216 | // dff_rdata_w0_m_scanin[36] | |
| 1217 | // dff_wdata_m_scanin[120] | |
| 1218 | // dff_wdata_m_scanin[48] | |
| 1219 | // dff_rdata_w3_m_scanin[43] | |
| 1220 | // dff_rdata_w2_m_scanin[43] | |
| 1221 | // dff_rdata_w1_m_scanin[43] | |
| 1222 | // dff_rdata_w0_m_scanin[43] | |
| 1223 | // dff_wdata_m_scanin[111] | |
| 1224 | // dff_wdata_m_scanin[39] | |
| 1225 | // dff_rdata_w3_m_scanin[35] | |
| 1226 | // dff_rdata_w2_m_scanin[35] | |
| 1227 | // dff_rdata_w1_m_scanin[35] | |
| 1228 | // dff_rdata_w0_m_scanin[35] | |
| 1229 | // dff_wdata_m_scanin[119] | |
| 1230 | // dff_wdata_m_scanin[47] | |
| 1231 | // dff_rdata_w3_m_scanin[42] | |
| 1232 | // dff_rdata_w2_m_scanin[42] | |
| 1233 | // dff_rdata_w1_m_scanin[42] | |
| 1234 | // dff_rdata_w0_m_scanin[42] | |
| 1235 | // dff_wdata_m_scanin[110] | |
| 1236 | // dff_wdata_m_scanin[38] | |
| 1237 | // dff_rdata_w3_m_scanin[34] | |
| 1238 | // dff_rdata_w2_m_scanin[34] | |
| 1239 | // dff_rdata_w1_m_scanin[34] | |
| 1240 | // dff_rdata_w0_m_scanin[34] | |
| 1241 | // dff_wdata_m_scanin[118] | |
| 1242 | // dff_wdata_m_scanin[46] | |
| 1243 | // dff_rdata_w3_m_scanin[41] | |
| 1244 | // dff_rdata_w2_m_scanin[41] | |
| 1245 | // dff_rdata_w1_m_scanin[41] | |
| 1246 | // dff_rdata_w0_m_scanin[41] | |
| 1247 | // dff_wdata_m_scanin[109] | |
| 1248 | // dff_wdata_m_scanin[37] | |
| 1249 | // dff_rdata_w3_m_scanin[33] | |
| 1250 | // dff_rdata_w2_m_scanin[33] | |
| 1251 | // dff_rdata_w1_m_scanin[33] | |
| 1252 | // dff_rdata_w0_m_scanin[33] | |
| 1253 | // dff_wdata_m_scanin[117] | |
| 1254 | // dff_wdata_m_scanin[45] | |
| 1255 | // dff_rdata_w3_m_scanin[40] | |
| 1256 | // dff_rdata_w2_m_scanin[40] | |
| 1257 | // dff_rdata_w1_m_scanin[40] | |
| 1258 | // dff_rdata_w0_m_scanin[40] | |
| 1259 | // dff_wdata_m_scanin[108] | |
| 1260 | // dff_wdata_m_scanin[36] | |
| 1261 | // dff_rdata_w3_m_scanin[32] | |
| 1262 | // dff_rdata_w2_m_scanin[32] | |
| 1263 | // dff_rdata_w1_m_scanin[32] | |
| 1264 | // dff_rdata_w0_m_scanin[32] | |
| 1265 | // dff_ctl_m_1_scanin[15] | |
| 1266 | // dff_ctl_m_1_scanin[7] | |
| 1267 | // dff_ctl_m_1_scanin[14] | |
| 1268 | // dff_ctl_m_1_scanin[6] | |
| 1269 | // dff_ctl_m_1_scanin[13] | |
| 1270 | // dff_ctl_m_1_scanin[5] | |
| 1271 | // dff_ctl_m_1_scanin[12] | |
| 1272 | // dff_ctl_m_1_scanin[4] | |
| 1273 | // dff_byte_perr_w2_scanin[7] | |
| 1274 | // dff_byte_perr_w3_scanin[7] | |
| 1275 | // dff_byte_perr_w3_scanin[6] | |
| 1276 | // dff_byte_perr_w2_scanin[6] | |
| 1277 | // dff_byte_perr_w2_scanin[5] | |
| 1278 | // dff_byte_perr_w3_scanin[5] | |
| 1279 | // dff_byte_perr_w3_scanin[4] | |
| 1280 | // dff_byte_perr_w2_scanin[4] | |
| 1281 | // dff_ctl_m_0_scanin[0] | |
| 1282 | // dff_ctl_b_scanin[4] | |
| 1283 | // dff_ctl_b_scanin[0] | |
| 1284 | // dff_ctl_b_scanin[1] | |
| 1285 | // dff_ctl_b_scanin[2] | |
| 1286 | // dff_ctl_b_scanin[3] | |
| 1287 | // lat_ctl_eb_scanin[6] | |
| 1288 | // lat_ctl_eb_scanin[1] | |
| 1289 | // lat_ctl_eb_scanin[0] | |
| 1290 | // lat_ctl_eb_scanin[2] | |
| 1291 | // lat_ctl_eb_scanin[3] | |
| 1292 | // lat_addr_scanin[1] | |
| 1293 | // lat_addr_scanin[0] | |
| 1294 | // lat_addr_scanin[7] | |
| 1295 | // lat_addr_scanin[6] | |
| 1296 | // lat_addr_scanin[5] | |
| 1297 | // lat_addr_scanin[4] | |
| 1298 | // lat_addr_scanin[3] | |
| 1299 | // lat_addr_scanin[2] | |
| 1300 | // lat_ctl_eb_scanin[4] | |
| 1301 | // dff_ctl_m_0_scanin[1] | |
| 1302 | // dff_ctl_m_0_scanin[2] | |
| 1303 | // lat_ctl_eb_scanin[5] | |
| 1304 | // dff_byte_perr_w0_scanin[0] | |
| 1305 | // dff_byte_perr_w1_scanin[0] | |
| 1306 | // dff_byte_perr_w1_scanin[1] | |
| 1307 | // dff_byte_perr_w0_scanin[1] | |
| 1308 | // dff_byte_perr_w0_scanin[2] | |
| 1309 | // dff_byte_perr_w1_scanin[2] | |
| 1310 | // dff_byte_perr_w1_scanin[3] | |
| 1311 | // dff_byte_perr_w0_scanin[3] | |
| 1312 | // dff_wdata_m_scanin[80] | |
| 1313 | // dff_wdata_m_scanin[8] | |
| 1314 | // dff_rparity_w3_m_scanin[0] | |
| 1315 | // dff_rparity_w2_m_scanin[0] | |
| 1316 | // dff_rparity_w1_m_scanin[0] | |
| 1317 | // dff_rparity_w0_m_scanin[0] | |
| 1318 | // dff_wdata_m_scanin[89] | |
| 1319 | // dff_wdata_m_scanin[17] | |
| 1320 | // dff_rparity_w3_m_scanin[1] | |
| 1321 | // dff_rparity_w2_m_scanin[1] | |
| 1322 | // dff_rparity_w1_m_scanin[1] | |
| 1323 | // dff_rparity_w0_m_scanin[1] | |
| 1324 | // dff_wdata_m_scanin[72] | |
| 1325 | // dff_wdata_m_scanin[0] | |
| 1326 | // dff_rdata_w3_m_scanin[0] | |
| 1327 | // dff_rdata_w2_m_scanin[0] | |
| 1328 | // dff_rdata_w1_m_scanin[0] | |
| 1329 | // dff_rdata_w0_m_scanin[0] | |
| 1330 | // dff_wdata_m_scanin[81] | |
| 1331 | // dff_wdata_m_scanin[9] | |
| 1332 | // dff_rdata_w3_m_scanin[8] | |
| 1333 | // dff_rdata_w2_m_scanin[8] | |
| 1334 | // dff_rdata_w1_m_scanin[8] | |
| 1335 | // dff_rdata_w0_m_scanin[8] | |
| 1336 | // dff_wdata_m_scanin[73] | |
| 1337 | // dff_wdata_m_scanin[1] | |
| 1338 | // dff_rdata_w3_m_scanin[1] | |
| 1339 | // dff_rdata_w2_m_scanin[1] | |
| 1340 | // dff_rdata_w1_m_scanin[1] | |
| 1341 | // dff_rdata_w0_m_scanin[1] | |
| 1342 | // dff_wdata_m_scanin[82] | |
| 1343 | // dff_wdata_m_scanin[10] | |
| 1344 | // dff_rdata_w3_m_scanin[9] | |
| 1345 | // dff_rdata_w2_m_scanin[9] | |
| 1346 | // dff_rdata_w1_m_scanin[9] | |
| 1347 | // dff_rdata_w0_m_scanin[9] | |
| 1348 | // dff_wdata_m_scanin[74] | |
| 1349 | // dff_wdata_m_scanin[2] | |
| 1350 | // dff_rdata_w3_m_scanin[2] | |
| 1351 | // dff_rdata_w2_m_scanin[2] | |
| 1352 | // dff_rdata_w1_m_scanin[2] | |
| 1353 | // dff_rdata_w0_m_scanin[2] | |
| 1354 | // dff_wdata_m_scanin[83] | |
| 1355 | // dff_wdata_m_scanin[11] | |
| 1356 | // dff_rdata_w3_m_scanin[10] | |
| 1357 | // dff_rdata_w2_m_scanin[10] | |
| 1358 | // dff_rdata_w1_m_scanin[10] | |
| 1359 | // dff_rdata_w0_m_scanin[10] | |
| 1360 | // dff_wdata_m_scanin[75] | |
| 1361 | // dff_wdata_m_scanin[3] | |
| 1362 | // dff_rdata_w3_m_scanin[3] | |
| 1363 | // dff_rdata_w2_m_scanin[3] | |
| 1364 | // dff_rdata_w1_m_scanin[3] | |
| 1365 | // dff_rdata_w0_m_scanin[3] | |
| 1366 | // dff_wdata_m_scanin[84] | |
| 1367 | // dff_wdata_m_scanin[12] | |
| 1368 | // dff_rdata_w3_m_scanin[11] | |
| 1369 | // dff_rdata_w2_m_scanin[11] | |
| 1370 | // dff_rdata_w1_m_scanin[11] | |
| 1371 | // dff_rdata_w0_m_scanin[11] | |
| 1372 | // dff_wdata_m_scanin[76] | |
| 1373 | // dff_wdata_m_scanin[4] | |
| 1374 | // dff_rdata_w3_m_scanin[4] | |
| 1375 | // dff_rdata_w2_m_scanin[4] | |
| 1376 | // dff_rdata_w1_m_scanin[4] | |
| 1377 | // dff_rdata_w0_m_scanin[4] | |
| 1378 | // dff_wdata_m_scanin[85] | |
| 1379 | // dff_wdata_m_scanin[13] | |
| 1380 | // dff_rdata_w3_m_scanin[12] | |
| 1381 | // dff_rdata_w2_m_scanin[12] | |
| 1382 | // dff_rdata_w1_m_scanin[12] | |
| 1383 | // dff_rdata_w0_m_scanin[12] | |
| 1384 | // dff_wdata_m_scanin[77] | |
| 1385 | // dff_wdata_m_scanin[5] | |
| 1386 | // dff_rdata_w3_m_scanin[5] | |
| 1387 | // dff_rdata_w2_m_scanin[5] | |
| 1388 | // dff_rdata_w1_m_scanin[5] | |
| 1389 | // dff_rdata_w0_m_scanin[5] | |
| 1390 | // dff_wdata_m_scanin[86] | |
| 1391 | // dff_wdata_m_scanin[14] | |
| 1392 | // dff_rdata_w3_m_scanin[13] | |
| 1393 | // dff_rdata_w2_m_scanin[13] | |
| 1394 | // dff_rdata_w1_m_scanin[13] | |
| 1395 | // dff_rdata_w0_m_scanin[13] | |
| 1396 | // dff_wdata_m_scanin[78] | |
| 1397 | // dff_wdata_m_scanin[6] | |
| 1398 | // dff_rdata_w3_m_scanin[6] | |
| 1399 | // dff_rdata_w2_m_scanin[6] | |
| 1400 | // dff_rdata_w1_m_scanin[6] | |
| 1401 | // dff_rdata_w0_m_scanin[6] | |
| 1402 | // dff_wdata_m_scanin[87] | |
| 1403 | // dff_wdata_m_scanin[15] | |
| 1404 | // dff_rdata_w3_m_scanin[14] | |
| 1405 | // dff_rdata_w2_m_scanin[14] | |
| 1406 | // dff_rdata_w1_m_scanin[14] | |
| 1407 | // dff_rdata_w0_m_scanin[14] | |
| 1408 | // dff_wdata_m_scanin[79] | |
| 1409 | // dff_wdata_m_scanin[7] | |
| 1410 | // dff_rdata_w3_m_scanin[7] | |
| 1411 | // dff_rdata_w2_m_scanin[7] | |
| 1412 | // dff_rdata_w1_m_scanin[7] | |
| 1413 | // dff_rdata_w0_m_scanin[7] | |
| 1414 | // dff_wdata_m_scanin[88] | |
| 1415 | // dff_wdata_m_scanin[16] | |
| 1416 | // dff_rdata_w3_m_scanin[15] | |
| 1417 | // dff_rdata_w2_m_scanin[15] | |
| 1418 | // dff_rdata_w1_m_scanin[15] | |
| 1419 | // dff_rdata_w0_m_scanin[15] | |
| 1420 | // dff_wdata_m_scanin[98] | |
| 1421 | // dff_wdata_m_scanin[26] | |
| 1422 | // dff_rparity_w3_m_scanin[2] | |
| 1423 | // dff_rparity_w2_m_scanin[2] | |
| 1424 | // dff_rparity_w1_m_scanin[2] | |
| 1425 | // dff_rparity_w0_m_scanin[2] | |
| 1426 | // dff_wdata_m_scanin[107] | |
| 1427 | // dff_wdata_m_scanin[35] | |
| 1428 | // dff_rparity_w3_m_scanin[3] | |
| 1429 | // dff_rparity_w2_m_scanin[3] | |
| 1430 | // dff_rparity_w1_m_scanin[3] | |
| 1431 | // dff_rparity_w0_m_scanin[3] | |
| 1432 | // dff_wdata_m_scanin[90] | |
| 1433 | // dff_wdata_m_scanin[18] | |
| 1434 | // dff_rdata_w3_m_scanin[16] | |
| 1435 | // dff_rdata_w2_m_scanin[16] | |
| 1436 | // dff_rdata_w1_m_scanin[16] | |
| 1437 | // dff_rdata_w0_m_scanin[16] | |
| 1438 | // dff_wdata_m_scanin[99] | |
| 1439 | // dff_wdata_m_scanin[27] | |
| 1440 | // dff_rdata_w3_m_scanin[24] | |
| 1441 | // dff_rdata_w2_m_scanin[24] | |
| 1442 | // dff_rdata_w1_m_scanin[24] | |
| 1443 | // dff_rdata_w0_m_scanin[24] | |
| 1444 | // dff_wdata_m_scanin[91] | |
| 1445 | // dff_wdata_m_scanin[19] | |
| 1446 | // dff_rdata_w3_m_scanin[17] | |
| 1447 | // dff_rdata_w2_m_scanin[17] | |
| 1448 | // dff_rdata_w1_m_scanin[17] | |
| 1449 | // dff_rdata_w0_m_scanin[17] | |
| 1450 | // dff_wdata_m_scanin[100] | |
| 1451 | // dff_wdata_m_scanin[28] | |
| 1452 | // dff_rdata_w3_m_scanin[25] | |
| 1453 | // dff_rdata_w2_m_scanin[25] | |
| 1454 | // dff_rdata_w1_m_scanin[25] | |
| 1455 | // dff_rdata_w0_m_scanin[25] | |
| 1456 | // dff_wdata_m_scanin[92] | |
| 1457 | // dff_wdata_m_scanin[20] | |
| 1458 | // dff_rdata_w3_m_scanin[18] | |
| 1459 | // dff_rdata_w2_m_scanin[18] | |
| 1460 | // dff_rdata_w1_m_scanin[18] | |
| 1461 | // dff_rdata_w0_m_scanin[18] | |
| 1462 | // dff_wdata_m_scanin[101] | |
| 1463 | // dff_wdata_m_scanin[29] | |
| 1464 | // dff_rdata_w3_m_scanin[26] | |
| 1465 | // dff_rdata_w2_m_scanin[26] | |
| 1466 | // dff_rdata_w1_m_scanin[26] | |
| 1467 | // dff_rdata_w0_m_scanin[26] | |
| 1468 | // dff_wdata_m_scanin[93] | |
| 1469 | // dff_wdata_m_scanin[21] | |
| 1470 | // dff_rdata_w3_m_scanin[19] | |
| 1471 | // dff_rdata_w2_m_scanin[19] | |
| 1472 | // dff_rdata_w1_m_scanin[19] | |
| 1473 | // dff_rdata_w0_m_scanin[19] | |
| 1474 | // dff_wdata_m_scanin[102] | |
| 1475 | // dff_wdata_m_scanin[30] | |
| 1476 | // dff_rdata_w3_m_scanin[27] | |
| 1477 | // dff_rdata_w2_m_scanin[27] | |
| 1478 | // dff_rdata_w1_m_scanin[27] | |
| 1479 | // dff_rdata_w0_m_scanin[27] | |
| 1480 | // dff_wdata_m_scanin[94] | |
| 1481 | // dff_wdata_m_scanin[22] | |
| 1482 | // dff_rdata_w3_m_scanin[20] | |
| 1483 | // dff_rdata_w2_m_scanin[20] | |
| 1484 | // dff_rdata_w1_m_scanin[20] | |
| 1485 | // dff_rdata_w0_m_scanin[20] | |
| 1486 | // dff_wdata_m_scanin[103] | |
| 1487 | // dff_wdata_m_scanin[31] | |
| 1488 | // dff_rdata_w3_m_scanin[28] | |
| 1489 | // dff_rdata_w2_m_scanin[28] | |
| 1490 | // dff_rdata_w1_m_scanin[28] | |
| 1491 | // dff_rdata_w0_m_scanin[28] | |
| 1492 | // dff_wdata_m_scanin[95] | |
| 1493 | // dff_wdata_m_scanin[23] | |
| 1494 | // dff_rdata_w3_m_scanin[21] | |
| 1495 | // dff_rdata_w2_m_scanin[21] | |
| 1496 | // dff_rdata_w1_m_scanin[21] | |
| 1497 | // dff_rdata_w0_m_scanin[21] | |
| 1498 | // dff_wdata_m_scanin[104] | |
| 1499 | // dff_wdata_m_scanin[32] | |
| 1500 | // dff_rdata_w3_m_scanin[29] | |
| 1501 | // dff_rdata_w2_m_scanin[29] | |
| 1502 | // dff_rdata_w1_m_scanin[29] | |
| 1503 | // dff_rdata_w0_m_scanin[29] | |
| 1504 | // dff_wdata_m_scanin[96] | |
| 1505 | // dff_wdata_m_scanin[24] | |
| 1506 | // dff_rdata_w3_m_scanin[22] | |
| 1507 | // dff_rdata_w2_m_scanin[22] | |
| 1508 | // dff_rdata_w1_m_scanin[22] | |
| 1509 | // dff_rdata_w0_m_scanin[22] | |
| 1510 | // dff_wdata_m_scanin[105] | |
| 1511 | // dff_wdata_m_scanin[33] | |
| 1512 | // dff_rdata_w3_m_scanin[30] | |
| 1513 | // dff_rdata_w2_m_scanin[30] | |
| 1514 | // dff_rdata_w1_m_scanin[30] | |
| 1515 | // dff_rdata_w0_m_scanin[30] | |
| 1516 | // dff_wdata_m_scanin[97] | |
| 1517 | // dff_wdata_m_scanin[25] | |
| 1518 | // dff_rdata_w3_m_scanin[23] | |
| 1519 | // dff_rdata_w2_m_scanin[23] | |
| 1520 | // dff_rdata_w1_m_scanin[23] | |
| 1521 | // dff_rdata_w0_m_scanin[23] | |
| 1522 | // dff_wdata_m_scanin[106] | |
| 1523 | // dff_wdata_m_scanin[34] | |
| 1524 | // dff_rdata_w3_m_scanin[31] | |
| 1525 | // dff_rdata_w2_m_scanin[31] | |
| 1526 | // dff_rdata_w1_m_scanin[31] | |
| 1527 | // dff_rdata_w0_m_scanin[31] | |
| 1528 | // dff_ctl_m_1_scanin[8] | |
| 1529 | // dff_ctl_m_1_scanin[0] | |
| 1530 | // dff_ctl_m_1_scanin[9] | |
| 1531 | // dff_ctl_m_1_scanin[1] | |
| 1532 | // dff_ctl_m_1_scanin[10] | |
| 1533 | // dff_ctl_m_1_scanin[2] | |
| 1534 | // dff_ctl_m_1_scanin[11] | |
| 1535 | // dff_ctl_m_1_scanin[3] | |
| 1536 | // dff_byte_perr_w2_scanin[0] | |
| 1537 | // dff_byte_perr_w3_scanin[0] | |
| 1538 | // dff_byte_perr_w3_scanin[1] | |
| 1539 | // dff_byte_perr_w2_scanin[1] | |
| 1540 | // dff_byte_perr_w2_scanin[2] | |
| 1541 | // dff_byte_perr_w3_scanin[2] | |
| 1542 | // dff_byte_perr_w3_scanin[3] | |
| 1543 | // dff_byte_perr_w2_scanin[3] | |
| 1544 | // dff_msb_w3_scanin[7] | |
| 1545 | // dff_msb_w2_scanin[7] | |
| 1546 | // dff_msb_w1_scanin[7] | |
| 1547 | // dff_msb_w0_scanin[7] | |
| 1548 | // dff_msb_w3_scanin[6] | |
| 1549 | // dff_msb_w2_scanin[6] | |
| 1550 | // dff_msb_w1_scanin[6] | |
| 1551 | // dff_msb_w0_scanin[6] | |
| 1552 | // dff_msb_w3_scanin[5] | |
| 1553 | // dff_msb_w2_scanin[5] | |
| 1554 | // dff_msb_w1_scanin[5] | |
| 1555 | // dff_msb_w0_scanin[5] | |
| 1556 | // dff_msb_w3_scanin[4] | |
| 1557 | // dff_msb_w2_scanin[4] | |
| 1558 | // dff_msb_w1_scanin[4] | |
| 1559 | // dff_msb_w0_scanin[4] | |
| 1560 | // dff_msb_w3_scanin[0] | |
| 1561 | // dff_msb_w2_scanin[0] | |
| 1562 | // dff_msb_w1_scanin[0] | |
| 1563 | // dff_msb_w0_scanin[0] | |
| 1564 | // dff_msb_w3_scanin[1] | |
| 1565 | // dff_msb_w2_scanin[1] | |
| 1566 | // dff_msb_w1_scanin[1] | |
| 1567 | // dff_msb_w0_scanin[1] | |
| 1568 | // dff_msb_w3_scanin[2] | |
| 1569 | // dff_msb_w2_scanin[2] | |
| 1570 | // dff_msb_w1_scanin[2] | |
| 1571 | // dff_msb_w0_scanin[2] | |
| 1572 | // dff_msb_w3_scanin[3] | |
| 1573 | // dff_msb_w2_scanin[3] | |
| 1574 | // dff_msb_w1_scanin[3] | |
| 1575 | // dff_msb_w0_scanin[3] | |
| 1576 | // dff_red_out_scanin[2] | |
| 1577 | // dff_red_out_scanin[3] | |
| 1578 | // dff_red_out_scanin[4] | |
| 1579 | // dff_red_out_scanin[5] | |
| 1580 | // dff_red_out_scanin[6] | |
| 1581 | // dff_red_out_scanin[7] | |
| 1582 | // dff_red_out_scanin[0] | |
| 1583 | // dff_red_out_scanin[1] | |
| 1584 | // dff_red_in_scanin[2] | |
| 1585 | // dff_red_in_scanin[3] | |
| 1586 | // dff_red_in_scanin[1] | |
| 1587 | // dff_red_in_scanin[0] | |
| 1588 | // dff_red_in_scanin[6] | |
| 1589 | // dff_red_in_scanin[7] | |
| 1590 | // dff_red_in_scanin[8] | |
| 1591 | // dff_red_in_scanin[9] | |
| 1592 | // dff_red_in_scanin[10] | |
| 1593 | // dff_red_in_scanin[11] | |
| 1594 | // dff_red_in_scanin[4] | |
| 1595 | // dff_red_in_scanin[5] | |
| 1596 | // scanorder end | |
| 1597 | // fixscan start | |
| 1598 | assign dff_byte_perr_w0_scanin[7]=scan_in; | |
| 1599 | assign dff_byte_perr_w1_scanin[7]=dff_byte_perr_w0_scanout[7]; | |
| 1600 | assign dff_byte_perr_w1_scanin[6]=dff_byte_perr_w1_scanout[7]; | |
| 1601 | assign dff_byte_perr_w0_scanin[6]=dff_byte_perr_w1_scanout[6]; | |
| 1602 | assign dff_byte_perr_w0_scanin[5]=dff_byte_perr_w0_scanout[6]; | |
| 1603 | assign dff_byte_perr_w1_scanin[5]=dff_byte_perr_w0_scanout[5]; | |
| 1604 | assign dff_byte_perr_w1_scanin[4]=dff_byte_perr_w1_scanout[5]; | |
| 1605 | assign dff_byte_perr_w0_scanin[4]=dff_byte_perr_w1_scanout[4]; | |
| 1606 | assign dff_wdata_m_scanin[143]=dff_byte_perr_w0_scanout[4]; | |
| 1607 | assign dff_wdata_m_scanin[71]=dff_wdata_m_scanout[143]; | |
| 1608 | assign dff_rparity_w3_m_scanin[7]=dff_wdata_m_scanout[71]; | |
| 1609 | assign dff_rparity_w2_m_scanin[7]=dff_rparity_w3_m_scanout[7]; | |
| 1610 | assign dff_rparity_w1_m_scanin[7]=dff_rparity_w2_m_scanout[7]; | |
| 1611 | assign dff_rparity_w0_m_scanin[7]=dff_rparity_w1_m_scanout[7]; | |
| 1612 | assign dff_wdata_m_scanin[134]=dff_rparity_w0_m_scanout[7]; | |
| 1613 | assign dff_wdata_m_scanin[62]=dff_wdata_m_scanout[134]; | |
| 1614 | assign dff_rparity_w3_m_scanin[6]=dff_wdata_m_scanout[62]; | |
| 1615 | assign dff_rparity_w2_m_scanin[6]=dff_rparity_w3_m_scanout[6]; | |
| 1616 | assign dff_rparity_w1_m_scanin[6]=dff_rparity_w2_m_scanout[6]; | |
| 1617 | assign dff_rparity_w0_m_scanin[6]=dff_rparity_w1_m_scanout[6]; | |
| 1618 | assign dff_wdata_m_scanin[142]=dff_rparity_w0_m_scanout[6]; | |
| 1619 | assign dff_wdata_m_scanin[70]=dff_wdata_m_scanout[142]; | |
| 1620 | assign dff_rdata_w3_m_scanin[63]=dff_wdata_m_scanout[70]; | |
| 1621 | assign dff_rdata_w2_m_scanin[63]=dff_rdata_w3_m_scanout[63]; | |
| 1622 | assign dff_rdata_w1_m_scanin[63]=dff_rdata_w2_m_scanout[63]; | |
| 1623 | assign dff_rdata_w0_m_scanin[63]=dff_rdata_w1_m_scanout[63]; | |
| 1624 | assign dff_wdata_m_scanin[133]=dff_rdata_w0_m_scanout[63]; | |
| 1625 | assign dff_wdata_m_scanin[61]=dff_wdata_m_scanout[133]; | |
| 1626 | assign dff_rdata_w3_m_scanin[55]=dff_wdata_m_scanout[61]; | |
| 1627 | assign dff_rdata_w2_m_scanin[55]=dff_rdata_w3_m_scanout[55]; | |
| 1628 | assign dff_rdata_w1_m_scanin[55]=dff_rdata_w2_m_scanout[55]; | |
| 1629 | assign dff_rdata_w0_m_scanin[55]=dff_rdata_w1_m_scanout[55]; | |
| 1630 | assign dff_wdata_m_scanin[141]=dff_rdata_w0_m_scanout[55]; | |
| 1631 | assign dff_wdata_m_scanin[69]=dff_wdata_m_scanout[141]; | |
| 1632 | assign dff_rdata_w3_m_scanin[62]=dff_wdata_m_scanout[69]; | |
| 1633 | assign dff_rdata_w2_m_scanin[62]=dff_rdata_w3_m_scanout[62]; | |
| 1634 | assign dff_rdata_w1_m_scanin[62]=dff_rdata_w2_m_scanout[62]; | |
| 1635 | assign dff_rdata_w0_m_scanin[62]=dff_rdata_w1_m_scanout[62]; | |
| 1636 | assign dff_wdata_m_scanin[132]=dff_rdata_w0_m_scanout[62]; | |
| 1637 | assign dff_wdata_m_scanin[60]=dff_wdata_m_scanout[132]; | |
| 1638 | assign dff_rdata_w3_m_scanin[54]=dff_wdata_m_scanout[60]; | |
| 1639 | assign dff_rdata_w2_m_scanin[54]=dff_rdata_w3_m_scanout[54]; | |
| 1640 | assign dff_rdata_w1_m_scanin[54]=dff_rdata_w2_m_scanout[54]; | |
| 1641 | assign dff_rdata_w0_m_scanin[54]=dff_rdata_w1_m_scanout[54]; | |
| 1642 | assign dff_wdata_m_scanin[140]=dff_rdata_w0_m_scanout[54]; | |
| 1643 | assign dff_wdata_m_scanin[68]=dff_wdata_m_scanout[140]; | |
| 1644 | assign dff_rdata_w3_m_scanin[61]=dff_wdata_m_scanout[68]; | |
| 1645 | assign dff_rdata_w2_m_scanin[61]=dff_rdata_w3_m_scanout[61]; | |
| 1646 | assign dff_rdata_w1_m_scanin[61]=dff_rdata_w2_m_scanout[61]; | |
| 1647 | assign dff_rdata_w0_m_scanin[61]=dff_rdata_w1_m_scanout[61]; | |
| 1648 | assign dff_wdata_m_scanin[131]=dff_rdata_w0_m_scanout[61]; | |
| 1649 | assign dff_wdata_m_scanin[59]=dff_wdata_m_scanout[131]; | |
| 1650 | assign dff_rdata_w3_m_scanin[53]=dff_wdata_m_scanout[59]; | |
| 1651 | assign dff_rdata_w2_m_scanin[53]=dff_rdata_w3_m_scanout[53]; | |
| 1652 | assign dff_rdata_w1_m_scanin[53]=dff_rdata_w2_m_scanout[53]; | |
| 1653 | assign dff_rdata_w0_m_scanin[53]=dff_rdata_w1_m_scanout[53]; | |
| 1654 | assign dff_wdata_m_scanin[139]=dff_rdata_w0_m_scanout[53]; | |
| 1655 | assign dff_wdata_m_scanin[67]=dff_wdata_m_scanout[139]; | |
| 1656 | assign dff_rdata_w3_m_scanin[60]=dff_wdata_m_scanout[67]; | |
| 1657 | assign dff_rdata_w2_m_scanin[60]=dff_rdata_w3_m_scanout[60]; | |
| 1658 | assign dff_rdata_w1_m_scanin[60]=dff_rdata_w2_m_scanout[60]; | |
| 1659 | assign dff_rdata_w0_m_scanin[60]=dff_rdata_w1_m_scanout[60]; | |
| 1660 | assign dff_wdata_m_scanin[130]=dff_rdata_w0_m_scanout[60]; | |
| 1661 | assign dff_wdata_m_scanin[58]=dff_wdata_m_scanout[130]; | |
| 1662 | assign dff_rdata_w3_m_scanin[52]=dff_wdata_m_scanout[58]; | |
| 1663 | assign dff_rdata_w2_m_scanin[52]=dff_rdata_w3_m_scanout[52]; | |
| 1664 | assign dff_rdata_w1_m_scanin[52]=dff_rdata_w2_m_scanout[52]; | |
| 1665 | assign dff_rdata_w0_m_scanin[52]=dff_rdata_w1_m_scanout[52]; | |
| 1666 | assign dff_wdata_m_scanin[138]=dff_rdata_w0_m_scanout[52]; | |
| 1667 | assign dff_wdata_m_scanin[66]=dff_wdata_m_scanout[138]; | |
| 1668 | assign dff_rdata_w3_m_scanin[59]=dff_wdata_m_scanout[66]; | |
| 1669 | assign dff_rdata_w2_m_scanin[59]=dff_rdata_w3_m_scanout[59]; | |
| 1670 | assign dff_rdata_w1_m_scanin[59]=dff_rdata_w2_m_scanout[59]; | |
| 1671 | assign dff_rdata_w0_m_scanin[59]=dff_rdata_w1_m_scanout[59]; | |
| 1672 | assign dff_wdata_m_scanin[129]=dff_rdata_w0_m_scanout[59]; | |
| 1673 | assign dff_wdata_m_scanin[57]=dff_wdata_m_scanout[129]; | |
| 1674 | assign dff_rdata_w3_m_scanin[51]=dff_wdata_m_scanout[57]; | |
| 1675 | assign dff_rdata_w2_m_scanin[51]=dff_rdata_w3_m_scanout[51]; | |
| 1676 | assign dff_rdata_w1_m_scanin[51]=dff_rdata_w2_m_scanout[51]; | |
| 1677 | assign dff_rdata_w0_m_scanin[51]=dff_rdata_w1_m_scanout[51]; | |
| 1678 | assign dff_wdata_m_scanin[137]=dff_rdata_w0_m_scanout[51]; | |
| 1679 | assign dff_wdata_m_scanin[65]=dff_wdata_m_scanout[137]; | |
| 1680 | assign dff_rdata_w3_m_scanin[58]=dff_wdata_m_scanout[65]; | |
| 1681 | assign dff_rdata_w2_m_scanin[58]=dff_rdata_w3_m_scanout[58]; | |
| 1682 | assign dff_rdata_w1_m_scanin[58]=dff_rdata_w2_m_scanout[58]; | |
| 1683 | assign dff_rdata_w0_m_scanin[58]=dff_rdata_w1_m_scanout[58]; | |
| 1684 | assign dff_wdata_m_scanin[128]=dff_rdata_w0_m_scanout[58]; | |
| 1685 | assign dff_wdata_m_scanin[56]=dff_wdata_m_scanout[128]; | |
| 1686 | assign dff_rdata_w3_m_scanin[50]=dff_wdata_m_scanout[56]; | |
| 1687 | assign dff_rdata_w2_m_scanin[50]=dff_rdata_w3_m_scanout[50]; | |
| 1688 | assign dff_rdata_w1_m_scanin[50]=dff_rdata_w2_m_scanout[50]; | |
| 1689 | assign dff_rdata_w0_m_scanin[50]=dff_rdata_w1_m_scanout[50]; | |
| 1690 | assign dff_wdata_m_scanin[136]=dff_rdata_w0_m_scanout[50]; | |
| 1691 | assign dff_wdata_m_scanin[64]=dff_wdata_m_scanout[136]; | |
| 1692 | assign dff_rdata_w3_m_scanin[57]=dff_wdata_m_scanout[64]; | |
| 1693 | assign dff_rdata_w2_m_scanin[57]=dff_rdata_w3_m_scanout[57]; | |
| 1694 | assign dff_rdata_w1_m_scanin[57]=dff_rdata_w2_m_scanout[57]; | |
| 1695 | assign dff_rdata_w0_m_scanin[57]=dff_rdata_w1_m_scanout[57]; | |
| 1696 | assign dff_wdata_m_scanin[127]=dff_rdata_w0_m_scanout[57]; | |
| 1697 | assign dff_wdata_m_scanin[55]=dff_wdata_m_scanout[127]; | |
| 1698 | assign dff_rdata_w3_m_scanin[49]=dff_wdata_m_scanout[55]; | |
| 1699 | assign dff_rdata_w2_m_scanin[49]=dff_rdata_w3_m_scanout[49]; | |
| 1700 | assign dff_rdata_w1_m_scanin[49]=dff_rdata_w2_m_scanout[49]; | |
| 1701 | assign dff_rdata_w0_m_scanin[49]=dff_rdata_w1_m_scanout[49]; | |
| 1702 | assign dff_wdata_m_scanin[135]=dff_rdata_w0_m_scanout[49]; | |
| 1703 | assign dff_wdata_m_scanin[63]=dff_wdata_m_scanout[135]; | |
| 1704 | assign dff_rdata_w3_m_scanin[56]=dff_wdata_m_scanout[63]; | |
| 1705 | assign dff_rdata_w2_m_scanin[56]=dff_rdata_w3_m_scanout[56]; | |
| 1706 | assign dff_rdata_w1_m_scanin[56]=dff_rdata_w2_m_scanout[56]; | |
| 1707 | assign dff_rdata_w0_m_scanin[56]=dff_rdata_w1_m_scanout[56]; | |
| 1708 | assign dff_wdata_m_scanin[126]=dff_rdata_w0_m_scanout[56]; | |
| 1709 | assign dff_wdata_m_scanin[54]=dff_wdata_m_scanout[126]; | |
| 1710 | assign dff_rdata_w3_m_scanin[48]=dff_wdata_m_scanout[54]; | |
| 1711 | assign dff_rdata_w2_m_scanin[48]=dff_rdata_w3_m_scanout[48]; | |
| 1712 | assign dff_rdata_w1_m_scanin[48]=dff_rdata_w2_m_scanout[48]; | |
| 1713 | assign dff_rdata_w0_m_scanin[48]=dff_rdata_w1_m_scanout[48]; | |
| 1714 | assign dff_wdata_m_scanin[125]=dff_rdata_w0_m_scanout[48]; | |
| 1715 | assign dff_wdata_m_scanin[53]=dff_wdata_m_scanout[125]; | |
| 1716 | assign dff_rparity_w3_m_scanin[5]=dff_wdata_m_scanout[53]; | |
| 1717 | assign dff_rparity_w2_m_scanin[5]=dff_rparity_w3_m_scanout[5]; | |
| 1718 | assign dff_rparity_w1_m_scanin[5]=dff_rparity_w2_m_scanout[5]; | |
| 1719 | assign dff_rparity_w0_m_scanin[5]=dff_rparity_w1_m_scanout[5]; | |
| 1720 | assign dff_wdata_m_scanin[116]=dff_rparity_w0_m_scanout[5]; | |
| 1721 | assign dff_wdata_m_scanin[44]=dff_wdata_m_scanout[116]; | |
| 1722 | assign dff_rparity_w3_m_scanin[4]=dff_wdata_m_scanout[44]; | |
| 1723 | assign dff_rparity_w2_m_scanin[4]=dff_rparity_w3_m_scanout[4]; | |
| 1724 | assign dff_rparity_w1_m_scanin[4]=dff_rparity_w2_m_scanout[4]; | |
| 1725 | assign dff_rparity_w0_m_scanin[4]=dff_rparity_w1_m_scanout[4]; | |
| 1726 | assign dff_wdata_m_scanin[124]=dff_rparity_w0_m_scanout[4]; | |
| 1727 | assign dff_wdata_m_scanin[52]=dff_wdata_m_scanout[124]; | |
| 1728 | assign dff_rdata_w3_m_scanin[47]=dff_wdata_m_scanout[52]; | |
| 1729 | assign dff_rdata_w2_m_scanin[47]=dff_rdata_w3_m_scanout[47]; | |
| 1730 | assign dff_rdata_w1_m_scanin[47]=dff_rdata_w2_m_scanout[47]; | |
| 1731 | assign dff_rdata_w0_m_scanin[47]=dff_rdata_w1_m_scanout[47]; | |
| 1732 | assign dff_wdata_m_scanin[115]=dff_rdata_w0_m_scanout[47]; | |
| 1733 | assign dff_wdata_m_scanin[43]=dff_wdata_m_scanout[115]; | |
| 1734 | assign dff_rdata_w3_m_scanin[39]=dff_wdata_m_scanout[43]; | |
| 1735 | assign dff_rdata_w2_m_scanin[39]=dff_rdata_w3_m_scanout[39]; | |
| 1736 | assign dff_rdata_w1_m_scanin[39]=dff_rdata_w2_m_scanout[39]; | |
| 1737 | assign dff_rdata_w0_m_scanin[39]=dff_rdata_w1_m_scanout[39]; | |
| 1738 | assign dff_wdata_m_scanin[123]=dff_rdata_w0_m_scanout[39]; | |
| 1739 | assign dff_wdata_m_scanin[51]=dff_wdata_m_scanout[123]; | |
| 1740 | assign dff_rdata_w3_m_scanin[46]=dff_wdata_m_scanout[51]; | |
| 1741 | assign dff_rdata_w2_m_scanin[46]=dff_rdata_w3_m_scanout[46]; | |
| 1742 | assign dff_rdata_w1_m_scanin[46]=dff_rdata_w2_m_scanout[46]; | |
| 1743 | assign dff_rdata_w0_m_scanin[46]=dff_rdata_w1_m_scanout[46]; | |
| 1744 | assign dff_wdata_m_scanin[114]=dff_rdata_w0_m_scanout[46]; | |
| 1745 | assign dff_wdata_m_scanin[42]=dff_wdata_m_scanout[114]; | |
| 1746 | assign dff_rdata_w3_m_scanin[38]=dff_wdata_m_scanout[42]; | |
| 1747 | assign dff_rdata_w2_m_scanin[38]=dff_rdata_w3_m_scanout[38]; | |
| 1748 | assign dff_rdata_w1_m_scanin[38]=dff_rdata_w2_m_scanout[38]; | |
| 1749 | assign dff_rdata_w0_m_scanin[38]=dff_rdata_w1_m_scanout[38]; | |
| 1750 | assign dff_wdata_m_scanin[122]=dff_rdata_w0_m_scanout[38]; | |
| 1751 | assign dff_wdata_m_scanin[50]=dff_wdata_m_scanout[122]; | |
| 1752 | assign dff_rdata_w3_m_scanin[45]=dff_wdata_m_scanout[50]; | |
| 1753 | assign dff_rdata_w2_m_scanin[45]=dff_rdata_w3_m_scanout[45]; | |
| 1754 | assign dff_rdata_w1_m_scanin[45]=dff_rdata_w2_m_scanout[45]; | |
| 1755 | assign dff_rdata_w0_m_scanin[45]=dff_rdata_w1_m_scanout[45]; | |
| 1756 | assign dff_wdata_m_scanin[113]=dff_rdata_w0_m_scanout[45]; | |
| 1757 | assign dff_wdata_m_scanin[41]=dff_wdata_m_scanout[113]; | |
| 1758 | assign dff_rdata_w3_m_scanin[37]=dff_wdata_m_scanout[41]; | |
| 1759 | assign dff_rdata_w2_m_scanin[37]=dff_rdata_w3_m_scanout[37]; | |
| 1760 | assign dff_rdata_w1_m_scanin[37]=dff_rdata_w2_m_scanout[37]; | |
| 1761 | assign dff_rdata_w0_m_scanin[37]=dff_rdata_w1_m_scanout[37]; | |
| 1762 | assign dff_wdata_m_scanin[121]=dff_rdata_w0_m_scanout[37]; | |
| 1763 | assign dff_wdata_m_scanin[49]=dff_wdata_m_scanout[121]; | |
| 1764 | assign dff_rdata_w3_m_scanin[44]=dff_wdata_m_scanout[49]; | |
| 1765 | assign dff_rdata_w2_m_scanin[44]=dff_rdata_w3_m_scanout[44]; | |
| 1766 | assign dff_rdata_w1_m_scanin[44]=dff_rdata_w2_m_scanout[44]; | |
| 1767 | assign dff_rdata_w0_m_scanin[44]=dff_rdata_w1_m_scanout[44]; | |
| 1768 | assign dff_wdata_m_scanin[112]=dff_rdata_w0_m_scanout[44]; | |
| 1769 | assign dff_wdata_m_scanin[40]=dff_wdata_m_scanout[112]; | |
| 1770 | assign dff_rdata_w3_m_scanin[36]=dff_wdata_m_scanout[40]; | |
| 1771 | assign dff_rdata_w2_m_scanin[36]=dff_rdata_w3_m_scanout[36]; | |
| 1772 | assign dff_rdata_w1_m_scanin[36]=dff_rdata_w2_m_scanout[36]; | |
| 1773 | assign dff_rdata_w0_m_scanin[36]=dff_rdata_w1_m_scanout[36]; | |
| 1774 | assign dff_wdata_m_scanin[120]=dff_rdata_w0_m_scanout[36]; | |
| 1775 | assign dff_wdata_m_scanin[48]=dff_wdata_m_scanout[120]; | |
| 1776 | assign dff_rdata_w3_m_scanin[43]=dff_wdata_m_scanout[48]; | |
| 1777 | assign dff_rdata_w2_m_scanin[43]=dff_rdata_w3_m_scanout[43]; | |
| 1778 | assign dff_rdata_w1_m_scanin[43]=dff_rdata_w2_m_scanout[43]; | |
| 1779 | assign dff_rdata_w0_m_scanin[43]=dff_rdata_w1_m_scanout[43]; | |
| 1780 | assign dff_wdata_m_scanin[111]=dff_rdata_w0_m_scanout[43]; | |
| 1781 | assign dff_wdata_m_scanin[39]=dff_wdata_m_scanout[111]; | |
| 1782 | assign dff_rdata_w3_m_scanin[35]=dff_wdata_m_scanout[39]; | |
| 1783 | assign dff_rdata_w2_m_scanin[35]=dff_rdata_w3_m_scanout[35]; | |
| 1784 | assign dff_rdata_w1_m_scanin[35]=dff_rdata_w2_m_scanout[35]; | |
| 1785 | assign dff_rdata_w0_m_scanin[35]=dff_rdata_w1_m_scanout[35]; | |
| 1786 | assign dff_wdata_m_scanin[119]=dff_rdata_w0_m_scanout[35]; | |
| 1787 | assign dff_wdata_m_scanin[47]=dff_wdata_m_scanout[119]; | |
| 1788 | assign dff_rdata_w3_m_scanin[42]=dff_wdata_m_scanout[47]; | |
| 1789 | assign dff_rdata_w2_m_scanin[42]=dff_rdata_w3_m_scanout[42]; | |
| 1790 | assign dff_rdata_w1_m_scanin[42]=dff_rdata_w2_m_scanout[42]; | |
| 1791 | assign dff_rdata_w0_m_scanin[42]=dff_rdata_w1_m_scanout[42]; | |
| 1792 | assign dff_wdata_m_scanin[110]=dff_rdata_w0_m_scanout[42]; | |
| 1793 | assign dff_wdata_m_scanin[38]=dff_wdata_m_scanout[110]; | |
| 1794 | assign dff_rdata_w3_m_scanin[34]=dff_wdata_m_scanout[38]; | |
| 1795 | assign dff_rdata_w2_m_scanin[34]=dff_rdata_w3_m_scanout[34]; | |
| 1796 | assign dff_rdata_w1_m_scanin[34]=dff_rdata_w2_m_scanout[34]; | |
| 1797 | assign dff_rdata_w0_m_scanin[34]=dff_rdata_w1_m_scanout[34]; | |
| 1798 | assign dff_wdata_m_scanin[118]=dff_rdata_w0_m_scanout[34]; | |
| 1799 | assign dff_wdata_m_scanin[46]=dff_wdata_m_scanout[118]; | |
| 1800 | assign dff_rdata_w3_m_scanin[41]=dff_wdata_m_scanout[46]; | |
| 1801 | assign dff_rdata_w2_m_scanin[41]=dff_rdata_w3_m_scanout[41]; | |
| 1802 | assign dff_rdata_w1_m_scanin[41]=dff_rdata_w2_m_scanout[41]; | |
| 1803 | assign dff_rdata_w0_m_scanin[41]=dff_rdata_w1_m_scanout[41]; | |
| 1804 | assign dff_wdata_m_scanin[109]=dff_rdata_w0_m_scanout[41]; | |
| 1805 | assign dff_wdata_m_scanin[37]=dff_wdata_m_scanout[109]; | |
| 1806 | assign dff_rdata_w3_m_scanin[33]=dff_wdata_m_scanout[37]; | |
| 1807 | assign dff_rdata_w2_m_scanin[33]=dff_rdata_w3_m_scanout[33]; | |
| 1808 | assign dff_rdata_w1_m_scanin[33]=dff_rdata_w2_m_scanout[33]; | |
| 1809 | assign dff_rdata_w0_m_scanin[33]=dff_rdata_w1_m_scanout[33]; | |
| 1810 | assign dff_wdata_m_scanin[117]=dff_rdata_w0_m_scanout[33]; | |
| 1811 | assign dff_wdata_m_scanin[45]=dff_wdata_m_scanout[117]; | |
| 1812 | assign dff_rdata_w3_m_scanin[40]=dff_wdata_m_scanout[45]; | |
| 1813 | assign dff_rdata_w2_m_scanin[40]=dff_rdata_w3_m_scanout[40]; | |
| 1814 | assign dff_rdata_w1_m_scanin[40]=dff_rdata_w2_m_scanout[40]; | |
| 1815 | assign dff_rdata_w0_m_scanin[40]=dff_rdata_w1_m_scanout[40]; | |
| 1816 | assign dff_wdata_m_scanin[108]=dff_rdata_w0_m_scanout[40]; | |
| 1817 | assign dff_wdata_m_scanin[36]=dff_wdata_m_scanout[108]; | |
| 1818 | assign dff_rdata_w3_m_scanin[32]=dff_wdata_m_scanout[36]; | |
| 1819 | assign dff_rdata_w2_m_scanin[32]=dff_rdata_w3_m_scanout[32]; | |
| 1820 | assign dff_rdata_w1_m_scanin[32]=dff_rdata_w2_m_scanout[32]; | |
| 1821 | assign dff_rdata_w0_m_scanin[32]=dff_rdata_w1_m_scanout[32]; | |
| 1822 | assign dff_ctl_m_1_scanin[15]=dff_rdata_w0_m_scanout[32]; | |
| 1823 | assign dff_ctl_m_1_scanin[7]=dff_ctl_m_1_scanout[15]; | |
| 1824 | assign dff_ctl_m_1_scanin[14]=dff_ctl_m_1_scanout[7]; | |
| 1825 | assign dff_ctl_m_1_scanin[6]=dff_ctl_m_1_scanout[14]; | |
| 1826 | assign dff_ctl_m_1_scanin[13]=dff_ctl_m_1_scanout[6]; | |
| 1827 | assign dff_ctl_m_1_scanin[5]=dff_ctl_m_1_scanout[13]; | |
| 1828 | assign dff_ctl_m_1_scanin[12]=dff_ctl_m_1_scanout[5]; | |
| 1829 | assign dff_ctl_m_1_scanin[4]=dff_ctl_m_1_scanout[12]; | |
| 1830 | assign dff_byte_perr_w2_scanin[7]=dff_ctl_m_1_scanout[4]; | |
| 1831 | assign dff_byte_perr_w3_scanin[7]=dff_byte_perr_w2_scanout[7]; | |
| 1832 | assign dff_byte_perr_w3_scanin[6]=dff_byte_perr_w3_scanout[7]; | |
| 1833 | assign dff_byte_perr_w2_scanin[6]=dff_byte_perr_w3_scanout[6]; | |
| 1834 | assign dff_byte_perr_w2_scanin[5]=dff_byte_perr_w2_scanout[6]; | |
| 1835 | assign dff_byte_perr_w3_scanin[5]=dff_byte_perr_w2_scanout[5]; | |
| 1836 | assign dff_byte_perr_w3_scanin[4]=dff_byte_perr_w3_scanout[5]; | |
| 1837 | assign dff_byte_perr_w2_scanin[4]=dff_byte_perr_w3_scanout[4]; | |
| 1838 | assign dff_ctl_m_0_scanin[0]=dff_byte_perr_w2_scanout[4]; | |
| 1839 | assign dff_ctl_b_scanin[4]=dff_ctl_m_0_scanout[0]; | |
| 1840 | assign dff_ctl_b_scanin[0]=dff_ctl_b_scanout[4]; | |
| 1841 | assign dff_ctl_b_scanin[1]=dff_ctl_b_scanout[0]; | |
| 1842 | assign dff_ctl_b_scanin[2]=dff_ctl_b_scanout[1]; | |
| 1843 | assign dff_ctl_b_scanin[3]=dff_ctl_b_scanout[2]; | |
| 1844 | assign lat_ctl_eb_scanin[6]=dff_ctl_b_scanout[3]; | |
| 1845 | assign lat_ctl_eb_scanin[1]=lat_ctl_eb_scanout[6]; | |
| 1846 | assign lat_ctl_eb_scanin[0]=lat_ctl_eb_scanout[1]; | |
| 1847 | assign lat_ctl_eb_scanin[2]=lat_ctl_eb_scanout[0]; | |
| 1848 | assign lat_ctl_eb_scanin[3]=lat_ctl_eb_scanout[2]; | |
| 1849 | assign lat_addr_scanin[1]=lat_ctl_eb_scanout[3]; | |
| 1850 | assign lat_addr_scanin[0]=lat_addr_scanout[1]; | |
| 1851 | assign lat_addr_scanin[7]=lat_addr_scanout[0]; | |
| 1852 | assign lat_addr_scanin[6]=lat_addr_scanout[7]; | |
| 1853 | assign lat_addr_scanin[5]=lat_addr_scanout[6]; | |
| 1854 | assign lat_addr_scanin[4]=lat_addr_scanout[5]; | |
| 1855 | assign lat_addr_scanin[3]=lat_addr_scanout[4]; | |
| 1856 | assign lat_addr_scanin[2]=lat_addr_scanout[3]; | |
| 1857 | assign lat_ctl_eb_scanin[4]=lat_addr_scanout[2]; | |
| 1858 | assign dff_ctl_m_0_scanin[1]=lat_ctl_eb_scanout[4]; | |
| 1859 | assign dff_ctl_m_0_scanin[2]=dff_ctl_m_0_scanout[1]; | |
| 1860 | assign lat_ctl_eb_scanin[5]=dff_ctl_m_0_scanout[2]; | |
| 1861 | assign dff_byte_perr_w0_scanin[0]=lat_ctl_eb_scanout[5]; | |
| 1862 | assign dff_byte_perr_w1_scanin[0]=dff_byte_perr_w0_scanout[0]; | |
| 1863 | assign dff_byte_perr_w1_scanin[1]=dff_byte_perr_w1_scanout[0]; | |
| 1864 | assign dff_byte_perr_w0_scanin[1]=dff_byte_perr_w1_scanout[1]; | |
| 1865 | assign dff_byte_perr_w0_scanin[2]=dff_byte_perr_w0_scanout[1]; | |
| 1866 | assign dff_byte_perr_w1_scanin[2]=dff_byte_perr_w0_scanout[2]; | |
| 1867 | assign dff_byte_perr_w1_scanin[3]=dff_byte_perr_w1_scanout[2]; | |
| 1868 | assign dff_byte_perr_w0_scanin[3]=dff_byte_perr_w1_scanout[3]; | |
| 1869 | assign dff_wdata_m_scanin[80]=dff_byte_perr_w0_scanout[3]; | |
| 1870 | assign dff_wdata_m_scanin[8]=dff_wdata_m_scanout[80]; | |
| 1871 | assign dff_rparity_w3_m_scanin[0]=dff_wdata_m_scanout[8]; | |
| 1872 | assign dff_rparity_w2_m_scanin[0]=dff_rparity_w3_m_scanout[0]; | |
| 1873 | assign dff_rparity_w1_m_scanin[0]=dff_rparity_w2_m_scanout[0]; | |
| 1874 | assign dff_rparity_w0_m_scanin[0]=dff_rparity_w1_m_scanout[0]; | |
| 1875 | assign dff_wdata_m_scanin[89]=dff_rparity_w0_m_scanout[0]; | |
| 1876 | assign dff_wdata_m_scanin[17]=dff_wdata_m_scanout[89]; | |
| 1877 | assign dff_rparity_w3_m_scanin[1]=dff_wdata_m_scanout[17]; | |
| 1878 | assign dff_rparity_w2_m_scanin[1]=dff_rparity_w3_m_scanout[1]; | |
| 1879 | assign dff_rparity_w1_m_scanin[1]=dff_rparity_w2_m_scanout[1]; | |
| 1880 | assign dff_rparity_w0_m_scanin[1]=dff_rparity_w1_m_scanout[1]; | |
| 1881 | assign dff_wdata_m_scanin[72]=dff_rparity_w0_m_scanout[1]; | |
| 1882 | assign dff_wdata_m_scanin[0]=dff_wdata_m_scanout[72]; | |
| 1883 | assign dff_rdata_w3_m_scanin[0]=dff_wdata_m_scanout[0]; | |
| 1884 | assign dff_rdata_w2_m_scanin[0]=dff_rdata_w3_m_scanout[0]; | |
| 1885 | assign dff_rdata_w1_m_scanin[0]=dff_rdata_w2_m_scanout[0]; | |
| 1886 | assign dff_rdata_w0_m_scanin[0]=dff_rdata_w1_m_scanout[0]; | |
| 1887 | assign dff_wdata_m_scanin[81]=dff_rdata_w0_m_scanout[0]; | |
| 1888 | assign dff_wdata_m_scanin[9]=dff_wdata_m_scanout[81]; | |
| 1889 | assign dff_rdata_w3_m_scanin[8]=dff_wdata_m_scanout[9]; | |
| 1890 | assign dff_rdata_w2_m_scanin[8]=dff_rdata_w3_m_scanout[8]; | |
| 1891 | assign dff_rdata_w1_m_scanin[8]=dff_rdata_w2_m_scanout[8]; | |
| 1892 | assign dff_rdata_w0_m_scanin[8]=dff_rdata_w1_m_scanout[8]; | |
| 1893 | assign dff_wdata_m_scanin[73]=dff_rdata_w0_m_scanout[8]; | |
| 1894 | assign dff_wdata_m_scanin[1]=dff_wdata_m_scanout[73]; | |
| 1895 | assign dff_rdata_w3_m_scanin[1]=dff_wdata_m_scanout[1]; | |
| 1896 | assign dff_rdata_w2_m_scanin[1]=dff_rdata_w3_m_scanout[1]; | |
| 1897 | assign dff_rdata_w1_m_scanin[1]=dff_rdata_w2_m_scanout[1]; | |
| 1898 | assign dff_rdata_w0_m_scanin[1]=dff_rdata_w1_m_scanout[1]; | |
| 1899 | assign dff_wdata_m_scanin[82]=dff_rdata_w0_m_scanout[1]; | |
| 1900 | assign dff_wdata_m_scanin[10]=dff_wdata_m_scanout[82]; | |
| 1901 | assign dff_rdata_w3_m_scanin[9]=dff_wdata_m_scanout[10]; | |
| 1902 | assign dff_rdata_w2_m_scanin[9]=dff_rdata_w3_m_scanout[9]; | |
| 1903 | assign dff_rdata_w1_m_scanin[9]=dff_rdata_w2_m_scanout[9]; | |
| 1904 | assign dff_rdata_w0_m_scanin[9]=dff_rdata_w1_m_scanout[9]; | |
| 1905 | assign dff_wdata_m_scanin[74]=dff_rdata_w0_m_scanout[9]; | |
| 1906 | assign dff_wdata_m_scanin[2]=dff_wdata_m_scanout[74]; | |
| 1907 | assign dff_rdata_w3_m_scanin[2]=dff_wdata_m_scanout[2]; | |
| 1908 | assign dff_rdata_w2_m_scanin[2]=dff_rdata_w3_m_scanout[2]; | |
| 1909 | assign dff_rdata_w1_m_scanin[2]=dff_rdata_w2_m_scanout[2]; | |
| 1910 | assign dff_rdata_w0_m_scanin[2]=dff_rdata_w1_m_scanout[2]; | |
| 1911 | assign dff_wdata_m_scanin[83]=dff_rdata_w0_m_scanout[2]; | |
| 1912 | assign dff_wdata_m_scanin[11]=dff_wdata_m_scanout[83]; | |
| 1913 | assign dff_rdata_w3_m_scanin[10]=dff_wdata_m_scanout[11]; | |
| 1914 | assign dff_rdata_w2_m_scanin[10]=dff_rdata_w3_m_scanout[10]; | |
| 1915 | assign dff_rdata_w1_m_scanin[10]=dff_rdata_w2_m_scanout[10]; | |
| 1916 | assign dff_rdata_w0_m_scanin[10]=dff_rdata_w1_m_scanout[10]; | |
| 1917 | assign dff_wdata_m_scanin[75]=dff_rdata_w0_m_scanout[10]; | |
| 1918 | assign dff_wdata_m_scanin[3]=dff_wdata_m_scanout[75]; | |
| 1919 | assign dff_rdata_w3_m_scanin[3]=dff_wdata_m_scanout[3]; | |
| 1920 | assign dff_rdata_w2_m_scanin[3]=dff_rdata_w3_m_scanout[3]; | |
| 1921 | assign dff_rdata_w1_m_scanin[3]=dff_rdata_w2_m_scanout[3]; | |
| 1922 | assign dff_rdata_w0_m_scanin[3]=dff_rdata_w1_m_scanout[3]; | |
| 1923 | assign dff_wdata_m_scanin[84]=dff_rdata_w0_m_scanout[3]; | |
| 1924 | assign dff_wdata_m_scanin[12]=dff_wdata_m_scanout[84]; | |
| 1925 | assign dff_rdata_w3_m_scanin[11]=dff_wdata_m_scanout[12]; | |
| 1926 | assign dff_rdata_w2_m_scanin[11]=dff_rdata_w3_m_scanout[11]; | |
| 1927 | assign dff_rdata_w1_m_scanin[11]=dff_rdata_w2_m_scanout[11]; | |
| 1928 | assign dff_rdata_w0_m_scanin[11]=dff_rdata_w1_m_scanout[11]; | |
| 1929 | assign dff_wdata_m_scanin[76]=dff_rdata_w0_m_scanout[11]; | |
| 1930 | assign dff_wdata_m_scanin[4]=dff_wdata_m_scanout[76]; | |
| 1931 | assign dff_rdata_w3_m_scanin[4]=dff_wdata_m_scanout[4]; | |
| 1932 | assign dff_rdata_w2_m_scanin[4]=dff_rdata_w3_m_scanout[4]; | |
| 1933 | assign dff_rdata_w1_m_scanin[4]=dff_rdata_w2_m_scanout[4]; | |
| 1934 | assign dff_rdata_w0_m_scanin[4]=dff_rdata_w1_m_scanout[4]; | |
| 1935 | assign dff_wdata_m_scanin[85]=dff_rdata_w0_m_scanout[4]; | |
| 1936 | assign dff_wdata_m_scanin[13]=dff_wdata_m_scanout[85]; | |
| 1937 | assign dff_rdata_w3_m_scanin[12]=dff_wdata_m_scanout[13]; | |
| 1938 | assign dff_rdata_w2_m_scanin[12]=dff_rdata_w3_m_scanout[12]; | |
| 1939 | assign dff_rdata_w1_m_scanin[12]=dff_rdata_w2_m_scanout[12]; | |
| 1940 | assign dff_rdata_w0_m_scanin[12]=dff_rdata_w1_m_scanout[12]; | |
| 1941 | assign dff_wdata_m_scanin[77]=dff_rdata_w0_m_scanout[12]; | |
| 1942 | assign dff_wdata_m_scanin[5]=dff_wdata_m_scanout[77]; | |
| 1943 | assign dff_rdata_w3_m_scanin[5]=dff_wdata_m_scanout[5]; | |
| 1944 | assign dff_rdata_w2_m_scanin[5]=dff_rdata_w3_m_scanout[5]; | |
| 1945 | assign dff_rdata_w1_m_scanin[5]=dff_rdata_w2_m_scanout[5]; | |
| 1946 | assign dff_rdata_w0_m_scanin[5]=dff_rdata_w1_m_scanout[5]; | |
| 1947 | assign dff_wdata_m_scanin[86]=dff_rdata_w0_m_scanout[5]; | |
| 1948 | assign dff_wdata_m_scanin[14]=dff_wdata_m_scanout[86]; | |
| 1949 | assign dff_rdata_w3_m_scanin[13]=dff_wdata_m_scanout[14]; | |
| 1950 | assign dff_rdata_w2_m_scanin[13]=dff_rdata_w3_m_scanout[13]; | |
| 1951 | assign dff_rdata_w1_m_scanin[13]=dff_rdata_w2_m_scanout[13]; | |
| 1952 | assign dff_rdata_w0_m_scanin[13]=dff_rdata_w1_m_scanout[13]; | |
| 1953 | assign dff_wdata_m_scanin[78]=dff_rdata_w0_m_scanout[13]; | |
| 1954 | assign dff_wdata_m_scanin[6]=dff_wdata_m_scanout[78]; | |
| 1955 | assign dff_rdata_w3_m_scanin[6]=dff_wdata_m_scanout[6]; | |
| 1956 | assign dff_rdata_w2_m_scanin[6]=dff_rdata_w3_m_scanout[6]; | |
| 1957 | assign dff_rdata_w1_m_scanin[6]=dff_rdata_w2_m_scanout[6]; | |
| 1958 | assign dff_rdata_w0_m_scanin[6]=dff_rdata_w1_m_scanout[6]; | |
| 1959 | assign dff_wdata_m_scanin[87]=dff_rdata_w0_m_scanout[6]; | |
| 1960 | assign dff_wdata_m_scanin[15]=dff_wdata_m_scanout[87]; | |
| 1961 | assign dff_rdata_w3_m_scanin[14]=dff_wdata_m_scanout[15]; | |
| 1962 | assign dff_rdata_w2_m_scanin[14]=dff_rdata_w3_m_scanout[14]; | |
| 1963 | assign dff_rdata_w1_m_scanin[14]=dff_rdata_w2_m_scanout[14]; | |
| 1964 | assign dff_rdata_w0_m_scanin[14]=dff_rdata_w1_m_scanout[14]; | |
| 1965 | assign dff_wdata_m_scanin[79]=dff_rdata_w0_m_scanout[14]; | |
| 1966 | assign dff_wdata_m_scanin[7]=dff_wdata_m_scanout[79]; | |
| 1967 | assign dff_rdata_w3_m_scanin[7]=dff_wdata_m_scanout[7]; | |
| 1968 | assign dff_rdata_w2_m_scanin[7]=dff_rdata_w3_m_scanout[7]; | |
| 1969 | assign dff_rdata_w1_m_scanin[7]=dff_rdata_w2_m_scanout[7]; | |
| 1970 | assign dff_rdata_w0_m_scanin[7]=dff_rdata_w1_m_scanout[7]; | |
| 1971 | assign dff_wdata_m_scanin[88]=dff_rdata_w0_m_scanout[7]; | |
| 1972 | assign dff_wdata_m_scanin[16]=dff_wdata_m_scanout[88]; | |
| 1973 | assign dff_rdata_w3_m_scanin[15]=dff_wdata_m_scanout[16]; | |
| 1974 | assign dff_rdata_w2_m_scanin[15]=dff_rdata_w3_m_scanout[15]; | |
| 1975 | assign dff_rdata_w1_m_scanin[15]=dff_rdata_w2_m_scanout[15]; | |
| 1976 | assign dff_rdata_w0_m_scanin[15]=dff_rdata_w1_m_scanout[15]; | |
| 1977 | assign dff_wdata_m_scanin[98]=dff_rdata_w0_m_scanout[15]; | |
| 1978 | assign dff_wdata_m_scanin[26]=dff_wdata_m_scanout[98]; | |
| 1979 | assign dff_rparity_w3_m_scanin[2]=dff_wdata_m_scanout[26]; | |
| 1980 | assign dff_rparity_w2_m_scanin[2]=dff_rparity_w3_m_scanout[2]; | |
| 1981 | assign dff_rparity_w1_m_scanin[2]=dff_rparity_w2_m_scanout[2]; | |
| 1982 | assign dff_rparity_w0_m_scanin[2]=dff_rparity_w1_m_scanout[2]; | |
| 1983 | assign dff_wdata_m_scanin[107]=dff_rparity_w0_m_scanout[2]; | |
| 1984 | assign dff_wdata_m_scanin[35]=dff_wdata_m_scanout[107]; | |
| 1985 | assign dff_rparity_w3_m_scanin[3]=dff_wdata_m_scanout[35]; | |
| 1986 | assign dff_rparity_w2_m_scanin[3]=dff_rparity_w3_m_scanout[3]; | |
| 1987 | assign dff_rparity_w1_m_scanin[3]=dff_rparity_w2_m_scanout[3]; | |
| 1988 | assign dff_rparity_w0_m_scanin[3]=dff_rparity_w1_m_scanout[3]; | |
| 1989 | assign dff_wdata_m_scanin[90]=dff_rparity_w0_m_scanout[3]; | |
| 1990 | assign dff_wdata_m_scanin[18]=dff_wdata_m_scanout[90]; | |
| 1991 | assign dff_rdata_w3_m_scanin[16]=dff_wdata_m_scanout[18]; | |
| 1992 | assign dff_rdata_w2_m_scanin[16]=dff_rdata_w3_m_scanout[16]; | |
| 1993 | assign dff_rdata_w1_m_scanin[16]=dff_rdata_w2_m_scanout[16]; | |
| 1994 | assign dff_rdata_w0_m_scanin[16]=dff_rdata_w1_m_scanout[16]; | |
| 1995 | assign dff_wdata_m_scanin[99]=dff_rdata_w0_m_scanout[16]; | |
| 1996 | assign dff_wdata_m_scanin[27]=dff_wdata_m_scanout[99]; | |
| 1997 | assign dff_rdata_w3_m_scanin[24]=dff_wdata_m_scanout[27]; | |
| 1998 | assign dff_rdata_w2_m_scanin[24]=dff_rdata_w3_m_scanout[24]; | |
| 1999 | assign dff_rdata_w1_m_scanin[24]=dff_rdata_w2_m_scanout[24]; | |
| 2000 | assign dff_rdata_w0_m_scanin[24]=dff_rdata_w1_m_scanout[24]; | |
| 2001 | assign dff_wdata_m_scanin[91]=dff_rdata_w0_m_scanout[24]; | |
| 2002 | assign dff_wdata_m_scanin[19]=dff_wdata_m_scanout[91]; | |
| 2003 | assign dff_rdata_w3_m_scanin[17]=dff_wdata_m_scanout[19]; | |
| 2004 | assign dff_rdata_w2_m_scanin[17]=dff_rdata_w3_m_scanout[17]; | |
| 2005 | assign dff_rdata_w1_m_scanin[17]=dff_rdata_w2_m_scanout[17]; | |
| 2006 | assign dff_rdata_w0_m_scanin[17]=dff_rdata_w1_m_scanout[17]; | |
| 2007 | assign dff_wdata_m_scanin[100]=dff_rdata_w0_m_scanout[17]; | |
| 2008 | assign dff_wdata_m_scanin[28]=dff_wdata_m_scanout[100]; | |
| 2009 | assign dff_rdata_w3_m_scanin[25]=dff_wdata_m_scanout[28]; | |
| 2010 | assign dff_rdata_w2_m_scanin[25]=dff_rdata_w3_m_scanout[25]; | |
| 2011 | assign dff_rdata_w1_m_scanin[25]=dff_rdata_w2_m_scanout[25]; | |
| 2012 | assign dff_rdata_w0_m_scanin[25]=dff_rdata_w1_m_scanout[25]; | |
| 2013 | assign dff_wdata_m_scanin[92]=dff_rdata_w0_m_scanout[25]; | |
| 2014 | assign dff_wdata_m_scanin[20]=dff_wdata_m_scanout[92]; | |
| 2015 | assign dff_rdata_w3_m_scanin[18]=dff_wdata_m_scanout[20]; | |
| 2016 | assign dff_rdata_w2_m_scanin[18]=dff_rdata_w3_m_scanout[18]; | |
| 2017 | assign dff_rdata_w1_m_scanin[18]=dff_rdata_w2_m_scanout[18]; | |
| 2018 | assign dff_rdata_w0_m_scanin[18]=dff_rdata_w1_m_scanout[18]; | |
| 2019 | assign dff_wdata_m_scanin[101]=dff_rdata_w0_m_scanout[18]; | |
| 2020 | assign dff_wdata_m_scanin[29]=dff_wdata_m_scanout[101]; | |
| 2021 | assign dff_rdata_w3_m_scanin[26]=dff_wdata_m_scanout[29]; | |
| 2022 | assign dff_rdata_w2_m_scanin[26]=dff_rdata_w3_m_scanout[26]; | |
| 2023 | assign dff_rdata_w1_m_scanin[26]=dff_rdata_w2_m_scanout[26]; | |
| 2024 | assign dff_rdata_w0_m_scanin[26]=dff_rdata_w1_m_scanout[26]; | |
| 2025 | assign dff_wdata_m_scanin[93]=dff_rdata_w0_m_scanout[26]; | |
| 2026 | assign dff_wdata_m_scanin[21]=dff_wdata_m_scanout[93]; | |
| 2027 | assign dff_rdata_w3_m_scanin[19]=dff_wdata_m_scanout[21]; | |
| 2028 | assign dff_rdata_w2_m_scanin[19]=dff_rdata_w3_m_scanout[19]; | |
| 2029 | assign dff_rdata_w1_m_scanin[19]=dff_rdata_w2_m_scanout[19]; | |
| 2030 | assign dff_rdata_w0_m_scanin[19]=dff_rdata_w1_m_scanout[19]; | |
| 2031 | assign dff_wdata_m_scanin[102]=dff_rdata_w0_m_scanout[19]; | |
| 2032 | assign dff_wdata_m_scanin[30]=dff_wdata_m_scanout[102]; | |
| 2033 | assign dff_rdata_w3_m_scanin[27]=dff_wdata_m_scanout[30]; | |
| 2034 | assign dff_rdata_w2_m_scanin[27]=dff_rdata_w3_m_scanout[27]; | |
| 2035 | assign dff_rdata_w1_m_scanin[27]=dff_rdata_w2_m_scanout[27]; | |
| 2036 | assign dff_rdata_w0_m_scanin[27]=dff_rdata_w1_m_scanout[27]; | |
| 2037 | assign dff_wdata_m_scanin[94]=dff_rdata_w0_m_scanout[27]; | |
| 2038 | assign dff_wdata_m_scanin[22]=dff_wdata_m_scanout[94]; | |
| 2039 | assign dff_rdata_w3_m_scanin[20]=dff_wdata_m_scanout[22]; | |
| 2040 | assign dff_rdata_w2_m_scanin[20]=dff_rdata_w3_m_scanout[20]; | |
| 2041 | assign dff_rdata_w1_m_scanin[20]=dff_rdata_w2_m_scanout[20]; | |
| 2042 | assign dff_rdata_w0_m_scanin[20]=dff_rdata_w1_m_scanout[20]; | |
| 2043 | assign dff_wdata_m_scanin[103]=dff_rdata_w0_m_scanout[20]; | |
| 2044 | assign dff_wdata_m_scanin[31]=dff_wdata_m_scanout[103]; | |
| 2045 | assign dff_rdata_w3_m_scanin[28]=dff_wdata_m_scanout[31]; | |
| 2046 | assign dff_rdata_w2_m_scanin[28]=dff_rdata_w3_m_scanout[28]; | |
| 2047 | assign dff_rdata_w1_m_scanin[28]=dff_rdata_w2_m_scanout[28]; | |
| 2048 | assign dff_rdata_w0_m_scanin[28]=dff_rdata_w1_m_scanout[28]; | |
| 2049 | assign dff_wdata_m_scanin[95]=dff_rdata_w0_m_scanout[28]; | |
| 2050 | assign dff_wdata_m_scanin[23]=dff_wdata_m_scanout[95]; | |
| 2051 | assign dff_rdata_w3_m_scanin[21]=dff_wdata_m_scanout[23]; | |
| 2052 | assign dff_rdata_w2_m_scanin[21]=dff_rdata_w3_m_scanout[21]; | |
| 2053 | assign dff_rdata_w1_m_scanin[21]=dff_rdata_w2_m_scanout[21]; | |
| 2054 | assign dff_rdata_w0_m_scanin[21]=dff_rdata_w1_m_scanout[21]; | |
| 2055 | assign dff_wdata_m_scanin[104]=dff_rdata_w0_m_scanout[21]; | |
| 2056 | assign dff_wdata_m_scanin[32]=dff_wdata_m_scanout[104]; | |
| 2057 | assign dff_rdata_w3_m_scanin[29]=dff_wdata_m_scanout[32]; | |
| 2058 | assign dff_rdata_w2_m_scanin[29]=dff_rdata_w3_m_scanout[29]; | |
| 2059 | assign dff_rdata_w1_m_scanin[29]=dff_rdata_w2_m_scanout[29]; | |
| 2060 | assign dff_rdata_w0_m_scanin[29]=dff_rdata_w1_m_scanout[29]; | |
| 2061 | assign dff_wdata_m_scanin[96]=dff_rdata_w0_m_scanout[29]; | |
| 2062 | assign dff_wdata_m_scanin[24]=dff_wdata_m_scanout[96]; | |
| 2063 | assign dff_rdata_w3_m_scanin[22]=dff_wdata_m_scanout[24]; | |
| 2064 | assign dff_rdata_w2_m_scanin[22]=dff_rdata_w3_m_scanout[22]; | |
| 2065 | assign dff_rdata_w1_m_scanin[22]=dff_rdata_w2_m_scanout[22]; | |
| 2066 | assign dff_rdata_w0_m_scanin[22]=dff_rdata_w1_m_scanout[22]; | |
| 2067 | assign dff_wdata_m_scanin[105]=dff_rdata_w0_m_scanout[22]; | |
| 2068 | assign dff_wdata_m_scanin[33]=dff_wdata_m_scanout[105]; | |
| 2069 | assign dff_rdata_w3_m_scanin[30]=dff_wdata_m_scanout[33]; | |
| 2070 | assign dff_rdata_w2_m_scanin[30]=dff_rdata_w3_m_scanout[30]; | |
| 2071 | assign dff_rdata_w1_m_scanin[30]=dff_rdata_w2_m_scanout[30]; | |
| 2072 | assign dff_rdata_w0_m_scanin[30]=dff_rdata_w1_m_scanout[30]; | |
| 2073 | assign dff_wdata_m_scanin[97]=dff_rdata_w0_m_scanout[30]; | |
| 2074 | assign dff_wdata_m_scanin[25]=dff_wdata_m_scanout[97]; | |
| 2075 | assign dff_rdata_w3_m_scanin[23]=dff_wdata_m_scanout[25]; | |
| 2076 | assign dff_rdata_w2_m_scanin[23]=dff_rdata_w3_m_scanout[23]; | |
| 2077 | assign dff_rdata_w1_m_scanin[23]=dff_rdata_w2_m_scanout[23]; | |
| 2078 | assign dff_rdata_w0_m_scanin[23]=dff_rdata_w1_m_scanout[23]; | |
| 2079 | assign dff_wdata_m_scanin[106]=dff_rdata_w0_m_scanout[23]; | |
| 2080 | assign dff_wdata_m_scanin[34]=dff_wdata_m_scanout[106]; | |
| 2081 | assign dff_rdata_w3_m_scanin[31]=dff_wdata_m_scanout[34]; | |
| 2082 | assign dff_rdata_w2_m_scanin[31]=dff_rdata_w3_m_scanout[31]; | |
| 2083 | assign dff_rdata_w1_m_scanin[31]=dff_rdata_w2_m_scanout[31]; | |
| 2084 | assign dff_rdata_w0_m_scanin[31]=dff_rdata_w1_m_scanout[31]; | |
| 2085 | assign dff_ctl_m_1_scanin[8]=dff_rdata_w0_m_scanout[31]; | |
| 2086 | assign dff_ctl_m_1_scanin[0]=dff_ctl_m_1_scanout[8]; | |
| 2087 | assign dff_ctl_m_1_scanin[9]=dff_ctl_m_1_scanout[0]; | |
| 2088 | assign dff_ctl_m_1_scanin[1]=dff_ctl_m_1_scanout[9]; | |
| 2089 | assign dff_ctl_m_1_scanin[10]=dff_ctl_m_1_scanout[1]; | |
| 2090 | assign dff_ctl_m_1_scanin[2]=dff_ctl_m_1_scanout[10]; | |
| 2091 | assign dff_ctl_m_1_scanin[11]=dff_ctl_m_1_scanout[2]; | |
| 2092 | assign dff_ctl_m_1_scanin[3]=dff_ctl_m_1_scanout[11]; | |
| 2093 | assign dff_byte_perr_w2_scanin[0]=dff_ctl_m_1_scanout[3]; | |
| 2094 | assign dff_byte_perr_w3_scanin[0]=dff_byte_perr_w2_scanout[0]; | |
| 2095 | assign dff_byte_perr_w3_scanin[1]=dff_byte_perr_w3_scanout[0]; | |
| 2096 | assign dff_byte_perr_w2_scanin[1]=dff_byte_perr_w3_scanout[1]; | |
| 2097 | assign dff_byte_perr_w2_scanin[2]=dff_byte_perr_w2_scanout[1]; | |
| 2098 | assign dff_byte_perr_w3_scanin[2]=dff_byte_perr_w2_scanout[2]; | |
| 2099 | assign dff_byte_perr_w3_scanin[3]=dff_byte_perr_w3_scanout[2]; | |
| 2100 | assign dff_byte_perr_w2_scanin[3]=dff_byte_perr_w3_scanout[3]; | |
| 2101 | assign dff_msb_w3_scanin[7]=dff_byte_perr_w2_scanout[3]; | |
| 2102 | assign dff_msb_w2_scanin[7]=dff_msb_w3_scanout[7]; | |
| 2103 | assign dff_msb_w1_scanin[7]=dff_msb_w2_scanout[7]; | |
| 2104 | assign dff_msb_w0_scanin[7]=dff_msb_w1_scanout[7]; | |
| 2105 | assign dff_msb_w3_scanin[6]=dff_msb_w0_scanout[7]; | |
| 2106 | assign dff_msb_w2_scanin[6]=dff_msb_w3_scanout[6]; | |
| 2107 | assign dff_msb_w1_scanin[6]=dff_msb_w2_scanout[6]; | |
| 2108 | assign dff_msb_w0_scanin[6]=dff_msb_w1_scanout[6]; | |
| 2109 | assign dff_msb_w3_scanin[5]=dff_msb_w0_scanout[6]; | |
| 2110 | assign dff_msb_w2_scanin[5]=dff_msb_w3_scanout[5]; | |
| 2111 | assign dff_msb_w1_scanin[5]=dff_msb_w2_scanout[5]; | |
| 2112 | assign dff_msb_w0_scanin[5]=dff_msb_w1_scanout[5]; | |
| 2113 | assign dff_msb_w3_scanin[4]=dff_msb_w0_scanout[5]; | |
| 2114 | assign dff_msb_w2_scanin[4]=dff_msb_w3_scanout[4]; | |
| 2115 | assign dff_msb_w1_scanin[4]=dff_msb_w2_scanout[4]; | |
| 2116 | assign dff_msb_w0_scanin[4]=dff_msb_w1_scanout[4]; | |
| 2117 | assign dff_msb_w3_scanin[0]=dff_msb_w0_scanout[4]; | |
| 2118 | assign dff_msb_w2_scanin[0]=dff_msb_w3_scanout[0]; | |
| 2119 | assign dff_msb_w1_scanin[0]=dff_msb_w2_scanout[0]; | |
| 2120 | assign dff_msb_w0_scanin[0]=dff_msb_w1_scanout[0]; | |
| 2121 | assign dff_msb_w3_scanin[1]=dff_msb_w0_scanout[0]; | |
| 2122 | assign dff_msb_w2_scanin[1]=dff_msb_w3_scanout[1]; | |
| 2123 | assign dff_msb_w1_scanin[1]=dff_msb_w2_scanout[1]; | |
| 2124 | assign dff_msb_w0_scanin[1]=dff_msb_w1_scanout[1]; | |
| 2125 | assign dff_msb_w3_scanin[2]=dff_msb_w0_scanout[1]; | |
| 2126 | assign dff_msb_w2_scanin[2]=dff_msb_w3_scanout[2]; | |
| 2127 | assign dff_msb_w1_scanin[2]=dff_msb_w2_scanout[2]; | |
| 2128 | assign dff_msb_w0_scanin[2]=dff_msb_w1_scanout[2]; | |
| 2129 | assign dff_msb_w3_scanin[3]=dff_msb_w0_scanout[2]; | |
| 2130 | assign dff_msb_w2_scanin[3]=dff_msb_w3_scanout[3]; | |
| 2131 | assign dff_msb_w1_scanin[3]=dff_msb_w2_scanout[3]; | |
| 2132 | assign dff_msb_w0_scanin[3]=dff_msb_w1_scanout[3]; | |
| 2133 | assign dff_red_out_scanin[2]=dff_msb_w0_scanout[3]; | |
| 2134 | assign dff_red_out_scanin[3]=dff_red_out_scanout[2]; | |
| 2135 | assign dff_red_out_scanin[4]=dff_red_out_scanout[3]; | |
| 2136 | assign dff_red_out_scanin[5]=dff_red_out_scanout[4]; | |
| 2137 | assign dff_red_out_scanin[6]=dff_red_out_scanout[5]; | |
| 2138 | assign dff_red_out_scanin[7]=dff_red_out_scanout[6]; | |
| 2139 | assign dff_red_out_scanin[0]=dff_red_out_scanout[7]; | |
| 2140 | assign dff_red_out_scanin[1]=dff_red_out_scanout[0]; | |
| 2141 | assign dff_red_in_scanin[2]=dff_red_out_scanout[1]; | |
| 2142 | assign dff_red_in_scanin[3]=dff_red_in_scanout[2]; | |
| 2143 | assign dff_red_in_scanin[1]=dff_red_in_scanout[3]; | |
| 2144 | assign dff_red_in_scanin[0]=dff_red_in_scanout[1]; | |
| 2145 | assign dff_red_in_scanin[6]=dff_red_in_scanout[0]; | |
| 2146 | assign dff_red_in_scanin[7]=dff_red_in_scanout[6]; | |
| 2147 | assign dff_red_in_scanin[8]=dff_red_in_scanout[7]; | |
| 2148 | assign dff_red_in_scanin[9]=dff_red_in_scanout[8]; | |
| 2149 | assign dff_red_in_scanin[10]=dff_red_in_scanout[9]; | |
| 2150 | assign dff_red_in_scanin[11]=dff_red_in_scanout[10]; | |
| 2151 | assign dff_red_in_scanin[4]=dff_red_in_scanout[11]; | |
| 2152 | assign dff_red_in_scanin[5]=dff_red_in_scanout[4]; | |
| 2153 | assign scan_out=dff_red_in_scanout[5]; | |
| 2154 | // fixscan end | |
| 2155 | ||
| 2156 | // synopsys translate_on | |
| 2157 | ||
| 2158 | endmodule | |
| 2159 | ||
| 2160 | ||
| 2161 | ||
| 2162 | ||
| 2163 | ||
| 2164 | ||
| 2165 | ||
| 2166 | ||
| 2167 | // any PARAMS parms go into naming of macro | |
| 2168 | ||
| 2169 | module n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro ( | |
| 2170 | l2clk, | |
| 2171 | l1en, | |
| 2172 | pce_ov, | |
| 2173 | stop, | |
| 2174 | se, | |
| 2175 | l1clk); | |
| 2176 | ||
| 2177 | ||
| 2178 | input l2clk; | |
| 2179 | input l1en; | |
| 2180 | input pce_ov; | |
| 2181 | input stop; | |
| 2182 | input se; | |
| 2183 | output l1clk; | |
| 2184 | ||
| 2185 | ||
| 2186 | ||
| 2187 | ||
| 2188 | ||
| 2189 | cl_sc1_l1hdr_8x c_0 ( | |
| 2190 | ||
| 2191 | ||
| 2192 | .l2clk(l2clk), | |
| 2193 | .pce(l1en), | |
| 2194 | .l1clk(l1clk), | |
| 2195 | .se(se), | |
| 2196 | .pce_ov(pce_ov), | |
| 2197 | .stop(stop) | |
| 2198 | ); | |
| 2199 | ||
| 2200 | ||
| 2201 | ||
| 2202 | endmodule | |
| 2203 | ||
| 2204 | ||
| 2205 | ||
| 2206 | ||
| 2207 | ||
| 2208 | ||
| 2209 | ||
| 2210 | ||
| 2211 | ||
| 2212 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 2213 | // also for pass-gate with decoder | |
| 2214 | ||
| 2215 | ||
| 2216 | ||
| 2217 | ||
| 2218 | ||
| 2219 | // any PARAMS parms go into naming of macro | |
| 2220 | ||
| 2221 | module n2_dca_sp_9kb_cust_mux_macro__mux_aope__ports_2__width_8 ( | |
| 2222 | din0, | |
| 2223 | din1, | |
| 2224 | sel0, | |
| 2225 | dout); | |
| 2226 | wire psel0; | |
| 2227 | wire psel1; | |
| 2228 | ||
| 2229 | input [7:0] din0; | |
| 2230 | input [7:0] din1; | |
| 2231 | input sel0; | |
| 2232 | output [7:0] dout; | |
| 2233 | ||
| 2234 | ||
| 2235 | ||
| 2236 | ||
| 2237 | ||
| 2238 | cl_dp1_penc2_8x c0_0 ( | |
| 2239 | .sel0(sel0), | |
| 2240 | .psel0(psel0), | |
| 2241 | .psel1(psel1) | |
| 2242 | ); | |
| 2243 | ||
| 2244 | mux2s #(8) d0_0 ( | |
| 2245 | .sel0(psel0), | |
| 2246 | .sel1(psel1), | |
| 2247 | .in0(din0[7:0]), | |
| 2248 | .in1(din1[7:0]), | |
| 2249 | .dout(dout[7:0]) | |
| 2250 | ); | |
| 2251 | ||
| 2252 | ||
| 2253 | ||
| 2254 | ||
| 2255 | ||
| 2256 | ||
| 2257 | ||
| 2258 | ||
| 2259 | ||
| 2260 | ||
| 2261 | ||
| 2262 | ||
| 2263 | ||
| 2264 | endmodule | |
| 2265 | ||
| 2266 | ||
| 2267 | // | |
| 2268 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
| 2269 | // | |
| 2270 | // | |
| 2271 | ||
| 2272 | ||
| 2273 | ||
| 2274 | ||
| 2275 | ||
| 2276 | module n2_dca_sp_9kb_cust_tisram_msff_macro__fs_1__width_8 ( | |
| 2277 | d, | |
| 2278 | scan_in, | |
| 2279 | l1clk, | |
| 2280 | siclk, | |
| 2281 | soclk, | |
| 2282 | scan_out, | |
| 2283 | latout, | |
| 2284 | latout_l); | |
| 2285 | input [7:0] d; | |
| 2286 | input [7:0] scan_in; | |
| 2287 | input l1clk; | |
| 2288 | input siclk; | |
| 2289 | input soclk; | |
| 2290 | output [7:0] scan_out; | |
| 2291 | output [7:0] latout; | |
| 2292 | output [7:0] latout_l; | |
| 2293 | ||
| 2294 | ||
| 2295 | ||
| 2296 | ||
| 2297 | ||
| 2298 | ||
| 2299 | tisram_msff #(8) d0_0 ( | |
| 2300 | .d(d[7:0]), | |
| 2301 | .si(scan_in[7:0]), | |
| 2302 | .so(scan_out[7:0]), | |
| 2303 | .l1clk(l1clk), | |
| 2304 | .siclk(siclk), | |
| 2305 | .soclk(soclk), | |
| 2306 | .latout(latout[7:0]), | |
| 2307 | .latout_l(latout_l[7:0]) | |
| 2308 | ); | |
| 2309 | ||
| 2310 | ||
| 2311 | ||
| 2312 | ||
| 2313 | ||
| 2314 | ||
| 2315 | ||
| 2316 | ||
| 2317 | ||
| 2318 | ||
| 2319 | ||
| 2320 | ||
| 2321 | //place::generic_place($width,$stack,$left); | |
| 2322 | ||
| 2323 | endmodule | |
| 2324 | ||
| 2325 | ||
| 2326 | ||
| 2327 | ||
| 2328 | ||
| 2329 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 2330 | // also for pass-gate with decoder | |
| 2331 | ||
| 2332 | ||
| 2333 | ||
| 2334 | ||
| 2335 | ||
| 2336 | // any PARAMS parms go into naming of macro | |
| 2337 | ||
| 2338 | module n2_dca_sp_9kb_cust_mux_macro__mux_aodec__ports_4__width_4 ( | |
| 2339 | din0, | |
| 2340 | din1, | |
| 2341 | din2, | |
| 2342 | din3, | |
| 2343 | sel, | |
| 2344 | dout); | |
| 2345 | wire psel0; | |
| 2346 | wire psel1; | |
| 2347 | wire psel2; | |
| 2348 | wire psel3; | |
| 2349 | ||
| 2350 | input [3:0] din0; | |
| 2351 | input [3:0] din1; | |
| 2352 | input [3:0] din2; | |
| 2353 | input [3:0] din3; | |
| 2354 | input [1:0] sel; | |
| 2355 | output [3:0] dout; | |
| 2356 | ||
| 2357 | ||
| 2358 | ||
| 2359 | ||
| 2360 | ||
| 2361 | cl_dp1_pdec4_8x c0_0 ( | |
| 2362 | .test(1'b1), | |
| 2363 | .sel0(sel[0]), | |
| 2364 | .sel1(sel[1]), | |
| 2365 | .psel0(psel0), | |
| 2366 | .psel1(psel1), | |
| 2367 | .psel2(psel2), | |
| 2368 | .psel3(psel3) | |
| 2369 | ); | |
| 2370 | ||
| 2371 | mux4s #(4) d0_0 ( | |
| 2372 | .sel0(psel0), | |
| 2373 | .sel1(psel1), | |
| 2374 | .sel2(psel2), | |
| 2375 | .sel3(psel3), | |
| 2376 | .in0(din0[3:0]), | |
| 2377 | .in1(din1[3:0]), | |
| 2378 | .in2(din2[3:0]), | |
| 2379 | .in3(din3[3:0]), | |
| 2380 | .dout(dout[3:0]) | |
| 2381 | ); | |
| 2382 | ||
| 2383 | ||
| 2384 | ||
| 2385 | ||
| 2386 | ||
| 2387 | ||
| 2388 | ||
| 2389 | ||
| 2390 | ||
| 2391 | ||
| 2392 | ||
| 2393 | ||
| 2394 | ||
| 2395 | endmodule | |
| 2396 | ||
| 2397 | ||
| 2398 | // | |
| 2399 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
| 2400 | // | |
| 2401 | // | |
| 2402 | ||
| 2403 | ||
| 2404 | ||
| 2405 | ||
| 2406 | ||
| 2407 | module n2_dca_sp_9kb_cust_tisram_msff_macro__fs_1__width_7 ( | |
| 2408 | d, | |
| 2409 | scan_in, | |
| 2410 | l1clk, | |
| 2411 | siclk, | |
| 2412 | soclk, | |
| 2413 | scan_out, | |
| 2414 | latout, | |
| 2415 | latout_l); | |
| 2416 | input [6:0] d; | |
| 2417 | input [6:0] scan_in; | |
| 2418 | input l1clk; | |
| 2419 | input siclk; | |
| 2420 | input soclk; | |
| 2421 | output [6:0] scan_out; | |
| 2422 | output [6:0] latout; | |
| 2423 | output [6:0] latout_l; | |
| 2424 | ||
| 2425 | ||
| 2426 | ||
| 2427 | ||
| 2428 | ||
| 2429 | ||
| 2430 | tisram_msff #(7) d0_0 ( | |
| 2431 | .d(d[6:0]), | |
| 2432 | .si(scan_in[6:0]), | |
| 2433 | .so(scan_out[6:0]), | |
| 2434 | .l1clk(l1clk), | |
| 2435 | .siclk(siclk), | |
| 2436 | .soclk(soclk), | |
| 2437 | .latout(latout[6:0]), | |
| 2438 | .latout_l(latout_l[6:0]) | |
| 2439 | ); | |
| 2440 | ||
| 2441 | ||
| 2442 | ||
| 2443 | ||
| 2444 | ||
| 2445 | ||
| 2446 | ||
| 2447 | ||
| 2448 | ||
| 2449 | ||
| 2450 | ||
| 2451 | ||
| 2452 | //place::generic_place($width,$stack,$left); | |
| 2453 | ||
| 2454 | endmodule | |
| 2455 | ||
| 2456 | ||
| 2457 | ||
| 2458 | ||
| 2459 | ||
| 2460 | ||
| 2461 | ||
| 2462 | ||
| 2463 | ||
| 2464 | // any PARAMS parms go into naming of macro | |
| 2465 | ||
| 2466 | module n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_3 ( | |
| 2467 | din, | |
| 2468 | l1clk, | |
| 2469 | scan_in, | |
| 2470 | siclk, | |
| 2471 | soclk, | |
| 2472 | dout, | |
| 2473 | scan_out); | |
| 2474 | wire [2:0] fdin; | |
| 2475 | ||
| 2476 | input [2:0] din; | |
| 2477 | input l1clk; | |
| 2478 | input [2:0] scan_in; | |
| 2479 | ||
| 2480 | ||
| 2481 | input siclk; | |
| 2482 | input soclk; | |
| 2483 | ||
| 2484 | output [2:0] dout; | |
| 2485 | output [2:0] scan_out; | |
| 2486 | assign fdin[2:0] = din[2:0]; | |
| 2487 | ||
| 2488 | ||
| 2489 | ||
| 2490 | ||
| 2491 | ||
| 2492 | ||
| 2493 | dff #(3) d0_0 ( | |
| 2494 | .l1clk(l1clk), | |
| 2495 | .siclk(siclk), | |
| 2496 | .soclk(soclk), | |
| 2497 | .d(fdin[2:0]), | |
| 2498 | .si(scan_in[2:0]), | |
| 2499 | .so(scan_out[2:0]), | |
| 2500 | .q(dout[2:0]) | |
| 2501 | ); | |
| 2502 | ||
| 2503 | ||
| 2504 | ||
| 2505 | ||
| 2506 | ||
| 2507 | ||
| 2508 | ||
| 2509 | ||
| 2510 | ||
| 2511 | ||
| 2512 | ||
| 2513 | ||
| 2514 | endmodule | |
| 2515 | ||
| 2516 | ||
| 2517 | ||
| 2518 | ||
| 2519 | ||
| 2520 | ||
| 2521 | ||
| 2522 | ||
| 2523 | ||
| 2524 | // | |
| 2525 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
| 2526 | // | |
| 2527 | // | |
| 2528 | ||
| 2529 | ||
| 2530 | ||
| 2531 | ||
| 2532 | ||
| 2533 | module n2_dca_sp_9kb_cust_tisram_msff_macro__fs_1__width_16 ( | |
| 2534 | d, | |
| 2535 | scan_in, | |
| 2536 | l1clk, | |
| 2537 | siclk, | |
| 2538 | soclk, | |
| 2539 | scan_out, | |
| 2540 | latout, | |
| 2541 | latout_l); | |
| 2542 | input [15:0] d; | |
| 2543 | input [15:0] scan_in; | |
| 2544 | input l1clk; | |
| 2545 | input siclk; | |
| 2546 | input soclk; | |
| 2547 | output [15:0] scan_out; | |
| 2548 | output [15:0] latout; | |
| 2549 | output [15:0] latout_l; | |
| 2550 | ||
| 2551 | ||
| 2552 | ||
| 2553 | ||
| 2554 | ||
| 2555 | ||
| 2556 | tisram_msff #(16) d0_0 ( | |
| 2557 | .d(d[15:0]), | |
| 2558 | .si(scan_in[15:0]), | |
| 2559 | .so(scan_out[15:0]), | |
| 2560 | .l1clk(l1clk), | |
| 2561 | .siclk(siclk), | |
| 2562 | .soclk(soclk), | |
| 2563 | .latout(latout[15:0]), | |
| 2564 | .latout_l(latout_l[15:0]) | |
| 2565 | ); | |
| 2566 | ||
| 2567 | ||
| 2568 | ||
| 2569 | ||
| 2570 | ||
| 2571 | ||
| 2572 | ||
| 2573 | ||
| 2574 | ||
| 2575 | ||
| 2576 | ||
| 2577 | ||
| 2578 | //place::generic_place($width,$stack,$left); | |
| 2579 | ||
| 2580 | endmodule | |
| 2581 | ||
| 2582 | ||
| 2583 | ||
| 2584 | ||
| 2585 | ||
| 2586 | ||
| 2587 | ||
| 2588 | ||
| 2589 | ||
| 2590 | // any PARAMS parms go into naming of macro | |
| 2591 | ||
| 2592 | module n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_5 ( | |
| 2593 | din, | |
| 2594 | l1clk, | |
| 2595 | scan_in, | |
| 2596 | siclk, | |
| 2597 | soclk, | |
| 2598 | dout, | |
| 2599 | scan_out); | |
| 2600 | wire [4:0] fdin; | |
| 2601 | ||
| 2602 | input [4:0] din; | |
| 2603 | input l1clk; | |
| 2604 | input [4:0] scan_in; | |
| 2605 | ||
| 2606 | ||
| 2607 | input siclk; | |
| 2608 | input soclk; | |
| 2609 | ||
| 2610 | output [4:0] dout; | |
| 2611 | output [4:0] scan_out; | |
| 2612 | assign fdin[4:0] = din[4:0]; | |
| 2613 | ||
| 2614 | ||
| 2615 | ||
| 2616 | ||
| 2617 | ||
| 2618 | ||
| 2619 | dff #(5) d0_0 ( | |
| 2620 | .l1clk(l1clk), | |
| 2621 | .siclk(siclk), | |
| 2622 | .soclk(soclk), | |
| 2623 | .d(fdin[4:0]), | |
| 2624 | .si(scan_in[4:0]), | |
| 2625 | .so(scan_out[4:0]), | |
| 2626 | .q(dout[4:0]) | |
| 2627 | ); | |
| 2628 | ||
| 2629 | ||
| 2630 | ||
| 2631 | ||
| 2632 | ||
| 2633 | ||
| 2634 | ||
| 2635 | ||
| 2636 | ||
| 2637 | ||
| 2638 | ||
| 2639 | ||
| 2640 | endmodule | |
| 2641 | ||
| 2642 | ||
| 2643 | ||
| 2644 | ||
| 2645 | ||
| 2646 | ||
| 2647 | ||
| 2648 | ||
| 2649 | ||
| 2650 | ||
| 2651 | ||
| 2652 | ||
| 2653 | ||
| 2654 | // any PARAMS parms go into naming of macro | |
| 2655 | ||
| 2656 | module n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_144 ( | |
| 2657 | din, | |
| 2658 | l1clk, | |
| 2659 | scan_in, | |
| 2660 | siclk, | |
| 2661 | soclk, | |
| 2662 | dout, | |
| 2663 | scan_out); | |
| 2664 | wire [143:0] fdin; | |
| 2665 | ||
| 2666 | input [143:0] din; | |
| 2667 | input l1clk; | |
| 2668 | input [143:0] scan_in; | |
| 2669 | ||
| 2670 | ||
| 2671 | input siclk; | |
| 2672 | input soclk; | |
| 2673 | ||
| 2674 | output [143:0] dout; | |
| 2675 | output [143:0] scan_out; | |
| 2676 | assign fdin[143:0] = din[143:0]; | |
| 2677 | ||
| 2678 | ||
| 2679 | ||
| 2680 | ||
| 2681 | ||
| 2682 | ||
| 2683 | dff #(144) d0_0 ( | |
| 2684 | .l1clk(l1clk), | |
| 2685 | .siclk(siclk), | |
| 2686 | .soclk(soclk), | |
| 2687 | .d(fdin[143:0]), | |
| 2688 | .si(scan_in[143:0]), | |
| 2689 | .so(scan_out[143:0]), | |
| 2690 | .q(dout[143:0]) | |
| 2691 | ); | |
| 2692 | ||
| 2693 | ||
| 2694 | ||
| 2695 | ||
| 2696 | ||
| 2697 | ||
| 2698 | ||
| 2699 | ||
| 2700 | ||
| 2701 | ||
| 2702 | ||
| 2703 | ||
| 2704 | endmodule | |
| 2705 | ||
| 2706 | ||
| 2707 | ||
| 2708 | ||
| 2709 | ||
| 2710 | ||
| 2711 | ||
| 2712 | ||
| 2713 | module n2_dca_sp_9kb_array ( | |
| 2714 | l1clk, | |
| 2715 | l1clk_wr, | |
| 2716 | l1clk_red, | |
| 2717 | rd_en_top_b, | |
| 2718 | rd_en_bot_b, | |
| 2719 | rd_en_a, | |
| 2720 | wr_en_a, | |
| 2721 | wr_en_b, | |
| 2722 | wr_inh_b, | |
| 2723 | addr_b, | |
| 2724 | byte_wr_en_b, | |
| 2725 | wr_waysel_b, | |
| 2726 | dcache_wdata_m, | |
| 2727 | dcache_wparity_m, | |
| 2728 | dcache_rdata_w0_m, | |
| 2729 | rparity_w0_m, | |
| 2730 | dcache_rdata_w1_m, | |
| 2731 | rparity_w1_m, | |
| 2732 | dcache_rdata_w2_m, | |
| 2733 | rparity_w2_m, | |
| 2734 | dcache_rdata_w3_m, | |
| 2735 | rparity_w3_m, | |
| 2736 | fuse_dca_repair_value, | |
| 2737 | fuse_dca_repair_en, | |
| 2738 | fuse_dca_rid, | |
| 2739 | fuse_dca_wen, | |
| 2740 | fuse_red_reset, | |
| 2741 | dca_fuse_repair_value, | |
| 2742 | dca_fuse_repair_en, | |
| 2743 | vnw_ary); | |
| 2744 | wire fuse_red_reset_qual; | |
| 2745 | wire fuse_dca_wen_qual; | |
| 2746 | wire [3:0] red_id; | |
| 2747 | wire [3:0] red_reg_clk_; | |
| 2748 | wire [5:0] red_data; | |
| 2749 | wire [1:0] red_enable; | |
| 2750 | wire [8:0] w0_byte7_l_unused; | |
| 2751 | wire [8:0] w0_byte6_l_unused; | |
| 2752 | wire [8:0] w0_byte5_l_unused; | |
| 2753 | wire [8:0] w0_byte4_l_unused; | |
| 2754 | wire [8:0] w0_byte3_l_unused; | |
| 2755 | wire [8:0] w0_byte2_l_unused; | |
| 2756 | wire [8:0] w0_byte1_l_unused; | |
| 2757 | wire [8:0] w0_byte0_l_unused; | |
| 2758 | wire [8:0] w1_byte7_l_unused; | |
| 2759 | wire [8:0] w1_byte6_l_unused; | |
| 2760 | wire [8:0] w1_byte5_l_unused; | |
| 2761 | wire [8:0] w1_byte4_l_unused; | |
| 2762 | wire [8:0] w1_byte3_l_unused; | |
| 2763 | wire [8:0] w1_byte2_l_unused; | |
| 2764 | wire [8:0] w1_byte1_l_unused; | |
| 2765 | wire [8:0] w1_byte0_l_unused; | |
| 2766 | wire [8:0] w2_byte7_l_unused; | |
| 2767 | wire [8:0] w2_byte6_l_unused; | |
| 2768 | wire [8:0] w2_byte5_l_unused; | |
| 2769 | wire [8:0] w2_byte4_l_unused; | |
| 2770 | wire [8:0] w2_byte3_l_unused; | |
| 2771 | wire [8:0] w2_byte2_l_unused; | |
| 2772 | wire [8:0] w2_byte1_l_unused; | |
| 2773 | wire [8:0] w2_byte0_l_unused; | |
| 2774 | wire [8:0] w3_byte7_l_unused; | |
| 2775 | wire [8:0] w3_byte6_l_unused; | |
| 2776 | wire [8:0] w3_byte5_l_unused; | |
| 2777 | wire [8:0] w3_byte4_l_unused; | |
| 2778 | wire [8:0] w3_byte3_l_unused; | |
| 2779 | wire [8:0] w3_byte2_l_unused; | |
| 2780 | wire [8:0] w3_byte1_l_unused; | |
| 2781 | wire [8:0] w3_byte0_l_unused; | |
| 2782 | ||
| 2783 | ||
| 2784 | input l1clk; // l1clk from l1clk_header | |
| 2785 | input l1clk_wr; | |
| 2786 | input l1clk_red; | |
| 2787 | input rd_en_top_b; // e_cycle b_phase signal | |
| 2788 | input rd_en_bot_b; // e_cycle b_phase signal | |
| 2789 | input rd_en_a; // m_cycle a_phase signal | |
| 2790 | input wr_en_a; // m_cycle a_phase signal | |
| 2791 | input wr_en_b; // e_cycle b_phase signal | |
| 2792 | input wr_inh_b; // e_cycle b_phase signal | |
| 2793 | input [10:3] addr_b; // e_cycle b_phase signal | |
| 2794 | input [15:0] byte_wr_en_b; // e_cycle b_phase signal | |
| 2795 | input [3:0] wr_waysel_b; // e_cycle b_phase signal | |
| 2796 | ||
| 2797 | input [127:0] dcache_wdata_m; | |
| 2798 | input [15:0] dcache_wparity_m; | |
| 2799 | ||
| 2800 | output [63:0] dcache_rdata_w0_m; | |
| 2801 | output [7:0] rparity_w0_m; | |
| 2802 | output [63:0] dcache_rdata_w1_m; | |
| 2803 | output [7:0] rparity_w1_m; | |
| 2804 | output [63:0] dcache_rdata_w2_m; | |
| 2805 | output [7:0] rparity_w2_m; | |
| 2806 | output [63:0] dcache_rdata_w3_m; | |
| 2807 | output [7:0] rparity_w3_m; | |
| 2808 | ||
| 2809 | input [5:0] fuse_dca_repair_value; | |
| 2810 | input [1:0] fuse_dca_repair_en; | |
| 2811 | input [1:0] fuse_dca_rid; | |
| 2812 | input fuse_dca_wen; | |
| 2813 | input fuse_red_reset; | |
| 2814 | output [5:0] dca_fuse_repair_value; | |
| 2815 | output [1:0] dca_fuse_repair_en; | |
| 2816 | ||
| 2817 | input vnw_ary; | |
| 2818 | ||
| 2819 | /////////////////////////////////////////// | |
| 2820 | // Redundancy register logic | |
| 2821 | /////////////////////////////////////////// | |
| 2822 | ||
| 2823 | // Clock and data enables | |
| 2824 | ||
| 2825 | assign fuse_red_reset_qual = fuse_red_reset & ~wr_inh_b; | |
| 2826 | assign fuse_dca_wen_qual = fuse_dca_wen & ~wr_inh_b; | |
| 2827 | ||
| 2828 | assign red_id[0] = ~fuse_dca_rid[1] & ~fuse_dca_rid[0]; | |
| 2829 | assign red_id[1] = ~fuse_dca_rid[1] & fuse_dca_rid[0]; | |
| 2830 | assign red_id[2] = fuse_dca_rid[1] & ~fuse_dca_rid[0]; | |
| 2831 | assign red_id[3] = fuse_dca_rid[1] & fuse_dca_rid[0]; | |
| 2832 | ||
| 2833 | assign red_reg_clk_[0] = ~(~l1clk_red & ((red_id[0] & fuse_dca_wen_qual) | fuse_red_reset_qual)); | |
| 2834 | assign red_reg_clk_[1] = ~(~l1clk_red & ((red_id[1] & fuse_dca_wen_qual) | fuse_red_reset_qual)); | |
| 2835 | assign red_reg_clk_[2] = ~(~l1clk_red & ((red_id[2] & fuse_dca_wen_qual) | fuse_red_reset_qual)); | |
| 2836 | assign red_reg_clk_[3] = ~(~l1clk_red & ((red_id[3] & fuse_dca_wen_qual) | fuse_red_reset_qual)); | |
| 2837 | ||
| 2838 | assign red_data[5:0] = fuse_dca_repair_value[5:0] & {6{~fuse_red_reset_qual}}; | |
| 2839 | assign red_enable[1:0] = fuse_dca_repair_en[1:0] & {2{~fuse_red_reset_qual}}; | |
| 2840 | ||
| 2841 | // 4 set of 8 registers. | |
| 2842 | // register is a simple b_latch. active when clk is low. | |
| 2843 | ||
| 2844 | reg [5:0] red_reg_d_bl; | |
| 2845 | reg [5:0] red_reg_d_br; | |
| 2846 | reg [5:0] red_reg_d_tl; | |
| 2847 | reg [5:0] red_reg_d_tr; | |
| 2848 | reg [1:0] red_reg_en_bl; | |
| 2849 | reg [1:0] red_reg_en_br; | |
| 2850 | reg [1:0] red_reg_en_tl; | |
| 2851 | reg [1:0] red_reg_en_tr; | |
| 2852 | ||
| 2853 | `ifndef NOINITMEM | |
| 2854 | // Initialize the arrays. | |
| 2855 | initial begin | |
| 2856 | red_reg_d_bl[5:0] = 6'd0; | |
| 2857 | red_reg_en_bl[1:0] = 2'd0; | |
| 2858 | red_reg_d_br[5:0] = 6'd0; | |
| 2859 | red_reg_en_br[1:0] = 2'd0; | |
| 2860 | red_reg_d_tl[5:0] = 6'd0; | |
| 2861 | red_reg_en_tl[1:0] = 2'd0; | |
| 2862 | red_reg_d_tr[5:0] = 6'd0; | |
| 2863 | red_reg_en_tr[1:0] = 2'd0; | |
| 2864 | end | |
| 2865 | `endif | |
| 2866 | ||
| 2867 | always @(red_reg_clk_ or red_data or red_enable) begin | |
| 2868 | if (~red_reg_clk_[0]) begin | |
| 2869 | red_reg_d_bl[5:0] = red_data[5:0]; | |
| 2870 | red_reg_en_bl[1:0] = red_enable[1:0]; | |
| 2871 | end | |
| 2872 | if (~red_reg_clk_[1]) begin | |
| 2873 | red_reg_d_br[5:0] = red_data[5:0]; | |
| 2874 | red_reg_en_br[1:0] = red_enable[1:0]; | |
| 2875 | end | |
| 2876 | if (~red_reg_clk_[2]) begin | |
| 2877 | red_reg_d_tl[5:0] = red_data[5:0]; | |
| 2878 | red_reg_en_tl[1:0] = red_enable[1:0]; | |
| 2879 | end | |
| 2880 | if (~red_reg_clk_[3]) begin | |
| 2881 | red_reg_d_tr[5:0] = red_data[5:0]; | |
| 2882 | red_reg_en_tr[1:0] = red_enable[1:0]; | |
| 2883 | end | |
| 2884 | end | |
| 2885 | ||
| 2886 | // output muxing | |
| 2887 | assign dca_fuse_repair_value[5:0] = (red_reg_d_tr[5:0] & {6{red_id[3]}}) | | |
| 2888 | (red_reg_d_tl[5:0] & {6{red_id[2]}}) | | |
| 2889 | (red_reg_d_br[5:0] & {6{red_id[1]}}) | | |
| 2890 | (red_reg_d_bl[5:0] & {6{red_id[0]}}); | |
| 2891 | ||
| 2892 | assign dca_fuse_repair_en[1:0] = (red_reg_en_tr[1:0] & {2{red_id[3]}}) | | |
| 2893 | (red_reg_en_tl[1:0] & {2{red_id[2]}}) | | |
| 2894 | (red_reg_en_br[1:0] & {2{red_id[1]}}) | | |
| 2895 | (red_reg_en_bl[1:0] & {2{red_id[0]}}) ; | |
| 2896 | ||
| 2897 | // The two subarrays | |
| 2898 | ||
| 2899 | n2_dca_sp_9kb_bank way01 ( | |
| 2900 | .red_data_l (red_reg_d_tl[5:0]), | |
| 2901 | .red_enable_l (red_reg_en_tl[1:0]), | |
| 2902 | .red_data_r (red_reg_d_tr[5:0]), | |
| 2903 | .red_enable_r (red_reg_en_tr[1:0]), | |
| 2904 | .rd_en_b (rd_en_top_b), | |
| 2905 | .wr_waysel_b (wr_waysel_b[1:0]), | |
| 2906 | .wrd_byte15_a ({dcache_wparity_m[15],dcache_wdata_m[127:120]}), | |
| 2907 | .wrd_byte14_a ({dcache_wparity_m[14],dcache_wdata_m[119:112]}), | |
| 2908 | .wrd_byte13_a ({dcache_wparity_m[13],dcache_wdata_m[111:104]}), | |
| 2909 | .wrd_byte12_a ({dcache_wparity_m[12],dcache_wdata_m[103:96]}), | |
| 2910 | .wrd_byte11_a ({dcache_wparity_m[11],dcache_wdata_m[95:88]}), | |
| 2911 | .wrd_byte10_a ({dcache_wparity_m[10],dcache_wdata_m[87:80]}), | |
| 2912 | .wrd_byte9_a ({dcache_wparity_m[9],dcache_wdata_m[79:72]}), | |
| 2913 | .wrd_byte8_a ({dcache_wparity_m[8],dcache_wdata_m[71:64]}), | |
| 2914 | .wrd_byte7_a ({dcache_wparity_m[7],dcache_wdata_m[63:56]}), | |
| 2915 | .wrd_byte6_a ({dcache_wparity_m[6],dcache_wdata_m[55:48]}), | |
| 2916 | .wrd_byte5_a ({dcache_wparity_m[5],dcache_wdata_m[47:40]}), | |
| 2917 | .wrd_byte4_a ({dcache_wparity_m[4],dcache_wdata_m[39:32]}), | |
| 2918 | .wrd_byte3_a ({dcache_wparity_m[3],dcache_wdata_m[31:24]}), | |
| 2919 | .wrd_byte2_a ({dcache_wparity_m[2],dcache_wdata_m[23:16]}), | |
| 2920 | .wrd_byte1_a ({dcache_wparity_m[1],dcache_wdata_m[15:8]}), | |
| 2921 | .wrd_byte0_a ({dcache_wparity_m[0],dcache_wdata_m[7:0]}), | |
| 2922 | .w0_byte7_h ({rparity_w0_m[7],dcache_rdata_w0_m[63:56]}), | |
| 2923 | .w0_byte6_h ({rparity_w0_m[6],dcache_rdata_w0_m[55:48]}), | |
| 2924 | .w0_byte5_h ({rparity_w0_m[5],dcache_rdata_w0_m[47:40]}), | |
| 2925 | .w0_byte4_h ({rparity_w0_m[4],dcache_rdata_w0_m[39:32]}), | |
| 2926 | .w0_byte3_h ({rparity_w0_m[3],dcache_rdata_w0_m[31:24]}), | |
| 2927 | .w0_byte2_h ({rparity_w0_m[2],dcache_rdata_w0_m[23:16]}), | |
| 2928 | .w0_byte1_h ({rparity_w0_m[1],dcache_rdata_w0_m[15:8]}), | |
| 2929 | .w0_byte0_h ({rparity_w0_m[0],dcache_rdata_w0_m[7:0]}), | |
| 2930 | .w1_byte7_h ({rparity_w1_m[7],dcache_rdata_w1_m[63:56]}), | |
| 2931 | .w1_byte6_h ({rparity_w1_m[6],dcache_rdata_w1_m[55:48]}), | |
| 2932 | .w1_byte5_h ({rparity_w1_m[5],dcache_rdata_w1_m[47:40]}), | |
| 2933 | .w1_byte4_h ({rparity_w1_m[4],dcache_rdata_w1_m[39:32]}), | |
| 2934 | .w1_byte3_h ({rparity_w1_m[3],dcache_rdata_w1_m[31:24]}), | |
| 2935 | .w1_byte2_h ({rparity_w1_m[2],dcache_rdata_w1_m[23:16]}), | |
| 2936 | .w1_byte1_h ({rparity_w1_m[1],dcache_rdata_w1_m[15:8]}), | |
| 2937 | .w1_byte0_h ({rparity_w1_m[0],dcache_rdata_w1_m[7:0]}), | |
| 2938 | .w0_byte7_l (w0_byte7_l_unused[8:0]), | |
| 2939 | .w0_byte6_l (w0_byte6_l_unused[8:0]), | |
| 2940 | .w0_byte5_l (w0_byte5_l_unused[8:0]), | |
| 2941 | .w0_byte4_l (w0_byte4_l_unused[8:0]), | |
| 2942 | .w0_byte3_l (w0_byte3_l_unused[8:0]), | |
| 2943 | .w0_byte2_l (w0_byte2_l_unused[8:0]), | |
| 2944 | .w0_byte1_l (w0_byte1_l_unused[8:0]), | |
| 2945 | .w0_byte0_l (w0_byte0_l_unused[8:0]), | |
| 2946 | .w1_byte7_l (w1_byte7_l_unused[8:0]), | |
| 2947 | .w1_byte6_l (w1_byte6_l_unused[8:0]), | |
| 2948 | .w1_byte5_l (w1_byte5_l_unused[8:0]), | |
| 2949 | .w1_byte4_l (w1_byte4_l_unused[8:0]), | |
| 2950 | .w1_byte3_l (w1_byte3_l_unused[8:0]), | |
| 2951 | .w1_byte2_l (w1_byte2_l_unused[8:0]), | |
| 2952 | .w1_byte1_l (w1_byte1_l_unused[8:0]), | |
| 2953 | .w1_byte0_l (w1_byte0_l_unused[8:0]), | |
| 2954 | .l1clk(l1clk), | |
| 2955 | .l1clk_wr(l1clk_wr), | |
| 2956 | .rd_en_a(rd_en_a), | |
| 2957 | .wr_en_a(wr_en_a), | |
| 2958 | .wr_en_b(wr_en_b), | |
| 2959 | .wr_inh_b(wr_inh_b), | |
| 2960 | .addr_b(addr_b[10:3]), | |
| 2961 | .byte_wr_en_b(byte_wr_en_b[15:0]), | |
| 2962 | .vnw_ary(vnw_ary) | |
| 2963 | ); | |
| 2964 | ||
| 2965 | n2_dca_sp_9kb_bank way23 ( | |
| 2966 | .red_data_l (red_reg_d_bl[5:0]), | |
| 2967 | .red_enable_l (red_reg_en_bl[1:0]), | |
| 2968 | .red_data_r (red_reg_d_br[5:0]), | |
| 2969 | .red_enable_r (red_reg_en_br[1:0]), | |
| 2970 | .rd_en_b (rd_en_bot_b), | |
| 2971 | .wr_waysel_b (wr_waysel_b[3:2]), | |
| 2972 | .wrd_byte15_a ({dcache_wparity_m[15],dcache_wdata_m[127:120]}), | |
| 2973 | .wrd_byte14_a ({dcache_wparity_m[14],dcache_wdata_m[119:112]}), | |
| 2974 | .wrd_byte13_a ({dcache_wparity_m[13],dcache_wdata_m[111:104]}), | |
| 2975 | .wrd_byte12_a ({dcache_wparity_m[12],dcache_wdata_m[103:96]}), | |
| 2976 | .wrd_byte11_a ({dcache_wparity_m[11],dcache_wdata_m[95:88]}), | |
| 2977 | .wrd_byte10_a ({dcache_wparity_m[10],dcache_wdata_m[87:80]}), | |
| 2978 | .wrd_byte9_a ({dcache_wparity_m[9],dcache_wdata_m[79:72]}), | |
| 2979 | .wrd_byte8_a ({dcache_wparity_m[8],dcache_wdata_m[71:64]}), | |
| 2980 | .wrd_byte7_a ({dcache_wparity_m[7],dcache_wdata_m[63:56]}), | |
| 2981 | .wrd_byte6_a ({dcache_wparity_m[6],dcache_wdata_m[55:48]}), | |
| 2982 | .wrd_byte5_a ({dcache_wparity_m[5],dcache_wdata_m[47:40]}), | |
| 2983 | .wrd_byte4_a ({dcache_wparity_m[4],dcache_wdata_m[39:32]}), | |
| 2984 | .wrd_byte3_a ({dcache_wparity_m[3],dcache_wdata_m[31:24]}), | |
| 2985 | .wrd_byte2_a ({dcache_wparity_m[2],dcache_wdata_m[23:16]}), | |
| 2986 | .wrd_byte1_a ({dcache_wparity_m[1],dcache_wdata_m[15:8]}), | |
| 2987 | .wrd_byte0_a ({dcache_wparity_m[0],dcache_wdata_m[7:0]}), | |
| 2988 | .w0_byte7_h ({rparity_w2_m[7],dcache_rdata_w2_m[63:56]}), | |
| 2989 | .w0_byte6_h ({rparity_w2_m[6],dcache_rdata_w2_m[55:48]}), | |
| 2990 | .w0_byte5_h ({rparity_w2_m[5],dcache_rdata_w2_m[47:40]}), | |
| 2991 | .w0_byte4_h ({rparity_w2_m[4],dcache_rdata_w2_m[39:32]}), | |
| 2992 | .w0_byte3_h ({rparity_w2_m[3],dcache_rdata_w2_m[31:24]}), | |
| 2993 | .w0_byte2_h ({rparity_w2_m[2],dcache_rdata_w2_m[23:16]}), | |
| 2994 | .w0_byte1_h ({rparity_w2_m[1],dcache_rdata_w2_m[15:8]}), | |
| 2995 | .w0_byte0_h ({rparity_w2_m[0],dcache_rdata_w2_m[7:0]}), | |
| 2996 | .w1_byte7_h ({rparity_w3_m[7],dcache_rdata_w3_m[63:56]}), | |
| 2997 | .w1_byte6_h ({rparity_w3_m[6],dcache_rdata_w3_m[55:48]}), | |
| 2998 | .w1_byte5_h ({rparity_w3_m[5],dcache_rdata_w3_m[47:40]}), | |
| 2999 | .w1_byte4_h ({rparity_w3_m[4],dcache_rdata_w3_m[39:32]}), | |
| 3000 | .w1_byte3_h ({rparity_w3_m[3],dcache_rdata_w3_m[31:24]}), | |
| 3001 | .w1_byte2_h ({rparity_w3_m[2],dcache_rdata_w3_m[23:16]}), | |
| 3002 | .w1_byte1_h ({rparity_w3_m[1],dcache_rdata_w3_m[15:8]}), | |
| 3003 | .w1_byte0_h ({rparity_w3_m[0],dcache_rdata_w3_m[7:0]}), | |
| 3004 | .w0_byte7_l (w2_byte7_l_unused[8:0]), | |
| 3005 | .w0_byte6_l (w2_byte6_l_unused[8:0]), | |
| 3006 | .w0_byte5_l (w2_byte5_l_unused[8:0]), | |
| 3007 | .w0_byte4_l (w2_byte4_l_unused[8:0]), | |
| 3008 | .w0_byte3_l (w2_byte3_l_unused[8:0]), | |
| 3009 | .w0_byte2_l (w2_byte2_l_unused[8:0]), | |
| 3010 | .w0_byte1_l (w2_byte1_l_unused[8:0]), | |
| 3011 | .w0_byte0_l (w2_byte0_l_unused[8:0]), | |
| 3012 | .w1_byte7_l (w3_byte7_l_unused[8:0]), | |
| 3013 | .w1_byte6_l (w3_byte6_l_unused[8:0]), | |
| 3014 | .w1_byte5_l (w3_byte5_l_unused[8:0]), | |
| 3015 | .w1_byte4_l (w3_byte4_l_unused[8:0]), | |
| 3016 | .w1_byte3_l (w3_byte3_l_unused[8:0]), | |
| 3017 | .w1_byte2_l (w3_byte2_l_unused[8:0]), | |
| 3018 | .w1_byte1_l (w3_byte1_l_unused[8:0]), | |
| 3019 | .w1_byte0_l (w3_byte0_l_unused[8:0]), | |
| 3020 | .l1clk(l1clk), | |
| 3021 | .l1clk_wr(l1clk_wr), | |
| 3022 | .rd_en_a(rd_en_a), | |
| 3023 | .wr_en_a(wr_en_a), | |
| 3024 | .wr_en_b(wr_en_b), | |
| 3025 | .wr_inh_b(wr_inh_b), | |
| 3026 | .addr_b(addr_b[10:3]), | |
| 3027 | .byte_wr_en_b(byte_wr_en_b[15:0]), | |
| 3028 | .vnw_ary(vnw_ary) | |
| 3029 | ); | |
| 3030 | ||
| 3031 | ||
| 3032 | supply0 vss; | |
| 3033 | supply1 vdd; | |
| 3034 | endmodule | |
| 3035 | ||
| 3036 | ||
| 3037 | ||
| 3038 | module n2_dca_sp_9kb_bank ( | |
| 3039 | l1clk, | |
| 3040 | l1clk_wr, | |
| 3041 | rd_en_b, | |
| 3042 | rd_en_a, | |
| 3043 | wr_en_a, | |
| 3044 | wr_en_b, | |
| 3045 | wr_inh_b, | |
| 3046 | addr_b, | |
| 3047 | byte_wr_en_b, | |
| 3048 | wr_waysel_b, | |
| 3049 | red_data_l, | |
| 3050 | red_data_r, | |
| 3051 | red_enable_l, | |
| 3052 | red_enable_r, | |
| 3053 | vnw_ary, | |
| 3054 | wrd_byte15_a, | |
| 3055 | wrd_byte14_a, | |
| 3056 | wrd_byte13_a, | |
| 3057 | wrd_byte12_a, | |
| 3058 | wrd_byte11_a, | |
| 3059 | wrd_byte10_a, | |
| 3060 | wrd_byte9_a, | |
| 3061 | wrd_byte8_a, | |
| 3062 | wrd_byte7_a, | |
| 3063 | wrd_byte6_a, | |
| 3064 | wrd_byte5_a, | |
| 3065 | wrd_byte4_a, | |
| 3066 | wrd_byte3_a, | |
| 3067 | wrd_byte2_a, | |
| 3068 | wrd_byte1_a, | |
| 3069 | wrd_byte0_a, | |
| 3070 | w1_byte7_h, | |
| 3071 | w1_byte6_h, | |
| 3072 | w1_byte5_h, | |
| 3073 | w1_byte4_h, | |
| 3074 | w1_byte3_h, | |
| 3075 | w1_byte2_h, | |
| 3076 | w1_byte1_h, | |
| 3077 | w1_byte0_h, | |
| 3078 | w1_byte7_l, | |
| 3079 | w1_byte6_l, | |
| 3080 | w1_byte5_l, | |
| 3081 | w1_byte4_l, | |
| 3082 | w1_byte3_l, | |
| 3083 | w1_byte2_l, | |
| 3084 | w1_byte1_l, | |
| 3085 | w1_byte0_l, | |
| 3086 | w0_byte7_h, | |
| 3087 | w0_byte6_h, | |
| 3088 | w0_byte5_h, | |
| 3089 | w0_byte4_h, | |
| 3090 | w0_byte3_h, | |
| 3091 | w0_byte2_h, | |
| 3092 | w0_byte1_h, | |
| 3093 | w0_byte0_h, | |
| 3094 | w0_byte7_l, | |
| 3095 | w0_byte6_l, | |
| 3096 | w0_byte5_l, | |
| 3097 | w0_byte4_l, | |
| 3098 | w0_byte3_l, | |
| 3099 | w0_byte2_l, | |
| 3100 | w0_byte1_l, | |
| 3101 | w0_byte0_l); | |
| 3102 | ||
| 3103 | `define WIDTH 288 | |
| 3104 | `define ENTRIES 128 | |
| 3105 | ||
| 3106 | // way0 and way1 are interleaved physically across 2 subbanks | |
| 3107 | // [288,277,..................,145,144] -- xdec -- [143,142,.............,1,0] | |
| 3108 | // H L H L H L H L -- xdec -- L H L H L H L H | |
| 3109 | // way1 = [288,287,284,283,...,151,150,147,146 -- xdec -- 141,140,137,136,...,5,4,1,0 | |
| 3110 | // way0 = [286,285,282,281,...,149,148,145,144 -- xdec -- 143,142,139,138,...,7,6,3,2 | |
| 3111 | ||
| 3112 | input l1clk; // l1clk from l1clk_header | |
| 3113 | input l1clk_wr; // l1clk from l1clk_header | |
| 3114 | input rd_en_b; // e_cycle b_phase signal | |
| 3115 | input rd_en_a; // m_cycle a_phase signal | |
| 3116 | input wr_en_a; // m_cycle a_phase signal | |
| 3117 | input wr_en_b; // e_cycle b_phase signal | |
| 3118 | input wr_inh_b; // e_cycle b_phase signal | |
| 3119 | input [10:3] addr_b; // e_cycle b_phase signal | |
| 3120 | input [15:0] byte_wr_en_b; // e_cycle b_phase signal | |
| 3121 | input [1:0] wr_waysel_b; // e_cycle b_phase signal | |
| 3122 | ||
| 3123 | input [5:0] red_data_l; | |
| 3124 | input [5:0] red_data_r; | |
| 3125 | input [1:0] red_enable_l; | |
| 3126 | input [1:0] red_enable_r; | |
| 3127 | ||
| 3128 | input vnw_ary; | |
| 3129 | ||
| 3130 | input [8:0] wrd_byte15_a; // m_cycle a_phase signal | |
| 3131 | input [8:0] wrd_byte14_a; | |
| 3132 | input [8:0] wrd_byte13_a; | |
| 3133 | input [8:0] wrd_byte12_a; | |
| 3134 | input [8:0] wrd_byte11_a; | |
| 3135 | input [8:0] wrd_byte10_a; | |
| 3136 | input [8:0] wrd_byte9_a; | |
| 3137 | input [8:0] wrd_byte8_a; | |
| 3138 | input [8:0] wrd_byte7_a; | |
| 3139 | input [8:0] wrd_byte6_a; | |
| 3140 | input [8:0] wrd_byte5_a; | |
| 3141 | input [8:0] wrd_byte4_a; | |
| 3142 | input [8:0] wrd_byte3_a; | |
| 3143 | input [8:0] wrd_byte2_a; | |
| 3144 | input [8:0] wrd_byte1_a; | |
| 3145 | input [8:0] wrd_byte0_a; | |
| 3146 | ||
| 3147 | output [8:0] w1_byte7_h; // m_cycle b_phase clock-like signal | |
| 3148 | output [8:0] w1_byte6_h; | |
| 3149 | output [8:0] w1_byte5_h; | |
| 3150 | output [8:0] w1_byte4_h; | |
| 3151 | output [8:0] w1_byte3_h; | |
| 3152 | output [8:0] w1_byte2_h; | |
| 3153 | output [8:0] w1_byte1_h; | |
| 3154 | output [8:0] w1_byte0_h; | |
| 3155 | output [8:0] w1_byte7_l; | |
| 3156 | output [8:0] w1_byte6_l; | |
| 3157 | output [8:0] w1_byte5_l; | |
| 3158 | output [8:0] w1_byte4_l; | |
| 3159 | output [8:0] w1_byte3_l; | |
| 3160 | output [8:0] w1_byte2_l; | |
| 3161 | output [8:0] w1_byte1_l; | |
| 3162 | output [8:0] w1_byte0_l; | |
| 3163 | ||
| 3164 | output [8:0] w0_byte7_h; // m_cycle b_phase clock-like signal | |
| 3165 | output [8:0] w0_byte6_h; | |
| 3166 | output [8:0] w0_byte5_h; | |
| 3167 | output [8:0] w0_byte4_h; | |
| 3168 | output [8:0] w0_byte3_h; | |
| 3169 | output [8:0] w0_byte2_h; | |
| 3170 | output [8:0] w0_byte1_h; | |
| 3171 | output [8:0] w0_byte0_h; | |
| 3172 | output [8:0] w0_byte7_l; | |
| 3173 | output [8:0] w0_byte6_l; | |
| 3174 | output [8:0] w0_byte5_l; | |
| 3175 | output [8:0] w0_byte4_l; | |
| 3176 | output [8:0] w0_byte3_l; | |
| 3177 | output [8:0] w0_byte2_l; | |
| 3178 | output [8:0] w0_byte1_l; | |
| 3179 | output [8:0] w0_byte0_l; | |
| 3180 | ||
| 3181 | ||
| 3182 | ||
| 3183 | ||
| 3184 | ||
| 3185 | ||
| 3186 | ||
| 3187 | reg [71:0] w0_sao_h; | |
| 3188 | reg [71:0] w0_sao_l; | |
| 3189 | reg [71:0] w1_sao_h; | |
| 3190 | reg [71:0] w1_sao_l; | |
| 3191 | ||
| 3192 | ||
| 3193 | ||
| 3194 | ||
| 3195 | n2_dca_sp_9kb_subbank left ( | |
| 3196 | .byte_wr_en_b ({byte_wr_en_b[15],byte_wr_en_b[7],byte_wr_en_b[14],byte_wr_en_b[6], | |
| 3197 | byte_wr_en_b[13],byte_wr_en_b[5],byte_wr_en_b[12],byte_wr_en_b[4]}), | |
| 3198 | .wr_data_a ({wrd_byte15_a[8], wrd_byte7_a[8], wrd_byte14_a[8], wrd_byte6_a[8], | |
| 3199 | wrd_byte15_a[7], wrd_byte7_a[7], wrd_byte14_a[7], wrd_byte6_a[7], | |
| 3200 | wrd_byte15_a[6], wrd_byte7_a[6], wrd_byte14_a[6], wrd_byte6_a[6], | |
| 3201 | wrd_byte15_a[5], wrd_byte7_a[5], wrd_byte14_a[5], wrd_byte6_a[5], | |
| 3202 | wrd_byte15_a[4], wrd_byte7_a[4], wrd_byte14_a[4], wrd_byte6_a[4], | |
| 3203 | wrd_byte15_a[3], wrd_byte7_a[3], wrd_byte14_a[3], wrd_byte6_a[3], | |
| 3204 | wrd_byte15_a[2], wrd_byte7_a[2], wrd_byte14_a[2], wrd_byte6_a[2], | |
| 3205 | wrd_byte15_a[1], wrd_byte7_a[1], wrd_byte14_a[1], wrd_byte6_a[1], | |
| 3206 | wrd_byte15_a[0], wrd_byte7_a[0], wrd_byte14_a[0], wrd_byte6_a[0], | |
| 3207 | wrd_byte13_a[8], wrd_byte5_a[8], wrd_byte12_a[8], wrd_byte4_a[8], | |
| 3208 | wrd_byte13_a[7], wrd_byte5_a[7], wrd_byte12_a[7], wrd_byte4_a[7], | |
| 3209 | wrd_byte13_a[6], wrd_byte5_a[6], wrd_byte12_a[6], wrd_byte4_a[6], | |
| 3210 | wrd_byte13_a[5], wrd_byte5_a[5], wrd_byte12_a[5], wrd_byte4_a[5], | |
| 3211 | wrd_byte13_a[4], wrd_byte5_a[4], wrd_byte12_a[4], wrd_byte4_a[4], | |
| 3212 | wrd_byte13_a[3], wrd_byte5_a[3], wrd_byte12_a[3], wrd_byte4_a[3], | |
| 3213 | wrd_byte13_a[2], wrd_byte5_a[2], wrd_byte12_a[2], wrd_byte4_a[2], | |
| 3214 | wrd_byte13_a[1], wrd_byte5_a[1], wrd_byte12_a[1], wrd_byte4_a[1], | |
| 3215 | wrd_byte13_a[0], wrd_byte5_a[0], wrd_byte12_a[0], wrd_byte4_a[0]}), | |
| 3216 | .red_data (red_data_l[5:0]), | |
| 3217 | .red_en (red_enable_l[1:0]), | |
| 3218 | .w0_rdata_h ({w0_byte7_h[8],w0_byte6_h[8],w0_byte7_h[7],w0_byte6_h[7], | |
| 3219 | w0_byte7_h[6],w0_byte6_h[6],w0_byte7_h[5],w0_byte6_h[5], | |
| 3220 | w0_byte7_h[4],w0_byte6_h[4],w0_byte7_h[3],w0_byte6_h[3], | |
| 3221 | w0_byte7_h[2],w0_byte6_h[2],w0_byte7_h[1],w0_byte6_h[1], | |
| 3222 | w0_byte7_h[0],w0_byte6_h[0],w0_byte5_h[8],w0_byte4_h[8], | |
| 3223 | w0_byte5_h[7],w0_byte4_h[7],w0_byte5_h[6],w0_byte4_h[6], | |
| 3224 | w0_byte5_h[5],w0_byte4_h[5],w0_byte5_h[4],w0_byte4_h[4], | |
| 3225 | w0_byte5_h[3],w0_byte4_h[3],w0_byte5_h[2],w0_byte4_h[2], | |
| 3226 | w0_byte5_h[1],w0_byte4_h[1],w0_byte5_h[0],w0_byte4_h[0]}), | |
| 3227 | .w0_rdata_l ({w0_byte7_l[8],w0_byte6_l[8],w0_byte7_l[7],w0_byte6_l[7], | |
| 3228 | w0_byte7_l[6],w0_byte6_l[6],w0_byte7_l[5],w0_byte6_l[5], | |
| 3229 | w0_byte7_l[4],w0_byte6_l[4],w0_byte7_l[3],w0_byte6_l[3], | |
| 3230 | w0_byte7_l[2],w0_byte6_l[2],w0_byte7_l[1],w0_byte6_l[1], | |
| 3231 | w0_byte7_l[0],w0_byte6_l[0],w0_byte5_l[8],w0_byte4_l[8], | |
| 3232 | w0_byte5_l[7],w0_byte4_l[7],w0_byte5_l[6],w0_byte4_l[6], | |
| 3233 | w0_byte5_l[5],w0_byte4_l[5],w0_byte5_l[4],w0_byte4_l[4], | |
| 3234 | w0_byte5_l[3],w0_byte4_l[3],w0_byte5_l[2],w0_byte4_l[2], | |
| 3235 | w0_byte5_l[1],w0_byte4_l[1],w0_byte5_l[0],w0_byte4_l[0]}), | |
| 3236 | .w1_rdata_h ({w1_byte7_h[8],w1_byte6_h[8],w1_byte7_h[7],w1_byte6_h[7], | |
| 3237 | w1_byte7_h[6],w1_byte6_h[6],w1_byte7_h[5],w1_byte6_h[5], | |
| 3238 | w1_byte7_h[4],w1_byte6_h[4],w1_byte7_h[3],w1_byte6_h[3], | |
| 3239 | w1_byte7_h[2],w1_byte6_h[2],w1_byte7_h[1],w1_byte6_h[1], | |
| 3240 | w1_byte7_h[0],w1_byte6_h[0],w1_byte5_h[8],w1_byte4_h[8], | |
| 3241 | w1_byte5_h[7],w1_byte4_h[7],w1_byte5_h[6],w1_byte4_h[6], | |
| 3242 | w1_byte5_h[5],w1_byte4_h[5],w1_byte5_h[4],w1_byte4_h[4], | |
| 3243 | w1_byte5_h[3],w1_byte4_h[3],w1_byte5_h[2],w1_byte4_h[2], | |
| 3244 | w1_byte5_h[1],w1_byte4_h[1],w1_byte5_h[0],w1_byte4_h[0]}), | |
| 3245 | .w1_rdata_l ({w1_byte7_l[8],w1_byte6_l[8],w1_byte7_l[7],w1_byte6_l[7], | |
| 3246 | w1_byte7_l[6],w1_byte6_l[6],w1_byte7_l[5],w1_byte6_l[5], | |
| 3247 | w1_byte7_l[4],w1_byte6_l[4],w1_byte7_l[3],w1_byte6_l[3], | |
| 3248 | w1_byte7_l[2],w1_byte6_l[2],w1_byte7_l[1],w1_byte6_l[1], | |
| 3249 | w1_byte7_l[0],w1_byte6_l[0],w1_byte5_l[8],w1_byte4_l[8], | |
| 3250 | w1_byte5_l[7],w1_byte4_l[7],w1_byte5_l[6],w1_byte4_l[6], | |
| 3251 | w1_byte5_l[5],w1_byte4_l[5],w1_byte5_l[4],w1_byte4_l[4], | |
| 3252 | w1_byte5_l[3],w1_byte4_l[3],w1_byte5_l[2],w1_byte4_l[2], | |
| 3253 | w1_byte5_l[1],w1_byte4_l[1],w1_byte5_l[0],w1_byte4_l[0]}), | |
| 3254 | .l1clk(l1clk), | |
| 3255 | .l1clk_wr(l1clk_wr), | |
| 3256 | .rd_en_b(rd_en_b), | |
| 3257 | .rd_en_a(rd_en_a), | |
| 3258 | .wr_en_a(wr_en_a), | |
| 3259 | .wr_en_b(wr_en_b), | |
| 3260 | .wr_inh_b(wr_inh_b), | |
| 3261 | .addr_b(addr_b[10:3]), | |
| 3262 | .wr_waysel_b(wr_waysel_b[1:0]), | |
| 3263 | .vnw_ary(vnw_ary) | |
| 3264 | ); | |
| 3265 | ||
| 3266 | // The right subbank is a mirrored copy of the left (redundant columns on the left), | |
| 3267 | // so all I/O's must be reverse ordered. | |
| 3268 | ||
| 3269 | n2_dca_sp_9kb_subbank right ( | |
| 3270 | .byte_wr_en_b ({byte_wr_en_b[8],byte_wr_en_b[0],byte_wr_en_b[9],byte_wr_en_b[1], | |
| 3271 | byte_wr_en_b[10],byte_wr_en_b[2],byte_wr_en_b[11],byte_wr_en_b[3]}), | |
| 3272 | .wr_data_a ({wrd_byte8_a[8], wrd_byte0_a[8], wrd_byte9_a[8], wrd_byte1_a[8], | |
| 3273 | wrd_byte8_a[0], wrd_byte0_a[0], wrd_byte9_a[0], wrd_byte1_a[0], | |
| 3274 | wrd_byte8_a[1], wrd_byte0_a[1], wrd_byte9_a[1], wrd_byte1_a[1], | |
| 3275 | wrd_byte8_a[2], wrd_byte0_a[2], wrd_byte9_a[2], wrd_byte1_a[2], | |
| 3276 | wrd_byte8_a[3], wrd_byte0_a[3], wrd_byte9_a[3], wrd_byte1_a[3], | |
| 3277 | wrd_byte8_a[4], wrd_byte0_a[4], wrd_byte9_a[4], wrd_byte1_a[4], | |
| 3278 | wrd_byte8_a[5], wrd_byte0_a[5], wrd_byte9_a[5], wrd_byte1_a[5], | |
| 3279 | wrd_byte8_a[6], wrd_byte0_a[6], wrd_byte9_a[6], wrd_byte1_a[6], | |
| 3280 | wrd_byte8_a[7], wrd_byte0_a[7], wrd_byte9_a[7], wrd_byte1_a[7], | |
| 3281 | wrd_byte10_a[8], wrd_byte2_a[8], wrd_byte11_a[8], wrd_byte3_a[8], | |
| 3282 | wrd_byte10_a[0], wrd_byte2_a[0], wrd_byte11_a[0], wrd_byte3_a[0], | |
| 3283 | wrd_byte10_a[1], wrd_byte2_a[1], wrd_byte11_a[1], wrd_byte3_a[1], | |
| 3284 | wrd_byte10_a[2], wrd_byte2_a[2], wrd_byte11_a[2], wrd_byte3_a[2], | |
| 3285 | wrd_byte10_a[3], wrd_byte2_a[3], wrd_byte11_a[3], wrd_byte3_a[3], | |
| 3286 | wrd_byte10_a[4], wrd_byte2_a[4], wrd_byte11_a[4], wrd_byte3_a[4], | |
| 3287 | wrd_byte10_a[5], wrd_byte2_a[5], wrd_byte11_a[5], wrd_byte3_a[5], | |
| 3288 | wrd_byte10_a[6], wrd_byte2_a[6], wrd_byte11_a[6], wrd_byte3_a[6], | |
| 3289 | wrd_byte10_a[7], wrd_byte2_a[7], wrd_byte11_a[7], wrd_byte3_a[7]}), | |
| 3290 | .red_data (red_data_r[5:0]), | |
| 3291 | .red_en (red_enable_r[1:0]), | |
| 3292 | .w0_rdata_h ({w0_byte0_h[8],w0_byte1_h[8],w0_byte0_h[0],w0_byte1_h[0], | |
| 3293 | w0_byte0_h[1],w0_byte1_h[1],w0_byte0_h[2],w0_byte1_h[2], | |
| 3294 | w0_byte0_h[3],w0_byte1_h[3],w0_byte0_h[4],w0_byte1_h[4], | |
| 3295 | w0_byte0_h[5],w0_byte1_h[5],w0_byte0_h[6],w0_byte1_h[6], | |
| 3296 | w0_byte0_h[7],w0_byte1_h[7],w0_byte2_h[8],w0_byte3_h[8], | |
| 3297 | w0_byte2_h[0],w0_byte3_h[0],w0_byte2_h[1],w0_byte3_h[1], | |
| 3298 | w0_byte2_h[2],w0_byte3_h[2],w0_byte2_h[3],w0_byte3_h[3], | |
| 3299 | w0_byte2_h[4],w0_byte3_h[4],w0_byte2_h[5],w0_byte3_h[5], | |
| 3300 | w0_byte2_h[6],w0_byte3_h[6],w0_byte2_h[7],w0_byte3_h[7]}), | |
| 3301 | .w0_rdata_l ({w0_byte0_l[8],w0_byte1_l[8],w0_byte0_l[0],w0_byte1_l[0], | |
| 3302 | w0_byte0_l[1],w0_byte1_l[1],w0_byte0_l[2],w0_byte1_l[2], | |
| 3303 | w0_byte0_l[3],w0_byte1_l[3],w0_byte0_l[4],w0_byte1_l[4], | |
| 3304 | w0_byte0_l[5],w0_byte1_l[5],w0_byte0_l[6],w0_byte1_l[6], | |
| 3305 | w0_byte0_l[7],w0_byte1_l[7],w0_byte2_l[8],w0_byte3_l[8], | |
| 3306 | w0_byte2_l[0],w0_byte3_l[0],w0_byte2_l[1],w0_byte3_l[1], | |
| 3307 | w0_byte2_l[2],w0_byte3_l[2],w0_byte2_l[3],w0_byte3_l[3], | |
| 3308 | w0_byte2_l[4],w0_byte3_l[4],w0_byte2_l[5],w0_byte3_l[5], | |
| 3309 | w0_byte2_l[6],w0_byte3_l[6],w0_byte2_l[7],w0_byte3_l[7]}), | |
| 3310 | .w1_rdata_h ({w1_byte0_h[8],w1_byte1_h[8],w1_byte0_h[0],w1_byte1_h[0], | |
| 3311 | w1_byte0_h[1],w1_byte1_h[1],w1_byte0_h[2],w1_byte1_h[2], | |
| 3312 | w1_byte0_h[3],w1_byte1_h[3],w1_byte0_h[4],w1_byte1_h[4], | |
| 3313 | w1_byte0_h[5],w1_byte1_h[5],w1_byte0_h[6],w1_byte1_h[6], | |
| 3314 | w1_byte0_h[7],w1_byte1_h[7],w1_byte2_h[8],w1_byte3_h[8], | |
| 3315 | w1_byte2_h[0],w1_byte3_h[0],w1_byte2_h[1],w1_byte3_h[1], | |
| 3316 | w1_byte2_h[2],w1_byte3_h[2],w1_byte2_h[3],w1_byte3_h[3], | |
| 3317 | w1_byte2_h[4],w1_byte3_h[4],w1_byte2_h[5],w1_byte3_h[5], | |
| 3318 | w1_byte2_h[6],w1_byte3_h[6],w1_byte2_h[7],w1_byte3_h[7]}), | |
| 3319 | .w1_rdata_l ({w1_byte0_l[8],w1_byte1_l[8],w1_byte0_l[0],w1_byte1_l[0], | |
| 3320 | w1_byte0_l[1],w1_byte1_l[1],w1_byte0_l[2],w1_byte1_l[2], | |
| 3321 | w1_byte0_l[3],w1_byte1_l[3],w1_byte0_l[4],w1_byte1_l[4], | |
| 3322 | w1_byte0_l[5],w1_byte1_l[5],w1_byte0_l[6],w1_byte1_l[6], | |
| 3323 | w1_byte0_l[7],w1_byte1_l[7],w1_byte2_l[8],w1_byte3_l[8], | |
| 3324 | w1_byte2_l[0],w1_byte3_l[0],w1_byte2_l[1],w1_byte3_l[1], | |
| 3325 | w1_byte2_l[2],w1_byte3_l[2],w1_byte2_l[3],w1_byte3_l[3], | |
| 3326 | w1_byte2_l[4],w1_byte3_l[4],w1_byte2_l[5],w1_byte3_l[5], | |
| 3327 | w1_byte2_l[6],w1_byte3_l[6],w1_byte2_l[7],w1_byte3_l[7]}), | |
| 3328 | .l1clk(l1clk), | |
| 3329 | .l1clk_wr(l1clk_wr), | |
| 3330 | .rd_en_b(rd_en_b), | |
| 3331 | .rd_en_a(rd_en_a), | |
| 3332 | .wr_en_a(wr_en_a), | |
| 3333 | .wr_en_b(wr_en_b), | |
| 3334 | .wr_inh_b(wr_inh_b), | |
| 3335 | .addr_b(addr_b[10:3]), | |
| 3336 | .wr_waysel_b(wr_waysel_b[1:0]), | |
| 3337 | .vnw_ary(vnw_ary) | |
| 3338 | ); | |
| 3339 | ||
| 3340 | ||
| 3341 | ||
| 3342 | ||
| 3343 | ||
| 3344 | ||
| 3345 | ||
| 3346 | ||
| 3347 | ||
| 3348 | ||
| 3349 | ||
| 3350 | ||
| 3351 | ||
| 3352 | ||
| 3353 | ||
| 3354 | ||
| 3355 | ||
| 3356 | ||
| 3357 | ||
| 3358 | ||
| 3359 | ||
| 3360 | ||
| 3361 | ||
| 3362 | ||
| 3363 | ||
| 3364 | ||
| 3365 | ||
| 3366 | ||
| 3367 | ||
| 3368 | ||
| 3369 | ||
| 3370 | ||
| 3371 | supply0 vss; | |
| 3372 | supply1 vdd; | |
| 3373 | endmodule | |
| 3374 | ||
| 3375 | ||
| 3376 | ||
| 3377 | ||
| 3378 | module n2_dca_sp_9kb_subbank ( | |
| 3379 | l1clk, | |
| 3380 | l1clk_wr, | |
| 3381 | rd_en_b, | |
| 3382 | rd_en_a, | |
| 3383 | wr_en_a, | |
| 3384 | wr_en_b, | |
| 3385 | wr_inh_b, | |
| 3386 | addr_b, | |
| 3387 | byte_wr_en_b, | |
| 3388 | wr_waysel_b, | |
| 3389 | wr_data_a, | |
| 3390 | red_data, | |
| 3391 | red_en, | |
| 3392 | vnw_ary, | |
| 3393 | w0_rdata_h, | |
| 3394 | w0_rdata_l, | |
| 3395 | w1_rdata_h, | |
| 3396 | w1_rdata_l); | |
| 3397 | wire red_shift_en; | |
| 3398 | wire [143:0] data_in; | |
| 3399 | wire [143:0] byte_mask; | |
| 3400 | wire w0_wcs; | |
| 3401 | wire w1_wcs; | |
| 3402 | wire [143:0] way_mask; | |
| 3403 | wire [143:0] local_dout; | |
| 3404 | wire rcs_l; | |
| 3405 | wire [35:0] w0_dout; | |
| 3406 | wire [35:0] w1_dout; | |
| 3407 | ||
| 3408 | ||
| 3409 | `define ENTRIES 128 | |
| 3410 | ||
| 3411 | // way0 and way1 are interleaved physically across 2 subbanks | |
| 3412 | // [288,277,..................,145,144] -- xdec -- [143,142,.............,1,0] | |
| 3413 | // H L H L H L H L -- xdec -- L H L H L H L H | |
| 3414 | // way1 = [288,287,284,283,...,151,150,147,146 -- xdec -- 141,140,137,136,...,5,4,1,0 | |
| 3415 | // way0 = [286,285,282,281,...,149,148,145,144 -- xdec -- 143,142,139,138,...,7,6,3,2 | |
| 3416 | ||
| 3417 | input l1clk; // l1clk from l1clk_header | |
| 3418 | input l1clk_wr; // l1clk from l1clk_header | |
| 3419 | input rd_en_b; // e_cycle b_phase signal | |
| 3420 | input rd_en_a; // m_cycle a_phase signal | |
| 3421 | input wr_en_a; // m_cycle a_phase signal | |
| 3422 | input wr_en_b; // e_cycle b_phase signal | |
| 3423 | input wr_inh_b; // e_cycle b_phase signal | |
| 3424 | input [10:3] addr_b; // e_cycle b_phase signal | |
| 3425 | input [7:0] byte_wr_en_b; // e_cycle b_phase signal | |
| 3426 | input [1:0] wr_waysel_b; // e_cycle b_phase signal | |
| 3427 | ||
| 3428 | input [71:0] wr_data_a; // m_cycle a_phase signal | |
| 3429 | ||
| 3430 | input [5:0] red_data; | |
| 3431 | input [1:0] red_en; | |
| 3432 | ||
| 3433 | input vnw_ary; | |
| 3434 | ||
| 3435 | output [35:0] w0_rdata_h; // m_cycle b_phase clock-like signal | |
| 3436 | output [35:0] w0_rdata_l; // m_cycle b_phase clock-like signal | |
| 3437 | output [35:0] w1_rdata_h; // m_cycle b_phase clock-like signal | |
| 3438 | output [35:0] w1_rdata_l; // m_cycle b_phase clock-like signal | |
| 3439 | ||
| 3440 | // synopsys translate_off | |
| 3441 | ||
| 3442 | reg [147:0] mem[`ENTRIES-1:0]; | |
| 3443 | reg [143:0] dout; | |
| 3444 | reg [35:0] w0_sao_h; | |
| 3445 | reg [35:0] w0_sao_l; | |
| 3446 | reg [35:0] w1_sao_h; | |
| 3447 | reg [35:0] w1_sao_l; | |
| 3448 | ||
| 3449 | wire [147:0] wr_data; | |
| 3450 | wire [143:0] din; | |
| 3451 | wire [147:0] temp; | |
| 3452 | ||
| 3453 | ||
| 3454 | assign red_shift_en = red_en[1] & red_en[0]; | |
| 3455 | ||
| 3456 | ////////////////////////////////// | |
| 3457 | // Initialize to zeros | |
| 3458 | `ifndef NOINITMEM | |
| 3459 | integer i; | |
| 3460 | initial begin | |
| 3461 | for (i=0;i<128;i=i+1) begin | |
| 3462 | mem[i] = 148'd0; | |
| 3463 | end | |
| 3464 | end | |
| 3465 | `endif | |
| 3466 | ||
| 3467 | ///////////////////////////// | |
| 3468 | // wrdata input mapping | |
| 3469 | //////////////////////////// | |
| 3470 | ||
| 3471 | assign data_in[143:0] = { | |
| 3472 | wr_data_a[71],wr_data_a[70],wr_data_a[71],wr_data_a[70], | |
| 3473 | wr_data_a[69],wr_data_a[68],wr_data_a[69],wr_data_a[68], | |
| 3474 | wr_data_a[67],wr_data_a[66],wr_data_a[67],wr_data_a[66], | |
| 3475 | wr_data_a[65],wr_data_a[64],wr_data_a[65],wr_data_a[64], | |
| 3476 | wr_data_a[63],wr_data_a[62],wr_data_a[63],wr_data_a[62], | |
| 3477 | wr_data_a[61],wr_data_a[60],wr_data_a[61],wr_data_a[60], | |
| 3478 | wr_data_a[59],wr_data_a[58],wr_data_a[59],wr_data_a[58], | |
| 3479 | wr_data_a[57],wr_data_a[56],wr_data_a[57],wr_data_a[56], | |
| 3480 | wr_data_a[55],wr_data_a[54],wr_data_a[55],wr_data_a[54], | |
| 3481 | wr_data_a[53],wr_data_a[52],wr_data_a[53],wr_data_a[52], | |
| 3482 | wr_data_a[51],wr_data_a[50],wr_data_a[51],wr_data_a[50], | |
| 3483 | wr_data_a[49],wr_data_a[48],wr_data_a[49],wr_data_a[48], | |
| 3484 | wr_data_a[47],wr_data_a[46],wr_data_a[47],wr_data_a[46], | |
| 3485 | wr_data_a[45],wr_data_a[44],wr_data_a[45],wr_data_a[44], | |
| 3486 | wr_data_a[43],wr_data_a[42],wr_data_a[43],wr_data_a[42], | |
| 3487 | wr_data_a[41],wr_data_a[40],wr_data_a[41],wr_data_a[40], | |
| 3488 | wr_data_a[39],wr_data_a[38],wr_data_a[39],wr_data_a[38], | |
| 3489 | wr_data_a[37],wr_data_a[36],wr_data_a[37],wr_data_a[36], | |
| 3490 | wr_data_a[35],wr_data_a[34],wr_data_a[35],wr_data_a[34], | |
| 3491 | wr_data_a[33],wr_data_a[32],wr_data_a[33],wr_data_a[32], | |
| 3492 | wr_data_a[31],wr_data_a[30],wr_data_a[31],wr_data_a[30], | |
| 3493 | wr_data_a[29],wr_data_a[28],wr_data_a[29],wr_data_a[28], | |
| 3494 | wr_data_a[27],wr_data_a[26],wr_data_a[27],wr_data_a[26], | |
| 3495 | wr_data_a[25],wr_data_a[24],wr_data_a[25],wr_data_a[24], | |
| 3496 | wr_data_a[23],wr_data_a[22],wr_data_a[23],wr_data_a[22], | |
| 3497 | wr_data_a[21],wr_data_a[20],wr_data_a[21],wr_data_a[20], | |
| 3498 | wr_data_a[19],wr_data_a[18],wr_data_a[19],wr_data_a[18], | |
| 3499 | wr_data_a[17],wr_data_a[16],wr_data_a[17],wr_data_a[16], | |
| 3500 | wr_data_a[15],wr_data_a[14],wr_data_a[15],wr_data_a[14], | |
| 3501 | wr_data_a[13],wr_data_a[12],wr_data_a[13],wr_data_a[12], | |
| 3502 | wr_data_a[11],wr_data_a[10],wr_data_a[11],wr_data_a[10], | |
| 3503 | wr_data_a[9],wr_data_a[8],wr_data_a[9],wr_data_a[8], | |
| 3504 | wr_data_a[7],wr_data_a[6],wr_data_a[7],wr_data_a[6], | |
| 3505 | wr_data_a[5],wr_data_a[4],wr_data_a[5],wr_data_a[4], | |
| 3506 | wr_data_a[3],wr_data_a[2],wr_data_a[3],wr_data_a[2], | |
| 3507 | wr_data_a[1],wr_data_a[0],wr_data_a[1],wr_data_a[0]}; | |
| 3508 | ||
| 3509 | //////////////////////////////// | |
| 3510 | // Encode mask for byte enables | |
| 3511 | //////////////////////////////// | |
| 3512 | assign byte_mask[143:0] = { | |
| 3513 | {9{byte_wr_en_b[7],byte_wr_en_b[6],byte_wr_en_b[7],byte_wr_en_b[6], | |
| 3514 | byte_wr_en_b[5],byte_wr_en_b[4],byte_wr_en_b[5],byte_wr_en_b[4]}}, | |
| 3515 | {9{byte_wr_en_b[3],byte_wr_en_b[2],byte_wr_en_b[3],byte_wr_en_b[2], | |
| 3516 | byte_wr_en_b[1],byte_wr_en_b[0],byte_wr_en_b[1],byte_wr_en_b[0]}}}; | |
| 3517 | ||
| 3518 | //////////////////////////////// | |
| 3519 | // Encode mask for way enables | |
| 3520 | //////////////////////////////// | |
| 3521 | assign w0_wcs = wr_waysel_b[0] & wr_en_b & ~wr_inh_b & ~rd_en_b ; // way0 write | |
| 3522 | assign w1_wcs = wr_waysel_b[1] & wr_en_b & ~wr_inh_b & ~rd_en_b ; // way1 write | |
| 3523 | ||
| 3524 | assign way_mask[143:0] = { {36{ {2{w1_wcs}},{2{w0_wcs}} }} }; | |
| 3525 | ||
| 3526 | ||
| 3527 | assign din[143:0] = ( (byte_mask[143:0] & way_mask[143:0]) & data_in[143:0]) | | |
| 3528 | (~(byte_mask[143:0] & way_mask[143:0]) & local_dout[143:0]); | |
| 3529 | ||
| 3530 | ////////////////////////// | |
| 3531 | // Redundancy write shifter | |
| 3532 | ////////////////////////// | |
| 3533 | ||
| 3534 | assign wr_data[ 3: 0] = din[ 3: 0]; | |
| 3535 | assign wr_data[ 7: 4] = (red_shift_en && (red_data >= 6'd0 )) ? din[ 7: 4] : din[ 3: 0]; | |
| 3536 | assign wr_data[ 11: 8] = (red_shift_en && (red_data >= 6'd1 )) ? din[ 11: 8] : din[ 7: 4]; | |
| 3537 | assign wr_data[ 15: 12] = (red_shift_en && (red_data >= 6'd2 )) ? din[ 15: 12] : din[ 11: 8]; | |
| 3538 | assign wr_data[ 19: 16] = (red_shift_en && (red_data >= 6'd3 )) ? din[ 19: 16] : din[ 15: 12]; | |
| 3539 | assign wr_data[ 23: 20] = (red_shift_en && (red_data >= 6'd4 )) ? din[ 23: 20] : din[ 19: 16]; | |
| 3540 | assign wr_data[ 27: 24] = (red_shift_en && (red_data >= 6'd5 )) ? din[ 27: 24] : din[ 23: 20]; | |
| 3541 | assign wr_data[ 31: 28] = (red_shift_en && (red_data >= 6'd6 )) ? din[ 31: 28] : din[ 27: 24]; | |
| 3542 | assign wr_data[ 35: 32] = (red_shift_en && (red_data >= 6'd7 )) ? din[ 35: 32] : din[ 31: 28]; | |
| 3543 | assign wr_data[ 39: 36] = (red_shift_en && (red_data >= 6'd8 )) ? din[ 39: 36] : din[ 35: 32]; | |
| 3544 | assign wr_data[ 43: 40] = (red_shift_en && (red_data >= 6'd9 )) ? din[ 43: 40] : din[ 39: 36]; | |
| 3545 | assign wr_data[ 47: 44] = (red_shift_en && (red_data >= 6'd10)) ? din[ 47: 44] : din[ 43: 40]; | |
| 3546 | assign wr_data[ 51: 48] = (red_shift_en && (red_data >= 6'd11)) ? din[ 51: 48] : din[ 47: 44]; | |
| 3547 | assign wr_data[ 55: 52] = (red_shift_en && (red_data >= 6'd12)) ? din[ 55: 52] : din[ 51: 48]; | |
| 3548 | assign wr_data[ 59: 56] = (red_shift_en && (red_data >= 6'd13)) ? din[ 59: 56] : din[ 55: 52]; | |
| 3549 | assign wr_data[ 63: 60] = (red_shift_en && (red_data >= 6'd14)) ? din[ 63: 60] : din[ 59: 56]; | |
| 3550 | assign wr_data[ 67: 64] = (red_shift_en && (red_data >= 6'd15)) ? din[ 67: 64] : din[ 63: 60]; | |
| 3551 | assign wr_data[ 71: 68] = (red_shift_en && (red_data >= 6'd16)) ? din[ 71: 68] : din[ 67: 64]; | |
| 3552 | assign wr_data[ 75: 72] = (red_shift_en && (red_data >= 6'd17)) ? din[ 75: 72] : din[ 71: 68]; | |
| 3553 | assign wr_data[ 79: 76] = (red_shift_en && (red_data >= 6'd18)) ? din[ 79: 76] : din[ 75: 72]; | |
| 3554 | assign wr_data[ 83: 80] = (red_shift_en && (red_data >= 6'd19)) ? din[ 83: 80] : din[ 79: 76]; | |
| 3555 | assign wr_data[ 87: 84] = (red_shift_en && (red_data >= 6'd20)) ? din[ 87: 84] : din[ 83: 80]; | |
| 3556 | assign wr_data[ 91: 88] = (red_shift_en && (red_data >= 6'd21)) ? din[ 91: 88] : din[ 87: 84]; | |
| 3557 | assign wr_data[ 95: 92] = (red_shift_en && (red_data >= 6'd22)) ? din[ 95: 92] : din[ 91: 88]; | |
| 3558 | assign wr_data[ 99: 96] = (red_shift_en && (red_data >= 6'd23)) ? din[ 99: 96] : din[ 95: 92]; | |
| 3559 | assign wr_data[103:100] = (red_shift_en && (red_data >= 6'd24)) ? din[103:100] : din[ 99: 96]; | |
| 3560 | assign wr_data[107:104] = (red_shift_en && (red_data >= 6'd25)) ? din[107:104] : din[103:100]; | |
| 3561 | assign wr_data[111:108] = (red_shift_en && (red_data >= 6'd26)) ? din[111:108] : din[107:104]; | |
| 3562 | assign wr_data[115:112] = (red_shift_en && (red_data >= 6'd27)) ? din[115:112] : din[111:108]; | |
| 3563 | assign wr_data[119:116] = (red_shift_en && (red_data >= 6'd28)) ? din[119:116] : din[115:112]; | |
| 3564 | assign wr_data[123:120] = (red_shift_en && (red_data >= 6'd29)) ? din[123:120] : din[119:116]; | |
| 3565 | assign wr_data[127:124] = (red_shift_en && (red_data >= 6'd30)) ? din[127:124] : din[123:120]; | |
| 3566 | assign wr_data[131:128] = (red_shift_en && (red_data >= 6'd31)) ? din[131:128] : din[127:124]; | |
| 3567 | assign wr_data[135:132] = (red_shift_en && (red_data >= 6'd32)) ? din[135:132] : din[131:128]; | |
| 3568 | assign wr_data[139:136] = (red_shift_en && (red_data >= 6'd33)) ? din[139:136] : din[135:132]; | |
| 3569 | assign wr_data[143:140] = (red_shift_en && (red_data >= 6'd34)) ? din[143:140] : din[139:136]; | |
| 3570 | assign wr_data[147:144] = (red_shift_en && (red_data >= 6'd35)) ? 4'bx : din[143:140]; | |
| 3571 | ||
| 3572 | ////////////////////// | |
| 3573 | // Write array | |
| 3574 | ////////////////////// | |
| 3575 | assign rcs_l = rd_en_b & ~wr_en_b; // read for both way0 & way1 | |
| 3576 | ||
| 3577 | always @ (negedge l1clk_wr) begin | |
| 3578 | if ((w0_wcs | w1_wcs) & ~rcs_l & vnw_ary) begin | |
| 3579 | mem[addr_b[10:4]] <= wr_data; | |
| 3580 | ||
| 3581 | ||
| 3582 | end | |
| 3583 | end | |
| 3584 | ||
| 3585 | assign temp[147:0] = mem[addr_b[10:4]]; | |
| 3586 | ||
| 3587 | ////////////////////////// | |
| 3588 | // Redundancy read shifter | |
| 3589 | ////////////////////////// | |
| 3590 | ||
| 3591 | assign local_dout[ 3: 0] = (red_shift_en && (red_data >= 6'd0 )) ? temp[ 3: 0] : temp[ 7: 4]; | |
| 3592 | assign local_dout[ 7: 4] = (red_shift_en && (red_data >= 6'd1 )) ? temp[ 7: 4] : temp[ 11: 8]; | |
| 3593 | assign local_dout[ 11: 8] = (red_shift_en && (red_data >= 6'd2 )) ? temp[ 11: 8] : temp[ 15: 12]; | |
| 3594 | assign local_dout[ 15: 12] = (red_shift_en && (red_data >= 6'd3 )) ? temp[ 15: 12] : temp[ 19: 16]; | |
| 3595 | assign local_dout[ 19: 16] = (red_shift_en && (red_data >= 6'd4 )) ? temp[ 19: 16] : temp[ 23: 20]; | |
| 3596 | assign local_dout[ 23: 20] = (red_shift_en && (red_data >= 6'd5 )) ? temp[ 23: 20] : temp[ 27: 24]; | |
| 3597 | assign local_dout[ 27: 24] = (red_shift_en && (red_data >= 6'd6 )) ? temp[ 27: 24] : temp[ 31: 28]; | |
| 3598 | assign local_dout[ 31: 28] = (red_shift_en && (red_data >= 6'd7 )) ? temp[ 31: 28] : temp[ 35: 32]; | |
| 3599 | assign local_dout[ 35: 32] = (red_shift_en && (red_data >= 6'd8 )) ? temp[ 35: 32] : temp[ 39: 36]; | |
| 3600 | assign local_dout[ 39: 36] = (red_shift_en && (red_data >= 6'd9 )) ? temp[ 39: 36] : temp[ 43: 40]; | |
| 3601 | assign local_dout[ 43: 40] = (red_shift_en && (red_data >= 6'd10)) ? temp[ 43: 40] : temp[ 47: 44]; | |
| 3602 | assign local_dout[ 47: 44] = (red_shift_en && (red_data >= 6'd11)) ? temp[ 47: 44] : temp[ 51: 48]; | |
| 3603 | assign local_dout[ 51: 48] = (red_shift_en && (red_data >= 6'd12)) ? temp[ 51: 48] : temp[ 55: 52]; | |
| 3604 | assign local_dout[ 55: 52] = (red_shift_en && (red_data >= 6'd13)) ? temp[ 55: 52] : temp[ 59: 56]; | |
| 3605 | assign local_dout[ 59: 56] = (red_shift_en && (red_data >= 6'd14)) ? temp[ 59: 56] : temp[ 63: 60]; | |
| 3606 | assign local_dout[ 63: 60] = (red_shift_en && (red_data >= 6'd15)) ? temp[ 63: 60] : temp[ 67: 64]; | |
| 3607 | assign local_dout[ 67: 64] = (red_shift_en && (red_data >= 6'd16)) ? temp[ 67: 64] : temp[ 71: 68]; | |
| 3608 | assign local_dout[ 71: 68] = (red_shift_en && (red_data >= 6'd17)) ? temp[ 71: 68] : temp[ 75: 72]; | |
| 3609 | assign local_dout[ 75: 72] = (red_shift_en && (red_data >= 6'd18)) ? temp[ 75: 72] : temp[ 79: 76]; | |
| 3610 | assign local_dout[ 79: 76] = (red_shift_en && (red_data >= 6'd19)) ? temp[ 79: 76] : temp[ 83: 80]; | |
| 3611 | assign local_dout[ 83: 80] = (red_shift_en && (red_data >= 6'd20)) ? temp[ 83: 80] : temp[ 87: 84]; | |
| 3612 | assign local_dout[ 87: 84] = (red_shift_en && (red_data >= 6'd21)) ? temp[ 87: 84] : temp[ 91: 88]; | |
| 3613 | assign local_dout[ 91: 88] = (red_shift_en && (red_data >= 6'd22)) ? temp[ 91: 88] : temp[ 95: 92]; | |
| 3614 | assign local_dout[ 95: 92] = (red_shift_en && (red_data >= 6'd23)) ? temp[ 95: 92] : temp[ 99: 96]; | |
| 3615 | assign local_dout[ 99: 96] = (red_shift_en && (red_data >= 6'd24)) ? temp[ 99: 96] : temp[103:100]; | |
| 3616 | assign local_dout[103:100] = (red_shift_en && (red_data >= 6'd25)) ? temp[103:100] : temp[107:104]; | |
| 3617 | assign local_dout[107:104] = (red_shift_en && (red_data >= 6'd26)) ? temp[107:104] : temp[111:108]; | |
| 3618 | assign local_dout[111:108] = (red_shift_en && (red_data >= 6'd27)) ? temp[111:108] : temp[115:112]; | |
| 3619 | assign local_dout[115:112] = (red_shift_en && (red_data >= 6'd28)) ? temp[115:112] : temp[119:116]; | |
| 3620 | assign local_dout[119:116] = (red_shift_en && (red_data >= 6'd29)) ? temp[119:116] : temp[123:120]; | |
| 3621 | assign local_dout[123:120] = (red_shift_en && (red_data >= 6'd30)) ? temp[123:120] : temp[127:124]; | |
| 3622 | assign local_dout[127:124] = (red_shift_en && (red_data >= 6'd31)) ? temp[127:124] : temp[131:128]; | |
| 3623 | assign local_dout[131:128] = (red_shift_en && (red_data >= 6'd32)) ? temp[131:128] : temp[135:132]; | |
| 3624 | assign local_dout[135:132] = (red_shift_en && (red_data >= 6'd33)) ? temp[135:132] : temp[139:136]; | |
| 3625 | assign local_dout[139:136] = (red_shift_en && (red_data >= 6'd34)) ? temp[139:136] : temp[143:140]; | |
| 3626 | assign local_dout[143:140] = (red_shift_en && (red_data >= 6'd35)) ? temp[143:140] : temp[147:144]; | |
| 3627 | ||
| 3628 | ////////////////////// | |
| 3629 | // Read array | |
| 3630 | ////////////////////// | |
| 3631 | always @(posedge l1clk) begin | |
| 3632 | if (rcs_l & vnw_ary) begin | |
| 3633 | if (w0_wcs | w1_wcs | wr_inh_b) | |
| 3634 | dout[143:0] <= 144'hx; | |
| 3635 | else | |
| 3636 | dout[143:0] <= local_dout[143:0]; | |
| 3637 | end | |
| 3638 | end | |
| 3639 | ||
| 3640 | // Precharge | |
| 3641 | always @(negedge l1clk) begin | |
| 3642 | dout[143:0] <= 144'h0; | |
| 3643 | end | |
| 3644 | ||
| 3645 | ////////////////////////// | |
| 3646 | // rd_data column mux | |
| 3647 | ////////////////////////// | |
| 3648 | assign w0_dout[35:0] = addr_b[3] ? | |
| 3649 | { dout[140], dout[136], dout[132], dout[128], dout[124], dout[120], | |
| 3650 | dout[116], dout[112], dout[108], dout[104], dout[100], dout[96], | |
| 3651 | dout[92], dout[88], dout[84], dout[80], dout[76], dout[72], | |
| 3652 | dout[68], dout[64], dout[60], dout[56], dout[52], dout[48], | |
| 3653 | dout[44], dout[40], dout[36], dout[32], dout[28], dout[24], | |
| 3654 | dout[20], dout[16], dout[12], dout[8], dout[4], dout[0]} : | |
| 3655 | { dout[141], dout[137], dout[133], dout[129], dout[125], dout[121], | |
| 3656 | dout[117], dout[113], dout[109], dout[105], dout[101], dout[97], | |
| 3657 | dout[93], dout[89], dout[85], dout[81], dout[77], dout[73], | |
| 3658 | dout[69], dout[65], dout[61], dout[57], dout[53], dout[49], | |
| 3659 | dout[45], dout[41], dout[37], dout[33], dout[29], dout[25], | |
| 3660 | dout[21], dout[17], dout[13], dout[9], dout[5], dout[1]} ; | |
| 3661 | ||
| 3662 | assign w1_dout[35:0] = addr_b[3] ? | |
| 3663 | { dout[142], dout[138], dout[134], dout[130], dout[126], dout[122], | |
| 3664 | dout[118], dout[114], dout[110], dout[106], dout[102], dout[98], | |
| 3665 | dout[94], dout[90], dout[86], dout[82], dout[78], dout[74], | |
| 3666 | dout[70], dout[66], dout[62], dout[58], dout[54], dout[50], | |
| 3667 | dout[46], dout[42], dout[38], dout[34], dout[30], dout[26], | |
| 3668 | dout[22], dout[18], dout[14], dout[10], dout[6], dout[2]} : | |
| 3669 | { dout[143], dout[139], dout[135], dout[131], dout[127], dout[123], | |
| 3670 | dout[119], dout[115], dout[111], dout[107], dout[103], dout[99], | |
| 3671 | dout[95], dout[91], dout[87], dout[83], dout[79], dout[75], | |
| 3672 | dout[71], dout[67], dout[63], dout[59], dout[55], dout[51], | |
| 3673 | dout[47], dout[43], dout[39], dout[35], dout[31], dout[27], | |
| 3674 | dout[23], dout[19], dout[15], dout[11], dout[7], dout[3]} ; | |
| 3675 | ||
| 3676 | // Need dual-rail at the outputs | |
| 3677 | always @(negedge l1clk or posedge wr_inh_b) begin | |
| 3678 | if (wr_inh_b) begin | |
| 3679 | w0_sao_h[35:0] <= 36'hx; | |
| 3680 | w0_sao_l[35:0] <= 36'hx; | |
| 3681 | w1_sao_h[35:0] <= 36'hx; | |
| 3682 | w1_sao_l[35:0] <= 36'hx; | |
| 3683 | end | |
| 3684 | else begin | |
| 3685 | w0_sao_h[35:0] <= w0_dout[35:0] & {36{(rd_en_a & ~wr_en_a)}}; | |
| 3686 | w0_sao_l[35:0] <= ~w0_dout[35:0] & {36{(rd_en_a & ~wr_en_a)}}; | |
| 3687 | w1_sao_h[35:0] <= w1_dout[35:0] & {36{(rd_en_a & ~wr_en_a)}}; | |
| 3688 | w1_sao_l[35:0] <= ~w1_dout[35:0] & {36{(rd_en_a & ~wr_en_a)}}; | |
| 3689 | end | |
| 3690 | end | |
| 3691 | always @(posedge l1clk or negedge rd_en_a) begin | |
| 3692 | w0_sao_h[35:0] <= 36'h0; | |
| 3693 | w0_sao_l[35:0] <= 36'h0; | |
| 3694 | w1_sao_h[35:0] <= 36'h0; | |
| 3695 | w1_sao_l[35:0] <= 36'h0; | |
| 3696 | end | |
| 3697 | ||
| 3698 | ////////////////////////// | |
| 3699 | // rd_data out mapping | |
| 3700 | ////////////////////////// | |
| 3701 | assign w0_rdata_h[35:0] = w0_sao_h[35:0] ; | |
| 3702 | assign w0_rdata_l[35:0] = w0_sao_l[35:0] ; | |
| 3703 | assign w1_rdata_h[35:0] = w1_sao_h[35:0] ; | |
| 3704 | assign w1_rdata_l[35:0] = w1_sao_l[35:0] ; | |
| 3705 | ||
| 3706 | ||
| 3707 | supply0 vss; | |
| 3708 | supply1 vdd; | |
| 3709 | ||
| 3710 | // synopsys translate_on | |
| 3711 | ||
| 3712 | endmodule | |
| 3713 | ||
| 3714 | ||
| 3715 | ||
| 3716 | ||
| 3717 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 3718 | // also for pass-gate with decoder | |
| 3719 | ||
| 3720 | ||
| 3721 | ||
| 3722 | ||
| 3723 | ||
| 3724 | // any PARAMS parms go into naming of macro | |
| 3725 | ||
| 3726 | module n2_dca_sp_9kb_cust_mux_macro__mux_aope__ports_2__width_64 ( | |
| 3727 | din0, | |
| 3728 | din1, | |
| 3729 | sel0, | |
| 3730 | dout); | |
| 3731 | wire psel0; | |
| 3732 | wire psel1; | |
| 3733 | ||
| 3734 | input [63:0] din0; | |
| 3735 | input [63:0] din1; | |
| 3736 | input sel0; | |
| 3737 | output [63:0] dout; | |
| 3738 | ||
| 3739 | ||
| 3740 | ||
| 3741 | ||
| 3742 | ||
| 3743 | cl_dp1_penc2_8x c0_0 ( | |
| 3744 | .sel0(sel0), | |
| 3745 | .psel0(psel0), | |
| 3746 | .psel1(psel1) | |
| 3747 | ); | |
| 3748 | ||
| 3749 | mux2s #(64) d0_0 ( | |
| 3750 | .sel0(psel0), | |
| 3751 | .sel1(psel1), | |
| 3752 | .in0(din0[63:0]), | |
| 3753 | .in1(din1[63:0]), | |
| 3754 | .dout(dout[63:0]) | |
| 3755 | ); | |
| 3756 | ||
| 3757 | ||
| 3758 | ||
| 3759 | ||
| 3760 | ||
| 3761 | ||
| 3762 | ||
| 3763 | ||
| 3764 | ||
| 3765 | ||
| 3766 | ||
| 3767 | ||
| 3768 | ||
| 3769 | endmodule | |
| 3770 | ||
| 3771 | ||
| 3772 | ||
| 3773 | ||
| 3774 | ||
| 3775 | ||
| 3776 | // any PARAMS parms go into naming of macro | |
| 3777 | ||
| 3778 | module n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 ( | |
| 3779 | din, | |
| 3780 | l1clk, | |
| 3781 | scan_in, | |
| 3782 | siclk, | |
| 3783 | soclk, | |
| 3784 | dout, | |
| 3785 | scan_out); | |
| 3786 | wire [7:0] fdin; | |
| 3787 | ||
| 3788 | input [7:0] din; | |
| 3789 | input l1clk; | |
| 3790 | input [7:0] scan_in; | |
| 3791 | ||
| 3792 | ||
| 3793 | input siclk; | |
| 3794 | input soclk; | |
| 3795 | ||
| 3796 | output [7:0] dout; | |
| 3797 | output [7:0] scan_out; | |
| 3798 | assign fdin[7:0] = din[7:0]; | |
| 3799 | ||
| 3800 | ||
| 3801 | ||
| 3802 | ||
| 3803 | ||
| 3804 | ||
| 3805 | dff #(8) d0_0 ( | |
| 3806 | .l1clk(l1clk), | |
| 3807 | .siclk(siclk), | |
| 3808 | .soclk(soclk), | |
| 3809 | .d(fdin[7:0]), | |
| 3810 | .si(scan_in[7:0]), | |
| 3811 | .so(scan_out[7:0]), | |
| 3812 | .q(dout[7:0]) | |
| 3813 | ); | |
| 3814 | ||
| 3815 | ||
| 3816 | ||
| 3817 | ||
| 3818 | ||
| 3819 | ||
| 3820 | ||
| 3821 | ||
| 3822 | ||
| 3823 | ||
| 3824 | ||
| 3825 | ||
| 3826 | endmodule | |
| 3827 | ||
| 3828 | ||
| 3829 | ||
| 3830 | ||
| 3831 | ||
| 3832 | ||
| 3833 | ||
| 3834 | ||
| 3835 | ||
| 3836 | ||
| 3837 | ||
| 3838 | ||
| 3839 | ||
| 3840 | // any PARAMS parms go into naming of macro | |
| 3841 | ||
| 3842 | module n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_64 ( | |
| 3843 | din, | |
| 3844 | l1clk, | |
| 3845 | scan_in, | |
| 3846 | siclk, | |
| 3847 | soclk, | |
| 3848 | dout, | |
| 3849 | scan_out); | |
| 3850 | wire [63:0] fdin; | |
| 3851 | ||
| 3852 | input [63:0] din; | |
| 3853 | input l1clk; | |
| 3854 | input [63:0] scan_in; | |
| 3855 | ||
| 3856 | ||
| 3857 | input siclk; | |
| 3858 | input soclk; | |
| 3859 | ||
| 3860 | output [63:0] dout; | |
| 3861 | output [63:0] scan_out; | |
| 3862 | assign fdin[63:0] = din[63:0]; | |
| 3863 | ||
| 3864 | ||
| 3865 | ||
| 3866 | ||
| 3867 | ||
| 3868 | ||
| 3869 | dff #(64) d0_0 ( | |
| 3870 | .l1clk(l1clk), | |
| 3871 | .siclk(siclk), | |
| 3872 | .soclk(soclk), | |
| 3873 | .d(fdin[63:0]), | |
| 3874 | .si(scan_in[63:0]), | |
| 3875 | .so(scan_out[63:0]), | |
| 3876 | .q(dout[63:0]) | |
| 3877 | ); | |
| 3878 | ||
| 3879 | ||
| 3880 | ||
| 3881 | ||
| 3882 | ||
| 3883 | ||
| 3884 | ||
| 3885 | ||
| 3886 | ||
| 3887 | ||
| 3888 | ||
| 3889 | ||
| 3890 | endmodule | |
| 3891 | ||
| 3892 | ||
| 3893 | ||
| 3894 | ||
| 3895 | ||
| 3896 | ||
| 3897 | ||
| 3898 | ||
| 3899 | ||
| 3900 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 3901 | // also for pass-gate with decoder | |
| 3902 | ||
| 3903 | ||
| 3904 | ||
| 3905 | ||
| 3906 | ||
| 3907 | // any PARAMS parms go into naming of macro | |
| 3908 | ||
| 3909 | module n2_dca_sp_9kb_cust_mux_macro__mux_aope__ports_2__width_4 ( | |
| 3910 | din0, | |
| 3911 | din1, | |
| 3912 | sel0, | |
| 3913 | dout); | |
| 3914 | wire psel0; | |
| 3915 | wire psel1; | |
| 3916 | ||
| 3917 | input [3:0] din0; | |
| 3918 | input [3:0] din1; | |
| 3919 | input sel0; | |
| 3920 | output [3:0] dout; | |
| 3921 | ||
| 3922 | ||
| 3923 | ||
| 3924 | ||
| 3925 | ||
| 3926 | cl_dp1_penc2_8x c0_0 ( | |
| 3927 | .sel0(sel0), | |
| 3928 | .psel0(psel0), | |
| 3929 | .psel1(psel1) | |
| 3930 | ); | |
| 3931 | ||
| 3932 | mux2s #(4) d0_0 ( | |
| 3933 | .sel0(psel0), | |
| 3934 | .sel1(psel1), | |
| 3935 | .in0(din0[3:0]), | |
| 3936 | .in1(din1[3:0]), | |
| 3937 | .dout(dout[3:0]) | |
| 3938 | ); | |
| 3939 | ||
| 3940 | ||
| 3941 | ||
| 3942 | ||
| 3943 | ||
| 3944 | ||
| 3945 | ||
| 3946 | ||
| 3947 | ||
| 3948 | ||
| 3949 | ||
| 3950 | ||
| 3951 | ||
| 3952 | endmodule | |
| 3953 | ||
| 3954 | ||
| 3955 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 3956 | // also for pass-gate with decoder | |
| 3957 | ||
| 3958 | ||
| 3959 | ||
| 3960 | ||
| 3961 | ||
| 3962 | // any PARAMS parms go into naming of macro | |
| 3963 | ||
| 3964 | module n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_4__width_64 ( | |
| 3965 | din0, | |
| 3966 | sel0, | |
| 3967 | din1, | |
| 3968 | sel1, | |
| 3969 | din2, | |
| 3970 | sel2, | |
| 3971 | din3, | |
| 3972 | sel3, | |
| 3973 | dout); | |
| 3974 | wire buffout0; | |
| 3975 | wire buffout1; | |
| 3976 | wire buffout2; | |
| 3977 | wire buffout3; | |
| 3978 | ||
| 3979 | input [63:0] din0; | |
| 3980 | input sel0; | |
| 3981 | input [63:0] din1; | |
| 3982 | input sel1; | |
| 3983 | input [63:0] din2; | |
| 3984 | input sel2; | |
| 3985 | input [63:0] din3; | |
| 3986 | input sel3; | |
| 3987 | output [63:0] dout; | |
| 3988 | ||
| 3989 | ||
| 3990 | ||
| 3991 | ||
| 3992 | ||
| 3993 | cl_dp1_muxbuff4_8x c0_0 ( | |
| 3994 | .in0(sel0), | |
| 3995 | .in1(sel1), | |
| 3996 | .in2(sel2), | |
| 3997 | .in3(sel3), | |
| 3998 | .out0(buffout0), | |
| 3999 | .out1(buffout1), | |
| 4000 | .out2(buffout2), | |
| 4001 | .out3(buffout3) | |
| 4002 | ); | |
| 4003 | mux4s #(64) d0_0 ( | |
| 4004 | .sel0(buffout0), | |
| 4005 | .sel1(buffout1), | |
| 4006 | .sel2(buffout2), | |
| 4007 | .sel3(buffout3), | |
| 4008 | .in0(din0[63:0]), | |
| 4009 | .in1(din1[63:0]), | |
| 4010 | .in2(din2[63:0]), | |
| 4011 | .in3(din3[63:0]), | |
| 4012 | .dout(dout[63:0]) | |
| 4013 | ); | |
| 4014 | ||
| 4015 | ||
| 4016 | ||
| 4017 | ||
| 4018 | ||
| 4019 | ||
| 4020 | ||
| 4021 | ||
| 4022 | ||
| 4023 | ||
| 4024 | ||
| 4025 | ||
| 4026 | ||
| 4027 | endmodule | |
| 4028 | ||
| 4029 | ||
| 4030 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 4031 | // also for pass-gate with decoder | |
| 4032 | ||
| 4033 | ||
| 4034 | ||
| 4035 | ||
| 4036 | ||
| 4037 | // any PARAMS parms go into naming of macro | |
| 4038 | ||
| 4039 | module n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_4__width_8 ( | |
| 4040 | din0, | |
| 4041 | sel0, | |
| 4042 | din1, | |
| 4043 | sel1, | |
| 4044 | din2, | |
| 4045 | sel2, | |
| 4046 | din3, | |
| 4047 | sel3, | |
| 4048 | dout); | |
| 4049 | wire buffout0; | |
| 4050 | wire buffout1; | |
| 4051 | wire buffout2; | |
| 4052 | wire buffout3; | |
| 4053 | ||
| 4054 | input [7:0] din0; | |
| 4055 | input sel0; | |
| 4056 | input [7:0] din1; | |
| 4057 | input sel1; | |
| 4058 | input [7:0] din2; | |
| 4059 | input sel2; | |
| 4060 | input [7:0] din3; | |
| 4061 | input sel3; | |
| 4062 | output [7:0] dout; | |
| 4063 | ||
| 4064 | ||
| 4065 | ||
| 4066 | ||
| 4067 | ||
| 4068 | cl_dp1_muxbuff4_8x c0_0 ( | |
| 4069 | .in0(sel0), | |
| 4070 | .in1(sel1), | |
| 4071 | .in2(sel2), | |
| 4072 | .in3(sel3), | |
| 4073 | .out0(buffout0), | |
| 4074 | .out1(buffout1), | |
| 4075 | .out2(buffout2), | |
| 4076 | .out3(buffout3) | |
| 4077 | ); | |
| 4078 | mux4s #(8) d0_0 ( | |
| 4079 | .sel0(buffout0), | |
| 4080 | .sel1(buffout1), | |
| 4081 | .sel2(buffout2), | |
| 4082 | .sel3(buffout3), | |
| 4083 | .in0(din0[7:0]), | |
| 4084 | .in1(din1[7:0]), | |
| 4085 | .in2(din2[7:0]), | |
| 4086 | .in3(din3[7:0]), | |
| 4087 | .dout(dout[7:0]) | |
| 4088 | ); | |
| 4089 | ||
| 4090 | ||
| 4091 | ||
| 4092 | ||
| 4093 | ||
| 4094 | ||
| 4095 | ||
| 4096 | ||
| 4097 | ||
| 4098 | ||
| 4099 | ||
| 4100 | ||
| 4101 | ||
| 4102 | endmodule | |
| 4103 | ||
| 4104 | ||
| 4105 | // | |
| 4106 | // xor macro for ports = 2,3 | |
| 4107 | // | |
| 4108 | // | |
| 4109 | ||
| 4110 | ||
| 4111 | ||
| 4112 | ||
| 4113 | ||
| 4114 | module n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 ( | |
| 4115 | din0, | |
| 4116 | din1, | |
| 4117 | din2, | |
| 4118 | dout); | |
| 4119 | input [3:0] din0; | |
| 4120 | input [3:0] din1; | |
| 4121 | input [3:0] din2; | |
| 4122 | output [3:0] dout; | |
| 4123 | ||
| 4124 | ||
| 4125 | ||
| 4126 | ||
| 4127 | ||
| 4128 | xor3 #(4) d0_0 ( | |
| 4129 | .in0(din0[3:0]), | |
| 4130 | .in1(din1[3:0]), | |
| 4131 | .in2(din2[3:0]), | |
| 4132 | .out(dout[3:0]) | |
| 4133 | ); | |
| 4134 | ||
| 4135 | ||
| 4136 | ||
| 4137 | ||
| 4138 | ||
| 4139 | ||
| 4140 | ||
| 4141 | ||
| 4142 | endmodule | |
| 4143 | ||
| 4144 | ||
| 4145 | ||
| 4146 | ||
| 4147 | ||
| 4148 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 4149 | // also for pass-gate with decoder | |
| 4150 | ||
| 4151 | ||
| 4152 | ||
| 4153 | ||
| 4154 | ||
| 4155 | // any PARAMS parms go into naming of macro | |
| 4156 | ||
| 4157 | module n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_8__width_1 ( | |
| 4158 | din0, | |
| 4159 | sel0, | |
| 4160 | din1, | |
| 4161 | sel1, | |
| 4162 | din2, | |
| 4163 | sel2, | |
| 4164 | din3, | |
| 4165 | sel3, | |
| 4166 | din4, | |
| 4167 | sel4, | |
| 4168 | din5, | |
| 4169 | sel5, | |
| 4170 | din6, | |
| 4171 | sel6, | |
| 4172 | din7, | |
| 4173 | sel7, | |
| 4174 | dout); | |
| 4175 | wire buffout0; | |
| 4176 | wire buffout1; | |
| 4177 | wire buffout2; | |
| 4178 | wire buffout3; | |
| 4179 | wire buffout4; | |
| 4180 | wire buffout5; | |
| 4181 | wire buffout6; | |
| 4182 | wire buffout7; | |
| 4183 | ||
| 4184 | input [0:0] din0; | |
| 4185 | input sel0; | |
| 4186 | input [0:0] din1; | |
| 4187 | input sel1; | |
| 4188 | input [0:0] din2; | |
| 4189 | input sel2; | |
| 4190 | input [0:0] din3; | |
| 4191 | input sel3; | |
| 4192 | input [0:0] din4; | |
| 4193 | input sel4; | |
| 4194 | input [0:0] din5; | |
| 4195 | input sel5; | |
| 4196 | input [0:0] din6; | |
| 4197 | input sel6; | |
| 4198 | input [0:0] din7; | |
| 4199 | input sel7; | |
| 4200 | output [0:0] dout; | |
| 4201 | ||
| 4202 | ||
| 4203 | ||
| 4204 | ||
| 4205 | ||
| 4206 | cl_dp1_muxbuff8_8x c0_0 ( | |
| 4207 | .in0(sel0), | |
| 4208 | .in1(sel1), | |
| 4209 | .in2(sel2), | |
| 4210 | .in3(sel3), | |
| 4211 | .in4(sel4), | |
| 4212 | .in5(sel5), | |
| 4213 | .in6(sel6), | |
| 4214 | .in7(sel7), | |
| 4215 | .out0(buffout0), | |
| 4216 | .out1(buffout1), | |
| 4217 | .out2(buffout2), | |
| 4218 | .out3(buffout3), | |
| 4219 | .out4(buffout4), | |
| 4220 | .out5(buffout5), | |
| 4221 | .out6(buffout6), | |
| 4222 | .out7(buffout7) | |
| 4223 | ); | |
| 4224 | mux8s #(1) d0_0 ( | |
| 4225 | .sel0(buffout0), | |
| 4226 | .sel1(buffout1), | |
| 4227 | .sel2(buffout2), | |
| 4228 | .sel3(buffout3), | |
| 4229 | .sel4(buffout4), | |
| 4230 | .sel5(buffout5), | |
| 4231 | .sel6(buffout6), | |
| 4232 | .sel7(buffout7), | |
| 4233 | .in0(din0[0:0]), | |
| 4234 | .in1(din1[0:0]), | |
| 4235 | .in2(din2[0:0]), | |
| 4236 | .in3(din3[0:0]), | |
| 4237 | .in4(din4[0:0]), | |
| 4238 | .in5(din5[0:0]), | |
| 4239 | .in6(din6[0:0]), | |
| 4240 | .in7(din7[0:0]), | |
| 4241 | .dout(dout[0:0]) | |
| 4242 | ); | |
| 4243 | ||
| 4244 | ||
| 4245 | ||
| 4246 | ||
| 4247 | ||
| 4248 | ||
| 4249 | ||
| 4250 | ||
| 4251 | ||
| 4252 | ||
| 4253 | ||
| 4254 | ||
| 4255 | ||
| 4256 | endmodule | |
| 4257 | ||
| 4258 | ||
| 4259 | ||
| 4260 | ||
| 4261 | ||
| 4262 | ||
| 4263 | // any PARAMS parms go into naming of macro | |
| 4264 | ||
| 4265 | module n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_12 ( | |
| 4266 | din, | |
| 4267 | l1clk, | |
| 4268 | scan_in, | |
| 4269 | siclk, | |
| 4270 | soclk, | |
| 4271 | dout, | |
| 4272 | scan_out); | |
| 4273 | wire [11:0] fdin; | |
| 4274 | ||
| 4275 | input [11:0] din; | |
| 4276 | input l1clk; | |
| 4277 | input [11:0] scan_in; | |
| 4278 | ||
| 4279 | ||
| 4280 | input siclk; | |
| 4281 | input soclk; | |
| 4282 | ||
| 4283 | output [11:0] dout; | |
| 4284 | output [11:0] scan_out; | |
| 4285 | assign fdin[11:0] = din[11:0]; | |
| 4286 | ||
| 4287 | ||
| 4288 | ||
| 4289 | ||
| 4290 | ||
| 4291 | ||
| 4292 | dff #(12) d0_0 ( | |
| 4293 | .l1clk(l1clk), | |
| 4294 | .siclk(siclk), | |
| 4295 | .soclk(soclk), | |
| 4296 | .d(fdin[11:0]), | |
| 4297 | .si(scan_in[11:0]), | |
| 4298 | .so(scan_out[11:0]), | |
| 4299 | .q(dout[11:0]) | |
| 4300 | ); | |
| 4301 | ||
| 4302 | ||
| 4303 | ||
| 4304 | ||
| 4305 | ||
| 4306 | ||
| 4307 | ||
| 4308 | ||
| 4309 | ||
| 4310 | ||
| 4311 | ||
| 4312 | ||
| 4313 | endmodule | |
| 4314 | ||
| 4315 | `endif // `ifndef FPGA | |
| 4316 | ||
| 4317 | `ifdef FPGA | |
| 4318 | /* Source file "n2_dca_sp_9kb_cust_vj.v", line 1 */ | |
| 4319 | // No timescale specified | |
| 4320 | module n2_dca_sp_9kb_cust(dcache_rd_addr_e, dcache_alt_addr_e, | |
| 4321 | dcache_alt_addr_sel_e, dcache_rvld_e, dcache_wvld_e, dcache_clk_en_e, | |
| 4322 | dcache_wclk_en_e, dcache_rclk_en_m, dcache_wdata_e, dcache_wr_way_e, | |
| 4323 | dcache_byte_wr_en_e, dcache_alt_rsel_way_m, dcache_rsel_way_b, | |
| 4324 | dcache_alt_way_sel_m, lsu_l2fill_or_byp_data_m, dcache_bypass_e_, | |
| 4325 | dcache_rdata_b, dcache_rparity_b, dcache_perr_w0_b, dcache_perr_w1_b, | |
| 4326 | dcache_perr_w2_b, dcache_perr_w3_b, dcache_rdata_msb_w0_b, | |
| 4327 | dcache_rdata_msb_w1_b, dcache_rdata_msb_w2_b, dcache_rdata_msb_w3_b, | |
| 4328 | l2clk, scan_in, tcu_pce_ov, tcu_aclk, tcu_bclk, tcu_array_wr_inhibit, | |
| 4329 | tcu_scan_en, tcu_se_scancollar_in, tcu_se_scancollar_out, scan_out, | |
| 4330 | fuse_dca_repair_value, fuse_dca_repair_en, fuse_dca_rid, fuse_dca_wen, | |
| 4331 | fuse_red_reset, dca_fuse_repair_value, dca_fuse_repair_en, vnw_ary); | |
| 4332 | ||
| 4333 | input [10:3] dcache_rd_addr_e; | |
| 4334 | input [10:3] dcache_alt_addr_e; | |
| 4335 | input dcache_alt_addr_sel_e; | |
| 4336 | input dcache_rvld_e; | |
| 4337 | input dcache_wvld_e; | |
| 4338 | input dcache_clk_en_e; | |
| 4339 | input dcache_wclk_en_e; | |
| 4340 | input dcache_rclk_en_m; | |
| 4341 | input [143:0] dcache_wdata_e; | |
| 4342 | input [1:0] dcache_wr_way_e; | |
| 4343 | input [15:0] dcache_byte_wr_en_e; | |
| 4344 | input [3:0] dcache_alt_rsel_way_m; | |
| 4345 | input [3:0] dcache_rsel_way_b; | |
| 4346 | input dcache_alt_way_sel_m; | |
| 4347 | input [63:0] lsu_l2fill_or_byp_data_m; | |
| 4348 | input dcache_bypass_e_; | |
| 4349 | output [63:0] dcache_rdata_b; | |
| 4350 | output [7:0] dcache_rparity_b; | |
| 4351 | output dcache_perr_w0_b; | |
| 4352 | output dcache_perr_w1_b; | |
| 4353 | output dcache_perr_w2_b; | |
| 4354 | output dcache_perr_w3_b; | |
| 4355 | output [7:0] dcache_rdata_msb_w0_b; | |
| 4356 | output [7:0] dcache_rdata_msb_w1_b; | |
| 4357 | output [7:0] dcache_rdata_msb_w2_b; | |
| 4358 | output [7:0] dcache_rdata_msb_w3_b; | |
| 4359 | input l2clk; | |
| 4360 | input scan_in; | |
| 4361 | input tcu_pce_ov; | |
| 4362 | input tcu_aclk; | |
| 4363 | input tcu_bclk; | |
| 4364 | input tcu_array_wr_inhibit; | |
| 4365 | input tcu_scan_en; | |
| 4366 | input tcu_se_scancollar_in; | |
| 4367 | input tcu_se_scancollar_out; | |
| 4368 | output scan_out; | |
| 4369 | input [5:0] fuse_dca_repair_value; | |
| 4370 | input [1:0] fuse_dca_repair_en; | |
| 4371 | input [1:0] fuse_dca_rid; | |
| 4372 | input fuse_dca_wen; | |
| 4373 | input fuse_red_reset; | |
| 4374 | output [5:0] dca_fuse_repair_value; | |
| 4375 | output [1:0] dca_fuse_repair_en; | |
| 4376 | input vnw_ary; | |
| 4377 | ||
| 4378 | wire l1clk_in; | |
| 4379 | wire l1clk_in_pm; | |
| 4380 | wire l1clk_out_pm; | |
| 4381 | wire l1clk_out; | |
| 4382 | wire l1clk_free; | |
| 4383 | wire l1clk_free_wpm; | |
| 4384 | wire l1clk_red; | |
| 4385 | wire [10:3] dcache_rwaddr_e; | |
| 4386 | wire [7:0] lat_addr_scanin; | |
| 4387 | wire [7:0] lat_addr_scanout; | |
| 4388 | wire [10:3] dcache_rwaddr_eb; | |
| 4389 | wire [10:3] dcache_rwaddr_l_unused; | |
| 4390 | wire [3:0] wr_way_dec_e; | |
| 4391 | wire [6:0] lat_ctl_eb_scanin; | |
| 4392 | wire [6:0] lat_ctl_eb_scanout; | |
| 4393 | wire dcache_rvld_top_eb; | |
| 4394 | wire dcache_rvld_bot_eb; | |
| 4395 | wire dcache_wvld_eb; | |
| 4396 | wire [3:0] wr_way_dec_eb; | |
| 4397 | wire [6:0] lat_ctl_unused; | |
| 4398 | wire [2:0] dff_ctl_m_0_scanin; | |
| 4399 | wire [2:0] dff_ctl_m_0_scanout; | |
| 4400 | wire dcache_rvld_m; | |
| 4401 | wire dcache_wvld_m; | |
| 4402 | wire dcache_bypass_m_; | |
| 4403 | wire [15:0] dff_ctl_m_1_scanin; | |
| 4404 | wire [15:0] dff_ctl_m_1_scanout; | |
| 4405 | wire [15:0] byte_wr_en_eb; | |
| 4406 | wire [15:0] dff_ctl_l_unused; | |
| 4407 | wire [4:0] dff_ctl_b_scanin; | |
| 4408 | wire [4:0] dff_ctl_b_scanout; | |
| 4409 | wire dcache_alt_way_sel_b; | |
| 4410 | wire [3:0] dcache_alt_rsel_way_b; | |
| 4411 | wire [143:0] dff_wdata_m_scanin; | |
| 4412 | wire [143:0] dff_wdata_m_scanout; | |
| 4413 | wire [15:0] dcache_wparity_m; | |
| 4414 | wire [127:0] dcache_wdata_m; | |
| 4415 | wire [5:0] fuse_dca_repair_value_ff; | |
| 4416 | wire [1:0] fuse_dca_repair_en_ff; | |
| 4417 | wire [1:0] fuse_dca_rid_ff; | |
| 4418 | wire fuse_dca_wen_ff; | |
| 4419 | wire fuse_red_reset_ff; | |
| 4420 | wire [5:0] dca_fuse_repair_value_pre; | |
| 4421 | wire [1:0] dca_fuse_repair_en_pre; | |
| 4422 | wire [63:0] dcache_rdata_w0_m; | |
| 4423 | wire [63:0] rdata_w0_m; | |
| 4424 | wire [63:0] rdata_w1_m; | |
| 4425 | wire [63:0] dcache_rdata_w1_m; | |
| 4426 | wire [63:0] rdata_w2_m; | |
| 4427 | wire [63:0] dcache_rdata_w2_m; | |
| 4428 | wire [63:0] rdata_w3_m; | |
| 4429 | wire [63:0] dcache_rdata_w3_m; | |
| 4430 | wire [7:0] dff_msb_w0_scanin; | |
| 4431 | wire [7:0] dff_msb_w0_scanout; | |
| 4432 | wire [7:0] dff_msb_w1_scanin; | |
| 4433 | wire [7:0] dff_msb_w1_scanout; | |
| 4434 | wire [7:0] dff_msb_w2_scanin; | |
| 4435 | wire [7:0] dff_msb_w2_scanout; | |
| 4436 | wire [7:0] dff_msb_w3_scanin; | |
| 4437 | wire [7:0] dff_msb_w3_scanout; | |
| 4438 | wire [63:0] dff_rdata_w0_m_scanin; | |
| 4439 | wire [63:0] dff_rdata_w0_m_scanout; | |
| 4440 | wire [63:0] rdata_w0_b; | |
| 4441 | wire [7:0] dff_rparity_w0_m_scanin; | |
| 4442 | wire [7:0] dff_rparity_w0_m_scanout; | |
| 4443 | wire [7:0] rparity_w0_m; | |
| 4444 | wire [7:0] rparity_w0_b; | |
| 4445 | wire [63:0] dff_rdata_w1_m_scanin; | |
| 4446 | wire [63:0] dff_rdata_w1_m_scanout; | |
| 4447 | wire [63:0] rdata_w1_b; | |
| 4448 | wire [7:0] dff_rparity_w1_m_scanin; | |
| 4449 | wire [7:0] dff_rparity_w1_m_scanout; | |
| 4450 | wire [7:0] rparity_w1_m; | |
| 4451 | wire [7:0] rparity_w1_b; | |
| 4452 | wire [63:0] dff_rdata_w2_m_scanin; | |
| 4453 | wire [63:0] dff_rdata_w2_m_scanout; | |
| 4454 | wire [63:0] rdata_w2_b; | |
| 4455 | wire [7:0] dff_rparity_w2_m_scanin; | |
| 4456 | wire [7:0] dff_rparity_w2_m_scanout; | |
| 4457 | wire [7:0] rparity_w2_m; | |
| 4458 | wire [7:0] rparity_w2_b; | |
| 4459 | wire [63:0] dff_rdata_w3_m_scanin; | |
| 4460 | wire [63:0] dff_rdata_w3_m_scanout; | |
| 4461 | wire [63:0] rdata_w3_b; | |
| 4462 | wire [7:0] dff_rparity_w3_m_scanin; | |
| 4463 | wire [7:0] dff_rparity_w3_m_scanout; | |
| 4464 | wire [7:0] rparity_w3_m; | |
| 4465 | wire [7:0] rparity_w3_b; | |
| 4466 | wire [3:0] dcache_rd_sel_way_b; | |
| 4467 | wire w0_p0_0; | |
| 4468 | wire w0_p0_1; | |
| 4469 | wire w0_p0_2; | |
| 4470 | wire [7:0] w0_parity_m; | |
| 4471 | wire w0_p1_0; | |
| 4472 | wire w0_p1_1; | |
| 4473 | wire w0_p1_2; | |
| 4474 | wire w0_p2_0; | |
| 4475 | wire w0_p2_1; | |
| 4476 | wire w0_p2_2; | |
| 4477 | wire w0_p3_0; | |
| 4478 | wire w0_p3_1; | |
| 4479 | wire w0_p3_2; | |
| 4480 | wire w0_p4_0; | |
| 4481 | wire w0_p4_1; | |
| 4482 | wire w0_p4_2; | |
| 4483 | wire w0_p5_0; | |
| 4484 | wire w0_p5_1; | |
| 4485 | wire w0_p5_2; | |
| 4486 | wire w0_p6_0; | |
| 4487 | wire w0_p6_1; | |
| 4488 | wire w0_p6_2; | |
| 4489 | wire w0_p7_0; | |
| 4490 | wire w0_p7_1; | |
| 4491 | wire w0_p7_2; | |
| 4492 | wire w1_p0_0; | |
| 4493 | wire w1_p0_1; | |
| 4494 | wire w1_p0_2; | |
| 4495 | wire [7:0] w1_parity_m; | |
| 4496 | wire w1_p1_0; | |
| 4497 | wire w1_p1_1; | |
| 4498 | wire w1_p1_2; | |
| 4499 | wire w1_p2_0; | |
| 4500 | wire w1_p2_1; | |
| 4501 | wire w1_p2_2; | |
| 4502 | wire w1_p3_0; | |
| 4503 | wire w1_p3_1; | |
| 4504 | wire w1_p3_2; | |
| 4505 | wire w1_p4_0; | |
| 4506 | wire w1_p4_1; | |
| 4507 | wire w1_p4_2; | |
| 4508 | wire w1_p5_0; | |
| 4509 | wire w1_p5_1; | |
| 4510 | wire w1_p5_2; | |
| 4511 | wire w1_p6_0; | |
| 4512 | wire w1_p6_1; | |
| 4513 | wire w1_p6_2; | |
| 4514 | wire w1_p7_0; | |
| 4515 | wire w1_p7_1; | |
| 4516 | wire w1_p7_2; | |
| 4517 | wire w2_p0_0; | |
| 4518 | wire w2_p0_1; | |
| 4519 | wire w2_p0_2; | |
| 4520 | wire [7:0] w2_parity_m; | |
| 4521 | wire w2_p1_0; | |
| 4522 | wire w2_p1_1; | |
| 4523 | wire w2_p1_2; | |
| 4524 | wire w2_p2_0; | |
| 4525 | wire w2_p2_1; | |
| 4526 | wire w2_p2_2; | |
| 4527 | wire w2_p3_0; | |
| 4528 | wire w2_p3_1; | |
| 4529 | wire w2_p3_2; | |
| 4530 | wire w2_p4_0; | |
| 4531 | wire w2_p4_1; | |
| 4532 | wire w2_p4_2; | |
| 4533 | wire w2_p5_0; | |
| 4534 | wire w2_p5_1; | |
| 4535 | wire w2_p5_2; | |
| 4536 | wire w2_p6_0; | |
| 4537 | wire w2_p6_1; | |
| 4538 | wire w2_p6_2; | |
| 4539 | wire w2_p7_0; | |
| 4540 | wire w2_p7_1; | |
| 4541 | wire w2_p7_2; | |
| 4542 | wire w3_p0_0; | |
| 4543 | wire w3_p0_1; | |
| 4544 | wire w3_p0_2; | |
| 4545 | wire [7:0] w3_parity_m; | |
| 4546 | wire w3_p1_0; | |
| 4547 | wire w3_p1_1; | |
| 4548 | wire w3_p1_2; | |
| 4549 | wire w3_p2_0; | |
| 4550 | wire w3_p2_1; | |
| 4551 | wire w3_p2_2; | |
| 4552 | wire w3_p3_0; | |
| 4553 | wire w3_p3_1; | |
| 4554 | wire w3_p3_2; | |
| 4555 | wire w3_p4_0; | |
| 4556 | wire w3_p4_1; | |
| 4557 | wire w3_p4_2; | |
| 4558 | wire w3_p5_0; | |
| 4559 | wire w3_p5_1; | |
| 4560 | wire w3_p5_2; | |
| 4561 | wire w3_p6_0; | |
| 4562 | wire w3_p6_1; | |
| 4563 | wire w3_p6_2; | |
| 4564 | wire w3_p7_0; | |
| 4565 | wire w3_p7_1; | |
| 4566 | wire w3_p7_2; | |
| 4567 | wire [7:0] dff_byte_perr_w0_scanin; | |
| 4568 | wire [7:0] dff_byte_perr_w0_scanout; | |
| 4569 | wire [7:0] w0_parity_b; | |
| 4570 | wire [7:0] dff_byte_perr_w1_scanin; | |
| 4571 | wire [7:0] dff_byte_perr_w1_scanout; | |
| 4572 | wire [7:0] w1_parity_b; | |
| 4573 | wire [7:0] dff_byte_perr_w2_scanin; | |
| 4574 | wire [7:0] dff_byte_perr_w2_scanout; | |
| 4575 | wire [7:0] w2_parity_b; | |
| 4576 | wire [7:0] dff_byte_perr_w3_scanin; | |
| 4577 | wire [7:0] dff_byte_perr_w3_scanout; | |
| 4578 | wire [7:0] w3_parity_b; | |
| 4579 | wire w0_parity_err_b; | |
| 4580 | wire w1_parity_err_b; | |
| 4581 | wire w2_parity_err_b; | |
| 4582 | wire w3_parity_err_b; | |
| 4583 | wire [11:0] dff_red_in_scanin; | |
| 4584 | wire [11:0] dff_red_in_scanout; | |
| 4585 | wire [7:0] dff_red_out_scanin; | |
| 4586 | wire [7:0] dff_red_out_scanout; | |
| 4587 | wire pce_ov = tcu_pce_ov; | |
| 4588 | wire stop = 1'b0; | |
| 4589 | wire siclk = tcu_aclk; | |
| 4590 | wire soclk = tcu_bclk; | |
| 4591 | supply0 vss; | |
| 4592 | supply1 vdd; | |
| 4593 | ||
| 4594 | assign rdata_w1_m[63:0] = dcache_rdata_w1_m[63:0]; | |
| 4595 | assign rdata_w2_m[63:0] = dcache_rdata_w2_m[63:0]; | |
| 4596 | assign rdata_w3_m[63:0] = dcache_rdata_w3_m[63:0]; | |
| 4597 | assign dcache_perr_w0_b = w0_parity_err_b; | |
| 4598 | assign dcache_perr_w1_b = w1_parity_err_b; | |
| 4599 | assign dcache_perr_w2_b = w2_parity_err_b; | |
| 4600 | assign dcache_perr_w3_b = w3_parity_err_b; | |
| 4601 | assign dff_byte_perr_w0_scanin[7] = scan_in; | |
| 4602 | assign dff_byte_perr_w1_scanin[7] = dff_byte_perr_w0_scanout[7]; | |
| 4603 | assign dff_byte_perr_w1_scanin[6] = dff_byte_perr_w1_scanout[7]; | |
| 4604 | assign dff_byte_perr_w0_scanin[6] = dff_byte_perr_w1_scanout[6]; | |
| 4605 | assign dff_byte_perr_w0_scanin[5] = dff_byte_perr_w0_scanout[6]; | |
| 4606 | assign dff_byte_perr_w1_scanin[5] = dff_byte_perr_w0_scanout[5]; | |
| 4607 | assign dff_byte_perr_w1_scanin[4] = dff_byte_perr_w1_scanout[5]; | |
| 4608 | assign dff_byte_perr_w0_scanin[4] = dff_byte_perr_w1_scanout[4]; | |
| 4609 | assign dff_wdata_m_scanin[143] = dff_byte_perr_w0_scanout[4]; | |
| 4610 | assign dff_wdata_m_scanin[71] = dff_wdata_m_scanout[143]; | |
| 4611 | assign dff_rparity_w3_m_scanin[7] = dff_wdata_m_scanout[71]; | |
| 4612 | assign dff_rparity_w2_m_scanin[7] = dff_rparity_w3_m_scanout[7]; | |
| 4613 | assign dff_rparity_w1_m_scanin[7] = dff_rparity_w2_m_scanout[7]; | |
| 4614 | assign dff_rparity_w0_m_scanin[7] = dff_rparity_w1_m_scanout[7]; | |
| 4615 | assign dff_wdata_m_scanin[134] = dff_rparity_w0_m_scanout[7]; | |
| 4616 | assign dff_wdata_m_scanin[62] = dff_wdata_m_scanout[134]; | |
| 4617 | assign dff_rparity_w3_m_scanin[6] = dff_wdata_m_scanout[62]; | |
| 4618 | assign dff_rparity_w2_m_scanin[6] = dff_rparity_w3_m_scanout[6]; | |
| 4619 | assign dff_rparity_w1_m_scanin[6] = dff_rparity_w2_m_scanout[6]; | |
| 4620 | assign dff_rparity_w0_m_scanin[6] = dff_rparity_w1_m_scanout[6]; | |
| 4621 | assign dff_wdata_m_scanin[142] = dff_rparity_w0_m_scanout[6]; | |
| 4622 | assign dff_wdata_m_scanin[70] = dff_wdata_m_scanout[142]; | |
| 4623 | assign dff_rdata_w3_m_scanin[63] = dff_wdata_m_scanout[70]; | |
| 4624 | assign dff_rdata_w2_m_scanin[63] = dff_rdata_w3_m_scanout[63]; | |
| 4625 | assign dff_rdata_w1_m_scanin[63] = dff_rdata_w2_m_scanout[63]; | |
| 4626 | assign dff_rdata_w0_m_scanin[63] = dff_rdata_w1_m_scanout[63]; | |
| 4627 | assign dff_wdata_m_scanin[133] = dff_rdata_w0_m_scanout[63]; | |
| 4628 | assign dff_wdata_m_scanin[61] = dff_wdata_m_scanout[133]; | |
| 4629 | assign dff_rdata_w3_m_scanin[55] = dff_wdata_m_scanout[61]; | |
| 4630 | assign dff_rdata_w2_m_scanin[55] = dff_rdata_w3_m_scanout[55]; | |
| 4631 | assign dff_rdata_w1_m_scanin[55] = dff_rdata_w2_m_scanout[55]; | |
| 4632 | assign dff_rdata_w0_m_scanin[55] = dff_rdata_w1_m_scanout[55]; | |
| 4633 | assign dff_wdata_m_scanin[141] = dff_rdata_w0_m_scanout[55]; | |
| 4634 | assign dff_wdata_m_scanin[69] = dff_wdata_m_scanout[141]; | |
| 4635 | assign dff_rdata_w3_m_scanin[62] = dff_wdata_m_scanout[69]; | |
| 4636 | assign dff_rdata_w2_m_scanin[62] = dff_rdata_w3_m_scanout[62]; | |
| 4637 | assign dff_rdata_w1_m_scanin[62] = dff_rdata_w2_m_scanout[62]; | |
| 4638 | assign dff_rdata_w0_m_scanin[62] = dff_rdata_w1_m_scanout[62]; | |
| 4639 | assign dff_wdata_m_scanin[132] = dff_rdata_w0_m_scanout[62]; | |
| 4640 | assign dff_wdata_m_scanin[60] = dff_wdata_m_scanout[132]; | |
| 4641 | assign dff_rdata_w3_m_scanin[54] = dff_wdata_m_scanout[60]; | |
| 4642 | assign dff_rdata_w2_m_scanin[54] = dff_rdata_w3_m_scanout[54]; | |
| 4643 | assign dff_rdata_w1_m_scanin[54] = dff_rdata_w2_m_scanout[54]; | |
| 4644 | assign dff_rdata_w0_m_scanin[54] = dff_rdata_w1_m_scanout[54]; | |
| 4645 | assign dff_wdata_m_scanin[140] = dff_rdata_w0_m_scanout[54]; | |
| 4646 | assign dff_wdata_m_scanin[68] = dff_wdata_m_scanout[140]; | |
| 4647 | assign dff_rdata_w3_m_scanin[61] = dff_wdata_m_scanout[68]; | |
| 4648 | assign dff_rdata_w2_m_scanin[61] = dff_rdata_w3_m_scanout[61]; | |
| 4649 | assign dff_rdata_w1_m_scanin[61] = dff_rdata_w2_m_scanout[61]; | |
| 4650 | assign dff_rdata_w0_m_scanin[61] = dff_rdata_w1_m_scanout[61]; | |
| 4651 | assign dff_wdata_m_scanin[131] = dff_rdata_w0_m_scanout[61]; | |
| 4652 | assign dff_wdata_m_scanin[59] = dff_wdata_m_scanout[131]; | |
| 4653 | assign dff_rdata_w3_m_scanin[53] = dff_wdata_m_scanout[59]; | |
| 4654 | assign dff_rdata_w2_m_scanin[53] = dff_rdata_w3_m_scanout[53]; | |
| 4655 | assign dff_rdata_w1_m_scanin[53] = dff_rdata_w2_m_scanout[53]; | |
| 4656 | assign dff_rdata_w0_m_scanin[53] = dff_rdata_w1_m_scanout[53]; | |
| 4657 | assign dff_wdata_m_scanin[139] = dff_rdata_w0_m_scanout[53]; | |
| 4658 | assign dff_wdata_m_scanin[67] = dff_wdata_m_scanout[139]; | |
| 4659 | assign dff_rdata_w3_m_scanin[60] = dff_wdata_m_scanout[67]; | |
| 4660 | assign dff_rdata_w2_m_scanin[60] = dff_rdata_w3_m_scanout[60]; | |
| 4661 | assign dff_rdata_w1_m_scanin[60] = dff_rdata_w2_m_scanout[60]; | |
| 4662 | assign dff_rdata_w0_m_scanin[60] = dff_rdata_w1_m_scanout[60]; | |
| 4663 | assign dff_wdata_m_scanin[130] = dff_rdata_w0_m_scanout[60]; | |
| 4664 | assign dff_wdata_m_scanin[58] = dff_wdata_m_scanout[130]; | |
| 4665 | assign dff_rdata_w3_m_scanin[52] = dff_wdata_m_scanout[58]; | |
| 4666 | assign dff_rdata_w2_m_scanin[52] = dff_rdata_w3_m_scanout[52]; | |
| 4667 | assign dff_rdata_w1_m_scanin[52] = dff_rdata_w2_m_scanout[52]; | |
| 4668 | assign dff_rdata_w0_m_scanin[52] = dff_rdata_w1_m_scanout[52]; | |
| 4669 | assign dff_wdata_m_scanin[138] = dff_rdata_w0_m_scanout[52]; | |
| 4670 | assign dff_wdata_m_scanin[66] = dff_wdata_m_scanout[138]; | |
| 4671 | assign dff_rdata_w3_m_scanin[59] = dff_wdata_m_scanout[66]; | |
| 4672 | assign dff_rdata_w2_m_scanin[59] = dff_rdata_w3_m_scanout[59]; | |
| 4673 | assign dff_rdata_w1_m_scanin[59] = dff_rdata_w2_m_scanout[59]; | |
| 4674 | assign dff_rdata_w0_m_scanin[59] = dff_rdata_w1_m_scanout[59]; | |
| 4675 | assign dff_wdata_m_scanin[129] = dff_rdata_w0_m_scanout[59]; | |
| 4676 | assign dff_wdata_m_scanin[57] = dff_wdata_m_scanout[129]; | |
| 4677 | assign dff_rdata_w3_m_scanin[51] = dff_wdata_m_scanout[57]; | |
| 4678 | assign dff_rdata_w2_m_scanin[51] = dff_rdata_w3_m_scanout[51]; | |
| 4679 | assign dff_rdata_w1_m_scanin[51] = dff_rdata_w2_m_scanout[51]; | |
| 4680 | assign dff_rdata_w0_m_scanin[51] = dff_rdata_w1_m_scanout[51]; | |
| 4681 | assign dff_wdata_m_scanin[137] = dff_rdata_w0_m_scanout[51]; | |
| 4682 | assign dff_wdata_m_scanin[65] = dff_wdata_m_scanout[137]; | |
| 4683 | assign dff_rdata_w3_m_scanin[58] = dff_wdata_m_scanout[65]; | |
| 4684 | assign dff_rdata_w2_m_scanin[58] = dff_rdata_w3_m_scanout[58]; | |
| 4685 | assign dff_rdata_w1_m_scanin[58] = dff_rdata_w2_m_scanout[58]; | |
| 4686 | assign dff_rdata_w0_m_scanin[58] = dff_rdata_w1_m_scanout[58]; | |
| 4687 | assign dff_wdata_m_scanin[128] = dff_rdata_w0_m_scanout[58]; | |
| 4688 | assign dff_wdata_m_scanin[56] = dff_wdata_m_scanout[128]; | |
| 4689 | assign dff_rdata_w3_m_scanin[50] = dff_wdata_m_scanout[56]; | |
| 4690 | assign dff_rdata_w2_m_scanin[50] = dff_rdata_w3_m_scanout[50]; | |
| 4691 | assign dff_rdata_w1_m_scanin[50] = dff_rdata_w2_m_scanout[50]; | |
| 4692 | assign dff_rdata_w0_m_scanin[50] = dff_rdata_w1_m_scanout[50]; | |
| 4693 | assign dff_wdata_m_scanin[136] = dff_rdata_w0_m_scanout[50]; | |
| 4694 | assign dff_wdata_m_scanin[64] = dff_wdata_m_scanout[136]; | |
| 4695 | assign dff_rdata_w3_m_scanin[57] = dff_wdata_m_scanout[64]; | |
| 4696 | assign dff_rdata_w2_m_scanin[57] = dff_rdata_w3_m_scanout[57]; | |
| 4697 | assign dff_rdata_w1_m_scanin[57] = dff_rdata_w2_m_scanout[57]; | |
| 4698 | assign dff_rdata_w0_m_scanin[57] = dff_rdata_w1_m_scanout[57]; | |
| 4699 | assign dff_wdata_m_scanin[127] = dff_rdata_w0_m_scanout[57]; | |
| 4700 | assign dff_wdata_m_scanin[55] = dff_wdata_m_scanout[127]; | |
| 4701 | assign dff_rdata_w3_m_scanin[49] = dff_wdata_m_scanout[55]; | |
| 4702 | assign dff_rdata_w2_m_scanin[49] = dff_rdata_w3_m_scanout[49]; | |
| 4703 | assign dff_rdata_w1_m_scanin[49] = dff_rdata_w2_m_scanout[49]; | |
| 4704 | assign dff_rdata_w0_m_scanin[49] = dff_rdata_w1_m_scanout[49]; | |
| 4705 | assign dff_wdata_m_scanin[135] = dff_rdata_w0_m_scanout[49]; | |
| 4706 | assign dff_wdata_m_scanin[63] = dff_wdata_m_scanout[135]; | |
| 4707 | assign dff_rdata_w3_m_scanin[56] = dff_wdata_m_scanout[63]; | |
| 4708 | assign dff_rdata_w2_m_scanin[56] = dff_rdata_w3_m_scanout[56]; | |
| 4709 | assign dff_rdata_w1_m_scanin[56] = dff_rdata_w2_m_scanout[56]; | |
| 4710 | assign dff_rdata_w0_m_scanin[56] = dff_rdata_w1_m_scanout[56]; | |
| 4711 | assign dff_wdata_m_scanin[126] = dff_rdata_w0_m_scanout[56]; | |
| 4712 | assign dff_wdata_m_scanin[54] = dff_wdata_m_scanout[126]; | |
| 4713 | assign dff_rdata_w3_m_scanin[48] = dff_wdata_m_scanout[54]; | |
| 4714 | assign dff_rdata_w2_m_scanin[48] = dff_rdata_w3_m_scanout[48]; | |
| 4715 | assign dff_rdata_w1_m_scanin[48] = dff_rdata_w2_m_scanout[48]; | |
| 4716 | assign dff_rdata_w0_m_scanin[48] = dff_rdata_w1_m_scanout[48]; | |
| 4717 | assign dff_wdata_m_scanin[125] = dff_rdata_w0_m_scanout[48]; | |
| 4718 | assign dff_wdata_m_scanin[53] = dff_wdata_m_scanout[125]; | |
| 4719 | assign dff_rparity_w3_m_scanin[5] = dff_wdata_m_scanout[53]; | |
| 4720 | assign dff_rparity_w2_m_scanin[5] = dff_rparity_w3_m_scanout[5]; | |
| 4721 | assign dff_rparity_w1_m_scanin[5] = dff_rparity_w2_m_scanout[5]; | |
| 4722 | assign dff_rparity_w0_m_scanin[5] = dff_rparity_w1_m_scanout[5]; | |
| 4723 | assign dff_wdata_m_scanin[116] = dff_rparity_w0_m_scanout[5]; | |
| 4724 | assign dff_wdata_m_scanin[44] = dff_wdata_m_scanout[116]; | |
| 4725 | assign dff_rparity_w3_m_scanin[4] = dff_wdata_m_scanout[44]; | |
| 4726 | assign dff_rparity_w2_m_scanin[4] = dff_rparity_w3_m_scanout[4]; | |
| 4727 | assign dff_rparity_w1_m_scanin[4] = dff_rparity_w2_m_scanout[4]; | |
| 4728 | assign dff_rparity_w0_m_scanin[4] = dff_rparity_w1_m_scanout[4]; | |
| 4729 | assign dff_wdata_m_scanin[124] = dff_rparity_w0_m_scanout[4]; | |
| 4730 | assign dff_wdata_m_scanin[52] = dff_wdata_m_scanout[124]; | |
| 4731 | assign dff_rdata_w3_m_scanin[47] = dff_wdata_m_scanout[52]; | |
| 4732 | assign dff_rdata_w2_m_scanin[47] = dff_rdata_w3_m_scanout[47]; | |
| 4733 | assign dff_rdata_w1_m_scanin[47] = dff_rdata_w2_m_scanout[47]; | |
| 4734 | assign dff_rdata_w0_m_scanin[47] = dff_rdata_w1_m_scanout[47]; | |
| 4735 | assign dff_wdata_m_scanin[115] = dff_rdata_w0_m_scanout[47]; | |
| 4736 | assign dff_wdata_m_scanin[43] = dff_wdata_m_scanout[115]; | |
| 4737 | assign dff_rdata_w3_m_scanin[39] = dff_wdata_m_scanout[43]; | |
| 4738 | assign dff_rdata_w2_m_scanin[39] = dff_rdata_w3_m_scanout[39]; | |
| 4739 | assign dff_rdata_w1_m_scanin[39] = dff_rdata_w2_m_scanout[39]; | |
| 4740 | assign dff_rdata_w0_m_scanin[39] = dff_rdata_w1_m_scanout[39]; | |
| 4741 | assign dff_wdata_m_scanin[123] = dff_rdata_w0_m_scanout[39]; | |
| 4742 | assign dff_wdata_m_scanin[51] = dff_wdata_m_scanout[123]; | |
| 4743 | assign dff_rdata_w3_m_scanin[46] = dff_wdata_m_scanout[51]; | |
| 4744 | assign dff_rdata_w2_m_scanin[46] = dff_rdata_w3_m_scanout[46]; | |
| 4745 | assign dff_rdata_w1_m_scanin[46] = dff_rdata_w2_m_scanout[46]; | |
| 4746 | assign dff_rdata_w0_m_scanin[46] = dff_rdata_w1_m_scanout[46]; | |
| 4747 | assign dff_wdata_m_scanin[114] = dff_rdata_w0_m_scanout[46]; | |
| 4748 | assign dff_wdata_m_scanin[42] = dff_wdata_m_scanout[114]; | |
| 4749 | assign dff_rdata_w3_m_scanin[38] = dff_wdata_m_scanout[42]; | |
| 4750 | assign dff_rdata_w2_m_scanin[38] = dff_rdata_w3_m_scanout[38]; | |
| 4751 | assign dff_rdata_w1_m_scanin[38] = dff_rdata_w2_m_scanout[38]; | |
| 4752 | assign dff_rdata_w0_m_scanin[38] = dff_rdata_w1_m_scanout[38]; | |
| 4753 | assign dff_wdata_m_scanin[122] = dff_rdata_w0_m_scanout[38]; | |
| 4754 | assign dff_wdata_m_scanin[50] = dff_wdata_m_scanout[122]; | |
| 4755 | assign dff_rdata_w3_m_scanin[45] = dff_wdata_m_scanout[50]; | |
| 4756 | assign dff_rdata_w2_m_scanin[45] = dff_rdata_w3_m_scanout[45]; | |
| 4757 | assign dff_rdata_w1_m_scanin[45] = dff_rdata_w2_m_scanout[45]; | |
| 4758 | assign dff_rdata_w0_m_scanin[45] = dff_rdata_w1_m_scanout[45]; | |
| 4759 | assign dff_wdata_m_scanin[113] = dff_rdata_w0_m_scanout[45]; | |
| 4760 | assign dff_wdata_m_scanin[41] = dff_wdata_m_scanout[113]; | |
| 4761 | assign dff_rdata_w3_m_scanin[37] = dff_wdata_m_scanout[41]; | |
| 4762 | assign dff_rdata_w2_m_scanin[37] = dff_rdata_w3_m_scanout[37]; | |
| 4763 | assign dff_rdata_w1_m_scanin[37] = dff_rdata_w2_m_scanout[37]; | |
| 4764 | assign dff_rdata_w0_m_scanin[37] = dff_rdata_w1_m_scanout[37]; | |
| 4765 | assign dff_wdata_m_scanin[121] = dff_rdata_w0_m_scanout[37]; | |
| 4766 | assign dff_wdata_m_scanin[49] = dff_wdata_m_scanout[121]; | |
| 4767 | assign dff_rdata_w3_m_scanin[44] = dff_wdata_m_scanout[49]; | |
| 4768 | assign dff_rdata_w2_m_scanin[44] = dff_rdata_w3_m_scanout[44]; | |
| 4769 | assign dff_rdata_w1_m_scanin[44] = dff_rdata_w2_m_scanout[44]; | |
| 4770 | assign dff_rdata_w0_m_scanin[44] = dff_rdata_w1_m_scanout[44]; | |
| 4771 | assign dff_wdata_m_scanin[112] = dff_rdata_w0_m_scanout[44]; | |
| 4772 | assign dff_wdata_m_scanin[40] = dff_wdata_m_scanout[112]; | |
| 4773 | assign dff_rdata_w3_m_scanin[36] = dff_wdata_m_scanout[40]; | |
| 4774 | assign dff_rdata_w2_m_scanin[36] = dff_rdata_w3_m_scanout[36]; | |
| 4775 | assign dff_rdata_w1_m_scanin[36] = dff_rdata_w2_m_scanout[36]; | |
| 4776 | assign dff_rdata_w0_m_scanin[36] = dff_rdata_w1_m_scanout[36]; | |
| 4777 | assign dff_wdata_m_scanin[120] = dff_rdata_w0_m_scanout[36]; | |
| 4778 | assign dff_wdata_m_scanin[48] = dff_wdata_m_scanout[120]; | |
| 4779 | assign dff_rdata_w3_m_scanin[43] = dff_wdata_m_scanout[48]; | |
| 4780 | assign dff_rdata_w2_m_scanin[43] = dff_rdata_w3_m_scanout[43]; | |
| 4781 | assign dff_rdata_w1_m_scanin[43] = dff_rdata_w2_m_scanout[43]; | |
| 4782 | assign dff_rdata_w0_m_scanin[43] = dff_rdata_w1_m_scanout[43]; | |
| 4783 | assign dff_wdata_m_scanin[111] = dff_rdata_w0_m_scanout[43]; | |
| 4784 | assign dff_wdata_m_scanin[39] = dff_wdata_m_scanout[111]; | |
| 4785 | assign dff_rdata_w3_m_scanin[35] = dff_wdata_m_scanout[39]; | |
| 4786 | assign dff_rdata_w2_m_scanin[35] = dff_rdata_w3_m_scanout[35]; | |
| 4787 | assign dff_rdata_w1_m_scanin[35] = dff_rdata_w2_m_scanout[35]; | |
| 4788 | assign dff_rdata_w0_m_scanin[35] = dff_rdata_w1_m_scanout[35]; | |
| 4789 | assign dff_wdata_m_scanin[119] = dff_rdata_w0_m_scanout[35]; | |
| 4790 | assign dff_wdata_m_scanin[47] = dff_wdata_m_scanout[119]; | |
| 4791 | assign dff_rdata_w3_m_scanin[42] = dff_wdata_m_scanout[47]; | |
| 4792 | assign dff_rdata_w2_m_scanin[42] = dff_rdata_w3_m_scanout[42]; | |
| 4793 | assign dff_rdata_w1_m_scanin[42] = dff_rdata_w2_m_scanout[42]; | |
| 4794 | assign dff_rdata_w0_m_scanin[42] = dff_rdata_w1_m_scanout[42]; | |
| 4795 | assign dff_wdata_m_scanin[110] = dff_rdata_w0_m_scanout[42]; | |
| 4796 | assign dff_wdata_m_scanin[38] = dff_wdata_m_scanout[110]; | |
| 4797 | assign dff_rdata_w3_m_scanin[34] = dff_wdata_m_scanout[38]; | |
| 4798 | assign dff_rdata_w2_m_scanin[34] = dff_rdata_w3_m_scanout[34]; | |
| 4799 | assign dff_rdata_w1_m_scanin[34] = dff_rdata_w2_m_scanout[34]; | |
| 4800 | assign dff_rdata_w0_m_scanin[34] = dff_rdata_w1_m_scanout[34]; | |
| 4801 | assign dff_wdata_m_scanin[118] = dff_rdata_w0_m_scanout[34]; | |
| 4802 | assign dff_wdata_m_scanin[46] = dff_wdata_m_scanout[118]; | |
| 4803 | assign dff_rdata_w3_m_scanin[41] = dff_wdata_m_scanout[46]; | |
| 4804 | assign dff_rdata_w2_m_scanin[41] = dff_rdata_w3_m_scanout[41]; | |
| 4805 | assign dff_rdata_w1_m_scanin[41] = dff_rdata_w2_m_scanout[41]; | |
| 4806 | assign dff_rdata_w0_m_scanin[41] = dff_rdata_w1_m_scanout[41]; | |
| 4807 | assign dff_wdata_m_scanin[109] = dff_rdata_w0_m_scanout[41]; | |
| 4808 | assign dff_wdata_m_scanin[37] = dff_wdata_m_scanout[109]; | |
| 4809 | assign dff_rdata_w3_m_scanin[33] = dff_wdata_m_scanout[37]; | |
| 4810 | assign dff_rdata_w2_m_scanin[33] = dff_rdata_w3_m_scanout[33]; | |
| 4811 | assign dff_rdata_w1_m_scanin[33] = dff_rdata_w2_m_scanout[33]; | |
| 4812 | assign dff_rdata_w0_m_scanin[33] = dff_rdata_w1_m_scanout[33]; | |
| 4813 | assign dff_wdata_m_scanin[117] = dff_rdata_w0_m_scanout[33]; | |
| 4814 | assign dff_wdata_m_scanin[45] = dff_wdata_m_scanout[117]; | |
| 4815 | assign dff_rdata_w3_m_scanin[40] = dff_wdata_m_scanout[45]; | |
| 4816 | assign dff_rdata_w2_m_scanin[40] = dff_rdata_w3_m_scanout[40]; | |
| 4817 | assign dff_rdata_w1_m_scanin[40] = dff_rdata_w2_m_scanout[40]; | |
| 4818 | assign dff_rdata_w0_m_scanin[40] = dff_rdata_w1_m_scanout[40]; | |
| 4819 | assign dff_wdata_m_scanin[108] = dff_rdata_w0_m_scanout[40]; | |
| 4820 | assign dff_wdata_m_scanin[36] = dff_wdata_m_scanout[108]; | |
| 4821 | assign dff_rdata_w3_m_scanin[32] = dff_wdata_m_scanout[36]; | |
| 4822 | assign dff_rdata_w2_m_scanin[32] = dff_rdata_w3_m_scanout[32]; | |
| 4823 | assign dff_rdata_w1_m_scanin[32] = dff_rdata_w2_m_scanout[32]; | |
| 4824 | assign dff_rdata_w0_m_scanin[32] = dff_rdata_w1_m_scanout[32]; | |
| 4825 | assign dff_ctl_m_1_scanin[15] = dff_rdata_w0_m_scanout[32]; | |
| 4826 | assign dff_ctl_m_1_scanin[7] = dff_ctl_m_1_scanout[15]; | |
| 4827 | assign dff_ctl_m_1_scanin[14] = dff_ctl_m_1_scanout[7]; | |
| 4828 | assign dff_ctl_m_1_scanin[6] = dff_ctl_m_1_scanout[14]; | |
| 4829 | assign dff_ctl_m_1_scanin[13] = dff_ctl_m_1_scanout[6]; | |
| 4830 | assign dff_ctl_m_1_scanin[5] = dff_ctl_m_1_scanout[13]; | |
| 4831 | assign dff_ctl_m_1_scanin[12] = dff_ctl_m_1_scanout[5]; | |
| 4832 | assign dff_ctl_m_1_scanin[4] = dff_ctl_m_1_scanout[12]; | |
| 4833 | assign dff_byte_perr_w2_scanin[7] = dff_ctl_m_1_scanout[4]; | |
| 4834 | assign dff_byte_perr_w3_scanin[7] = dff_byte_perr_w2_scanout[7]; | |
| 4835 | assign dff_byte_perr_w3_scanin[6] = dff_byte_perr_w3_scanout[7]; | |
| 4836 | assign dff_byte_perr_w2_scanin[6] = dff_byte_perr_w3_scanout[6]; | |
| 4837 | assign dff_byte_perr_w2_scanin[5] = dff_byte_perr_w2_scanout[6]; | |
| 4838 | assign dff_byte_perr_w3_scanin[5] = dff_byte_perr_w2_scanout[5]; | |
| 4839 | assign dff_byte_perr_w3_scanin[4] = dff_byte_perr_w3_scanout[5]; | |
| 4840 | assign dff_byte_perr_w2_scanin[4] = dff_byte_perr_w3_scanout[4]; | |
| 4841 | assign dff_ctl_m_0_scanin[0] = dff_byte_perr_w2_scanout[4]; | |
| 4842 | assign dff_ctl_b_scanin[4] = dff_ctl_m_0_scanout[0]; | |
| 4843 | assign dff_ctl_b_scanin[0] = dff_ctl_b_scanout[4]; | |
| 4844 | assign dff_ctl_b_scanin[1] = dff_ctl_b_scanout[0]; | |
| 4845 | assign dff_ctl_b_scanin[2] = dff_ctl_b_scanout[1]; | |
| 4846 | assign dff_ctl_b_scanin[3] = dff_ctl_b_scanout[2]; | |
| 4847 | assign lat_ctl_eb_scanin[6] = dff_ctl_b_scanout[3]; | |
| 4848 | assign lat_ctl_eb_scanin[1] = lat_ctl_eb_scanout[6]; | |
| 4849 | assign lat_ctl_eb_scanin[0] = lat_ctl_eb_scanout[1]; | |
| 4850 | assign lat_ctl_eb_scanin[2] = lat_ctl_eb_scanout[0]; | |
| 4851 | assign lat_ctl_eb_scanin[3] = lat_ctl_eb_scanout[2]; | |
| 4852 | assign lat_addr_scanin[1] = lat_ctl_eb_scanout[3]; | |
| 4853 | assign lat_addr_scanin[0] = lat_addr_scanout[1]; | |
| 4854 | assign lat_addr_scanin[7] = lat_addr_scanout[0]; | |
| 4855 | assign lat_addr_scanin[6] = lat_addr_scanout[7]; | |
| 4856 | assign lat_addr_scanin[5] = lat_addr_scanout[6]; | |
| 4857 | assign lat_addr_scanin[4] = lat_addr_scanout[5]; | |
| 4858 | assign lat_addr_scanin[3] = lat_addr_scanout[4]; | |
| 4859 | assign lat_addr_scanin[2] = lat_addr_scanout[3]; | |
| 4860 | assign lat_ctl_eb_scanin[4] = lat_addr_scanout[2]; | |
| 4861 | assign dff_ctl_m_0_scanin[1] = lat_ctl_eb_scanout[4]; | |
| 4862 | assign dff_ctl_m_0_scanin[2] = dff_ctl_m_0_scanout[1]; | |
| 4863 | assign lat_ctl_eb_scanin[5] = dff_ctl_m_0_scanout[2]; | |
| 4864 | assign dff_byte_perr_w0_scanin[0] = lat_ctl_eb_scanout[5]; | |
| 4865 | assign dff_byte_perr_w1_scanin[0] = dff_byte_perr_w0_scanout[0]; | |
| 4866 | assign dff_byte_perr_w1_scanin[1] = dff_byte_perr_w1_scanout[0]; | |
| 4867 | assign dff_byte_perr_w0_scanin[1] = dff_byte_perr_w1_scanout[1]; | |
| 4868 | assign dff_byte_perr_w0_scanin[2] = dff_byte_perr_w0_scanout[1]; | |
| 4869 | assign dff_byte_perr_w1_scanin[2] = dff_byte_perr_w0_scanout[2]; | |
| 4870 | assign dff_byte_perr_w1_scanin[3] = dff_byte_perr_w1_scanout[2]; | |
| 4871 | assign dff_byte_perr_w0_scanin[3] = dff_byte_perr_w1_scanout[3]; | |
| 4872 | assign dff_wdata_m_scanin[80] = dff_byte_perr_w0_scanout[3]; | |
| 4873 | assign dff_wdata_m_scanin[8] = dff_wdata_m_scanout[80]; | |
| 4874 | assign dff_rparity_w3_m_scanin[0] = dff_wdata_m_scanout[8]; | |
| 4875 | assign dff_rparity_w2_m_scanin[0] = dff_rparity_w3_m_scanout[0]; | |
| 4876 | assign dff_rparity_w1_m_scanin[0] = dff_rparity_w2_m_scanout[0]; | |
| 4877 | assign dff_rparity_w0_m_scanin[0] = dff_rparity_w1_m_scanout[0]; | |
| 4878 | assign dff_wdata_m_scanin[89] = dff_rparity_w0_m_scanout[0]; | |
| 4879 | assign dff_wdata_m_scanin[17] = dff_wdata_m_scanout[89]; | |
| 4880 | assign dff_rparity_w3_m_scanin[1] = dff_wdata_m_scanout[17]; | |
| 4881 | assign dff_rparity_w2_m_scanin[1] = dff_rparity_w3_m_scanout[1]; | |
| 4882 | assign dff_rparity_w1_m_scanin[1] = dff_rparity_w2_m_scanout[1]; | |
| 4883 | assign dff_rparity_w0_m_scanin[1] = dff_rparity_w1_m_scanout[1]; | |
| 4884 | assign dff_wdata_m_scanin[72] = dff_rparity_w0_m_scanout[1]; | |
| 4885 | assign dff_wdata_m_scanin[0] = dff_wdata_m_scanout[72]; | |
| 4886 | assign dff_rdata_w3_m_scanin[0] = dff_wdata_m_scanout[0]; | |
| 4887 | assign dff_rdata_w2_m_scanin[0] = dff_rdata_w3_m_scanout[0]; | |
| 4888 | assign dff_rdata_w1_m_scanin[0] = dff_rdata_w2_m_scanout[0]; | |
| 4889 | assign dff_rdata_w0_m_scanin[0] = dff_rdata_w1_m_scanout[0]; | |
| 4890 | assign dff_wdata_m_scanin[81] = dff_rdata_w0_m_scanout[0]; | |
| 4891 | assign dff_wdata_m_scanin[9] = dff_wdata_m_scanout[81]; | |
| 4892 | assign dff_rdata_w3_m_scanin[8] = dff_wdata_m_scanout[9]; | |
| 4893 | assign dff_rdata_w2_m_scanin[8] = dff_rdata_w3_m_scanout[8]; | |
| 4894 | assign dff_rdata_w1_m_scanin[8] = dff_rdata_w2_m_scanout[8]; | |
| 4895 | assign dff_rdata_w0_m_scanin[8] = dff_rdata_w1_m_scanout[8]; | |
| 4896 | assign dff_wdata_m_scanin[73] = dff_rdata_w0_m_scanout[8]; | |
| 4897 | assign dff_wdata_m_scanin[1] = dff_wdata_m_scanout[73]; | |
| 4898 | assign dff_rdata_w3_m_scanin[1] = dff_wdata_m_scanout[1]; | |
| 4899 | assign dff_rdata_w2_m_scanin[1] = dff_rdata_w3_m_scanout[1]; | |
| 4900 | assign dff_rdata_w1_m_scanin[1] = dff_rdata_w2_m_scanout[1]; | |
| 4901 | assign dff_rdata_w0_m_scanin[1] = dff_rdata_w1_m_scanout[1]; | |
| 4902 | assign dff_wdata_m_scanin[82] = dff_rdata_w0_m_scanout[1]; | |
| 4903 | assign dff_wdata_m_scanin[10] = dff_wdata_m_scanout[82]; | |
| 4904 | assign dff_rdata_w3_m_scanin[9] = dff_wdata_m_scanout[10]; | |
| 4905 | assign dff_rdata_w2_m_scanin[9] = dff_rdata_w3_m_scanout[9]; | |
| 4906 | assign dff_rdata_w1_m_scanin[9] = dff_rdata_w2_m_scanout[9]; | |
| 4907 | assign dff_rdata_w0_m_scanin[9] = dff_rdata_w1_m_scanout[9]; | |
| 4908 | assign dff_wdata_m_scanin[74] = dff_rdata_w0_m_scanout[9]; | |
| 4909 | assign dff_wdata_m_scanin[2] = dff_wdata_m_scanout[74]; | |
| 4910 | assign dff_rdata_w3_m_scanin[2] = dff_wdata_m_scanout[2]; | |
| 4911 | assign dff_rdata_w2_m_scanin[2] = dff_rdata_w3_m_scanout[2]; | |
| 4912 | assign dff_rdata_w1_m_scanin[2] = dff_rdata_w2_m_scanout[2]; | |
| 4913 | assign dff_rdata_w0_m_scanin[2] = dff_rdata_w1_m_scanout[2]; | |
| 4914 | assign dff_wdata_m_scanin[83] = dff_rdata_w0_m_scanout[2]; | |
| 4915 | assign dff_wdata_m_scanin[11] = dff_wdata_m_scanout[83]; | |
| 4916 | assign dff_rdata_w3_m_scanin[10] = dff_wdata_m_scanout[11]; | |
| 4917 | assign dff_rdata_w2_m_scanin[10] = dff_rdata_w3_m_scanout[10]; | |
| 4918 | assign dff_rdata_w1_m_scanin[10] = dff_rdata_w2_m_scanout[10]; | |
| 4919 | assign dff_rdata_w0_m_scanin[10] = dff_rdata_w1_m_scanout[10]; | |
| 4920 | assign dff_wdata_m_scanin[75] = dff_rdata_w0_m_scanout[10]; | |
| 4921 | assign dff_wdata_m_scanin[3] = dff_wdata_m_scanout[75]; | |
| 4922 | assign dff_rdata_w3_m_scanin[3] = dff_wdata_m_scanout[3]; | |
| 4923 | assign dff_rdata_w2_m_scanin[3] = dff_rdata_w3_m_scanout[3]; | |
| 4924 | assign dff_rdata_w1_m_scanin[3] = dff_rdata_w2_m_scanout[3]; | |
| 4925 | assign dff_rdata_w0_m_scanin[3] = dff_rdata_w1_m_scanout[3]; | |
| 4926 | assign dff_wdata_m_scanin[84] = dff_rdata_w0_m_scanout[3]; | |
| 4927 | assign dff_wdata_m_scanin[12] = dff_wdata_m_scanout[84]; | |
| 4928 | assign dff_rdata_w3_m_scanin[11] = dff_wdata_m_scanout[12]; | |
| 4929 | assign dff_rdata_w2_m_scanin[11] = dff_rdata_w3_m_scanout[11]; | |
| 4930 | assign dff_rdata_w1_m_scanin[11] = dff_rdata_w2_m_scanout[11]; | |
| 4931 | assign dff_rdata_w0_m_scanin[11] = dff_rdata_w1_m_scanout[11]; | |
| 4932 | assign dff_wdata_m_scanin[76] = dff_rdata_w0_m_scanout[11]; | |
| 4933 | assign dff_wdata_m_scanin[4] = dff_wdata_m_scanout[76]; | |
| 4934 | assign dff_rdata_w3_m_scanin[4] = dff_wdata_m_scanout[4]; | |
| 4935 | assign dff_rdata_w2_m_scanin[4] = dff_rdata_w3_m_scanout[4]; | |
| 4936 | assign dff_rdata_w1_m_scanin[4] = dff_rdata_w2_m_scanout[4]; | |
| 4937 | assign dff_rdata_w0_m_scanin[4] = dff_rdata_w1_m_scanout[4]; | |
| 4938 | assign dff_wdata_m_scanin[85] = dff_rdata_w0_m_scanout[4]; | |
| 4939 | assign dff_wdata_m_scanin[13] = dff_wdata_m_scanout[85]; | |
| 4940 | assign dff_rdata_w3_m_scanin[12] = dff_wdata_m_scanout[13]; | |
| 4941 | assign dff_rdata_w2_m_scanin[12] = dff_rdata_w3_m_scanout[12]; | |
| 4942 | assign dff_rdata_w1_m_scanin[12] = dff_rdata_w2_m_scanout[12]; | |
| 4943 | assign dff_rdata_w0_m_scanin[12] = dff_rdata_w1_m_scanout[12]; | |
| 4944 | assign dff_wdata_m_scanin[77] = dff_rdata_w0_m_scanout[12]; | |
| 4945 | assign dff_wdata_m_scanin[5] = dff_wdata_m_scanout[77]; | |
| 4946 | assign dff_rdata_w3_m_scanin[5] = dff_wdata_m_scanout[5]; | |
| 4947 | assign dff_rdata_w2_m_scanin[5] = dff_rdata_w3_m_scanout[5]; | |
| 4948 | assign dff_rdata_w1_m_scanin[5] = dff_rdata_w2_m_scanout[5]; | |
| 4949 | assign dff_rdata_w0_m_scanin[5] = dff_rdata_w1_m_scanout[5]; | |
| 4950 | assign dff_wdata_m_scanin[86] = dff_rdata_w0_m_scanout[5]; | |
| 4951 | assign dff_wdata_m_scanin[14] = dff_wdata_m_scanout[86]; | |
| 4952 | assign dff_rdata_w3_m_scanin[13] = dff_wdata_m_scanout[14]; | |
| 4953 | assign dff_rdata_w2_m_scanin[13] = dff_rdata_w3_m_scanout[13]; | |
| 4954 | assign dff_rdata_w1_m_scanin[13] = dff_rdata_w2_m_scanout[13]; | |
| 4955 | assign dff_rdata_w0_m_scanin[13] = dff_rdata_w1_m_scanout[13]; | |
| 4956 | assign dff_wdata_m_scanin[78] = dff_rdata_w0_m_scanout[13]; | |
| 4957 | assign dff_wdata_m_scanin[6] = dff_wdata_m_scanout[78]; | |
| 4958 | assign dff_rdata_w3_m_scanin[6] = dff_wdata_m_scanout[6]; | |
| 4959 | assign dff_rdata_w2_m_scanin[6] = dff_rdata_w3_m_scanout[6]; | |
| 4960 | assign dff_rdata_w1_m_scanin[6] = dff_rdata_w2_m_scanout[6]; | |
| 4961 | assign dff_rdata_w0_m_scanin[6] = dff_rdata_w1_m_scanout[6]; | |
| 4962 | assign dff_wdata_m_scanin[87] = dff_rdata_w0_m_scanout[6]; | |
| 4963 | assign dff_wdata_m_scanin[15] = dff_wdata_m_scanout[87]; | |
| 4964 | assign dff_rdata_w3_m_scanin[14] = dff_wdata_m_scanout[15]; | |
| 4965 | assign dff_rdata_w2_m_scanin[14] = dff_rdata_w3_m_scanout[14]; | |
| 4966 | assign dff_rdata_w1_m_scanin[14] = dff_rdata_w2_m_scanout[14]; | |
| 4967 | assign dff_rdata_w0_m_scanin[14] = dff_rdata_w1_m_scanout[14]; | |
| 4968 | assign dff_wdata_m_scanin[79] = dff_rdata_w0_m_scanout[14]; | |
| 4969 | assign dff_wdata_m_scanin[7] = dff_wdata_m_scanout[79]; | |
| 4970 | assign dff_rdata_w3_m_scanin[7] = dff_wdata_m_scanout[7]; | |
| 4971 | assign dff_rdata_w2_m_scanin[7] = dff_rdata_w3_m_scanout[7]; | |
| 4972 | assign dff_rdata_w1_m_scanin[7] = dff_rdata_w2_m_scanout[7]; | |
| 4973 | assign dff_rdata_w0_m_scanin[7] = dff_rdata_w1_m_scanout[7]; | |
| 4974 | assign dff_wdata_m_scanin[88] = dff_rdata_w0_m_scanout[7]; | |
| 4975 | assign dff_wdata_m_scanin[16] = dff_wdata_m_scanout[88]; | |
| 4976 | assign dff_rdata_w3_m_scanin[15] = dff_wdata_m_scanout[16]; | |
| 4977 | assign dff_rdata_w2_m_scanin[15] = dff_rdata_w3_m_scanout[15]; | |
| 4978 | assign dff_rdata_w1_m_scanin[15] = dff_rdata_w2_m_scanout[15]; | |
| 4979 | assign dff_rdata_w0_m_scanin[15] = dff_rdata_w1_m_scanout[15]; | |
| 4980 | assign dff_wdata_m_scanin[98] = dff_rdata_w0_m_scanout[15]; | |
| 4981 | assign dff_wdata_m_scanin[26] = dff_wdata_m_scanout[98]; | |
| 4982 | assign dff_rparity_w3_m_scanin[2] = dff_wdata_m_scanout[26]; | |
| 4983 | assign dff_rparity_w2_m_scanin[2] = dff_rparity_w3_m_scanout[2]; | |
| 4984 | assign dff_rparity_w1_m_scanin[2] = dff_rparity_w2_m_scanout[2]; | |
| 4985 | assign dff_rparity_w0_m_scanin[2] = dff_rparity_w1_m_scanout[2]; | |
| 4986 | assign dff_wdata_m_scanin[107] = dff_rparity_w0_m_scanout[2]; | |
| 4987 | assign dff_wdata_m_scanin[35] = dff_wdata_m_scanout[107]; | |
| 4988 | assign dff_rparity_w3_m_scanin[3] = dff_wdata_m_scanout[35]; | |
| 4989 | assign dff_rparity_w2_m_scanin[3] = dff_rparity_w3_m_scanout[3]; | |
| 4990 | assign dff_rparity_w1_m_scanin[3] = dff_rparity_w2_m_scanout[3]; | |
| 4991 | assign dff_rparity_w0_m_scanin[3] = dff_rparity_w1_m_scanout[3]; | |
| 4992 | assign dff_wdata_m_scanin[90] = dff_rparity_w0_m_scanout[3]; | |
| 4993 | assign dff_wdata_m_scanin[18] = dff_wdata_m_scanout[90]; | |
| 4994 | assign dff_rdata_w3_m_scanin[16] = dff_wdata_m_scanout[18]; | |
| 4995 | assign dff_rdata_w2_m_scanin[16] = dff_rdata_w3_m_scanout[16]; | |
| 4996 | assign dff_rdata_w1_m_scanin[16] = dff_rdata_w2_m_scanout[16]; | |
| 4997 | assign dff_rdata_w0_m_scanin[16] = dff_rdata_w1_m_scanout[16]; | |
| 4998 | assign dff_wdata_m_scanin[99] = dff_rdata_w0_m_scanout[16]; | |
| 4999 | assign dff_wdata_m_scanin[27] = dff_wdata_m_scanout[99]; | |
| 5000 | assign dff_rdata_w3_m_scanin[24] = dff_wdata_m_scanout[27]; | |
| 5001 | assign dff_rdata_w2_m_scanin[24] = dff_rdata_w3_m_scanout[24]; | |
| 5002 | assign dff_rdata_w1_m_scanin[24] = dff_rdata_w2_m_scanout[24]; | |
| 5003 | assign dff_rdata_w0_m_scanin[24] = dff_rdata_w1_m_scanout[24]; | |
| 5004 | assign dff_wdata_m_scanin[91] = dff_rdata_w0_m_scanout[24]; | |
| 5005 | assign dff_wdata_m_scanin[19] = dff_wdata_m_scanout[91]; | |
| 5006 | assign dff_rdata_w3_m_scanin[17] = dff_wdata_m_scanout[19]; | |
| 5007 | assign dff_rdata_w2_m_scanin[17] = dff_rdata_w3_m_scanout[17]; | |
| 5008 | assign dff_rdata_w1_m_scanin[17] = dff_rdata_w2_m_scanout[17]; | |
| 5009 | assign dff_rdata_w0_m_scanin[17] = dff_rdata_w1_m_scanout[17]; | |
| 5010 | assign dff_wdata_m_scanin[100] = dff_rdata_w0_m_scanout[17]; | |
| 5011 | assign dff_wdata_m_scanin[28] = dff_wdata_m_scanout[100]; | |
| 5012 | assign dff_rdata_w3_m_scanin[25] = dff_wdata_m_scanout[28]; | |
| 5013 | assign dff_rdata_w2_m_scanin[25] = dff_rdata_w3_m_scanout[25]; | |
| 5014 | assign dff_rdata_w1_m_scanin[25] = dff_rdata_w2_m_scanout[25]; | |
| 5015 | assign dff_rdata_w0_m_scanin[25] = dff_rdata_w1_m_scanout[25]; | |
| 5016 | assign dff_wdata_m_scanin[92] = dff_rdata_w0_m_scanout[25]; | |
| 5017 | assign dff_wdata_m_scanin[20] = dff_wdata_m_scanout[92]; | |
| 5018 | assign dff_rdata_w3_m_scanin[18] = dff_wdata_m_scanout[20]; | |
| 5019 | assign dff_rdata_w2_m_scanin[18] = dff_rdata_w3_m_scanout[18]; | |
| 5020 | assign dff_rdata_w1_m_scanin[18] = dff_rdata_w2_m_scanout[18]; | |
| 5021 | assign dff_rdata_w0_m_scanin[18] = dff_rdata_w1_m_scanout[18]; | |
| 5022 | assign dff_wdata_m_scanin[101] = dff_rdata_w0_m_scanout[18]; | |
| 5023 | assign dff_wdata_m_scanin[29] = dff_wdata_m_scanout[101]; | |
| 5024 | assign dff_rdata_w3_m_scanin[26] = dff_wdata_m_scanout[29]; | |
| 5025 | assign dff_rdata_w2_m_scanin[26] = dff_rdata_w3_m_scanout[26]; | |
| 5026 | assign dff_rdata_w1_m_scanin[26] = dff_rdata_w2_m_scanout[26]; | |
| 5027 | assign dff_rdata_w0_m_scanin[26] = dff_rdata_w1_m_scanout[26]; | |
| 5028 | assign dff_wdata_m_scanin[93] = dff_rdata_w0_m_scanout[26]; | |
| 5029 | assign dff_wdata_m_scanin[21] = dff_wdata_m_scanout[93]; | |
| 5030 | assign dff_rdata_w3_m_scanin[19] = dff_wdata_m_scanout[21]; | |
| 5031 | assign dff_rdata_w2_m_scanin[19] = dff_rdata_w3_m_scanout[19]; | |
| 5032 | assign dff_rdata_w1_m_scanin[19] = dff_rdata_w2_m_scanout[19]; | |
| 5033 | assign dff_rdata_w0_m_scanin[19] = dff_rdata_w1_m_scanout[19]; | |
| 5034 | assign dff_wdata_m_scanin[102] = dff_rdata_w0_m_scanout[19]; | |
| 5035 | assign dff_wdata_m_scanin[30] = dff_wdata_m_scanout[102]; | |
| 5036 | assign dff_rdata_w3_m_scanin[27] = dff_wdata_m_scanout[30]; | |
| 5037 | assign dff_rdata_w2_m_scanin[27] = dff_rdata_w3_m_scanout[27]; | |
| 5038 | assign dff_rdata_w1_m_scanin[27] = dff_rdata_w2_m_scanout[27]; | |
| 5039 | assign dff_rdata_w0_m_scanin[27] = dff_rdata_w1_m_scanout[27]; | |
| 5040 | assign dff_wdata_m_scanin[94] = dff_rdata_w0_m_scanout[27]; | |
| 5041 | assign dff_wdata_m_scanin[22] = dff_wdata_m_scanout[94]; | |
| 5042 | assign dff_rdata_w3_m_scanin[20] = dff_wdata_m_scanout[22]; | |
| 5043 | assign dff_rdata_w2_m_scanin[20] = dff_rdata_w3_m_scanout[20]; | |
| 5044 | assign dff_rdata_w1_m_scanin[20] = dff_rdata_w2_m_scanout[20]; | |
| 5045 | assign dff_rdata_w0_m_scanin[20] = dff_rdata_w1_m_scanout[20]; | |
| 5046 | assign dff_wdata_m_scanin[103] = dff_rdata_w0_m_scanout[20]; | |
| 5047 | assign dff_wdata_m_scanin[31] = dff_wdata_m_scanout[103]; | |
| 5048 | assign dff_rdata_w3_m_scanin[28] = dff_wdata_m_scanout[31]; | |
| 5049 | assign dff_rdata_w2_m_scanin[28] = dff_rdata_w3_m_scanout[28]; | |
| 5050 | assign dff_rdata_w1_m_scanin[28] = dff_rdata_w2_m_scanout[28]; | |
| 5051 | assign dff_rdata_w0_m_scanin[28] = dff_rdata_w1_m_scanout[28]; | |
| 5052 | assign dff_wdata_m_scanin[95] = dff_rdata_w0_m_scanout[28]; | |
| 5053 | assign dff_wdata_m_scanin[23] = dff_wdata_m_scanout[95]; | |
| 5054 | assign dff_rdata_w3_m_scanin[21] = dff_wdata_m_scanout[23]; | |
| 5055 | assign dff_rdata_w2_m_scanin[21] = dff_rdata_w3_m_scanout[21]; | |
| 5056 | assign dff_rdata_w1_m_scanin[21] = dff_rdata_w2_m_scanout[21]; | |
| 5057 | assign dff_rdata_w0_m_scanin[21] = dff_rdata_w1_m_scanout[21]; | |
| 5058 | assign dff_wdata_m_scanin[104] = dff_rdata_w0_m_scanout[21]; | |
| 5059 | assign dff_wdata_m_scanin[32] = dff_wdata_m_scanout[104]; | |
| 5060 | assign dff_rdata_w3_m_scanin[29] = dff_wdata_m_scanout[32]; | |
| 5061 | assign dff_rdata_w2_m_scanin[29] = dff_rdata_w3_m_scanout[29]; | |
| 5062 | assign dff_rdata_w1_m_scanin[29] = dff_rdata_w2_m_scanout[29]; | |
| 5063 | assign dff_rdata_w0_m_scanin[29] = dff_rdata_w1_m_scanout[29]; | |
| 5064 | assign dff_wdata_m_scanin[96] = dff_rdata_w0_m_scanout[29]; | |
| 5065 | assign dff_wdata_m_scanin[24] = dff_wdata_m_scanout[96]; | |
| 5066 | assign dff_rdata_w3_m_scanin[22] = dff_wdata_m_scanout[24]; | |
| 5067 | assign dff_rdata_w2_m_scanin[22] = dff_rdata_w3_m_scanout[22]; | |
| 5068 | assign dff_rdata_w1_m_scanin[22] = dff_rdata_w2_m_scanout[22]; | |
| 5069 | assign dff_rdata_w0_m_scanin[22] = dff_rdata_w1_m_scanout[22]; | |
| 5070 | assign dff_wdata_m_scanin[105] = dff_rdata_w0_m_scanout[22]; | |
| 5071 | assign dff_wdata_m_scanin[33] = dff_wdata_m_scanout[105]; | |
| 5072 | assign dff_rdata_w3_m_scanin[30] = dff_wdata_m_scanout[33]; | |
| 5073 | assign dff_rdata_w2_m_scanin[30] = dff_rdata_w3_m_scanout[30]; | |
| 5074 | assign dff_rdata_w1_m_scanin[30] = dff_rdata_w2_m_scanout[30]; | |
| 5075 | assign dff_rdata_w0_m_scanin[30] = dff_rdata_w1_m_scanout[30]; | |
| 5076 | assign dff_wdata_m_scanin[97] = dff_rdata_w0_m_scanout[30]; | |
| 5077 | assign dff_wdata_m_scanin[25] = dff_wdata_m_scanout[97]; | |
| 5078 | assign dff_rdata_w3_m_scanin[23] = dff_wdata_m_scanout[25]; | |
| 5079 | assign dff_rdata_w2_m_scanin[23] = dff_rdata_w3_m_scanout[23]; | |
| 5080 | assign dff_rdata_w1_m_scanin[23] = dff_rdata_w2_m_scanout[23]; | |
| 5081 | assign dff_rdata_w0_m_scanin[23] = dff_rdata_w1_m_scanout[23]; | |
| 5082 | assign dff_wdata_m_scanin[106] = dff_rdata_w0_m_scanout[23]; | |
| 5083 | assign dff_wdata_m_scanin[34] = dff_wdata_m_scanout[106]; | |
| 5084 | assign dff_rdata_w3_m_scanin[31] = dff_wdata_m_scanout[34]; | |
| 5085 | assign dff_rdata_w2_m_scanin[31] = dff_rdata_w3_m_scanout[31]; | |
| 5086 | assign dff_rdata_w1_m_scanin[31] = dff_rdata_w2_m_scanout[31]; | |
| 5087 | assign dff_rdata_w0_m_scanin[31] = dff_rdata_w1_m_scanout[31]; | |
| 5088 | assign dff_ctl_m_1_scanin[8] = dff_rdata_w0_m_scanout[31]; | |
| 5089 | assign dff_ctl_m_1_scanin[0] = dff_ctl_m_1_scanout[8]; | |
| 5090 | assign dff_ctl_m_1_scanin[9] = dff_ctl_m_1_scanout[0]; | |
| 5091 | assign dff_ctl_m_1_scanin[1] = dff_ctl_m_1_scanout[9]; | |
| 5092 | assign dff_ctl_m_1_scanin[10] = dff_ctl_m_1_scanout[1]; | |
| 5093 | assign dff_ctl_m_1_scanin[2] = dff_ctl_m_1_scanout[10]; | |
| 5094 | assign dff_ctl_m_1_scanin[11] = dff_ctl_m_1_scanout[2]; | |
| 5095 | assign dff_ctl_m_1_scanin[3] = dff_ctl_m_1_scanout[11]; | |
| 5096 | assign dff_byte_perr_w2_scanin[0] = dff_ctl_m_1_scanout[3]; | |
| 5097 | assign dff_byte_perr_w3_scanin[0] = dff_byte_perr_w2_scanout[0]; | |
| 5098 | assign dff_byte_perr_w3_scanin[1] = dff_byte_perr_w3_scanout[0]; | |
| 5099 | assign dff_byte_perr_w2_scanin[1] = dff_byte_perr_w3_scanout[1]; | |
| 5100 | assign dff_byte_perr_w2_scanin[2] = dff_byte_perr_w2_scanout[1]; | |
| 5101 | assign dff_byte_perr_w3_scanin[2] = dff_byte_perr_w2_scanout[2]; | |
| 5102 | assign dff_byte_perr_w3_scanin[3] = dff_byte_perr_w3_scanout[2]; | |
| 5103 | assign dff_byte_perr_w2_scanin[3] = dff_byte_perr_w3_scanout[3]; | |
| 5104 | assign dff_msb_w3_scanin[7] = dff_byte_perr_w2_scanout[3]; | |
| 5105 | assign dff_msb_w2_scanin[7] = dff_msb_w3_scanout[7]; | |
| 5106 | assign dff_msb_w1_scanin[7] = dff_msb_w2_scanout[7]; | |
| 5107 | assign dff_msb_w0_scanin[7] = dff_msb_w1_scanout[7]; | |
| 5108 | assign dff_msb_w3_scanin[6] = dff_msb_w0_scanout[7]; | |
| 5109 | assign dff_msb_w2_scanin[6] = dff_msb_w3_scanout[6]; | |
| 5110 | assign dff_msb_w1_scanin[6] = dff_msb_w2_scanout[6]; | |
| 5111 | assign dff_msb_w0_scanin[6] = dff_msb_w1_scanout[6]; | |
| 5112 | assign dff_msb_w3_scanin[5] = dff_msb_w0_scanout[6]; | |
| 5113 | assign dff_msb_w2_scanin[5] = dff_msb_w3_scanout[5]; | |
| 5114 | assign dff_msb_w1_scanin[5] = dff_msb_w2_scanout[5]; | |
| 5115 | assign dff_msb_w0_scanin[5] = dff_msb_w1_scanout[5]; | |
| 5116 | assign dff_msb_w3_scanin[4] = dff_msb_w0_scanout[5]; | |
| 5117 | assign dff_msb_w2_scanin[4] = dff_msb_w3_scanout[4]; | |
| 5118 | assign dff_msb_w1_scanin[4] = dff_msb_w2_scanout[4]; | |
| 5119 | assign dff_msb_w0_scanin[4] = dff_msb_w1_scanout[4]; | |
| 5120 | assign dff_msb_w3_scanin[0] = dff_msb_w0_scanout[4]; | |
| 5121 | assign dff_msb_w2_scanin[0] = dff_msb_w3_scanout[0]; | |
| 5122 | assign dff_msb_w1_scanin[0] = dff_msb_w2_scanout[0]; | |
| 5123 | assign dff_msb_w0_scanin[0] = dff_msb_w1_scanout[0]; | |
| 5124 | assign dff_msb_w3_scanin[1] = dff_msb_w0_scanout[0]; | |
| 5125 | assign dff_msb_w2_scanin[1] = dff_msb_w3_scanout[1]; | |
| 5126 | assign dff_msb_w1_scanin[1] = dff_msb_w2_scanout[1]; | |
| 5127 | assign dff_msb_w0_scanin[1] = dff_msb_w1_scanout[1]; | |
| 5128 | assign dff_msb_w3_scanin[2] = dff_msb_w0_scanout[1]; | |
| 5129 | assign dff_msb_w2_scanin[2] = dff_msb_w3_scanout[2]; | |
| 5130 | assign dff_msb_w1_scanin[2] = dff_msb_w2_scanout[2]; | |
| 5131 | assign dff_msb_w0_scanin[2] = dff_msb_w1_scanout[2]; | |
| 5132 | assign dff_msb_w3_scanin[3] = dff_msb_w0_scanout[2]; | |
| 5133 | assign dff_msb_w2_scanin[3] = dff_msb_w3_scanout[3]; | |
| 5134 | assign dff_msb_w1_scanin[3] = dff_msb_w2_scanout[3]; | |
| 5135 | assign dff_msb_w0_scanin[3] = dff_msb_w1_scanout[3]; | |
| 5136 | assign dff_red_out_scanin[2] = dff_msb_w0_scanout[3]; | |
| 5137 | assign dff_red_out_scanin[3] = dff_red_out_scanout[2]; | |
| 5138 | assign dff_red_out_scanin[4] = dff_red_out_scanout[3]; | |
| 5139 | assign dff_red_out_scanin[5] = dff_red_out_scanout[4]; | |
| 5140 | assign dff_red_out_scanin[6] = dff_red_out_scanout[5]; | |
| 5141 | assign dff_red_out_scanin[7] = dff_red_out_scanout[6]; | |
| 5142 | assign dff_red_out_scanin[0] = dff_red_out_scanout[7]; | |
| 5143 | assign dff_red_out_scanin[1] = dff_red_out_scanout[0]; | |
| 5144 | assign dff_red_in_scanin[2] = dff_red_out_scanout[1]; | |
| 5145 | assign dff_red_in_scanin[3] = dff_red_in_scanout[2]; | |
| 5146 | assign dff_red_in_scanin[1] = dff_red_in_scanout[3]; | |
| 5147 | assign dff_red_in_scanin[0] = dff_red_in_scanout[1]; | |
| 5148 | assign dff_red_in_scanin[6] = dff_red_in_scanout[0]; | |
| 5149 | assign dff_red_in_scanin[7] = dff_red_in_scanout[6]; | |
| 5150 | assign dff_red_in_scanin[8] = dff_red_in_scanout[7]; | |
| 5151 | assign dff_red_in_scanin[9] = dff_red_in_scanout[8]; | |
| 5152 | assign dff_red_in_scanin[10] = dff_red_in_scanout[9]; | |
| 5153 | assign dff_red_in_scanin[11] = dff_red_in_scanout[10]; | |
| 5154 | assign dff_red_in_scanin[4] = dff_red_in_scanout[11]; | |
| 5155 | assign dff_red_in_scanin[5] = dff_red_in_scanout[4]; | |
| 5156 | assign scan_out = dff_red_in_scanout[5]; | |
| 5157 | ||
| 5158 | l1clkhdr_ctl_macro l1ch_in( | |
| 5159 | .l2clk (l2clk), | |
| 5160 | .l1en (1'b1), | |
| 5161 | .pce_ov (1'b1), | |
| 5162 | .se (tcu_se_scancollar_in), | |
| 5163 | .l1clk (l1clk_in), | |
| 5164 | .stop (stop)); | |
| 5165 | l1clkhdr_ctl_macro l1ch_in_pm( | |
| 5166 | .l2clk (l2clk), | |
| 5167 | .l1en (dcache_wclk_en_e), | |
| 5168 | .se (tcu_se_scancollar_in), | |
| 5169 | .l1clk (l1clk_in_pm), | |
| 5170 | .pce_ov (pce_ov), | |
| 5171 | .stop (stop)); | |
| 5172 | l1clkhdr_ctl_macro l1ch_out_pm( | |
| 5173 | .l2clk (l2clk), | |
| 5174 | .l1en (dcache_rclk_en_m), | |
| 5175 | .se (tcu_se_scancollar_out), | |
| 5176 | .l1clk (l1clk_out_pm), | |
| 5177 | .pce_ov (pce_ov), | |
| 5178 | .stop (stop)); | |
| 5179 | l1clkhdr_ctl_macro l1ch_out( | |
| 5180 | .l2clk (l2clk), | |
| 5181 | .l1en (1'b1), | |
| 5182 | .pce_ov (1'b1), | |
| 5183 | .se (tcu_se_scancollar_out), | |
| 5184 | .l1clk (l1clk_out), | |
| 5185 | .stop (stop)); | |
| 5186 | l1clkhdr_ctl_macro l1ch_free( | |
| 5187 | .l2clk (l2clk), | |
| 5188 | .l1en (dcache_clk_en_e), | |
| 5189 | .se (tcu_scan_en), | |
| 5190 | .l1clk (l1clk_free), | |
| 5191 | .pce_ov (pce_ov), | |
| 5192 | .stop (stop)); | |
| 5193 | l1clkhdr_ctl_macro l1ch_free_wpm( | |
| 5194 | .l2clk (l2clk), | |
| 5195 | .l1en (dcache_wclk_en_e), | |
| 5196 | .se (tcu_scan_en), | |
| 5197 | .l1clk (l1clk_free_wpm), | |
| 5198 | .pce_ov (pce_ov), | |
| 5199 | .stop (stop)); | |
| 5200 | l1clkhdr_ctl_macro l1ch_red( | |
| 5201 | .l2clk (l2clk), | |
| 5202 | .l1en (1'b1), | |
| 5203 | .pce_ov (1'b1), | |
| 5204 | .se (1'b0), | |
| 5205 | .l1clk (l1clk_red), | |
| 5206 | .stop (stop)); | |
| 5207 | mux_macro__mux_aope__ports_2__width_8 mx_addr_e( | |
| 5208 | .din0 (dcache_alt_addr_e[10:3]), | |
| 5209 | .din1 (dcache_rd_addr_e[10:3]), | |
| 5210 | .sel0 (dcache_alt_addr_sel_e), | |
| 5211 | .dout (dcache_rwaddr_e[10:3])); | |
| 5212 | tisram_msff_macro__fs_1__width_8 lat_addr( | |
| 5213 | .scan_in (lat_addr_scanin[7:0]), | |
| 5214 | .scan_out (lat_addr_scanout[7:0]), | |
| 5215 | .l1clk (l1clk_in), | |
| 5216 | .d (dcache_rwaddr_e[10:3]), | |
| 5217 | .latout (dcache_rwaddr_eb[10:3]), | |
| 5218 | .latout_l (dcache_rwaddr_l_unused[10:3]), | |
| 5219 | .siclk (siclk), | |
| 5220 | .soclk (soclk)); | |
| 5221 | mux_macro__mux_aodec__ports_4__width_4 wr_way_decode( | |
| 5222 | .din0 (4'b1), | |
| 5223 | .din1 (4'd2), | |
| 5224 | .din2 (4'd4), | |
| 5225 | .din3 (4'd8), | |
| 5226 | .sel (dcache_wr_way_e[1:0]), | |
| 5227 | .dout (wr_way_dec_e[3:0])); | |
| 5228 | tisram_msff_macro__fs_1__width_7 lat_ctl_eb( | |
| 5229 | .scan_in (lat_ctl_eb_scanin[6:0]), | |
| 5230 | .scan_out (lat_ctl_eb_scanout[6:0]), | |
| 5231 | .l1clk (l1clk_in), | |
| 5232 | .d ({dcache_rvld_e, dcache_rvld_e, | |
| 5233 | dcache_wvld_e, wr_way_dec_e[3:0]}), | |
| 5234 | .latout ({dcache_rvld_top_eb, | |
| 5235 | dcache_rvld_bot_eb, dcache_wvld_eb, wr_way_dec_eb[3:0]}), | |
| 5236 | .latout_l (lat_ctl_unused[6:0]), | |
| 5237 | .siclk (siclk), | |
| 5238 | .soclk (soclk)); | |
| 5239 | msff_ctl_macro__fs_1__width_3 dff_ctl_m_0( | |
| 5240 | .scan_in (dff_ctl_m_0_scanin[2:0]), | |
| 5241 | .scan_out (dff_ctl_m_0_scanout[2:0]), | |
| 5242 | .l1clk (l1clk_in), | |
| 5243 | .din ({dcache_rvld_e, dcache_wvld_e, | |
| 5244 | dcache_bypass_e_}), | |
| 5245 | .dout ({dcache_rvld_m, dcache_wvld_m, | |
| 5246 | dcache_bypass_m_}), | |
| 5247 | .siclk (siclk), | |
| 5248 | .soclk (soclk)); | |
| 5249 | tisram_msff_macro__fs_1__width_16 dff_ctl_m_1( | |
| 5250 | .scan_in (dff_ctl_m_1_scanin[15:0]), | |
| 5251 | .scan_out (dff_ctl_m_1_scanout[15:0]), | |
| 5252 | .l1clk (l1clk_in_pm), | |
| 5253 | .d (dcache_byte_wr_en_e[15:0]), | |
| 5254 | .latout (byte_wr_en_eb[15:0]), | |
| 5255 | .latout_l (dff_ctl_l_unused[15:0]), | |
| 5256 | .siclk (siclk), | |
| 5257 | .soclk (soclk)); | |
| 5258 | msff_ctl_macro__fs_1__width_5 dff_ctl_b( | |
| 5259 | .scan_in (dff_ctl_b_scanin[4:0]), | |
| 5260 | .scan_out (dff_ctl_b_scanout[4:0]), | |
| 5261 | .l1clk (l1clk_in), | |
| 5262 | .din ({dcache_alt_way_sel_m, | |
| 5263 | dcache_alt_rsel_way_m[3:0]}), | |
| 5264 | .dout ({dcache_alt_way_sel_b, | |
| 5265 | dcache_alt_rsel_way_b[3:0]}), | |
| 5266 | .siclk (siclk), | |
| 5267 | .soclk (soclk)); | |
| 5268 | msff_ctl_macro__fs_1__width_144 dff_wdata_m( | |
| 5269 | .scan_in (dff_wdata_m_scanin[143:0]), | |
| 5270 | .scan_out (dff_wdata_m_scanout[143:0]), | |
| 5271 | .l1clk (l1clk_in_pm), | |
| 5272 | .din (dcache_wdata_e[143:0]), | |
| 5273 | .dout ({dcache_wparity_m[15], | |
| 5274 | dcache_wdata_m[127:120], dcache_wparity_m[14], | |
| 5275 | dcache_wdata_m[119:112], dcache_wparity_m[13], | |
| 5276 | dcache_wdata_m[111:104], dcache_wparity_m[12], | |
| 5277 | dcache_wdata_m[103:96], dcache_wparity_m[11], | |
| 5278 | dcache_wdata_m[95:88], dcache_wparity_m[10], | |
| 5279 | dcache_wdata_m[87:80], dcache_wparity_m[9], | |
| 5280 | dcache_wdata_m[79:72], dcache_wparity_m[8], | |
| 5281 | dcache_wdata_m[71:64], dcache_wparity_m[7], | |
| 5282 | dcache_wdata_m[63:56], dcache_wparity_m[6], | |
| 5283 | dcache_wdata_m[55:48], dcache_wparity_m[5], | |
| 5284 | dcache_wdata_m[47:40], dcache_wparity_m[4], | |
| 5285 | dcache_wdata_m[39:32], dcache_wparity_m[3], | |
| 5286 | dcache_wdata_m[31:24], dcache_wparity_m[2], | |
| 5287 | dcache_wdata_m[23:16], dcache_wparity_m[1], | |
| 5288 | dcache_wdata_m[15:8], dcache_wparity_m[0], | |
| 5289 | dcache_wdata_m[7:0]}), | |
| 5290 | .siclk (siclk), | |
| 5291 | .soclk (soclk)); | |
| 5292 | n2_dca_sp_9kb_array array( | |
| 5293 | .l1clk (l1clk_free), | |
| 5294 | .l1clk_wr (l1clk_free_wpm), | |
| 5295 | .addr_b (dcache_rwaddr_eb[10:3]), | |
| 5296 | .rd_en_top_b (dcache_rvld_top_eb), | |
| 5297 | .rd_en_bot_b (dcache_rvld_bot_eb), | |
| 5298 | .rd_en_a (dcache_rvld_m), | |
| 5299 | .wr_en_b (dcache_wvld_eb), | |
| 5300 | .wr_en_a (dcache_wvld_m), | |
| 5301 | .wr_inh_b (tcu_array_wr_inhibit), | |
| 5302 | .byte_wr_en_b (byte_wr_en_eb[15:0]), | |
| 5303 | .wr_waysel_b (wr_way_dec_eb[3:0]), | |
| 5304 | .fuse_dca_repair_value (fuse_dca_repair_value_ff[5:0]), | |
| 5305 | .fuse_dca_repair_en (fuse_dca_repair_en_ff[1:0]), | |
| 5306 | .fuse_dca_rid (fuse_dca_rid_ff[1:0]), | |
| 5307 | .fuse_dca_wen (fuse_dca_wen_ff), | |
| 5308 | .fuse_red_reset (fuse_red_reset_ff), | |
| 5309 | .dca_fuse_repair_value | |
| 5310 | (dca_fuse_repair_value_pre[5:0]), | |
| 5311 | .dca_fuse_repair_en (dca_fuse_repair_en_pre[1:0]), | |
| 5312 | .l1clk_red (l1clk_red), | |
| 5313 | .dcache_wdata_m (dcache_wdata_m[127:0]), | |
| 5314 | .dcache_wparity_m (dcache_wparity_m[15:0]), | |
| 5315 | .dcache_rdata_w0_m (dcache_rdata_w0_m[63:0]), | |
| 5316 | .rparity_w0_m (rparity_w0_m[7:0]), | |
| 5317 | .dcache_rdata_w1_m (dcache_rdata_w1_m[63:0]), | |
| 5318 | .rparity_w1_m (rparity_w1_m[7:0]), | |
| 5319 | .dcache_rdata_w2_m (dcache_rdata_w2_m[63:0]), | |
| 5320 | .rparity_w2_m (rparity_w2_m[7:0]), | |
| 5321 | .dcache_rdata_w3_m (dcache_rdata_w3_m[63:0]), | |
| 5322 | .rparity_w3_m (rparity_w3_m[7:0]), | |
| 5323 | .vnw_ary (vnw_ary)); | |
| 5324 | mux_macro__mux_aope__ports_2__width_64 mx_way0_data( | |
| 5325 | .din0 (dcache_rdata_w0_m[63:0]), | |
| 5326 | .din1 | |
| 5327 | (lsu_l2fill_or_byp_data_m[63:0]), | |
| 5328 | .sel0 (dcache_bypass_m_), | |
| 5329 | .dout (rdata_w0_m[63:0])); | |
| 5330 | msff_ctl_macro__fs_1__width_8 dff_msb_w0( | |
| 5331 | .scan_in (dff_msb_w0_scanin[7:0]), | |
| 5332 | .scan_out (dff_msb_w0_scanout[7:0]), | |
| 5333 | .l1clk (l1clk_out_pm), | |
| 5334 | .din ({dcache_rdata_w0_m[63], | |
| 5335 | dcache_rdata_w0_m[55], dcache_rdata_w0_m[47], | |
| 5336 | dcache_rdata_w0_m[39], dcache_rdata_w0_m[31], | |
| 5337 | dcache_rdata_w0_m[23], dcache_rdata_w0_m[15], | |
| 5338 | dcache_rdata_w0_m[7]}), | |
| 5339 | .dout (dcache_rdata_msb_w0_b[7:0]), | |
| 5340 | .siclk (siclk), | |
| 5341 | .soclk (soclk)); | |
| 5342 | msff_ctl_macro__fs_1__width_8 dff_msb_w1( | |
| 5343 | .scan_in (dff_msb_w1_scanin[7:0]), | |
| 5344 | .scan_out (dff_msb_w1_scanout[7:0]), | |
| 5345 | .l1clk (l1clk_out_pm), | |
| 5346 | .din ({dcache_rdata_w1_m[63], | |
| 5347 | dcache_rdata_w1_m[55], dcache_rdata_w1_m[47], | |
| 5348 | dcache_rdata_w1_m[39], dcache_rdata_w1_m[31], | |
| 5349 | dcache_rdata_w1_m[23], dcache_rdata_w1_m[15], | |
| 5350 | dcache_rdata_w1_m[7]}), | |
| 5351 | .dout (dcache_rdata_msb_w1_b[7:0]), | |
| 5352 | .siclk (siclk), | |
| 5353 | .soclk (soclk)); | |
| 5354 | msff_ctl_macro__fs_1__width_8 dff_msb_w2( | |
| 5355 | .scan_in (dff_msb_w2_scanin[7:0]), | |
| 5356 | .scan_out (dff_msb_w2_scanout[7:0]), | |
| 5357 | .l1clk (l1clk_out_pm), | |
| 5358 | .din ({dcache_rdata_w2_m[63], | |
| 5359 | dcache_rdata_w2_m[55], dcache_rdata_w2_m[47], | |
| 5360 | dcache_rdata_w2_m[39], dcache_rdata_w2_m[31], | |
| 5361 | dcache_rdata_w2_m[23], dcache_rdata_w2_m[15], | |
| 5362 | dcache_rdata_w2_m[7]}), | |
| 5363 | .dout (dcache_rdata_msb_w2_b[7:0]), | |
| 5364 | .siclk (siclk), | |
| 5365 | .soclk (soclk)); | |
| 5366 | msff_ctl_macro__fs_1__width_8 dff_msb_w3( | |
| 5367 | .scan_in (dff_msb_w3_scanin[7:0]), | |
| 5368 | .scan_out (dff_msb_w3_scanout[7:0]), | |
| 5369 | .l1clk (l1clk_out_pm), | |
| 5370 | .din ({dcache_rdata_w3_m[63], | |
| 5371 | dcache_rdata_w3_m[55], dcache_rdata_w3_m[47], | |
| 5372 | dcache_rdata_w3_m[39], dcache_rdata_w3_m[31], | |
| 5373 | dcache_rdata_w3_m[23], dcache_rdata_w3_m[15], | |
| 5374 | dcache_rdata_w3_m[7]}), | |
| 5375 | .dout (dcache_rdata_msb_w3_b[7:0]), | |
| 5376 | .siclk (siclk), | |
| 5377 | .soclk (soclk)); | |
| 5378 | msff_ctl_macro__fs_1__width_64 dff_rdata_w0_m( | |
| 5379 | .scan_in (dff_rdata_w0_m_scanin[63:0]), | |
| 5380 | .scan_out (dff_rdata_w0_m_scanout[63:0]), | |
| 5381 | .l1clk (l1clk_out_pm), | |
| 5382 | .din (rdata_w0_m[63:0]), | |
| 5383 | .dout (rdata_w0_b[63:0]), | |
| 5384 | .siclk (siclk), | |
| 5385 | .soclk (soclk)); | |
| 5386 | msff_ctl_macro__fs_1__width_8 dff_rparity_w0_m( | |
| 5387 | .scan_in (dff_rparity_w0_m_scanin[7:0]), | |
| 5388 | .scan_out (dff_rparity_w0_m_scanout[7:0]), | |
| 5389 | .l1clk (l1clk_out_pm), | |
| 5390 | .din (rparity_w0_m[7:0]), | |
| 5391 | .dout (rparity_w0_b[7:0]), | |
| 5392 | .siclk (siclk), | |
| 5393 | .soclk (soclk)); | |
| 5394 | msff_ctl_macro__fs_1__width_64 dff_rdata_w1_m( | |
| 5395 | .scan_in (dff_rdata_w1_m_scanin[63:0]), | |
| 5396 | .scan_out (dff_rdata_w1_m_scanout[63:0]), | |
| 5397 | .l1clk (l1clk_out_pm), | |
| 5398 | .din (rdata_w1_m[63:0]), | |
| 5399 | .dout (rdata_w1_b[63:0]), | |
| 5400 | .siclk (siclk), | |
| 5401 | .soclk (soclk)); | |
| 5402 | msff_ctl_macro__fs_1__width_8 dff_rparity_w1_m( | |
| 5403 | .scan_in (dff_rparity_w1_m_scanin[7:0]), | |
| 5404 | .scan_out (dff_rparity_w1_m_scanout[7:0]), | |
| 5405 | .l1clk (l1clk_out_pm), | |
| 5406 | .din (rparity_w1_m[7:0]), | |
| 5407 | .dout (rparity_w1_b[7:0]), | |
| 5408 | .siclk (siclk), | |
| 5409 | .soclk (soclk)); | |
| 5410 | msff_ctl_macro__fs_1__width_64 dff_rdata_w2_m( | |
| 5411 | .scan_in (dff_rdata_w2_m_scanin[63:0]), | |
| 5412 | .scan_out (dff_rdata_w2_m_scanout[63:0]), | |
| 5413 | .l1clk (l1clk_out_pm), | |
| 5414 | .din (rdata_w2_m[63:0]), | |
| 5415 | .dout (rdata_w2_b[63:0]), | |
| 5416 | .siclk (siclk), | |
| 5417 | .soclk (soclk)); | |
| 5418 | msff_ctl_macro__fs_1__width_8 dff_rparity_w2_m( | |
| 5419 | .scan_in (dff_rparity_w2_m_scanin[7:0]), | |
| 5420 | .scan_out (dff_rparity_w2_m_scanout[7:0]), | |
| 5421 | .l1clk (l1clk_out_pm), | |
| 5422 | .din (rparity_w2_m[7:0]), | |
| 5423 | .dout (rparity_w2_b[7:0]), | |
| 5424 | .siclk (siclk), | |
| 5425 | .soclk (soclk)); | |
| 5426 | msff_ctl_macro__fs_1__width_64 dff_rdata_w3_m( | |
| 5427 | .scan_in (dff_rdata_w3_m_scanin[63:0]), | |
| 5428 | .scan_out (dff_rdata_w3_m_scanout[63:0]), | |
| 5429 | .l1clk (l1clk_out_pm), | |
| 5430 | .din (rdata_w3_m[63:0]), | |
| 5431 | .dout (rdata_w3_b[63:0]), | |
| 5432 | .siclk (siclk), | |
| 5433 | .soclk (soclk)); | |
| 5434 | msff_ctl_macro__fs_1__width_8 dff_rparity_w3_m( | |
| 5435 | .scan_in (dff_rparity_w3_m_scanin[7:0]), | |
| 5436 | .scan_out (dff_rparity_w3_m_scanout[7:0]), | |
| 5437 | .l1clk (l1clk_out_pm), | |
| 5438 | .din (rparity_w3_m[7:0]), | |
| 5439 | .dout (rparity_w3_b[7:0]), | |
| 5440 | .siclk (siclk), | |
| 5441 | .soclk (soclk)); | |
| 5442 | mux_macro__mux_aope__ports_2__width_4 mx_sel_way( | |
| 5443 | .din0 (dcache_alt_rsel_way_b[3:0]), | |
| 5444 | .din1 (dcache_rsel_way_b[3:0]), | |
| 5445 | .sel0 (dcache_alt_way_sel_b), | |
| 5446 | .dout (dcache_rd_sel_way_b[3:0])); | |
| 5447 | mux_macro__mux_aonpe__ports_4__width_64 mx_rdata_b( | |
| 5448 | .din0 (rdata_w0_b[63:0]), | |
| 5449 | .din1 (rdata_w1_b[63:0]), | |
| 5450 | .din2 (rdata_w2_b[63:0]), | |
| 5451 | .din3 (rdata_w3_b[63:0]), | |
| 5452 | .sel0 (dcache_rd_sel_way_b[0]), | |
| 5453 | .sel1 (dcache_rd_sel_way_b[1]), | |
| 5454 | .sel2 (dcache_rd_sel_way_b[2]), | |
| 5455 | .sel3 (dcache_rd_sel_way_b[3]), | |
| 5456 | .dout (dcache_rdata_b[63:0])); | |
| 5457 | mux_macro__mux_aonpe__ports_4__width_8 mx_rparity_b( | |
| 5458 | .din0 (rparity_w0_b[7:0]), | |
| 5459 | .din1 (rparity_w1_b[7:0]), | |
| 5460 | .din2 (rparity_w2_b[7:0]), | |
| 5461 | .din3 (rparity_w3_b[7:0]), | |
| 5462 | .sel0 (dcache_rd_sel_way_b[0]), | |
| 5463 | .sel1 (dcache_rd_sel_way_b[1]), | |
| 5464 | .sel2 (dcache_rd_sel_way_b[2]), | |
| 5465 | .sel3 (dcache_rd_sel_way_b[3]), | |
| 5466 | .dout (dcache_rparity_b[7:0])); | |
| 5467 | xor_macro__ports_3__width_4 w0_par0( | |
| 5468 | .din0 ({dcache_rdata_w0_m[0], | |
| 5469 | dcache_rdata_w0_m[3], dcache_rdata_w0_m[6], w0_p0_0}), | |
| 5470 | .din1 ({dcache_rdata_w0_m[1], | |
| 5471 | dcache_rdata_w0_m[4], dcache_rdata_w0_m[7], w0_p0_1}), | |
| 5472 | .din2 ({dcache_rdata_w0_m[2], | |
| 5473 | dcache_rdata_w0_m[5], rparity_w0_m[0], w0_p0_2}), | |
| 5474 | .dout ({w0_p0_0, w0_p0_1, w0_p0_2, | |
| 5475 | w0_parity_m[0]})); | |
| 5476 | xor_macro__ports_3__width_4 w0_par1( | |
| 5477 | .din0 ({dcache_rdata_w0_m[8], | |
| 5478 | dcache_rdata_w0_m[11], dcache_rdata_w0_m[14], w0_p1_0}), | |
| 5479 | .din1 ({dcache_rdata_w0_m[9], | |
| 5480 | dcache_rdata_w0_m[12], dcache_rdata_w0_m[15], w0_p1_1}), | |
| 5481 | .din2 ({dcache_rdata_w0_m[10], | |
| 5482 | dcache_rdata_w0_m[13], rparity_w0_m[1], w0_p1_2}), | |
| 5483 | .dout ({w0_p1_0, w0_p1_1, w0_p1_2, | |
| 5484 | w0_parity_m[1]})); | |
| 5485 | xor_macro__ports_3__width_4 w0_par2( | |
| 5486 | .din0 ({dcache_rdata_w0_m[16], | |
| 5487 | dcache_rdata_w0_m[19], dcache_rdata_w0_m[22], w0_p2_0}), | |
| 5488 | .din1 ({dcache_rdata_w0_m[17], | |
| 5489 | dcache_rdata_w0_m[20], dcache_rdata_w0_m[23], w0_p2_1}), | |
| 5490 | .din2 ({dcache_rdata_w0_m[18], | |
| 5491 | dcache_rdata_w0_m[21], rparity_w0_m[2], w0_p2_2}), | |
| 5492 | .dout ({w0_p2_0, w0_p2_1, w0_p2_2, | |
| 5493 | w0_parity_m[2]})); | |
| 5494 | xor_macro__ports_3__width_4 w0_par3( | |
| 5495 | .din0 ({dcache_rdata_w0_m[24], | |
| 5496 | dcache_rdata_w0_m[27], dcache_rdata_w0_m[30], w0_p3_0}), | |
| 5497 | .din1 ({dcache_rdata_w0_m[25], | |
| 5498 | dcache_rdata_w0_m[28], dcache_rdata_w0_m[31], w0_p3_1}), | |
| 5499 | .din2 ({dcache_rdata_w0_m[26], | |
| 5500 | dcache_rdata_w0_m[29], rparity_w0_m[3], w0_p3_2}), | |
| 5501 | .dout ({w0_p3_0, w0_p3_1, w0_p3_2, | |
| 5502 | w0_parity_m[3]})); | |
| 5503 | xor_macro__ports_3__width_4 w0_par4( | |
| 5504 | .din0 ({dcache_rdata_w0_m[32], | |
| 5505 | dcache_rdata_w0_m[35], dcache_rdata_w0_m[38], w0_p4_0}), | |
| 5506 | .din1 ({dcache_rdata_w0_m[33], | |
| 5507 | dcache_rdata_w0_m[36], dcache_rdata_w0_m[39], w0_p4_1}), | |
| 5508 | .din2 ({dcache_rdata_w0_m[34], | |
| 5509 | dcache_rdata_w0_m[37], rparity_w0_m[4], w0_p4_2}), | |
| 5510 | .dout ({w0_p4_0, w0_p4_1, w0_p4_2, | |
| 5511 | w0_parity_m[4]})); | |
| 5512 | xor_macro__ports_3__width_4 w0_par5( | |
| 5513 | .din0 ({dcache_rdata_w0_m[40], | |
| 5514 | dcache_rdata_w0_m[43], dcache_rdata_w0_m[46], w0_p5_0}), | |
| 5515 | .din1 ({dcache_rdata_w0_m[41], | |
| 5516 | dcache_rdata_w0_m[44], dcache_rdata_w0_m[47], w0_p5_1}), | |
| 5517 | .din2 ({dcache_rdata_w0_m[42], | |
| 5518 | dcache_rdata_w0_m[45], rparity_w0_m[5], w0_p5_2}), | |
| 5519 | .dout ({w0_p5_0, w0_p5_1, w0_p5_2, | |
| 5520 | w0_parity_m[5]})); | |
| 5521 | xor_macro__ports_3__width_4 w0_par6( | |
| 5522 | .din0 ({dcache_rdata_w0_m[48], | |
| 5523 | dcache_rdata_w0_m[51], dcache_rdata_w0_m[54], w0_p6_0}), | |
| 5524 | .din1 ({dcache_rdata_w0_m[49], | |
| 5525 | dcache_rdata_w0_m[52], dcache_rdata_w0_m[55], w0_p6_1}), | |
| 5526 | .din2 ({dcache_rdata_w0_m[50], | |
| 5527 | dcache_rdata_w0_m[53], rparity_w0_m[6], w0_p6_2}), | |
| 5528 | .dout ({w0_p6_0, w0_p6_1, w0_p6_2, | |
| 5529 | w0_parity_m[6]})); | |
| 5530 | xor_macro__ports_3__width_4 w0_par7( | |
| 5531 | .din0 ({dcache_rdata_w0_m[56], | |
| 5532 | dcache_rdata_w0_m[59], dcache_rdata_w0_m[62], w0_p7_0}), | |
| 5533 | .din1 ({dcache_rdata_w0_m[57], | |
| 5534 | dcache_rdata_w0_m[60], dcache_rdata_w0_m[63], w0_p7_1}), | |
| 5535 | .din2 ({dcache_rdata_w0_m[58], | |
| 5536 | dcache_rdata_w0_m[61], rparity_w0_m[7], w0_p7_2}), | |
| 5537 | .dout ({w0_p7_0, w0_p7_1, w0_p7_2, | |
| 5538 | w0_parity_m[7]})); | |
| 5539 | xor_macro__ports_3__width_4 w1_par0( | |
| 5540 | .din0 ({dcache_rdata_w1_m[0], | |
| 5541 | dcache_rdata_w1_m[3], dcache_rdata_w1_m[6], w1_p0_0}), | |
| 5542 | .din1 ({dcache_rdata_w1_m[1], | |
| 5543 | dcache_rdata_w1_m[4], dcache_rdata_w1_m[7], w1_p0_1}), | |
| 5544 | .din2 ({dcache_rdata_w1_m[2], | |
| 5545 | dcache_rdata_w1_m[5], rparity_w1_m[0], w1_p0_2}), | |
| 5546 | .dout ({w1_p0_0, w1_p0_1, w1_p0_2, | |
| 5547 | w1_parity_m[0]})); | |
| 5548 | xor_macro__ports_3__width_4 w1_par1( | |
| 5549 | .din0 ({dcache_rdata_w1_m[8], | |
| 5550 | dcache_rdata_w1_m[11], dcache_rdata_w1_m[14], w1_p1_0}), | |
| 5551 | .din1 ({dcache_rdata_w1_m[9], | |
| 5552 | dcache_rdata_w1_m[12], dcache_rdata_w1_m[15], w1_p1_1}), | |
| 5553 | .din2 ({dcache_rdata_w1_m[10], | |
| 5554 | dcache_rdata_w1_m[13], rparity_w1_m[1], w1_p1_2}), | |
| 5555 | .dout ({w1_p1_0, w1_p1_1, w1_p1_2, | |
| 5556 | w1_parity_m[1]})); | |
| 5557 | xor_macro__ports_3__width_4 w1_par2( | |
| 5558 | .din0 ({dcache_rdata_w1_m[16], | |
| 5559 | dcache_rdata_w1_m[19], dcache_rdata_w1_m[22], w1_p2_0}), | |
| 5560 | .din1 ({dcache_rdata_w1_m[17], | |
| 5561 | dcache_rdata_w1_m[20], dcache_rdata_w1_m[23], w1_p2_1}), | |
| 5562 | .din2 ({dcache_rdata_w1_m[18], | |
| 5563 | dcache_rdata_w1_m[21], rparity_w1_m[2], w1_p2_2}), | |
| 5564 | .dout ({w1_p2_0, w1_p2_1, w1_p2_2, | |
| 5565 | w1_parity_m[2]})); | |
| 5566 | xor_macro__ports_3__width_4 w1_par3( | |
| 5567 | .din0 ({dcache_rdata_w1_m[24], | |
| 5568 | dcache_rdata_w1_m[27], dcache_rdata_w1_m[30], w1_p3_0}), | |
| 5569 | .din1 ({dcache_rdata_w1_m[25], | |
| 5570 | dcache_rdata_w1_m[28], dcache_rdata_w1_m[31], w1_p3_1}), | |
| 5571 | .din2 ({dcache_rdata_w1_m[26], | |
| 5572 | dcache_rdata_w1_m[29], rparity_w1_m[3], w1_p3_2}), | |
| 5573 | .dout ({w1_p3_0, w1_p3_1, w1_p3_2, | |
| 5574 | w1_parity_m[3]})); | |
| 5575 | xor_macro__ports_3__width_4 w1_par4( | |
| 5576 | .din0 ({dcache_rdata_w1_m[32], | |
| 5577 | dcache_rdata_w1_m[35], dcache_rdata_w1_m[38], w1_p4_0}), | |
| 5578 | .din1 ({dcache_rdata_w1_m[33], | |
| 5579 | dcache_rdata_w1_m[36], dcache_rdata_w1_m[39], w1_p4_1}), | |
| 5580 | .din2 ({dcache_rdata_w1_m[34], | |
| 5581 | dcache_rdata_w1_m[37], rparity_w1_m[4], w1_p4_2}), | |
| 5582 | .dout ({w1_p4_0, w1_p4_1, w1_p4_2, | |
| 5583 | w1_parity_m[4]})); | |
| 5584 | xor_macro__ports_3__width_4 w1_par5( | |
| 5585 | .din0 ({dcache_rdata_w1_m[40], | |
| 5586 | dcache_rdata_w1_m[43], dcache_rdata_w1_m[46], w1_p5_0}), | |
| 5587 | .din1 ({dcache_rdata_w1_m[41], | |
| 5588 | dcache_rdata_w1_m[44], dcache_rdata_w1_m[47], w1_p5_1}), | |
| 5589 | .din2 ({dcache_rdata_w1_m[42], | |
| 5590 | dcache_rdata_w1_m[45], rparity_w1_m[5], w1_p5_2}), | |
| 5591 | .dout ({w1_p5_0, w1_p5_1, w1_p5_2, | |
| 5592 | w1_parity_m[5]})); | |
| 5593 | xor_macro__ports_3__width_4 w1_par6( | |
| 5594 | .din0 ({dcache_rdata_w1_m[48], | |
| 5595 | dcache_rdata_w1_m[51], dcache_rdata_w1_m[54], w1_p6_0}), | |
| 5596 | .din1 ({dcache_rdata_w1_m[49], | |
| 5597 | dcache_rdata_w1_m[52], dcache_rdata_w1_m[55], w1_p6_1}), | |
| 5598 | .din2 ({dcache_rdata_w1_m[50], | |
| 5599 | dcache_rdata_w1_m[53], rparity_w1_m[6], w1_p6_2}), | |
| 5600 | .dout ({w1_p6_0, w1_p6_1, w1_p6_2, | |
| 5601 | w1_parity_m[6]})); | |
| 5602 | xor_macro__ports_3__width_4 w1_par7( | |
| 5603 | .din0 ({dcache_rdata_w1_m[56], | |
| 5604 | dcache_rdata_w1_m[59], dcache_rdata_w1_m[62], w1_p7_0}), | |
| 5605 | .din1 ({dcache_rdata_w1_m[57], | |
| 5606 | dcache_rdata_w1_m[60], dcache_rdata_w1_m[63], w1_p7_1}), | |
| 5607 | .din2 ({dcache_rdata_w1_m[58], | |
| 5608 | dcache_rdata_w1_m[61], rparity_w1_m[7], w1_p7_2}), | |
| 5609 | .dout ({w1_p7_0, w1_p7_1, w1_p7_2, | |
| 5610 | w1_parity_m[7]})); | |
| 5611 | xor_macro__ports_3__width_4 w2_par0( | |
| 5612 | .din0 ({dcache_rdata_w2_m[0], | |
| 5613 | dcache_rdata_w2_m[3], dcache_rdata_w2_m[6], w2_p0_0}), | |
| 5614 | .din1 ({dcache_rdata_w2_m[1], | |
| 5615 | dcache_rdata_w2_m[4], dcache_rdata_w2_m[7], w2_p0_1}), | |
| 5616 | .din2 ({dcache_rdata_w2_m[2], | |
| 5617 | dcache_rdata_w2_m[5], rparity_w2_m[0], w2_p0_2}), | |
| 5618 | .dout ({w2_p0_0, w2_p0_1, w2_p0_2, | |
| 5619 | w2_parity_m[0]})); | |
| 5620 | xor_macro__ports_3__width_4 w2_par1( | |
| 5621 | .din0 ({dcache_rdata_w2_m[8], | |
| 5622 | dcache_rdata_w2_m[11], dcache_rdata_w2_m[14], w2_p1_0}), | |
| 5623 | .din1 ({dcache_rdata_w2_m[9], | |
| 5624 | dcache_rdata_w2_m[12], dcache_rdata_w2_m[15], w2_p1_1}), | |
| 5625 | .din2 ({dcache_rdata_w2_m[10], | |
| 5626 | dcache_rdata_w2_m[13], rparity_w2_m[1], w2_p1_2}), | |
| 5627 | .dout ({w2_p1_0, w2_p1_1, w2_p1_2, | |
| 5628 | w2_parity_m[1]})); | |
| 5629 | xor_macro__ports_3__width_4 w2_par2( | |
| 5630 | .din0 ({dcache_rdata_w2_m[16], | |
| 5631 | dcache_rdata_w2_m[19], dcache_rdata_w2_m[22], w2_p2_0}), | |
| 5632 | .din1 ({dcache_rdata_w2_m[17], | |
| 5633 | dcache_rdata_w2_m[20], dcache_rdata_w2_m[23], w2_p2_1}), | |
| 5634 | .din2 ({dcache_rdata_w2_m[18], | |
| 5635 | dcache_rdata_w2_m[21], rparity_w2_m[2], w2_p2_2}), | |
| 5636 | .dout ({w2_p2_0, w2_p2_1, w2_p2_2, | |
| 5637 | w2_parity_m[2]})); | |
| 5638 | xor_macro__ports_3__width_4 w2_par3( | |
| 5639 | .din0 ({dcache_rdata_w2_m[24], | |
| 5640 | dcache_rdata_w2_m[27], dcache_rdata_w2_m[30], w2_p3_0}), | |
| 5641 | .din1 ({dcache_rdata_w2_m[25], | |
| 5642 | dcache_rdata_w2_m[28], dcache_rdata_w2_m[31], w2_p3_1}), | |
| 5643 | .din2 ({dcache_rdata_w2_m[26], | |
| 5644 | dcache_rdata_w2_m[29], rparity_w2_m[3], w2_p3_2}), | |
| 5645 | .dout ({w2_p3_0, w2_p3_1, w2_p3_2, | |
| 5646 | w2_parity_m[3]})); | |
| 5647 | xor_macro__ports_3__width_4 w2_par4( | |
| 5648 | .din0 ({dcache_rdata_w2_m[32], | |
| 5649 | dcache_rdata_w2_m[35], dcache_rdata_w2_m[38], w2_p4_0}), | |
| 5650 | .din1 ({dcache_rdata_w2_m[33], | |
| 5651 | dcache_rdata_w2_m[36], dcache_rdata_w2_m[39], w2_p4_1}), | |
| 5652 | .din2 ({dcache_rdata_w2_m[34], | |
| 5653 | dcache_rdata_w2_m[37], rparity_w2_m[4], w2_p4_2}), | |
| 5654 | .dout ({w2_p4_0, w2_p4_1, w2_p4_2, | |
| 5655 | w2_parity_m[4]})); | |
| 5656 | xor_macro__ports_3__width_4 w2_par5( | |
| 5657 | .din0 ({dcache_rdata_w2_m[40], | |
| 5658 | dcache_rdata_w2_m[43], dcache_rdata_w2_m[46], w2_p5_0}), | |
| 5659 | .din1 ({dcache_rdata_w2_m[41], | |
| 5660 | dcache_rdata_w2_m[44], dcache_rdata_w2_m[47], w2_p5_1}), | |
| 5661 | .din2 ({dcache_rdata_w2_m[42], | |
| 5662 | dcache_rdata_w2_m[45], rparity_w2_m[5], w2_p5_2}), | |
| 5663 | .dout ({w2_p5_0, w2_p5_1, w2_p5_2, | |
| 5664 | w2_parity_m[5]})); | |
| 5665 | xor_macro__ports_3__width_4 w2_par6( | |
| 5666 | .din0 ({dcache_rdata_w2_m[48], | |
| 5667 | dcache_rdata_w2_m[51], dcache_rdata_w2_m[54], w2_p6_0}), | |
| 5668 | .din1 ({dcache_rdata_w2_m[49], | |
| 5669 | dcache_rdata_w2_m[52], dcache_rdata_w2_m[55], w2_p6_1}), | |
| 5670 | .din2 ({dcache_rdata_w2_m[50], | |
| 5671 | dcache_rdata_w2_m[53], rparity_w2_m[6], w2_p6_2}), | |
| 5672 | .dout ({w2_p6_0, w2_p6_1, w2_p6_2, | |
| 5673 | w2_parity_m[6]})); | |
| 5674 | xor_macro__ports_3__width_4 w2_par7( | |
| 5675 | .din0 ({dcache_rdata_w2_m[56], | |
| 5676 | dcache_rdata_w2_m[59], dcache_rdata_w2_m[62], w2_p7_0}), | |
| 5677 | .din1 ({dcache_rdata_w2_m[57], | |
| 5678 | dcache_rdata_w2_m[60], dcache_rdata_w2_m[63], w2_p7_1}), | |
| 5679 | .din2 ({dcache_rdata_w2_m[58], | |
| 5680 | dcache_rdata_w2_m[61], rparity_w2_m[7], w2_p7_2}), | |
| 5681 | .dout ({w2_p7_0, w2_p7_1, w2_p7_2, | |
| 5682 | w2_parity_m[7]})); | |
| 5683 | xor_macro__ports_3__width_4 w3_par0( | |
| 5684 | .din0 ({dcache_rdata_w3_m[0], | |
| 5685 | dcache_rdata_w3_m[3], dcache_rdata_w3_m[6], w3_p0_0}), | |
| 5686 | .din1 ({dcache_rdata_w3_m[1], | |
| 5687 | dcache_rdata_w3_m[4], dcache_rdata_w3_m[7], w3_p0_1}), | |
| 5688 | .din2 ({dcache_rdata_w3_m[2], | |
| 5689 | dcache_rdata_w3_m[5], rparity_w3_m[0], w3_p0_2}), | |
| 5690 | .dout ({w3_p0_0, w3_p0_1, w3_p0_2, | |
| 5691 | w3_parity_m[0]})); | |
| 5692 | xor_macro__ports_3__width_4 w3_par1( | |
| 5693 | .din0 ({dcache_rdata_w3_m[8], | |
| 5694 | dcache_rdata_w3_m[11], dcache_rdata_w3_m[14], w3_p1_0}), | |
| 5695 | .din1 ({dcache_rdata_w3_m[9], | |
| 5696 | dcache_rdata_w3_m[12], dcache_rdata_w3_m[15], w3_p1_1}), | |
| 5697 | .din2 ({dcache_rdata_w3_m[10], | |
| 5698 | dcache_rdata_w3_m[13], rparity_w3_m[1], w3_p1_2}), | |
| 5699 | .dout ({w3_p1_0, w3_p1_1, w3_p1_2, | |
| 5700 | w3_parity_m[1]})); | |
| 5701 | xor_macro__ports_3__width_4 w3_par2( | |
| 5702 | .din0 ({dcache_rdata_w3_m[16], | |
| 5703 | dcache_rdata_w3_m[19], dcache_rdata_w3_m[22], w3_p2_0}), | |
| 5704 | .din1 ({dcache_rdata_w3_m[17], | |
| 5705 | dcache_rdata_w3_m[20], dcache_rdata_w3_m[23], w3_p2_1}), | |
| 5706 | .din2 ({dcache_rdata_w3_m[18], | |
| 5707 | dcache_rdata_w3_m[21], rparity_w3_m[2], w3_p2_2}), | |
| 5708 | .dout ({w3_p2_0, w3_p2_1, w3_p2_2, | |
| 5709 | w3_parity_m[2]})); | |
| 5710 | xor_macro__ports_3__width_4 w3_par3( | |
| 5711 | .din0 ({dcache_rdata_w3_m[24], | |
| 5712 | dcache_rdata_w3_m[27], dcache_rdata_w3_m[30], w3_p3_0}), | |
| 5713 | .din1 ({dcache_rdata_w3_m[25], | |
| 5714 | dcache_rdata_w3_m[28], dcache_rdata_w3_m[31], w3_p3_1}), | |
| 5715 | .din2 ({dcache_rdata_w3_m[26], | |
| 5716 | dcache_rdata_w3_m[29], rparity_w3_m[3], w3_p3_2}), | |
| 5717 | .dout ({w3_p3_0, w3_p3_1, w3_p3_2, | |
| 5718 | w3_parity_m[3]})); | |
| 5719 | xor_macro__ports_3__width_4 w3_par4( | |
| 5720 | .din0 ({dcache_rdata_w3_m[32], | |
| 5721 | dcache_rdata_w3_m[35], dcache_rdata_w3_m[38], w3_p4_0}), | |
| 5722 | .din1 ({dcache_rdata_w3_m[33], | |
| 5723 | dcache_rdata_w3_m[36], dcache_rdata_w3_m[39], w3_p4_1}), | |
| 5724 | .din2 ({dcache_rdata_w3_m[34], | |
| 5725 | dcache_rdata_w3_m[37], rparity_w3_m[4], w3_p4_2}), | |
| 5726 | .dout ({w3_p4_0, w3_p4_1, w3_p4_2, | |
| 5727 | w3_parity_m[4]})); | |
| 5728 | xor_macro__ports_3__width_4 w3_par5( | |
| 5729 | .din0 ({dcache_rdata_w3_m[40], | |
| 5730 | dcache_rdata_w3_m[43], dcache_rdata_w3_m[46], w3_p5_0}), | |
| 5731 | .din1 ({dcache_rdata_w3_m[41], | |
| 5732 | dcache_rdata_w3_m[44], dcache_rdata_w3_m[47], w3_p5_1}), | |
| 5733 | .din2 ({dcache_rdata_w3_m[42], | |
| 5734 | dcache_rdata_w3_m[45], rparity_w3_m[5], w3_p5_2}), | |
| 5735 | .dout ({w3_p5_0, w3_p5_1, w3_p5_2, | |
| 5736 | w3_parity_m[5]})); | |
| 5737 | xor_macro__ports_3__width_4 w3_par6( | |
| 5738 | .din0 ({dcache_rdata_w3_m[48], | |
| 5739 | dcache_rdata_w3_m[51], dcache_rdata_w3_m[54], w3_p6_0}), | |
| 5740 | .din1 ({dcache_rdata_w3_m[49], | |
| 5741 | dcache_rdata_w3_m[52], dcache_rdata_w3_m[55], w3_p6_1}), | |
| 5742 | .din2 ({dcache_rdata_w3_m[50], | |
| 5743 | dcache_rdata_w3_m[53], rparity_w3_m[6], w3_p6_2}), | |
| 5744 | .dout ({w3_p6_0, w3_p6_1, w3_p6_2, | |
| 5745 | w3_parity_m[6]})); | |
| 5746 | xor_macro__ports_3__width_4 w3_par7( | |
| 5747 | .din0 ({dcache_rdata_w3_m[56], | |
| 5748 | dcache_rdata_w3_m[59], dcache_rdata_w3_m[62], w3_p7_0}), | |
| 5749 | .din1 ({dcache_rdata_w3_m[57], | |
| 5750 | dcache_rdata_w3_m[60], dcache_rdata_w3_m[63], w3_p7_1}), | |
| 5751 | .din2 ({dcache_rdata_w3_m[58], | |
| 5752 | dcache_rdata_w3_m[61], rparity_w3_m[7], w3_p7_2}), | |
| 5753 | .dout ({w3_p7_0, w3_p7_1, w3_p7_2, | |
| 5754 | w3_parity_m[7]})); | |
| 5755 | msff_ctl_macro__fs_1__width_8 dff_byte_perr_w0( | |
| 5756 | .scan_in (dff_byte_perr_w0_scanin[7:0]), | |
| 5757 | .scan_out (dff_byte_perr_w0_scanout[7:0]), | |
| 5758 | .l1clk (l1clk_out_pm), | |
| 5759 | .din (w0_parity_m[7:0]), | |
| 5760 | .dout (w0_parity_b[7:0]), | |
| 5761 | .siclk (siclk), | |
| 5762 | .soclk (soclk)); | |
| 5763 | msff_ctl_macro__fs_1__width_8 dff_byte_perr_w1( | |
| 5764 | .scan_in (dff_byte_perr_w1_scanin[7:0]), | |
| 5765 | .scan_out (dff_byte_perr_w1_scanout[7:0]), | |
| 5766 | .l1clk (l1clk_out_pm), | |
| 5767 | .din (w1_parity_m[7:0]), | |
| 5768 | .dout (w1_parity_b[7:0]), | |
| 5769 | .siclk (siclk), | |
| 5770 | .soclk (soclk)); | |
| 5771 | msff_ctl_macro__fs_1__width_8 dff_byte_perr_w2( | |
| 5772 | .scan_in (dff_byte_perr_w2_scanin[7:0]), | |
| 5773 | .scan_out (dff_byte_perr_w2_scanout[7:0]), | |
| 5774 | .l1clk (l1clk_out_pm), | |
| 5775 | .din (w2_parity_m[7:0]), | |
| 5776 | .dout (w2_parity_b[7:0]), | |
| 5777 | .siclk (siclk), | |
| 5778 | .soclk (soclk)); | |
| 5779 | msff_ctl_macro__fs_1__width_8 dff_byte_perr_w3( | |
| 5780 | .scan_in (dff_byte_perr_w3_scanin[7:0]), | |
| 5781 | .scan_out (dff_byte_perr_w3_scanout[7:0]), | |
| 5782 | .l1clk (l1clk_out_pm), | |
| 5783 | .din (w3_parity_m[7:0]), | |
| 5784 | .dout (w3_parity_b[7:0]), | |
| 5785 | .siclk (siclk), | |
| 5786 | .soclk (soclk)); | |
| 5787 | mux_macro__mux_aonpe__ports_8__width_1 parity_w0( | |
| 5788 | .din0 (1'b1), | |
| 5789 | .din1 (1'b1), | |
| 5790 | .din2 (1'b1), | |
| 5791 | .din3 (1'b1), | |
| 5792 | .din4 (1'b1), | |
| 5793 | .din5 (1'b1), | |
| 5794 | .din6 (1'b1), | |
| 5795 | .din7 (1'b1), | |
| 5796 | .sel0 (w0_parity_b[0]), | |
| 5797 | .sel1 (w0_parity_b[1]), | |
| 5798 | .sel2 (w0_parity_b[2]), | |
| 5799 | .sel3 (w0_parity_b[3]), | |
| 5800 | .sel4 (w0_parity_b[4]), | |
| 5801 | .sel5 (w0_parity_b[5]), | |
| 5802 | .sel6 (w0_parity_b[6]), | |
| 5803 | .sel7 (w0_parity_b[7]), | |
| 5804 | .dout (w0_parity_err_b)); | |
| 5805 | mux_macro__mux_aonpe__ports_8__width_1 parity_w1( | |
| 5806 | .din0 (1'b1), | |
| 5807 | .din1 (1'b1), | |
| 5808 | .din2 (1'b1), | |
| 5809 | .din3 (1'b1), | |
| 5810 | .din4 (1'b1), | |
| 5811 | .din5 (1'b1), | |
| 5812 | .din6 (1'b1), | |
| 5813 | .din7 (1'b1), | |
| 5814 | .sel0 (w1_parity_b[0]), | |
| 5815 | .sel1 (w1_parity_b[1]), | |
| 5816 | .sel2 (w1_parity_b[2]), | |
| 5817 | .sel3 (w1_parity_b[3]), | |
| 5818 | .sel4 (w1_parity_b[4]), | |
| 5819 | .sel5 (w1_parity_b[5]), | |
| 5820 | .sel6 (w1_parity_b[6]), | |
| 5821 | .sel7 (w1_parity_b[7]), | |
| 5822 | .dout (w1_parity_err_b)); | |
| 5823 | mux_macro__mux_aonpe__ports_8__width_1 parity_w2( | |
| 5824 | .din0 (1'b1), | |
| 5825 | .din1 (1'b1), | |
| 5826 | .din2 (1'b1), | |
| 5827 | .din3 (1'b1), | |
| 5828 | .din4 (1'b1), | |
| 5829 | .din5 (1'b1), | |
| 5830 | .din6 (1'b1), | |
| 5831 | .din7 (1'b1), | |
| 5832 | .sel0 (w2_parity_b[0]), | |
| 5833 | .sel1 (w2_parity_b[1]), | |
| 5834 | .sel2 (w2_parity_b[2]), | |
| 5835 | .sel3 (w2_parity_b[3]), | |
| 5836 | .sel4 (w2_parity_b[4]), | |
| 5837 | .sel5 (w2_parity_b[5]), | |
| 5838 | .sel6 (w2_parity_b[6]), | |
| 5839 | .sel7 (w2_parity_b[7]), | |
| 5840 | .dout (w2_parity_err_b)); | |
| 5841 | mux_macro__mux_aonpe__ports_8__width_1 parity_w3( | |
| 5842 | .din0 (1'b1), | |
| 5843 | .din1 (1'b1), | |
| 5844 | .din2 (1'b1), | |
| 5845 | .din3 (1'b1), | |
| 5846 | .din4 (1'b1), | |
| 5847 | .din5 (1'b1), | |
| 5848 | .din6 (1'b1), | |
| 5849 | .din7 (1'b1), | |
| 5850 | .sel0 (w3_parity_b[0]), | |
| 5851 | .sel1 (w3_parity_b[1]), | |
| 5852 | .sel2 (w3_parity_b[2]), | |
| 5853 | .sel3 (w3_parity_b[3]), | |
| 5854 | .sel4 (w3_parity_b[4]), | |
| 5855 | .sel5 (w3_parity_b[5]), | |
| 5856 | .sel6 (w3_parity_b[6]), | |
| 5857 | .sel7 (w3_parity_b[7]), | |
| 5858 | .dout (w3_parity_err_b)); | |
| 5859 | msff_ctl_macro__fs_1__width_12 dff_red_in( | |
| 5860 | .scan_in (dff_red_in_scanin[11:0]), | |
| 5861 | .scan_out (dff_red_in_scanout[11:0]), | |
| 5862 | .l1clk (l1clk_in), | |
| 5863 | .din ({fuse_dca_repair_value[5:0], | |
| 5864 | fuse_dca_repair_en[1:0], fuse_dca_rid[1:0], fuse_dca_wen, | |
| 5865 | fuse_red_reset}), | |
| 5866 | .dout ({fuse_dca_repair_value_ff[5:0], | |
| 5867 | fuse_dca_repair_en_ff[1:0], fuse_dca_rid_ff[1:0], | |
| 5868 | fuse_dca_wen_ff, fuse_red_reset_ff}), | |
| 5869 | .siclk (siclk), | |
| 5870 | .soclk (soclk)); | |
| 5871 | msff_ctl_macro__fs_1__width_8 dff_red_out( | |
| 5872 | .scan_in (dff_red_out_scanin[7:0]), | |
| 5873 | .scan_out (dff_red_out_scanout[7:0]), | |
| 5874 | .l1clk (l1clk_out), | |
| 5875 | .din | |
| 5876 | ({dca_fuse_repair_value_pre[5:0], dca_fuse_repair_en_pre[1:0]}), | |
| 5877 | .dout ({dca_fuse_repair_value[5:0], | |
| 5878 | dca_fuse_repair_en[1:0]}), | |
| 5879 | .siclk (siclk), | |
| 5880 | .soclk (soclk)); | |
| 5881 | endmodule | |
| 5882 | ||
| 5883 | `celldefine | |
| 5884 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 36871 */ | |
| 5885 | // No timescale specified | |
| 5886 | module mux_macro__mux_aonpe__ports_4__width_64(din0, sel0, din1, sel1, din2, | |
| 5887 | sel2, din3, sel3, dout); | |
| 5888 | ||
| 5889 | input [63:0] din0; | |
| 5890 | input sel0; | |
| 5891 | input [63:0] din1; | |
| 5892 | input sel1; | |
| 5893 | input [63:0] din2; | |
| 5894 | input sel2; | |
| 5895 | input [63:0] din3; | |
| 5896 | input sel3; | |
| 5897 | output [63:0] dout; | |
| 5898 | ||
| 5899 | wire buffout0; | |
| 5900 | wire buffout1; | |
| 5901 | wire buffout2; | |
| 5902 | wire buffout3; | |
| 5903 | ||
| 5904 | cl_dp1_muxbuff4_8x c0_0( | |
| 5905 | .in0 (sel0), | |
| 5906 | .in1 (sel1), | |
| 5907 | .in2 (sel2), | |
| 5908 | .in3 (sel3), | |
| 5909 | .out0 (buffout0), | |
| 5910 | .out1 (buffout1), | |
| 5911 | .out2 (buffout2), | |
| 5912 | .out3 (buffout3)); | |
| 5913 | mux4s #(64) d0_0( | |
| 5914 | .sel0 (buffout0), | |
| 5915 | .sel1 (buffout1), | |
| 5916 | .sel2 (buffout2), | |
| 5917 | .sel3 (buffout3), | |
| 5918 | .in0 (din0[63:0]), | |
| 5919 | .in1 (din1[63:0]), | |
| 5920 | .in2 (din2[63:0]), | |
| 5921 | .in3 (din3[63:0]), | |
| 5922 | .dout (dout[63:0])); | |
| 5923 | endmodule | |
| 5924 | `endcelldefine | |
| 5925 | ||
| 5926 | `celldefine | |
| 5927 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 40507 */ | |
| 5928 | // No timescale specified | |
| 5929 | module msff_ctl_macro__fs_1__width_64(din, l1clk, scan_in, siclk, soclk, dout, | |
| 5930 | scan_out); | |
| 5931 | ||
| 5932 | input [63:0] din; | |
| 5933 | input l1clk; | |
| 5934 | input [63:0] scan_in; | |
| 5935 | input siclk; | |
| 5936 | input soclk; | |
| 5937 | output [63:0] dout; | |
| 5938 | output [63:0] scan_out; | |
| 5939 | ||
| 5940 | wire [63:0] fdin; | |
| 5941 | ||
| 5942 | assign fdin[63:0] = din[63:0]; | |
| 5943 | ||
| 5944 | dff #(64) d0_0( | |
| 5945 | .l1clk (l1clk), | |
| 5946 | .siclk (siclk), | |
| 5947 | .soclk (soclk), | |
| 5948 | .d (fdin[63:0]), | |
| 5949 | .si (scan_in[63:0]), | |
| 5950 | .so (scan_out[63:0]), | |
| 5951 | .q (dout[63:0])); | |
| 5952 | endmodule | |
| 5953 | `endcelldefine | |
| 5954 | ||
| 5955 | `celldefine | |
| 5956 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 58446 */ | |
| 5957 | // No timescale specified | |
| 5958 | module msff_ctl_macro__fs_1__width_5(din, l1clk, scan_in, siclk, soclk, dout, | |
| 5959 | scan_out); | |
| 5960 | ||
| 5961 | input [4:0] din; | |
| 5962 | input l1clk; | |
| 5963 | input [4:0] scan_in; | |
| 5964 | input siclk; | |
| 5965 | input soclk; | |
| 5966 | output [4:0] dout; | |
| 5967 | output [4:0] scan_out; | |
| 5968 | ||
| 5969 | wire [4:0] fdin; | |
| 5970 | ||
| 5971 | assign fdin[4:0] = din[4:0]; | |
| 5972 | ||
| 5973 | dff #(5) d0_0( | |
| 5974 | .l1clk (l1clk), | |
| 5975 | .siclk (siclk), | |
| 5976 | .soclk (soclk), | |
| 5977 | .d (fdin[4:0]), | |
| 5978 | .si (scan_in[4:0]), | |
| 5979 | .so (scan_out[4:0]), | |
| 5980 | .q (dout[4:0])); | |
| 5981 | endmodule | |
| 5982 | `endcelldefine | |
| 5983 | ||
| 5984 | `celldefine | |
| 5985 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 58527 */ | |
| 5986 | // No timescale specified | |
| 5987 | module msff_ctl_macro__fs_1__width_8(din, l1clk, scan_in, siclk, soclk, dout, | |
| 5988 | scan_out); | |
| 5989 | ||
| 5990 | input [7:0] din; | |
| 5991 | input l1clk; | |
| 5992 | input [7:0] scan_in; | |
| 5993 | input siclk; | |
| 5994 | input soclk; | |
| 5995 | output [7:0] dout; | |
| 5996 | output [7:0] scan_out; | |
| 5997 | ||
| 5998 | wire [7:0] fdin; | |
| 5999 | ||
| 6000 | assign fdin[7:0] = din[7:0]; | |
| 6001 | ||
| 6002 | dff #(8) d0_0( | |
| 6003 | .l1clk (l1clk), | |
| 6004 | .siclk (siclk), | |
| 6005 | .soclk (soclk), | |
| 6006 | .d (fdin[7:0]), | |
| 6007 | .si (scan_in[7:0]), | |
| 6008 | .so (scan_out[7:0]), | |
| 6009 | .q (dout[7:0])); | |
| 6010 | endmodule | |
| 6011 | `endcelldefine | |
| 6012 | ||
| 6013 | `celldefine | |
| 6014 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 61614 */ | |
| 6015 | // No timescale specified | |
| 6016 | module msff_ctl_macro__fs_1__width_3(din, l1clk, scan_in, siclk, soclk, dout, | |
| 6017 | scan_out); | |
| 6018 | ||
| 6019 | input [2:0] din; | |
| 6020 | input l1clk; | |
| 6021 | input [2:0] scan_in; | |
| 6022 | input siclk; | |
| 6023 | input soclk; | |
| 6024 | output [2:0] dout; | |
| 6025 | output [2:0] scan_out; | |
| 6026 | ||
| 6027 | wire [2:0] fdin; | |
| 6028 | ||
| 6029 | assign fdin[2:0] = din[2:0]; | |
| 6030 | ||
| 6031 | dff #(3) d0_0( | |
| 6032 | .l1clk (l1clk), | |
| 6033 | .siclk (siclk), | |
| 6034 | .soclk (soclk), | |
| 6035 | .d (fdin[2:0]), | |
| 6036 | .si (scan_in[2:0]), | |
| 6037 | .so (scan_out[2:0]), | |
| 6038 | .q (dout[2:0])); | |
| 6039 | endmodule | |
| 6040 | `endcelldefine | |
| 6041 | ||
| 6042 | `celldefine | |
| 6043 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 62461 */ | |
| 6044 | // No timescale specified | |
| 6045 | module mux_macro__mux_aonpe__ports_8__width_1(din0, sel0, din1, sel1, din2, | |
| 6046 | sel2, din3, sel3, din4, sel4, din5, sel5, din6, sel6, din7, sel7, dout); | |
| 6047 | ||
| 6048 | input [0:0] din0; | |
| 6049 | input sel0; | |
| 6050 | input [0:0] din1; | |
| 6051 | input sel1; | |
| 6052 | input [0:0] din2; | |
| 6053 | input sel2; | |
| 6054 | input [0:0] din3; | |
| 6055 | input sel3; | |
| 6056 | input [0:0] din4; | |
| 6057 | input sel4; | |
| 6058 | input [0:0] din5; | |
| 6059 | input sel5; | |
| 6060 | input [0:0] din6; | |
| 6061 | input sel6; | |
| 6062 | input [0:0] din7; | |
| 6063 | input sel7; | |
| 6064 | output [0:0] dout; | |
| 6065 | ||
| 6066 | wire buffout0; | |
| 6067 | wire buffout1; | |
| 6068 | wire buffout2; | |
| 6069 | wire buffout3; | |
| 6070 | wire buffout4; | |
| 6071 | wire buffout5; | |
| 6072 | wire buffout6; | |
| 6073 | wire buffout7; | |
| 6074 | ||
| 6075 | cl_dp1_muxbuff8_8x c0_0( | |
| 6076 | .in0 (sel0), | |
| 6077 | .in1 (sel1), | |
| 6078 | .in2 (sel2), | |
| 6079 | .in3 (sel3), | |
| 6080 | .in4 (sel4), | |
| 6081 | .in5 (sel5), | |
| 6082 | .in6 (sel6), | |
| 6083 | .in7 (sel7), | |
| 6084 | .out0 (buffout0), | |
| 6085 | .out1 (buffout1), | |
| 6086 | .out2 (buffout2), | |
| 6087 | .out3 (buffout3), | |
| 6088 | .out4 (buffout4), | |
| 6089 | .out5 (buffout5), | |
| 6090 | .out6 (buffout6), | |
| 6091 | .out7 (buffout7)); | |
| 6092 | mux8s #(1) d0_0( | |
| 6093 | .sel0 (buffout0), | |
| 6094 | .sel1 (buffout1), | |
| 6095 | .sel2 (buffout2), | |
| 6096 | .sel3 (buffout3), | |
| 6097 | .sel4 (buffout4), | |
| 6098 | .sel5 (buffout5), | |
| 6099 | .sel6 (buffout6), | |
| 6100 | .sel7 (buffout7), | |
| 6101 | .in0 (din0[0]), | |
| 6102 | .in1 (din1[0]), | |
| 6103 | .in2 (din2[0]), | |
| 6104 | .in3 (din3[0]), | |
| 6105 | .in4 (din4[0]), | |
| 6106 | .in5 (din5[0]), | |
| 6107 | .in6 (din6[0]), | |
| 6108 | .in7 (din7[0]), | |
| 6109 | .dout (dout[0])); | |
| 6110 | endmodule | |
| 6111 | `endcelldefine | |
| 6112 | ||
| 6113 | `celldefine | |
| 6114 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129372 */ | |
| 6115 | // No timescale specified | |
| 6116 | module mux_macro__mux_aope__ports_2__width_8(din0, din1, sel0, dout); | |
| 6117 | ||
| 6118 | input [7:0] din0; | |
| 6119 | input [7:0] din1; | |
| 6120 | input sel0; | |
| 6121 | output [7:0] dout; | |
| 6122 | ||
| 6123 | wire psel0; | |
| 6124 | wire psel1; | |
| 6125 | ||
| 6126 | cl_dp1_penc2_8x c0_0( | |
| 6127 | .sel0 (sel0), | |
| 6128 | .psel0 (psel0), | |
| 6129 | .psel1 (psel1)); | |
| 6130 | mux2s #(8) d0_0( | |
| 6131 | .sel0 (psel0), | |
| 6132 | .sel1 (psel1), | |
| 6133 | .in0 (din0[7:0]), | |
| 6134 | .in1 (din1[7:0]), | |
| 6135 | .dout (dout[7:0])); | |
| 6136 | endmodule | |
| 6137 | `endcelldefine | |
| 6138 | ||
| 6139 | `celldefine | |
| 6140 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129421 */ | |
| 6141 | // No timescale specified | |
| 6142 | module mux_macro__mux_aodec__ports_4__width_4(din0, din1, din2, din3, sel, dout) | |
| 6143 | ; | |
| 6144 | ||
| 6145 | input [3:0] din0; | |
| 6146 | input [3:0] din1; | |
| 6147 | input [3:0] din2; | |
| 6148 | input [3:0] din3; | |
| 6149 | input [1:0] sel; | |
| 6150 | output [3:0] dout; | |
| 6151 | ||
| 6152 | wire psel0; | |
| 6153 | wire psel1; | |
| 6154 | wire psel2; | |
| 6155 | wire psel3; | |
| 6156 | ||
| 6157 | cl_dp1_pdec4_8x c0_0( | |
| 6158 | .test (1'b1), | |
| 6159 | .sel0 (sel[0]), | |
| 6160 | .sel1 (sel[1]), | |
| 6161 | .psel0 (psel0), | |
| 6162 | .psel1 (psel1), | |
| 6163 | .psel2 (psel2), | |
| 6164 | .psel3 (psel3)); | |
| 6165 | mux4s #(4) d0_0( | |
| 6166 | .sel0 (psel0), | |
| 6167 | .sel1 (psel1), | |
| 6168 | .sel2 (psel2), | |
| 6169 | .sel3 (psel3), | |
| 6170 | .in0 (din0[3:0]), | |
| 6171 | .in1 (din1[3:0]), | |
| 6172 | .in2 (din2[3:0]), | |
| 6173 | .in3 (din3[3:0]), | |
| 6174 | .dout (dout[3:0])); | |
| 6175 | endmodule | |
| 6176 | `endcelldefine | |
| 6177 | ||
| 6178 | `celldefine | |
| 6179 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129458 */ | |
| 6180 | // No timescale specified | |
| 6181 | module tisram_msff_macro__fs_1__width_7(d, scan_in, l1clk, siclk, soclk, | |
| 6182 | scan_out, latout, latout_l); | |
| 6183 | ||
| 6184 | input [6:0] d; | |
| 6185 | input [6:0] scan_in; | |
| 6186 | input l1clk; | |
| 6187 | input siclk; | |
| 6188 | input soclk; | |
| 6189 | output [6:0] scan_out; | |
| 6190 | output [6:0] latout; | |
| 6191 | output [6:0] latout_l; | |
| 6192 | ||
| 6193 | tisram_msff #(7) d0_0( | |
| 6194 | .d (d[6:0]), | |
| 6195 | .si (scan_in[6:0]), | |
| 6196 | .so (scan_out[6:0]), | |
| 6197 | .l1clk (l1clk), | |
| 6198 | .siclk (siclk), | |
| 6199 | .soclk (soclk), | |
| 6200 | .latout (latout[6:0]), | |
| 6201 | .latout_l (latout_l[6:0])); | |
| 6202 | endmodule | |
| 6203 | `endcelldefine | |
| 6204 | ||
| 6205 | `celldefine | |
| 6206 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129483 */ | |
| 6207 | // No timescale specified | |
| 6208 | module tisram_msff_macro__fs_1__width_16(d, scan_in, l1clk, siclk, soclk, | |
| 6209 | scan_out, latout, latout_l); | |
| 6210 | ||
| 6211 | input [15:0] d; | |
| 6212 | input [15:0] scan_in; | |
| 6213 | input l1clk; | |
| 6214 | input siclk; | |
| 6215 | input soclk; | |
| 6216 | output [15:0] scan_out; | |
| 6217 | output [15:0] latout; | |
| 6218 | output [15:0] latout_l; | |
| 6219 | ||
| 6220 | tisram_msff #(16) d0_0( | |
| 6221 | .d (d[15:0]), | |
| 6222 | .si (scan_in[15:0]), | |
| 6223 | .so (scan_out[15:0]), | |
| 6224 | .l1clk (l1clk), | |
| 6225 | .siclk (siclk), | |
| 6226 | .soclk (soclk), | |
| 6227 | .latout (latout[15:0]), | |
| 6228 | .latout_l (latout_l[15:0])); | |
| 6229 | endmodule | |
| 6230 | `endcelldefine | |
| 6231 | ||
| 6232 | `celldefine | |
| 6233 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129508 */ | |
| 6234 | // No timescale specified | |
| 6235 | module msff_ctl_macro__fs_1__width_144(din, l1clk, scan_in, siclk, soclk, dout, | |
| 6236 | scan_out); | |
| 6237 | ||
| 6238 | input [143:0] din; | |
| 6239 | input l1clk; | |
| 6240 | input [143:0] scan_in; | |
| 6241 | input siclk; | |
| 6242 | input soclk; | |
| 6243 | output [143:0] dout; | |
| 6244 | output [143:0] scan_out; | |
| 6245 | ||
| 6246 | wire [143:0] fdin; | |
| 6247 | ||
| 6248 | assign fdin[143:0] = din[143:0]; | |
| 6249 | ||
| 6250 | dff #(144) d0_0( | |
| 6251 | .l1clk (l1clk), | |
| 6252 | .siclk (siclk), | |
| 6253 | .soclk (soclk), | |
| 6254 | .d (fdin[143:0]), | |
| 6255 | .si (scan_in[143:0]), | |
| 6256 | .so (scan_out[143:0]), | |
| 6257 | .q (dout[143:0])); | |
| 6258 | endmodule | |
| 6259 | `endcelldefine | |
| 6260 | ||
| 6261 | `celldefine | |
| 6262 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129535 */ | |
| 6263 | // No timescale specified | |
| 6264 | module n2_dca_sp_9kb_array(l1clk, l1clk_wr, l1clk_red, rd_en_top_b, rd_en_bot_b, | |
| 6265 | rd_en_a, wr_en_a, wr_en_b, wr_inh_b, addr_b, byte_wr_en_b, wr_waysel_b, | |
| 6266 | dcache_wdata_m, dcache_wparity_m, dcache_rdata_w0_m, rparity_w0_m, | |
| 6267 | dcache_rdata_w1_m, rparity_w1_m, dcache_rdata_w2_m, rparity_w2_m, | |
| 6268 | dcache_rdata_w3_m, rparity_w3_m, fuse_dca_repair_value, | |
| 6269 | fuse_dca_repair_en, fuse_dca_rid, fuse_dca_wen, fuse_red_reset, | |
| 6270 | dca_fuse_repair_value, dca_fuse_repair_en, vnw_ary); | |
| 6271 | ||
| 6272 | input l1clk; | |
| 6273 | input l1clk_wr; | |
| 6274 | input l1clk_red; | |
| 6275 | input rd_en_top_b; | |
| 6276 | input rd_en_bot_b; | |
| 6277 | input rd_en_a; | |
| 6278 | input wr_en_a; | |
| 6279 | input wr_en_b; | |
| 6280 | input wr_inh_b; | |
| 6281 | input [10:3] addr_b; | |
| 6282 | input [15:0] byte_wr_en_b; | |
| 6283 | input [3:0] wr_waysel_b; | |
| 6284 | input [127:0] dcache_wdata_m; | |
| 6285 | input [15:0] dcache_wparity_m; | |
| 6286 | output [63:0] dcache_rdata_w0_m; | |
| 6287 | output [7:0] rparity_w0_m; | |
| 6288 | output [63:0] dcache_rdata_w1_m; | |
| 6289 | output [7:0] rparity_w1_m; | |
| 6290 | output [63:0] dcache_rdata_w2_m; | |
| 6291 | output [7:0] rparity_w2_m; | |
| 6292 | output [63:0] dcache_rdata_w3_m; | |
| 6293 | output [7:0] rparity_w3_m; | |
| 6294 | input [5:0] fuse_dca_repair_value; | |
| 6295 | input [1:0] fuse_dca_repair_en; | |
| 6296 | input [1:0] fuse_dca_rid; | |
| 6297 | input fuse_dca_wen; | |
| 6298 | input fuse_red_reset; | |
| 6299 | output [5:0] dca_fuse_repair_value; | |
| 6300 | output [1:0] dca_fuse_repair_en; | |
| 6301 | input vnw_ary; | |
| 6302 | ||
| 6303 | wire fuse_red_reset_qual; | |
| 6304 | wire fuse_dca_wen_qual; | |
| 6305 | wire [3:0] red_id; | |
| 6306 | wire [3:0] red_reg_clk_; | |
| 6307 | wire [5:0] red_data; | |
| 6308 | wire [1:0] red_enable; | |
| 6309 | wire [8:0] w0_byte7_l_unused; | |
| 6310 | wire [8:0] w0_byte6_l_unused; | |
| 6311 | wire [8:0] w0_byte5_l_unused; | |
| 6312 | wire [8:0] w0_byte4_l_unused; | |
| 6313 | wire [8:0] w0_byte3_l_unused; | |
| 6314 | wire [8:0] w0_byte2_l_unused; | |
| 6315 | wire [8:0] w0_byte1_l_unused; | |
| 6316 | wire [8:0] w0_byte0_l_unused; | |
| 6317 | wire [8:0] w1_byte7_l_unused; | |
| 6318 | wire [8:0] w1_byte6_l_unused; | |
| 6319 | wire [8:0] w1_byte5_l_unused; | |
| 6320 | wire [8:0] w1_byte4_l_unused; | |
| 6321 | wire [8:0] w1_byte3_l_unused; | |
| 6322 | wire [8:0] w1_byte2_l_unused; | |
| 6323 | wire [8:0] w1_byte1_l_unused; | |
| 6324 | wire [8:0] w1_byte0_l_unused; | |
| 6325 | wire [8:0] w2_byte7_l_unused; | |
| 6326 | wire [8:0] w2_byte6_l_unused; | |
| 6327 | wire [8:0] w2_byte5_l_unused; | |
| 6328 | wire [8:0] w2_byte4_l_unused; | |
| 6329 | wire [8:0] w2_byte3_l_unused; | |
| 6330 | wire [8:0] w2_byte2_l_unused; | |
| 6331 | wire [8:0] w2_byte1_l_unused; | |
| 6332 | wire [8:0] w2_byte0_l_unused; | |
| 6333 | wire [8:0] w3_byte7_l_unused; | |
| 6334 | wire [8:0] w3_byte6_l_unused; | |
| 6335 | wire [8:0] w3_byte5_l_unused; | |
| 6336 | wire [8:0] w3_byte4_l_unused; | |
| 6337 | wire [8:0] w3_byte3_l_unused; | |
| 6338 | wire [8:0] w3_byte2_l_unused; | |
| 6339 | wire [8:0] w3_byte1_l_unused; | |
| 6340 | wire [8:0] w3_byte0_l_unused; | |
| 6341 | reg [5:0] red_reg_d_bl; | |
| 6342 | reg [5:0] red_reg_d_br; | |
| 6343 | reg [5:0] red_reg_d_tl; | |
| 6344 | reg [5:0] red_reg_d_tr; | |
| 6345 | reg [1:0] red_reg_en_bl; | |
| 6346 | reg [1:0] red_reg_en_br; | |
| 6347 | reg [1:0] red_reg_en_tl; | |
| 6348 | reg [1:0] red_reg_en_tr; | |
| 6349 | supply0 vss; | |
| 6350 | supply1 vdd; | |
| 6351 | ||
| 6352 | assign fuse_red_reset_qual = (fuse_red_reset & (~wr_inh_b)); | |
| 6353 | assign fuse_dca_wen_qual = (fuse_dca_wen & (~wr_inh_b)); | |
| 6354 | assign red_id[0] = ((~fuse_dca_rid[1]) & (~fuse_dca_rid[0])); | |
| 6355 | assign red_id[1] = ((~fuse_dca_rid[1]) & fuse_dca_rid[0]); | |
| 6356 | assign red_id[2] = (fuse_dca_rid[1] & (~fuse_dca_rid[0])); | |
| 6357 | assign red_id[3] = (fuse_dca_rid[1] & fuse_dca_rid[0]); | |
| 6358 | assign red_reg_clk_[0] = (~((~l1clk_red) & ((red_id[0] & | |
| 6359 | fuse_dca_wen_qual) | fuse_red_reset_qual))); | |
| 6360 | assign red_reg_clk_[1] = (~((~l1clk_red) & ((red_id[1] & | |
| 6361 | fuse_dca_wen_qual) | fuse_red_reset_qual))); | |
| 6362 | assign red_reg_clk_[2] = (~((~l1clk_red) & ((red_id[2] & | |
| 6363 | fuse_dca_wen_qual) | fuse_red_reset_qual))); | |
| 6364 | assign red_reg_clk_[3] = (~((~l1clk_red) & ((red_id[3] & | |
| 6365 | fuse_dca_wen_qual) | fuse_red_reset_qual))); | |
| 6366 | assign red_data[5:0] = (fuse_dca_repair_value[5:0] & {6 { | |
| 6367 | (~fuse_red_reset_qual)}}); | |
| 6368 | assign red_enable[1:0] = (fuse_dca_repair_en[1:0] & {2 { | |
| 6369 | (~fuse_red_reset_qual)}}); | |
| 6370 | assign dca_fuse_repair_value[5:0] = ((((red_reg_d_tr[5:0] & {6 { | |
| 6371 | red_id[3]}}) | (red_reg_d_tl[5:0] & {6 {red_id[2]}})) | ( | |
| 6372 | red_reg_d_br[5:0] & {6 {red_id[1]}})) | (red_reg_d_bl[5:0] & {6 | |
| 6373 | {red_id[0]}})); | |
| 6374 | assign dca_fuse_repair_en[1:0] = ((((red_reg_en_tr[1:0] & {2 {red_id[3]} | |
| 6375 | }) | (red_reg_en_tl[1:0] & {2 {red_id[2]}})) | ( | |
| 6376 | red_reg_en_br[1:0] & {2 {red_id[1]}})) | (red_reg_en_bl[1:0] & { | |
| 6377 | 2 {red_id[0]}})); | |
| 6378 | ||
| 6379 | n2_dca_sp_9kb_bank way01( | |
| 6380 | .red_data_l (red_reg_d_tl[5:0]), | |
| 6381 | .red_enable_l (red_reg_en_tl[1:0]), | |
| 6382 | .red_data_r (red_reg_d_tr[5:0]), | |
| 6383 | .red_enable_r (red_reg_en_tr[1:0]), | |
| 6384 | .rd_en_b (rd_en_top_b), | |
| 6385 | .wr_waysel_b (wr_waysel_b[1:0]), | |
| 6386 | .wrd_byte15_a ({dcache_wparity_m[15], | |
| 6387 | dcache_wdata_m[127:120]}), | |
| 6388 | .wrd_byte14_a ({dcache_wparity_m[14], | |
| 6389 | dcache_wdata_m[119:112]}), | |
| 6390 | .wrd_byte13_a ({dcache_wparity_m[13], | |
| 6391 | dcache_wdata_m[111:104]}), | |
| 6392 | .wrd_byte12_a ({dcache_wparity_m[12], | |
| 6393 | dcache_wdata_m[103:96]}), | |
| 6394 | .wrd_byte11_a ({dcache_wparity_m[11], | |
| 6395 | dcache_wdata_m[95:88]}), | |
| 6396 | .wrd_byte10_a ({dcache_wparity_m[10], | |
| 6397 | dcache_wdata_m[87:80]}), | |
| 6398 | .wrd_byte9_a ({dcache_wparity_m[9], | |
| 6399 | dcache_wdata_m[79:72]}), | |
| 6400 | .wrd_byte8_a ({dcache_wparity_m[8], | |
| 6401 | dcache_wdata_m[71:64]}), | |
| 6402 | .wrd_byte7_a ({dcache_wparity_m[7], | |
| 6403 | dcache_wdata_m[63:56]}), | |
| 6404 | .wrd_byte6_a ({dcache_wparity_m[6], | |
| 6405 | dcache_wdata_m[55:48]}), | |
| 6406 | .wrd_byte5_a ({dcache_wparity_m[5], | |
| 6407 | dcache_wdata_m[47:40]}), | |
| 6408 | .wrd_byte4_a ({dcache_wparity_m[4], | |
| 6409 | dcache_wdata_m[39:32]}), | |
| 6410 | .wrd_byte3_a ({dcache_wparity_m[3], | |
| 6411 | dcache_wdata_m[31:24]}), | |
| 6412 | .wrd_byte2_a ({dcache_wparity_m[2], | |
| 6413 | dcache_wdata_m[23:16]}), | |
| 6414 | .wrd_byte1_a ({dcache_wparity_m[1], | |
| 6415 | dcache_wdata_m[15:8]}), | |
| 6416 | .wrd_byte0_a ({dcache_wparity_m[0], | |
| 6417 | dcache_wdata_m[7:0]}), | |
| 6418 | .w0_byte7_h ({rparity_w0_m[7], | |
| 6419 | dcache_rdata_w0_m[63:56]}), | |
| 6420 | .w0_byte6_h ({rparity_w0_m[6], | |
| 6421 | dcache_rdata_w0_m[55:48]}), | |
| 6422 | .w0_byte5_h ({rparity_w0_m[5], | |
| 6423 | dcache_rdata_w0_m[47:40]}), | |
| 6424 | .w0_byte4_h ({rparity_w0_m[4], | |
| 6425 | dcache_rdata_w0_m[39:32]}), | |
| 6426 | .w0_byte3_h ({rparity_w0_m[3], | |
| 6427 | dcache_rdata_w0_m[31:24]}), | |
| 6428 | .w0_byte2_h ({rparity_w0_m[2], | |
| 6429 | dcache_rdata_w0_m[23:16]}), | |
| 6430 | .w0_byte1_h ({rparity_w0_m[1], | |
| 6431 | dcache_rdata_w0_m[15:8]}), | |
| 6432 | .w0_byte0_h ({rparity_w0_m[0], | |
| 6433 | dcache_rdata_w0_m[7:0]}), | |
| 6434 | .w1_byte7_h ({rparity_w1_m[7], | |
| 6435 | dcache_rdata_w1_m[63:56]}), | |
| 6436 | .w1_byte6_h ({rparity_w1_m[6], | |
| 6437 | dcache_rdata_w1_m[55:48]}), | |
| 6438 | .w1_byte5_h ({rparity_w1_m[5], | |
| 6439 | dcache_rdata_w1_m[47:40]}), | |
| 6440 | .w1_byte4_h ({rparity_w1_m[4], | |
| 6441 | dcache_rdata_w1_m[39:32]}), | |
| 6442 | .w1_byte3_h ({rparity_w1_m[3], | |
| 6443 | dcache_rdata_w1_m[31:24]}), | |
| 6444 | .w1_byte2_h ({rparity_w1_m[2], | |
| 6445 | dcache_rdata_w1_m[23:16]}), | |
| 6446 | .w1_byte1_h ({rparity_w1_m[1], | |
| 6447 | dcache_rdata_w1_m[15:8]}), | |
| 6448 | .w1_byte0_h ({rparity_w1_m[0], | |
| 6449 | dcache_rdata_w1_m[7:0]}), | |
| 6450 | .w0_byte7_l (w0_byte7_l_unused[8:0]), | |
| 6451 | .w0_byte6_l (w0_byte6_l_unused[8:0]), | |
| 6452 | .w0_byte5_l (w0_byte5_l_unused[8:0]), | |
| 6453 | .w0_byte4_l (w0_byte4_l_unused[8:0]), | |
| 6454 | .w0_byte3_l (w0_byte3_l_unused[8:0]), | |
| 6455 | .w0_byte2_l (w0_byte2_l_unused[8:0]), | |
| 6456 | .w0_byte1_l (w0_byte1_l_unused[8:0]), | |
| 6457 | .w0_byte0_l (w0_byte0_l_unused[8:0]), | |
| 6458 | .w1_byte7_l (w1_byte7_l_unused[8:0]), | |
| 6459 | .w1_byte6_l (w1_byte6_l_unused[8:0]), | |
| 6460 | .w1_byte5_l (w1_byte5_l_unused[8:0]), | |
| 6461 | .w1_byte4_l (w1_byte4_l_unused[8:0]), | |
| 6462 | .w1_byte3_l (w1_byte3_l_unused[8:0]), | |
| 6463 | .w1_byte2_l (w1_byte2_l_unused[8:0]), | |
| 6464 | .w1_byte1_l (w1_byte1_l_unused[8:0]), | |
| 6465 | .w1_byte0_l (w1_byte0_l_unused[8:0]), | |
| 6466 | .l1clk (l1clk), | |
| 6467 | .l1clk_wr (l1clk_wr), | |
| 6468 | .rd_en_a (rd_en_a), | |
| 6469 | .wr_en_a (wr_en_a), | |
| 6470 | .wr_en_b (wr_en_b), | |
| 6471 | .wr_inh_b (wr_inh_b), | |
| 6472 | .addr_b (addr_b[10:3]), | |
| 6473 | .byte_wr_en_b (byte_wr_en_b[15:0]), | |
| 6474 | .vnw_ary (vnw_ary)); | |
| 6475 | n2_dca_sp_9kb_bank way23( | |
| 6476 | .red_data_l (red_reg_d_bl[5:0]), | |
| 6477 | .red_enable_l (red_reg_en_bl[1:0]), | |
| 6478 | .red_data_r (red_reg_d_br[5:0]), | |
| 6479 | .red_enable_r (red_reg_en_br[1:0]), | |
| 6480 | .rd_en_b (rd_en_bot_b), | |
| 6481 | .wr_waysel_b (wr_waysel_b[3:2]), | |
| 6482 | .wrd_byte15_a ({dcache_wparity_m[15], | |
| 6483 | dcache_wdata_m[127:120]}), | |
| 6484 | .wrd_byte14_a ({dcache_wparity_m[14], | |
| 6485 | dcache_wdata_m[119:112]}), | |
| 6486 | .wrd_byte13_a ({dcache_wparity_m[13], | |
| 6487 | dcache_wdata_m[111:104]}), | |
| 6488 | .wrd_byte12_a ({dcache_wparity_m[12], | |
| 6489 | dcache_wdata_m[103:96]}), | |
| 6490 | .wrd_byte11_a ({dcache_wparity_m[11], | |
| 6491 | dcache_wdata_m[95:88]}), | |
| 6492 | .wrd_byte10_a ({dcache_wparity_m[10], | |
| 6493 | dcache_wdata_m[87:80]}), | |
| 6494 | .wrd_byte9_a ({dcache_wparity_m[9], | |
| 6495 | dcache_wdata_m[79:72]}), | |
| 6496 | .wrd_byte8_a ({dcache_wparity_m[8], | |
| 6497 | dcache_wdata_m[71:64]}), | |
| 6498 | .wrd_byte7_a ({dcache_wparity_m[7], | |
| 6499 | dcache_wdata_m[63:56]}), | |
| 6500 | .wrd_byte6_a ({dcache_wparity_m[6], | |
| 6501 | dcache_wdata_m[55:48]}), | |
| 6502 | .wrd_byte5_a ({dcache_wparity_m[5], | |
| 6503 | dcache_wdata_m[47:40]}), | |
| 6504 | .wrd_byte4_a ({dcache_wparity_m[4], | |
| 6505 | dcache_wdata_m[39:32]}), | |
| 6506 | .wrd_byte3_a ({dcache_wparity_m[3], | |
| 6507 | dcache_wdata_m[31:24]}), | |
| 6508 | .wrd_byte2_a ({dcache_wparity_m[2], | |
| 6509 | dcache_wdata_m[23:16]}), | |
| 6510 | .wrd_byte1_a ({dcache_wparity_m[1], | |
| 6511 | dcache_wdata_m[15:8]}), | |
| 6512 | .wrd_byte0_a ({dcache_wparity_m[0], | |
| 6513 | dcache_wdata_m[7:0]}), | |
| 6514 | .w0_byte7_h ({rparity_w2_m[7], | |
| 6515 | dcache_rdata_w2_m[63:56]}), | |
| 6516 | .w0_byte6_h ({rparity_w2_m[6], | |
| 6517 | dcache_rdata_w2_m[55:48]}), | |
| 6518 | .w0_byte5_h ({rparity_w2_m[5], | |
| 6519 | dcache_rdata_w2_m[47:40]}), | |
| 6520 | .w0_byte4_h ({rparity_w2_m[4], | |
| 6521 | dcache_rdata_w2_m[39:32]}), | |
| 6522 | .w0_byte3_h ({rparity_w2_m[3], | |
| 6523 | dcache_rdata_w2_m[31:24]}), | |
| 6524 | .w0_byte2_h ({rparity_w2_m[2], | |
| 6525 | dcache_rdata_w2_m[23:16]}), | |
| 6526 | .w0_byte1_h ({rparity_w2_m[1], | |
| 6527 | dcache_rdata_w2_m[15:8]}), | |
| 6528 | .w0_byte0_h ({rparity_w2_m[0], | |
| 6529 | dcache_rdata_w2_m[7:0]}), | |
| 6530 | .w1_byte7_h ({rparity_w3_m[7], | |
| 6531 | dcache_rdata_w3_m[63:56]}), | |
| 6532 | .w1_byte6_h ({rparity_w3_m[6], | |
| 6533 | dcache_rdata_w3_m[55:48]}), | |
| 6534 | .w1_byte5_h ({rparity_w3_m[5], | |
| 6535 | dcache_rdata_w3_m[47:40]}), | |
| 6536 | .w1_byte4_h ({rparity_w3_m[4], | |
| 6537 | dcache_rdata_w3_m[39:32]}), | |
| 6538 | .w1_byte3_h ({rparity_w3_m[3], | |
| 6539 | dcache_rdata_w3_m[31:24]}), | |
| 6540 | .w1_byte2_h ({rparity_w3_m[2], | |
| 6541 | dcache_rdata_w3_m[23:16]}), | |
| 6542 | .w1_byte1_h ({rparity_w3_m[1], | |
| 6543 | dcache_rdata_w3_m[15:8]}), | |
| 6544 | .w1_byte0_h ({rparity_w3_m[0], | |
| 6545 | dcache_rdata_w3_m[7:0]}), | |
| 6546 | .w0_byte7_l (w2_byte7_l_unused[8:0]), | |
| 6547 | .w0_byte6_l (w2_byte6_l_unused[8:0]), | |
| 6548 | .w0_byte5_l (w2_byte5_l_unused[8:0]), | |
| 6549 | .w0_byte4_l (w2_byte4_l_unused[8:0]), | |
| 6550 | .w0_byte3_l (w2_byte3_l_unused[8:0]), | |
| 6551 | .w0_byte2_l (w2_byte2_l_unused[8:0]), | |
| 6552 | .w0_byte1_l (w2_byte1_l_unused[8:0]), | |
| 6553 | .w0_byte0_l (w2_byte0_l_unused[8:0]), | |
| 6554 | .w1_byte7_l (w3_byte7_l_unused[8:0]), | |
| 6555 | .w1_byte6_l (w3_byte6_l_unused[8:0]), | |
| 6556 | .w1_byte5_l (w3_byte5_l_unused[8:0]), | |
| 6557 | .w1_byte4_l (w3_byte4_l_unused[8:0]), | |
| 6558 | .w1_byte3_l (w3_byte3_l_unused[8:0]), | |
| 6559 | .w1_byte2_l (w3_byte2_l_unused[8:0]), | |
| 6560 | .w1_byte1_l (w3_byte1_l_unused[8:0]), | |
| 6561 | .w1_byte0_l (w3_byte0_l_unused[8:0]), | |
| 6562 | .l1clk (l1clk), | |
| 6563 | .l1clk_wr (l1clk_wr), | |
| 6564 | .rd_en_a (rd_en_a), | |
| 6565 | .wr_en_a (wr_en_a), | |
| 6566 | .wr_en_b (wr_en_b), | |
| 6567 | .wr_inh_b (wr_inh_b), | |
| 6568 | .addr_b (addr_b[10:3]), | |
| 6569 | .byte_wr_en_b (byte_wr_en_b[15:0]), | |
| 6570 | .vnw_ary (vnw_ary)); | |
| 6571 | ||
| 6572 | initial begin | |
| 6573 | red_reg_d_bl[5:0] = 6'b0; | |
| 6574 | red_reg_en_bl[1:0] = 2'b0; | |
| 6575 | red_reg_d_br[5:0] = 6'b0; | |
| 6576 | red_reg_en_br[1:0] = 2'b0; | |
| 6577 | red_reg_d_tl[5:0] = 6'b0; | |
| 6578 | red_reg_en_tl[1:0] = 2'b0; | |
| 6579 | red_reg_d_tr[5:0] = 6'b0; | |
| 6580 | red_reg_en_tr[1:0] = 2'b0; | |
| 6581 | end | |
| 6582 | always @(red_reg_clk_ or red_data or red_enable) begin | |
| 6583 | if (~red_reg_clk_[0]) begin | |
| 6584 | red_reg_d_bl[5:0] = red_data[5:0]; | |
| 6585 | red_reg_en_bl[1:0] = red_enable[1:0]; | |
| 6586 | end | |
| 6587 | if (~red_reg_clk_[1]) begin | |
| 6588 | red_reg_d_br[5:0] = red_data[5:0]; | |
| 6589 | red_reg_en_br[1:0] = red_enable[1:0]; | |
| 6590 | end | |
| 6591 | if (~red_reg_clk_[2]) begin | |
| 6592 | red_reg_d_tl[5:0] = red_data[5:0]; | |
| 6593 | red_reg_en_tl[1:0] = red_enable[1:0]; | |
| 6594 | end | |
| 6595 | if (~red_reg_clk_[3]) begin | |
| 6596 | red_reg_d_tr[5:0] = red_data[5:0]; | |
| 6597 | red_reg_en_tr[1:0] = red_enable[1:0]; | |
| 6598 | end | |
| 6599 | end | |
| 6600 | endmodule | |
| 6601 | `endcelldefine | |
| 6602 | ||
| 6603 | `celldefine | |
| 6604 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129875 */ | |
| 6605 | // No timescale specified | |
| 6606 | module n2_dca_sp_9kb_bank(l1clk, l1clk_wr, rd_en_b, rd_en_a, wr_en_a, wr_en_b, | |
| 6607 | wr_inh_b, addr_b, byte_wr_en_b, wr_waysel_b, red_data_l, red_data_r, | |
| 6608 | red_enable_l, red_enable_r, vnw_ary, wrd_byte15_a, wrd_byte14_a, | |
| 6609 | wrd_byte13_a, wrd_byte12_a, wrd_byte11_a, wrd_byte10_a, wrd_byte9_a, | |
| 6610 | wrd_byte8_a, wrd_byte7_a, wrd_byte6_a, wrd_byte5_a, wrd_byte4_a, | |
| 6611 | wrd_byte3_a, wrd_byte2_a, wrd_byte1_a, wrd_byte0_a, w1_byte7_h, | |
| 6612 | w1_byte6_h, w1_byte5_h, w1_byte4_h, w1_byte3_h, w1_byte2_h, w1_byte1_h, | |
| 6613 | w1_byte0_h, w1_byte7_l, w1_byte6_l, w1_byte5_l, w1_byte4_l, w1_byte3_l, | |
| 6614 | w1_byte2_l, w1_byte1_l, w1_byte0_l, w0_byte7_h, w0_byte6_h, w0_byte5_h, | |
| 6615 | w0_byte4_h, w0_byte3_h, w0_byte2_h, w0_byte1_h, w0_byte0_h, w0_byte7_l, | |
| 6616 | w0_byte6_l, w0_byte5_l, w0_byte4_l, w0_byte3_l, w0_byte2_l, w0_byte1_l, | |
| 6617 | w0_byte0_l); | |
| 6618 | ||
| 6619 | input l1clk; | |
| 6620 | input l1clk_wr; | |
| 6621 | input rd_en_b; | |
| 6622 | input rd_en_a; | |
| 6623 | input wr_en_a; | |
| 6624 | input wr_en_b; | |
| 6625 | input wr_inh_b; | |
| 6626 | input [10:3] addr_b; | |
| 6627 | input [15:0] byte_wr_en_b; | |
| 6628 | input [1:0] wr_waysel_b; | |
| 6629 | input [5:0] red_data_l; | |
| 6630 | input [5:0] red_data_r; | |
| 6631 | input [1:0] red_enable_l; | |
| 6632 | input [1:0] red_enable_r; | |
| 6633 | input vnw_ary; | |
| 6634 | input [8:0] wrd_byte15_a; | |
| 6635 | input [8:0] wrd_byte14_a; | |
| 6636 | input [8:0] wrd_byte13_a; | |
| 6637 | input [8:0] wrd_byte12_a; | |
| 6638 | input [8:0] wrd_byte11_a; | |
| 6639 | input [8:0] wrd_byte10_a; | |
| 6640 | input [8:0] wrd_byte9_a; | |
| 6641 | input [8:0] wrd_byte8_a; | |
| 6642 | input [8:0] wrd_byte7_a; | |
| 6643 | input [8:0] wrd_byte6_a; | |
| 6644 | input [8:0] wrd_byte5_a; | |
| 6645 | input [8:0] wrd_byte4_a; | |
| 6646 | input [8:0] wrd_byte3_a; | |
| 6647 | input [8:0] wrd_byte2_a; | |
| 6648 | input [8:0] wrd_byte1_a; | |
| 6649 | input [8:0] wrd_byte0_a; | |
| 6650 | output [8:0] w1_byte7_h; | |
| 6651 | output [8:0] w1_byte6_h; | |
| 6652 | output [8:0] w1_byte5_h; | |
| 6653 | output [8:0] w1_byte4_h; | |
| 6654 | output [8:0] w1_byte3_h; | |
| 6655 | output [8:0] w1_byte2_h; | |
| 6656 | output [8:0] w1_byte1_h; | |
| 6657 | output [8:0] w1_byte0_h; | |
| 6658 | output [8:0] w1_byte7_l; | |
| 6659 | output [8:0] w1_byte6_l; | |
| 6660 | output [8:0] w1_byte5_l; | |
| 6661 | output [8:0] w1_byte4_l; | |
| 6662 | output [8:0] w1_byte3_l; | |
| 6663 | output [8:0] w1_byte2_l; | |
| 6664 | output [8:0] w1_byte1_l; | |
| 6665 | output [8:0] w1_byte0_l; | |
| 6666 | output [8:0] w0_byte7_h; | |
| 6667 | output [8:0] w0_byte6_h; | |
| 6668 | output [8:0] w0_byte5_h; | |
| 6669 | output [8:0] w0_byte4_h; | |
| 6670 | output [8:0] w0_byte3_h; | |
| 6671 | output [8:0] w0_byte2_h; | |
| 6672 | output [8:0] w0_byte1_h; | |
| 6673 | output [8:0] w0_byte0_h; | |
| 6674 | output [8:0] w0_byte7_l; | |
| 6675 | output [8:0] w0_byte6_l; | |
| 6676 | output [8:0] w0_byte5_l; | |
| 6677 | output [8:0] w0_byte4_l; | |
| 6678 | output [8:0] w0_byte3_l; | |
| 6679 | output [8:0] w0_byte2_l; | |
| 6680 | output [8:0] w0_byte1_l; | |
| 6681 | output [8:0] w0_byte0_l; | |
| 6682 | ||
| 6683 | wire [71:0] w0_sao_h; | |
| 6684 | wire [71:0] w0_sao_l; | |
| 6685 | wire [71:0] w1_sao_h; | |
| 6686 | wire [71:0] w1_sao_l; | |
| 6687 | wire [15:0] red_unused; | |
| 6688 | wire [143:0] wrd; | |
| 6689 | wire [287:0] din; | |
| 6690 | wire [287:0] byte_mask; | |
| 6691 | wire [287:0] byte_mask_inv; | |
| 6692 | wire [287:0] temp; | |
| 6693 | wire [287:0] new_data; | |
| 6694 | wire w0_wcs; | |
| 6695 | wire w1_wcs; | |
| 6696 | wire [287:0] wr_data; | |
| 6697 | wire rcs_l; | |
| 6698 | wire [71:0] w0_dout; | |
| 6699 | wire [71:0] w1_dout; | |
| 6700 | wire l1clk_b; | |
| 6701 | ||
| 6702 | reg [(288 - 1):0] mem[(128 - 1):0]; | |
| 6703 | reg [(288 - 1):0] local_dout; | |
| 6704 | integer i; | |
| 6705 | reg [71:0] w0_sao_h_r; | |
| 6706 | reg [71:0] w0_sao_l_r; | |
| 6707 | reg [71:0] w1_sao_h_r; | |
| 6708 | reg [71:0] w1_sao_l_r; | |
| 6709 | supply0 vss; | |
| 6710 | supply1 vdd; | |
| 6711 | ||
| 6712 | assign red_unused[15:0] = {red_data_l[5:0], red_enable_l[1:0], | |
| 6713 | red_data_r[5:0], red_enable_r[1:0]}; | |
| 6714 | assign wrd[143:0] = {wrd_byte15_a[8:0], wrd_byte14_a[8:0], | |
| 6715 | wrd_byte13_a[8:0], wrd_byte12_a[8:0], wrd_byte11_a[8:0], | |
| 6716 | wrd_byte10_a[8:0], wrd_byte9_a[8:0], wrd_byte8_a[8:0], | |
| 6717 | wrd_byte7_a[8:0], wrd_byte6_a[8:0], wrd_byte5_a[8:0], | |
| 6718 | wrd_byte4_a[8:0], wrd_byte3_a[8:0], wrd_byte2_a[8:0], | |
| 6719 | wrd_byte1_a[8:0], wrd_byte0_a[8:0]}; | |
| 6720 | assign din[287:0] = {wrd[143:0], wrd[143:0]}; | |
| 6721 | assign byte_mask[287:0] = {{9 {byte_wr_en_b[15]}}, {9 | |
| 6722 | {byte_wr_en_b[14]}}, {9 {byte_wr_en_b[13]}}, {9 | |
| 6723 | {byte_wr_en_b[12]}}, {9 {byte_wr_en_b[11]}}, {9 | |
| 6724 | {byte_wr_en_b[10]}}, {9 {byte_wr_en_b[9]}}, {9 | |
| 6725 | {byte_wr_en_b[8]}}, {9 {byte_wr_en_b[7]}}, {9 | |
| 6726 | {byte_wr_en_b[6]}}, {9 {byte_wr_en_b[5]}}, {9 | |
| 6727 | {byte_wr_en_b[4]}}, {9 {byte_wr_en_b[3]}}, {9 | |
| 6728 | {byte_wr_en_b[2]}}, {9 {byte_wr_en_b[1]}}, {9 | |
| 6729 | {byte_wr_en_b[0]}}, {9 {byte_wr_en_b[15]}}, {9 | |
| 6730 | {byte_wr_en_b[14]}}, {9 {byte_wr_en_b[13]}}, {9 | |
| 6731 | {byte_wr_en_b[12]}}, {9 {byte_wr_en_b[11]}}, {9 | |
| 6732 | {byte_wr_en_b[10]}}, {9 {byte_wr_en_b[9]}}, {9 | |
| 6733 | {byte_wr_en_b[8]}}, {9 {byte_wr_en_b[7]}}, {9 | |
| 6734 | {byte_wr_en_b[6]}}, {9 {byte_wr_en_b[5]}}, {9 | |
| 6735 | {byte_wr_en_b[4]}}, {9 {byte_wr_en_b[3]}}, {9 | |
| 6736 | {byte_wr_en_b[2]}}, {9 {byte_wr_en_b[1]}}, {9 {byte_wr_en_b[0]}} | |
| 6737 | }; | |
| 6738 | assign byte_mask_inv[287:0] = (~byte_mask[287:0]); | |
| 6739 | assign temp[287:0] = mem[addr_b[10:4]]; | |
| 6740 | assign new_data[287:0] = ((temp[287:0] & byte_mask_inv[287:0]) | ( | |
| 6741 | din[287:0] & byte_mask[287:0])); | |
| 6742 | assign w0_wcs = (((wr_waysel_b[0] & wr_en_b) & (~wr_inh_b)) & (~rd_en_b) | |
| 6743 | ); | |
| 6744 | assign w1_wcs = (((wr_waysel_b[1] & wr_en_b) & (~wr_inh_b)) & (~rd_en_b) | |
| 6745 | ); | |
| 6746 | assign wr_data[143:0] = (w0_wcs ? new_data[143:0] : temp[143:0]); | |
| 6747 | assign wr_data[287:144] = (w1_wcs ? new_data[287:144] : temp[287:144]); | |
| 6748 | assign rcs_l = (rd_en_b & (~wr_en_b)); | |
| 6749 | assign w0_dout[71:0] = (addr_b[3] ? local_dout[71:0] : | |
| 6750 | local_dout[143:72]); | |
| 6751 | assign w1_dout[71:0] = (addr_b[3] ? local_dout[215:144] : | |
| 6752 | local_dout[287:216]); | |
| 6753 | assign l1clk_b = (~l1clk); | |
| 6754 | assign w0_sao_h[71:0] = (w0_sao_h_r[71:0] & {72 {l1clk_b}}); | |
| 6755 | assign w0_sao_l[71:0] = (w0_sao_l_r[71:0] & {72 {l1clk_b}}); | |
| 6756 | assign w1_sao_h[71:0] = (w1_sao_h_r[71:0] & {72 {l1clk_b}}); | |
| 6757 | assign w1_sao_l[71:0] = (w1_sao_l_r[71:0] & {72 {l1clk_b}}); | |
| 6758 | assign w0_byte7_h[8:0] = w0_sao_h[71:63]; | |
| 6759 | assign w0_byte6_h[8:0] = w0_sao_h[62:54]; | |
| 6760 | assign w0_byte5_h[8:0] = w0_sao_h[53:45]; | |
| 6761 | assign w0_byte4_h[8:0] = w0_sao_h[44:36]; | |
| 6762 | assign w0_byte3_h[8:0] = w0_sao_h[35:27]; | |
| 6763 | assign w0_byte2_h[8:0] = w0_sao_h[26:18]; | |
| 6764 | assign w0_byte1_h[8:0] = w0_sao_h[17:9]; | |
| 6765 | assign w0_byte0_h[8:0] = w0_sao_h[8:0]; | |
| 6766 | assign w0_byte7_l[8:0] = w0_sao_l[71:63]; | |
| 6767 | assign w0_byte6_l[8:0] = w0_sao_l[62:54]; | |
| 6768 | assign w0_byte5_l[8:0] = w0_sao_l[53:45]; | |
| 6769 | assign w0_byte4_l[8:0] = w0_sao_l[44:36]; | |
| 6770 | assign w0_byte3_l[8:0] = w0_sao_l[35:27]; | |
| 6771 | assign w0_byte2_l[8:0] = w0_sao_l[26:18]; | |
| 6772 | assign w0_byte1_l[8:0] = w0_sao_l[17:9]; | |
| 6773 | assign w0_byte0_l[8:0] = w0_sao_l[8:0]; | |
| 6774 | assign w1_byte7_h[8:0] = w1_sao_h[71:63]; | |
| 6775 | assign w1_byte6_h[8:0] = w1_sao_h[62:54]; | |
| 6776 | assign w1_byte5_h[8:0] = w1_sao_h[53:45]; | |
| 6777 | assign w1_byte4_h[8:0] = w1_sao_h[44:36]; | |
| 6778 | assign w1_byte3_h[8:0] = w1_sao_h[35:27]; | |
| 6779 | assign w1_byte2_h[8:0] = w1_sao_h[26:18]; | |
| 6780 | assign w1_byte1_h[8:0] = w1_sao_h[17:9]; | |
| 6781 | assign w1_byte0_h[8:0] = w1_sao_h[8:0]; | |
| 6782 | assign w1_byte7_l[8:0] = w1_sao_l[71:63]; | |
| 6783 | assign w1_byte6_l[8:0] = w1_sao_l[62:54]; | |
| 6784 | assign w1_byte5_l[8:0] = w1_sao_l[53:45]; | |
| 6785 | assign w1_byte4_l[8:0] = w1_sao_l[44:36]; | |
| 6786 | assign w1_byte3_l[8:0] = w1_sao_l[35:27]; | |
| 6787 | assign w1_byte2_l[8:0] = w1_sao_l[26:18]; | |
| 6788 | assign w1_byte1_l[8:0] = w1_sao_l[17:9]; | |
| 6789 | assign w1_byte0_l[8:0] = w1_sao_l[8:0]; | |
| 6790 | ||
| 6791 | initial begin | |
| 6792 | for (i = 0; (i < 128); i = (i + 1)) begin | |
| 6793 | mem[i] = 288'b0; | |
| 6794 | end | |
| 6795 | end | |
| 6796 | always @(negedge l1clk_wr) begin | |
| 6797 | if (w0_wcs | w1_wcs) begin | |
| 6798 | if (rcs_l) begin | |
| 6799 | mem[addr_b[10:4]] <= 288'hxxxxxxxx; | |
| 6800 | end | |
| 6801 | else | |
| 6802 | begin | |
| 6803 | mem[addr_b[10:4]] <= wr_data; | |
| 6804 | end | |
| 6805 | end | |
| 6806 | end | |
| 6807 | always @(l1clk) begin | |
| 6808 | if (~l1clk) begin | |
| 6809 | local_dout[(288 - 1):0] <= 288'b0; | |
| 6810 | end | |
| 6811 | else | |
| 6812 | begin | |
| 6813 | if (rcs_l) begin | |
| 6814 | if ((w0_wcs | w1_wcs) | wr_inh_b) begin | |
| 6815 | local_dout[(288 - 1):0] <= 288'hxxxxxxxx; | |
| 6816 | end | |
| 6817 | else | |
| 6818 | begin | |
| 6819 | local_dout[(288 - 1):0] <= mem[addr_b[10:4]]; | |
| 6820 | end | |
| 6821 | end | |
| 6822 | end | |
| 6823 | end | |
| 6824 | always @(negedge l1clk) begin | |
| 6825 | w0_sao_h_r[71:0] <= (w0_dout[71:0] & {72 {(rd_en_a & (~wr_en_a))}}); | |
| 6826 | w0_sao_l_r[71:0] <= ((~w0_dout[71:0]) & {72 {(rd_en_a & (~wr_en_a))}}) | |
| 6827 | ; | |
| 6828 | w1_sao_h_r[71:0] <= (w1_dout[71:0] & {72 {(rd_en_a & (~wr_en_a))}}); | |
| 6829 | w1_sao_l_r[71:0] <= ((~w1_dout[71:0]) & {72 {(rd_en_a & (~wr_en_a))}}) | |
| 6830 | ; | |
| 6831 | end | |
| 6832 | endmodule | |
| 6833 | `endcelldefine | |
| 6834 | ||
| 6835 | `celldefine | |
| 6836 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 130103 */ | |
| 6837 | // No timescale specified | |
| 6838 | module mux_macro__mux_aope__ports_2__width_64(din0, din1, sel0, dout); | |
| 6839 | ||
| 6840 | input [63:0] din0; | |
| 6841 | input [63:0] din1; | |
| 6842 | input sel0; | |
| 6843 | output [63:0] dout; | |
| 6844 | ||
| 6845 | wire psel0; | |
| 6846 | wire psel1; | |
| 6847 | ||
| 6848 | cl_dp1_penc2_8x c0_0( | |
| 6849 | .sel0 (sel0), | |
| 6850 | .psel0 (psel0), | |
| 6851 | .psel1 (psel1)); | |
| 6852 | mux2s #(64) d0_0( | |
| 6853 | .sel0 (psel0), | |
| 6854 | .sel1 (psel1), | |
| 6855 | .in0 (din0[63:0]), | |
| 6856 | .in1 (din1[63:0]), | |
| 6857 | .dout (dout[63:0])); | |
| 6858 | endmodule | |
| 6859 | `endcelldefine | |
| 6860 | ||
| 6861 | `celldefine | |
| 6862 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 130127 */ | |
| 6863 | // No timescale specified | |
| 6864 | module mux_macro__mux_aope__ports_2__width_4(din0, din1, sel0, dout); | |
| 6865 | ||
| 6866 | input [3:0] din0; | |
| 6867 | input [3:0] din1; | |
| 6868 | input sel0; | |
| 6869 | output [3:0] dout; | |
| 6870 | ||
| 6871 | wire psel0; | |
| 6872 | wire psel1; | |
| 6873 | ||
| 6874 | cl_dp1_penc2_8x c0_0( | |
| 6875 | .sel0 (sel0), | |
| 6876 | .psel0 (psel0), | |
| 6877 | .psel1 (psel1)); | |
| 6878 | mux2s #(4) d0_0( | |
| 6879 | .sel0 (psel0), | |
| 6880 | .sel1 (psel1), | |
| 6881 | .in0 (din0[3:0]), | |
| 6882 | .in1 (din1[3:0]), | |
| 6883 | .dout (dout[3:0])); | |
| 6884 | endmodule | |
| 6885 | `endcelldefine | |
| 6886 | ||
| 6887 | `celldefine | |
| 6888 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 130151 */ | |
| 6889 | // No timescale specified | |
| 6890 | module mux_macro__mux_aonpe__ports_4__width_8(din0, sel0, din1, sel1, din2, | |
| 6891 | sel2, din3, sel3, dout); | |
| 6892 | ||
| 6893 | input [7:0] din0; | |
| 6894 | input sel0; | |
| 6895 | input [7:0] din1; | |
| 6896 | input sel1; | |
| 6897 | input [7:0] din2; | |
| 6898 | input sel2; | |
| 6899 | input [7:0] din3; | |
| 6900 | input sel3; | |
| 6901 | output [7:0] dout; | |
| 6902 | ||
| 6903 | wire buffout0; | |
| 6904 | wire buffout1; | |
| 6905 | wire buffout2; | |
| 6906 | wire buffout3; | |
| 6907 | ||
| 6908 | cl_dp1_muxbuff4_8x c0_0( | |
| 6909 | .in0 (sel0), | |
| 6910 | .in1 (sel1), | |
| 6911 | .in2 (sel2), | |
| 6912 | .in3 (sel3), | |
| 6913 | .out0 (buffout0), | |
| 6914 | .out1 (buffout1), | |
| 6915 | .out2 (buffout2), | |
| 6916 | .out3 (buffout3)); | |
| 6917 | mux4s #(8) d0_0( | |
| 6918 | .sel0 (buffout0), | |
| 6919 | .sel1 (buffout1), | |
| 6920 | .sel2 (buffout2), | |
| 6921 | .sel3 (buffout3), | |
| 6922 | .in0 (din0[7:0]), | |
| 6923 | .in1 (din1[7:0]), | |
| 6924 | .in2 (din2[7:0]), | |
| 6925 | .in3 (din3[7:0]), | |
| 6926 | .dout (dout[7:0])); | |
| 6927 | endmodule | |
| 6928 | `endcelldefine | |
| 6929 | ||
| 6930 | `celldefine | |
| 6931 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 130192 */ | |
| 6932 | // No timescale specified | |
| 6933 | module xor_macro__ports_3__width_4(din0, din1, din2, dout); | |
| 6934 | ||
| 6935 | input [3:0] din0; | |
| 6936 | input [3:0] din1; | |
| 6937 | input [3:0] din2; | |
| 6938 | output [3:0] dout; | |
| 6939 | ||
| 6940 | xor3 #(4) d0_0( | |
| 6941 | .in0 (din0[3:0]), | |
| 6942 | .in1 (din1[3:0]), | |
| 6943 | .in2 (din2[3:0]), | |
| 6944 | .out (dout[3:0])); | |
| 6945 | endmodule | |
| 6946 | `endcelldefine | |
| 6947 | ||
| 6948 | `celldefine | |
| 6949 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 130208 */ | |
| 6950 | // No timescale specified | |
| 6951 | module msff_ctl_macro__fs_1__width_12(din, l1clk, scan_in, siclk, soclk, dout, | |
| 6952 | scan_out); | |
| 6953 | ||
| 6954 | input [11:0] din; | |
| 6955 | input l1clk; | |
| 6956 | input [11:0] scan_in; | |
| 6957 | input siclk; | |
| 6958 | input soclk; | |
| 6959 | output [11:0] dout; | |
| 6960 | output [11:0] scan_out; | |
| 6961 | ||
| 6962 | wire [11:0] fdin; | |
| 6963 | ||
| 6964 | assign fdin[11:0] = din[11:0]; | |
| 6965 | ||
| 6966 | dff #(12) d0_0( | |
| 6967 | .l1clk (l1clk), | |
| 6968 | .siclk (siclk), | |
| 6969 | .soclk (soclk), | |
| 6970 | .d (fdin[11:0]), | |
| 6971 | .si (scan_in[11:0]), | |
| 6972 | .so (scan_out[11:0]), | |
| 6973 | .q (dout[11:0])); | |
| 6974 | endmodule | |
| 6975 | `endcelldefine | |
| 6976 | ||
| 6977 | `celldefine | |
| 6978 | /* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129396 */ | |
| 6979 | // No timescale specified | |
| 6980 | module tisram_msff_macro__fs_1__width_8(d, scan_in, l1clk, siclk, soclk, | |
| 6981 | scan_out, latout, latout_l); | |
| 6982 | ||
| 6983 | input [7:0] d; | |
| 6984 | input [7:0] scan_in; | |
| 6985 | input l1clk; | |
| 6986 | input siclk; | |
| 6987 | input soclk; | |
| 6988 | output [7:0] scan_out; | |
| 6989 | output [7:0] latout; | |
| 6990 | output [7:0] latout_l; | |
| 6991 | ||
| 6992 | tisram_msff #(8) d0_0( | |
| 6993 | .d (d[7:0]), | |
| 6994 | .si (scan_in[7:0]), | |
| 6995 | .so (scan_out[7:0]), | |
| 6996 | .l1clk (l1clk), | |
| 6997 | .siclk (siclk), | |
| 6998 | .soclk (soclk), | |
| 6999 | .latout (latout[7:0]), | |
| 7000 | .latout_l (latout_l[7:0])); | |
| 7001 | endmodule | |
| 7002 | `endcelldefine | |
| 7003 | ||
| 7004 | ||
| 7005 | `endif // `ifdef FPGA |