Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_icd_sp_16p5kb_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module n2_icd_sp_16p5kb_cust ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | tcu_aclk, | |
40 | tcu_bclk, | |
41 | tcu_array_wr_inhibit, | |
42 | tcu_se_scancollar_in, | |
43 | tcu_se_scancollar_out, | |
44 | tcu_scan_en, | |
45 | red_en_in, | |
46 | red_d_in, | |
47 | rid_in, | |
48 | red_wen, | |
49 | red_arst, | |
50 | ftp_icd_quad_0_en_bf, | |
51 | ftp_icd_quad_1_en_bf, | |
52 | ftp_icd_quad_2_en_bf, | |
53 | ftp_icd_quad_3_en_bf, | |
54 | agd_ic_index_bf, | |
55 | agc_fill_wrway_bf, | |
56 | cmu_ic_data, | |
57 | agd_asi_bist_wrdata, | |
58 | itb_icd_waysel_c, | |
59 | agc_word_en_bf, | |
60 | ftp_ic_rd_req_bf, | |
61 | ftp_ic_wr_req_bf, | |
62 | ftp_ic_wr_ps_en_bf, | |
63 | ftp_asi_mbist_access_bf, | |
64 | vnw_ary, | |
65 | icd_bus_0_instr_c, | |
66 | icd_bus_1_instr_c, | |
67 | icd_bus_2_instr_c, | |
68 | icd_bus_3_instr_c, | |
69 | scan_out, | |
70 | red_d_out, | |
71 | red_en_out) ; | |
72 | wire pce_ov; | |
73 | wire stop; | |
74 | wire siclk; | |
75 | wire soclk; | |
76 | wire wr_inhibit; | |
77 | wire l1clk_in; | |
78 | wire icd_quad_0_en_f_qual; | |
79 | wire l1clk_q0_out; | |
80 | wire icd_quad_1_en_f_qual; | |
81 | wire l1clk_q1_out; | |
82 | wire icd_quad_2_en_f_qual; | |
83 | wire l1clk_q2_out; | |
84 | wire icd_quad_3_en_f_qual; | |
85 | wire l1clk_q3_out; | |
86 | wire l1clk_free; | |
87 | wire l1clk_fuse_clk1; | |
88 | wire l1clk_red_in; | |
89 | wire l1clk_red_out; | |
90 | wire l1clk_int; | |
91 | wire l1clk_out; | |
92 | wire l1clk_wr; | |
93 | wire [10:2] index_bf_l; | |
94 | wire [2:0] wrway_bf_l; | |
95 | wire [7:0] word_en_bf_l; | |
96 | wire wr_inhibit_in_l; | |
97 | wire ic_rd_req_bf_l; | |
98 | wire ic_wr_req_bf_l; | |
99 | wire ftp_icd_quad_0_en_l_bf; | |
100 | wire ftp_icd_quad_1_en_l_bf; | |
101 | wire ftp_icd_quad_2_en_l_bf; | |
102 | wire ftp_icd_quad_3_en_l_bf; | |
103 | wire quad_en_0_latch_scanin; | |
104 | wire quad_en_0_latch_scanout; | |
105 | wire icd_quad_0_en_f_lat; | |
106 | wire icd_quad_0_en_f_lat_l; | |
107 | wire quad_en_1_latch_scanin; | |
108 | wire quad_en_1_latch_scanout; | |
109 | wire icd_quad_1_en_f_lat; | |
110 | wire icd_quad_1_en_f_lat_l; | |
111 | wire quad_en_2_latch_scanin; | |
112 | wire quad_en_2_latch_scanout; | |
113 | wire icd_quad_2_en_f_lat; | |
114 | wire icd_quad_2_en_f_lat_l; | |
115 | wire quad_en_3_latch_scanin; | |
116 | wire quad_en_3_latch_scanout; | |
117 | wire icd_quad_3_en_f_lat; | |
118 | wire icd_quad_3_en_f_lat_l; | |
119 | wire icd_quad_0_en_f_lat_unused; | |
120 | wire icd_quad_1_en_f_lat_unused; | |
121 | wire icd_quad_2_en_f_lat_unused; | |
122 | wire icd_quad_3_en_f_lat_unused; | |
123 | wire index_reg_i_scanin; | |
124 | wire index_reg_i_scanout; | |
125 | wire [10:2] index_f; | |
126 | wire [10:5] index_f_l; | |
127 | wire [4:2] index_f_l_unused; | |
128 | wire wrway_0_reg_scanin; | |
129 | wire wrway_0_reg_scanout; | |
130 | wire [2:0] wrway_f; | |
131 | wire [2:0] wrway_f_unused; | |
132 | wire wrway_1_reg_scanin; | |
133 | wire wrway_1_reg_scanout; | |
134 | wire wrway_2_reg_scanin; | |
135 | wire wrway_2_reg_scanout; | |
136 | wire wr_word_en_0_reg_scanin; | |
137 | wire wr_word_en_0_reg_scanout; | |
138 | wire [7:0] word_en_f; | |
139 | wire [7:0] word_en_f_unused; | |
140 | wire wr_word_en_1_reg_scanin; | |
141 | wire wr_word_en_1_reg_scanout; | |
142 | wire wr_word_en_2_reg_scanin; | |
143 | wire wr_word_en_2_reg_scanout; | |
144 | wire wr_word_en_3_reg_scanin; | |
145 | wire wr_word_en_3_reg_scanout; | |
146 | wire wr_word_en_4_reg_scanin; | |
147 | wire wr_word_en_4_reg_scanout; | |
148 | wire wr_word_en_5_reg_scanin; | |
149 | wire wr_word_en_5_reg_scanout; | |
150 | wire wr_word_en_6_reg_scanin; | |
151 | wire wr_word_en_6_reg_scanout; | |
152 | wire wr_word_en_7_reg_scanin; | |
153 | wire wr_word_en_7_reg_scanout; | |
154 | wire [3:0] quad_en_reg_scanin; | |
155 | wire [3:0] quad_en_reg_scanout; | |
156 | wire icd_quad_3_en_l_f; | |
157 | wire icd_quad_2_en_l_f; | |
158 | wire icd_quad_1_en_l_f; | |
159 | wire icd_quad_0_en_l_f; | |
160 | wire icd_quad_3_en_f; | |
161 | wire icd_quad_2_en_f; | |
162 | wire icd_quad_1_en_f; | |
163 | wire icd_quad_0_en_f; | |
164 | wire [0:0] wrreq_reg_scanin; | |
165 | wire [0:0] wrreq_reg_scanout; | |
166 | wire wrreq_f; | |
167 | wire wrreq_f_l_unused; | |
168 | wire wrreq_reg_b_scanin; | |
169 | wire wrreq_reg_b_scanout; | |
170 | wire wrreq_f_l; | |
171 | wire [0:0] ftp_access_f_reg_scanin; | |
172 | wire [0:0] ftp_access_f_reg_scanout; | |
173 | wire asi_access_f; | |
174 | wire rdreq_reg_scanin; | |
175 | wire rdreq_reg_scanout; | |
176 | wire rdreq_f_l_unused; | |
177 | wire rdreq_f_unused; | |
178 | wire rdreq_reg_b_scanin; | |
179 | wire rdreq_reg_b_scanout; | |
180 | wire rdreq_f; | |
181 | wire [263:0] wrdata_in; | |
182 | wire [32:0] wrdata_q0_0_scanin; | |
183 | wire [32:0] wrdata_q0_0_scanout; | |
184 | wire [263:0] wrdata_f; | |
185 | wire [32:0] wrdata_q1_1_scanin; | |
186 | wire [32:0] wrdata_q1_1_scanout; | |
187 | wire [32:0] wrdata_q2_2_scanin; | |
188 | wire [32:0] wrdata_q2_2_scanout; | |
189 | wire [32:0] wrdata_q3_3_scanin; | |
190 | wire [32:0] wrdata_q3_3_scanout; | |
191 | wire [32:0] wrdata_q0_4_scanin; | |
192 | wire [32:0] wrdata_q0_4_scanout; | |
193 | wire [32:0] wrdata_q1_5_scanin; | |
194 | wire [32:0] wrdata_q1_5_scanout; | |
195 | wire [32:0] wrdata_q2_6_scanin; | |
196 | wire [32:0] wrdata_q2_6_scanout; | |
197 | wire [32:0] wrdata_q3_7_scanin; | |
198 | wire [32:0] wrdata_q3_7_scanout; | |
199 | wire [4:0] red_d_reg_scanin; | |
200 | wire [4:0] red_d_reg_scanout; | |
201 | wire [4:0] red_d_ff; | |
202 | wire [1:0] red_en_reg_scanin; | |
203 | wire [1:0] red_en_reg_scanout; | |
204 | wire [1:0] red_en_ff; | |
205 | wire [3:0] rid_reg_scanin; | |
206 | wire [3:0] rid_reg_scanout; | |
207 | wire [3:0] rid_ff; | |
208 | wire [0:0] red_wen_reg_scanin; | |
209 | wire [0:0] red_wen_reg_scanout; | |
210 | wire red_wen_ff_and; | |
211 | wire red_wen_ff; | |
212 | wire [0:0] red_arst_reg_scanin; | |
213 | wire [0:0] red_arst_reg_scanout; | |
214 | wire red_arst_ff_and; | |
215 | wire red_arst_ff; | |
216 | wire [7:0] way_f_reg_scanin; | |
217 | wire [7:0] way_f_reg_scanout; | |
218 | wire [7:0] wrway_dec_bf; | |
219 | wire [7:0] wrway_dec_f; | |
220 | wire [7:0] way_c_reg_scanin; | |
221 | wire [7:0] way_c_reg_scanout; | |
222 | wire [7:0] wrway_dec_c; | |
223 | wire [0:0] ftp_access_c_reg_scanin; | |
224 | wire [0:0] ftp_access_c_reg_scanout; | |
225 | wire asi_access_c; | |
226 | wire ftp_access_c_dum_scanin; | |
227 | wire ftp_access_c_dum_scanout; | |
228 | wire asi_access_c_l; | |
229 | wire asi_access_c_l_inv; | |
230 | wire asi_access_c_inv; | |
231 | wire [7:0] muxed_way_sel_c; | |
232 | wire i4_i0_sel_upper; | |
233 | wire i4_i0_sel_upper_; | |
234 | wire i5_i1_sel_upper; | |
235 | wire i5_i1_sel_upper_; | |
236 | wire i6_i2_sel_upper_or_2; | |
237 | wire i6_i2_sel_upper; | |
238 | wire i6_i2_sel_upper_; | |
239 | wire i7_i3_sel_upper; | |
240 | wire i7_i3_sel_upper_; | |
241 | wire [7:0] wr_word_en_f_l; | |
242 | wire rdreq_f_q0_l; | |
243 | wire rdreq_f_q0; | |
244 | wire rdreq_f_q1_l; | |
245 | wire rdreq_f_q1; | |
246 | wire rdreq_f_q2_l; | |
247 | wire rdreq_f_q2; | |
248 | wire rdreq_f_q3_l; | |
249 | wire rdreq_f_q3; | |
250 | wire [7:0] wrway_dec_f_; | |
251 | wire [7:0] rid_sel_dec; | |
252 | wire [15:0] rid_sel; | |
253 | wire [32:0] rd_data_w0_i4_or_i0; | |
254 | wire [32:0] rd_data_w1_i4_or_i0; | |
255 | wire [32:0] rd_data_w2_i4_or_i0; | |
256 | wire [32:0] rd_data_w3_i4_or_i0; | |
257 | wire [32:0] rd_data_w4_i4_or_i0; | |
258 | wire [32:0] rd_data_w5_i4_or_i0; | |
259 | wire [32:0] rd_data_w6_i4_or_i0; | |
260 | wire [32:0] rd_data_w7_i4_or_i0; | |
261 | wire [4:0] reg_d_q0_w3_w0_lft_d; | |
262 | wire [1:0] reg_d_q0_w3_w0_lft_en; | |
263 | wire [4:0] reg_d_q0_w3_w0_rgt_d; | |
264 | wire [1:0] reg_d_q0_w3_w0_rgt_en; | |
265 | wire [4:0] reg_d_q0_w7_w4_lft_d; | |
266 | wire [1:0] reg_d_q0_w7_w4_lft_en; | |
267 | wire [4:0] reg_d_q0_w7_w4_rgt_d; | |
268 | wire [1:0] reg_d_q0_w7_w4_rgt_en; | |
269 | wire [32:0] rd_data_w0_i5_or_i1; | |
270 | wire [32:0] rd_data_w1_i5_or_i1; | |
271 | wire [32:0] rd_data_w2_i5_or_i1; | |
272 | wire [32:0] rd_data_w3_i5_or_i1; | |
273 | wire [32:0] rd_data_w4_i5_or_i1; | |
274 | wire [32:0] rd_data_w5_i5_or_i1; | |
275 | wire [32:0] rd_data_w6_i5_or_i1; | |
276 | wire [32:0] rd_data_w7_i5_or_i1; | |
277 | wire [4:0] reg_d_q1_w3_w0_lft_d; | |
278 | wire [1:0] reg_d_q1_w3_w0_lft_en; | |
279 | wire [4:0] reg_d_q1_w3_w0_rgt_d; | |
280 | wire [1:0] reg_d_q1_w3_w0_rgt_en; | |
281 | wire [4:0] reg_d_q1_w7_w4_lft_d; | |
282 | wire [1:0] reg_d_q1_w7_w4_lft_en; | |
283 | wire [4:0] reg_d_q1_w7_w4_rgt_d; | |
284 | wire [1:0] reg_d_q1_w7_w4_rgt_en; | |
285 | wire [32:0] rd_data_w0_i6_or_i2; | |
286 | wire [32:0] rd_data_w1_i6_or_i2; | |
287 | wire [32:0] rd_data_w2_i6_or_i2; | |
288 | wire [32:0] rd_data_w3_i6_or_i2; | |
289 | wire [32:0] rd_data_w4_i6_or_i2; | |
290 | wire [32:0] rd_data_w5_i6_or_i2; | |
291 | wire [32:0] rd_data_w6_i6_or_i2; | |
292 | wire [32:0] rd_data_w7_i6_or_i2; | |
293 | wire [4:0] reg_d_q2_w3_w0_lft_d; | |
294 | wire [1:0] reg_d_q2_w3_w0_lft_en; | |
295 | wire [4:0] reg_d_q2_w3_w0_rgt_d; | |
296 | wire [1:0] reg_d_q2_w3_w0_rgt_en; | |
297 | wire [4:0] reg_d_q2_w7_w4_lft_d; | |
298 | wire [1:0] reg_d_q2_w7_w4_lft_en; | |
299 | wire [4:0] reg_d_q2_w7_w4_rgt_d; | |
300 | wire [1:0] reg_d_q2_w7_w4_rgt_en; | |
301 | wire [32:0] rd_data_w0_i7_or_i3; | |
302 | wire [32:0] rd_data_w1_i7_or_i3; | |
303 | wire [32:0] rd_data_w2_i7_or_i3; | |
304 | wire [32:0] rd_data_w3_i7_or_i3; | |
305 | wire [32:0] rd_data_w4_i7_or_i3; | |
306 | wire [32:0] rd_data_w5_i7_or_i3; | |
307 | wire [32:0] rd_data_w6_i7_or_i3; | |
308 | wire [32:0] rd_data_w7_i7_or_i3; | |
309 | wire [4:0] reg_d_q3_w3_w0_lft_d; | |
310 | wire [1:0] reg_d_q3_w3_w0_lft_en; | |
311 | wire [4:0] reg_d_q3_w3_w0_rgt_d; | |
312 | wire [1:0] reg_d_q3_w3_w0_rgt_en; | |
313 | wire [4:0] reg_d_q3_w7_w4_lft_d; | |
314 | wire [1:0] reg_d_q3_w7_w4_lft_en; | |
315 | wire [4:0] reg_d_q3_w7_w4_rgt_d; | |
316 | wire [1:0] reg_d_q3_w7_w4_rgt_en; | |
317 | wire [32:0] data_bus_0_w0_reg_scanin; | |
318 | wire [32:0] data_bus_0_w0_reg_scanout; | |
319 | wire [32:0] data_bus_0_w0_c; | |
320 | wire [32:0] data_bus_1_w0_reg_scanin; | |
321 | wire [32:0] data_bus_1_w0_reg_scanout; | |
322 | wire [32:0] data_bus_1_w0_c; | |
323 | wire [32:0] data_bus_2_w0_reg_scanin; | |
324 | wire [32:0] data_bus_2_w0_reg_scanout; | |
325 | wire [32:0] data_bus_2_w0_c; | |
326 | wire [32:0] data_bus_3_w0_reg_scanin; | |
327 | wire [32:0] data_bus_3_w0_reg_scanout; | |
328 | wire [32:0] data_bus_3_w0_c; | |
329 | wire [32:0] data_bus_0_w1_reg_scanin; | |
330 | wire [32:0] data_bus_0_w1_reg_scanout; | |
331 | wire [32:0] data_bus_0_w1_c; | |
332 | wire [32:0] data_bus_1_w1_reg_scanin; | |
333 | wire [32:0] data_bus_1_w1_reg_scanout; | |
334 | wire [32:0] data_bus_1_w1_c; | |
335 | wire [32:0] data_bus_2_w1_reg_scanin; | |
336 | wire [32:0] data_bus_2_w1_reg_scanout; | |
337 | wire [32:0] data_bus_2_w1_c; | |
338 | wire [32:0] data_bus_3_w1_reg_scanin; | |
339 | wire [32:0] data_bus_3_w1_reg_scanout; | |
340 | wire [32:0] data_bus_3_w1_c; | |
341 | wire [32:0] data_bus_0_w2_reg_scanin; | |
342 | wire [32:0] data_bus_0_w2_reg_scanout; | |
343 | wire [32:0] data_bus_0_w2_c; | |
344 | wire [32:0] data_bus_1_w2_reg_scanin; | |
345 | wire [32:0] data_bus_1_w2_reg_scanout; | |
346 | wire [32:0] data_bus_1_w2_c; | |
347 | wire [32:0] data_bus_2_w2_reg_scanin; | |
348 | wire [32:0] data_bus_2_w2_reg_scanout; | |
349 | wire [32:0] data_bus_2_w2_c; | |
350 | wire [32:0] data_bus_3_w2_reg_scanin; | |
351 | wire [32:0] data_bus_3_w2_reg_scanout; | |
352 | wire [32:0] data_bus_3_w2_c; | |
353 | wire [32:0] data_bus_0_w3_reg_scanin; | |
354 | wire [32:0] data_bus_0_w3_reg_scanout; | |
355 | wire [32:0] data_bus_0_w3_c; | |
356 | wire [32:0] data_bus_1_w3_reg_scanin; | |
357 | wire [32:0] data_bus_1_w3_reg_scanout; | |
358 | wire [32:0] data_bus_1_w3_c; | |
359 | wire [32:0] data_bus_2_w3_reg_scanin; | |
360 | wire [32:0] data_bus_2_w3_reg_scanout; | |
361 | wire [32:0] data_bus_2_w3_c; | |
362 | wire [32:0] data_bus_3_w3_reg_scanin; | |
363 | wire [32:0] data_bus_3_w3_reg_scanout; | |
364 | wire [32:0] data_bus_3_w3_c; | |
365 | wire [32:0] data_bus_0_w4_reg_scanin; | |
366 | wire [32:0] data_bus_0_w4_reg_scanout; | |
367 | wire [32:0] data_bus_0_w4_c; | |
368 | wire [32:0] data_bus_1_w4_reg_scanin; | |
369 | wire [32:0] data_bus_1_w4_reg_scanout; | |
370 | wire [32:0] data_bus_1_w4_c; | |
371 | wire [32:0] data_bus_2_w4_reg_scanin; | |
372 | wire [32:0] data_bus_2_w4_reg_scanout; | |
373 | wire [32:0] data_bus_2_w4_c; | |
374 | wire [32:0] data_bus_3_w4_reg_scanin; | |
375 | wire [32:0] data_bus_3_w4_reg_scanout; | |
376 | wire [32:0] data_bus_3_w4_c; | |
377 | wire [32:0] data_bus_0_w5_reg_scanin; | |
378 | wire [32:0] data_bus_0_w5_reg_scanout; | |
379 | wire [32:0] data_bus_0_w5_c; | |
380 | wire [32:0] data_bus_1_w5_reg_scanin; | |
381 | wire [32:0] data_bus_1_w5_reg_scanout; | |
382 | wire [32:0] data_bus_1_w5_c; | |
383 | wire [32:0] data_bus_2_w5_reg_scanin; | |
384 | wire [32:0] data_bus_2_w5_reg_scanout; | |
385 | wire [32:0] data_bus_2_w5_c; | |
386 | wire [32:0] data_bus_3_w5_reg_scanin; | |
387 | wire [32:0] data_bus_3_w5_reg_scanout; | |
388 | wire [32:0] data_bus_3_w5_c; | |
389 | wire [32:0] data_bus_0_w6_reg_scanin; | |
390 | wire [32:0] data_bus_0_w6_reg_scanout; | |
391 | wire [32:0] data_bus_0_w6_c; | |
392 | wire [32:0] data_bus_1_w6_reg_scanin; | |
393 | wire [32:0] data_bus_1_w6_reg_scanout; | |
394 | wire [32:0] data_bus_1_w6_c; | |
395 | wire [32:0] data_bus_2_w6_reg_scanin; | |
396 | wire [32:0] data_bus_2_w6_reg_scanout; | |
397 | wire [32:0] data_bus_2_w6_c; | |
398 | wire [32:0] data_bus_3_w6_reg_scanin; | |
399 | wire [32:0] data_bus_3_w6_reg_scanout; | |
400 | wire [32:0] data_bus_3_w6_c; | |
401 | wire [32:0] data_bus_0_w7_reg_scanin; | |
402 | wire [32:0] data_bus_0_w7_reg_scanout; | |
403 | wire [32:0] data_bus_0_w7_c; | |
404 | wire [32:0] data_bus_1_w7_reg_scanin; | |
405 | wire [32:0] data_bus_1_w7_reg_scanout; | |
406 | wire [32:0] data_bus_1_w7_c; | |
407 | wire [32:0] data_bus_2_w7_reg_scanin; | |
408 | wire [32:0] data_bus_2_w7_reg_scanout; | |
409 | wire [32:0] data_bus_2_w7_c; | |
410 | wire [32:0] data_bus_3_w7_reg_scanin; | |
411 | wire [32:0] data_bus_3_w7_reg_scanout; | |
412 | wire [32:0] data_bus_3_w7_c; | |
413 | wire [4:0] reg_d_out_mux_0; | |
414 | wire [1:0] reg_en_out_mux_0; | |
415 | wire [4:0] reg_d_out_mux_1; | |
416 | wire [1:0] reg_en_out_mux_1; | |
417 | wire [4:0] red_mux_d_out; | |
418 | wire [1:0] red_mux_en_out; | |
419 | wire [4:0] red_d_out_reg_scanin; | |
420 | wire [4:0] red_d_out_reg_scanout; | |
421 | wire [1:0] red_en_out_reg_scanin; | |
422 | wire [1:0] red_en_out_reg_scanout; | |
423 | ||
424 | ||
425 | ||
426 | ||
427 | ||
428 | ||
429 | // make sure you have .l2clk(l2clk), 1 level up; run fixscan | |
430 | ||
431 | ||
432 | ||
433 | input l2clk; | |
434 | input scan_in; | |
435 | input tcu_pce_ov; | |
436 | input tcu_aclk; | |
437 | input tcu_bclk; | |
438 | input tcu_array_wr_inhibit; | |
439 | input tcu_se_scancollar_in; | |
440 | input tcu_se_scancollar_out; | |
441 | input tcu_scan_en; | |
442 | ||
443 | input [1:0] red_en_in ; | |
444 | input [4:0] red_d_in ; | |
445 | input [3:0] rid_in ; | |
446 | input red_wen ; | |
447 | input red_arst ; | |
448 | ||
449 | input ftp_icd_quad_0_en_bf; // enable quad 0 | |
450 | input ftp_icd_quad_1_en_bf; // enable quad 1 | |
451 | input ftp_icd_quad_2_en_bf; // enable quad 2 | |
452 | input ftp_icd_quad_3_en_bf; // enable quad 3 | |
453 | ||
454 | ||
455 | ||
456 | input [10:2] agd_ic_index_bf; // index to write to/read from | |
457 | input [2:0] agc_fill_wrway_bf; // way to write to | |
458 | input [263:0] cmu_ic_data; // 128b data, 4b parity | |
459 | input [32:0] agd_asi_bist_wrdata; // Debug wr data | |
460 | input [7:0] itb_icd_waysel_c; // read way select encoded | |
461 | input [7:0] agc_word_en_bf; // read/write word enable | |
462 | ||
463 | input ftp_ic_rd_req_bf; | |
464 | input ftp_ic_wr_req_bf; | |
465 | input ftp_ic_wr_ps_en_bf; | |
466 | input ftp_asi_mbist_access_bf; | |
467 | ||
468 | input vnw_ary; | |
469 | ||
470 | ||
471 | // outputs | |
472 | output [32:0] icd_bus_0_instr_c ; | |
473 | output [32:0] icd_bus_1_instr_c ; | |
474 | output [32:0] icd_bus_2_instr_c ; | |
475 | output [32:0] icd_bus_3_instr_c ; | |
476 | output scan_out; | |
477 | output [4:0] red_d_out ; | |
478 | output [1:0] red_en_out ; | |
479 | ||
480 | `ifndef FPGA | |
481 | // synopsys translate_off | |
482 | `endif | |
483 | ||
484 | assign pce_ov = tcu_pce_ov; | |
485 | assign stop = 1'b0 ; | |
486 | assign siclk = tcu_aclk ; | |
487 | assign soclk = tcu_bclk; | |
488 | assign wr_inhibit = tcu_array_wr_inhibit; | |
489 | ||
490 | // Temporary | |
491 | ||
492 | // assign red_d_out[4:0] = 5'b00000 ; | |
493 | // assign red_en_out[1:0] = 2'b00 ; | |
494 | //================================================ | |
495 | // Clock headers | |
496 | //================================================ | |
497 | n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_in ( | |
498 | .l2clk (l2clk), | |
499 | .l1en (1'b1), | |
500 | .se (tcu_se_scancollar_in), | |
501 | .l1clk (l1clk_in), | |
502 | .pce_ov(pce_ov), | |
503 | .stop(stop) | |
504 | ); | |
505 | ||
506 | // l1clkhdr_ctl_macro l1ch_q0_in ( | |
507 | // .l2clk (l2clk), | |
508 | // .l1en (ftp_icd_quad_0_en_bf), | |
509 | // .se (tcu_se_scancollar_in), | |
510 | // .l1clk (l1clk_q0_in) | |
511 | // ); | |
512 | ||
513 | // l1clkhdr_ctl_macro l1ch_q1_in ( | |
514 | // .l2clk (l2clk), | |
515 | // .l1en (ftp_icd_quad_1_en_bf), | |
516 | // .se (tcu_se_scancollar_in), | |
517 | // .l1clk (l1clk_q1_in) | |
518 | // ); | |
519 | ||
520 | // l1clkhdr_ctl_macro l1ch_q2_in ( | |
521 | // .l2clk (l2clk), | |
522 | // .l1en (ftp_icd_quad_2_en_bf), | |
523 | // .se (tcu_se_scancollar_in), | |
524 | // .l1clk (l1clk_q2_in) | |
525 | // ); | |
526 | ||
527 | // l1clkhdr_ctl_macro l1ch_q3_in ( | |
528 | // .l2clk (l2clk), | |
529 | // .l1en (ftp_icd_quad_3_en_bf), | |
530 | // .se (tcu_se_scancollar_in), | |
531 | // .l1clk (l1clk_q3_in) | |
532 | // ); | |
533 | ||
534 | ||
535 | n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_q0_out ( | |
536 | .l2clk (l2clk), | |
537 | .l1en (icd_quad_0_en_f_qual), | |
538 | .se (tcu_se_scancollar_out), | |
539 | .l1clk (l1clk_q0_out), | |
540 | .pce_ov(pce_ov), | |
541 | .stop(stop) | |
542 | ); | |
543 | ||
544 | n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_q1_out ( | |
545 | .l2clk (l2clk), | |
546 | .l1en (icd_quad_1_en_f_qual), | |
547 | .se (tcu_se_scancollar_out), | |
548 | .l1clk (l1clk_q1_out), | |
549 | .pce_ov(pce_ov), | |
550 | .stop(stop) | |
551 | ); | |
552 | ||
553 | n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_q2_out ( | |
554 | .l2clk (l2clk), | |
555 | .l1en (icd_quad_2_en_f_qual), | |
556 | .se (tcu_se_scancollar_out), | |
557 | .l1clk (l1clk_q2_out), | |
558 | .pce_ov(pce_ov), | |
559 | .stop(stop) | |
560 | ); | |
561 | ||
562 | n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_q3_out ( | |
563 | .l2clk (l2clk), | |
564 | .l1en (icd_quad_3_en_f_qual), | |
565 | .se (tcu_se_scancollar_out), | |
566 | .l1clk (l1clk_q3_out), | |
567 | .pce_ov(pce_ov), | |
568 | .stop(stop) | |
569 | ); | |
570 | ||
571 | ||
572 | n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_free ( | |
573 | .l2clk (l2clk), | |
574 | .l1en (1'b1), | |
575 | .se (tcu_scan_en), | |
576 | .l1clk (l1clk_free), | |
577 | .pce_ov(pce_ov), | |
578 | .stop(stop) | |
579 | ); | |
580 | ||
581 | n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_red_free ( | |
582 | .l2clk (l2clk), | |
583 | .l1en (1'b1), | |
584 | .se (1'b0), | |
585 | .l1clk (l1clk_fuse_clk1), | |
586 | .pce_ov(1'b1), | |
587 | .stop(1'b0) | |
588 | ); | |
589 | ||
590 | n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_red_in ( | |
591 | .l2clk (l2clk), | |
592 | .l1en (1'b1), | |
593 | .se (tcu_se_scancollar_in), | |
594 | .l1clk (l1clk_red_in), | |
595 | .pce_ov(1'b1), | |
596 | .stop(1'b0) | |
597 | ); | |
598 | ||
599 | n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_red_out ( | |
600 | .l2clk (l2clk), | |
601 | .l1en (1'b1), | |
602 | .se (tcu_se_scancollar_out), | |
603 | .l1clk (l1clk_red_out), | |
604 | .pce_ov(1'b1), | |
605 | .stop(1'b0) | |
606 | ); | |
607 | ||
608 | n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_int ( | |
609 | .l2clk (l2clk), | |
610 | .l1en (1'b1), | |
611 | .se (tcu_scan_en), | |
612 | .l1clk (l1clk_int), | |
613 | .pce_ov(pce_ov), | |
614 | .stop(stop) | |
615 | ); | |
616 | ||
617 | n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_out ( | |
618 | .l2clk (l2clk), | |
619 | .l1en (1'b1), | |
620 | .se (tcu_se_scancollar_out), | |
621 | .l1clk (l1clk_out), | |
622 | .pce_ov(pce_ov), | |
623 | .stop(stop) | |
624 | ); | |
625 | ||
626 | n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_wr ( | |
627 | .l2clk (l2clk), | |
628 | .l1en (ftp_ic_wr_ps_en_bf), | |
629 | .se (tcu_se_scancollar_in), | |
630 | .l1clk (l1clk_wr), | |
631 | .pce_ov(pce_ov), | |
632 | .stop(stop) | |
633 | ); | |
634 | ||
635 | ||
636 | ||
637 | //---------------------------------------------------------------------- | |
638 | // Declarations | |
639 | //---------------------------------------------------------------------- | |
640 | ||
641 | // local signals | |
642 | ||
643 | ||
644 | ||
645 | ||
646 | ||
647 | //////////////////////////////////////////////////////////// | |
648 | // | |
649 | // Code start here | |
650 | // | |
651 | //////////////////////////////////////////////////////////// | |
652 | // Inverters before the flops // | |
653 | ||
654 | n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_9 index_inv ( | |
655 | .din(agd_ic_index_bf[10:2]), | |
656 | .dout(index_bf_l[10:2]) | |
657 | ); | |
658 | ||
659 | ||
660 | n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_3 wrway_inv ( | |
661 | .din(agc_fill_wrway_bf[2:0]), | |
662 | .dout(wrway_bf_l[2:0]) | |
663 | ); | |
664 | ||
665 | n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_8 word_en_inv ( | |
666 | .din(agc_word_en_bf[7:0]), | |
667 | .dout(word_en_bf_l[7:0]) | |
668 | ); | |
669 | ||
670 | n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 wr_inhibit_inv ( | |
671 | .din(wr_inhibit), | |
672 | .dout(wr_inhibit_in_l) | |
673 | ); | |
674 | ||
675 | n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 ic_rd_req_inv ( | |
676 | .din(ftp_ic_rd_req_bf), | |
677 | .dout(ic_rd_req_bf_l) | |
678 | ); | |
679 | ||
680 | n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 ic_wr_req_inv ( | |
681 | .din(ftp_ic_wr_req_bf), | |
682 | .dout(ic_wr_req_bf_l) | |
683 | ); | |
684 | ||
685 | n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_4 quad_en_in_inv ( | |
686 | .din ({ftp_icd_quad_0_en_bf, ftp_icd_quad_1_en_bf , ftp_icd_quad_2_en_bf , ftp_icd_quad_3_en_bf}), | |
687 | .dout({ftp_icd_quad_0_en_l_bf, ftp_icd_quad_1_en_l_bf , ftp_icd_quad_2_en_l_bf , ftp_icd_quad_3_en_l_bf}) | |
688 | ); | |
689 | ||
690 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 quad_0_en_latch ( | |
691 | .scan_in(quad_en_0_latch_scanin), | |
692 | .scan_out(quad_en_0_latch_scanout), | |
693 | .l1clk(l1clk_in), | |
694 | .d(ftp_icd_quad_0_en_l_bf), | |
695 | .latout_l(icd_quad_0_en_f_lat), | |
696 | .latout(icd_quad_0_en_f_lat_l), | |
697 | .siclk(siclk), | |
698 | .soclk(soclk) | |
699 | ); | |
700 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 quad_1_en_latch ( | |
701 | .scan_in(quad_en_1_latch_scanin), | |
702 | .scan_out(quad_en_1_latch_scanout), | |
703 | .l1clk(l1clk_in), | |
704 | .d(ftp_icd_quad_1_en_l_bf), | |
705 | .latout_l(icd_quad_1_en_f_lat), | |
706 | .latout(icd_quad_1_en_f_lat_l), | |
707 | .siclk(siclk), | |
708 | .soclk(soclk) | |
709 | ); | |
710 | ||
711 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 quad_2_en_latch ( | |
712 | .scan_in(quad_en_2_latch_scanin), | |
713 | .scan_out(quad_en_2_latch_scanout), | |
714 | .l1clk(l1clk_in), | |
715 | .d(ftp_icd_quad_2_en_l_bf), | |
716 | .latout_l(icd_quad_2_en_f_lat), | |
717 | .latout(icd_quad_2_en_f_lat_l), | |
718 | .siclk(siclk), | |
719 | .soclk(soclk) | |
720 | ); | |
721 | ||
722 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 quad_3_en_latch ( | |
723 | .scan_in(quad_en_3_latch_scanin), | |
724 | .scan_out(quad_en_3_latch_scanout), | |
725 | .l1clk(l1clk_in), | |
726 | .d(ftp_icd_quad_3_en_l_bf), | |
727 | .latout_l(icd_quad_3_en_f_lat), | |
728 | .latout(icd_quad_3_en_f_lat_l), | |
729 | .siclk(siclk), | |
730 | .soclk(soclk) | |
731 | ); | |
732 | assign icd_quad_0_en_f_lat_unused = icd_quad_0_en_f_lat ; | |
733 | assign icd_quad_1_en_f_lat_unused = icd_quad_1_en_f_lat ; | |
734 | assign icd_quad_2_en_f_lat_unused = icd_quad_2_en_f_lat ; | |
735 | assign icd_quad_3_en_f_lat_unused = icd_quad_3_en_f_lat ; | |
736 | ||
737 | ||
738 | /////////////////////////////////////////////////////////////// | |
739 | // Flop the inputs // | |
740 | /////////////////////////////////////////////////////////////// | |
741 | ||
742 | ||
743 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_9 index_reg_i ( | |
744 | .scan_in(index_reg_i_scanin), | |
745 | .scan_out(index_reg_i_scanout), | |
746 | .l1clk ( l1clk_in ), | |
747 | .d ( index_bf_l[10:2] ), | |
748 | .latout_l( index_f[10:2] ), | |
749 | .latout( {index_f_l[10:5],index_f_l_unused[4:2]} ), | |
750 | .siclk(siclk), | |
751 | .soclk(soclk)); | |
752 | ||
753 | ||
754 | ||
755 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wrway_0_reg ( | |
756 | .scan_in(wrway_0_reg_scanin), | |
757 | .scan_out(wrway_0_reg_scanout), | |
758 | .l1clk ( l1clk_in ), | |
759 | .d ( wrway_bf_l[0] ), | |
760 | .latout_l( wrway_f[0] ), | |
761 | .latout( wrway_f_unused[0] ), | |
762 | .siclk(siclk), | |
763 | .soclk(soclk)); | |
764 | ||
765 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wrway_1_reg ( | |
766 | .scan_in(wrway_1_reg_scanin), | |
767 | .scan_out(wrway_1_reg_scanout), | |
768 | .l1clk ( l1clk_in ), | |
769 | .d ( wrway_bf_l[1] ), | |
770 | .latout_l( wrway_f[1] ), | |
771 | .latout( wrway_f_unused[1] ), | |
772 | .siclk(siclk), | |
773 | .soclk(soclk)); | |
774 | ||
775 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wrway_2_reg ( | |
776 | .scan_in(wrway_2_reg_scanin), | |
777 | .scan_out(wrway_2_reg_scanout), | |
778 | .l1clk ( l1clk_in ), | |
779 | .d ( wrway_bf_l[2] ), | |
780 | .latout_l( wrway_f[2] ), | |
781 | .latout( wrway_f_unused[2] ), | |
782 | .siclk(siclk), | |
783 | .soclk(soclk)); | |
784 | ||
785 | ||
786 | ||
787 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wr_word_en_0_reg ( | |
788 | .scan_in(wr_word_en_0_reg_scanin), | |
789 | .scan_out(wr_word_en_0_reg_scanout), | |
790 | .l1clk ( l1clk_in ), | |
791 | .d ( word_en_bf_l[0] ), | |
792 | .latout_l( word_en_f[0] ), | |
793 | .latout( word_en_f_unused[0] ), | |
794 | .siclk(siclk), | |
795 | .soclk(soclk)); | |
796 | ||
797 | ||
798 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wr_word_en_1_reg ( | |
799 | .scan_in(wr_word_en_1_reg_scanin), | |
800 | .scan_out(wr_word_en_1_reg_scanout), | |
801 | .l1clk ( l1clk_in ), | |
802 | .d ( word_en_bf_l[1] ), | |
803 | .latout_l( word_en_f[1] ), | |
804 | .latout( word_en_f_unused[1] ), | |
805 | .siclk(siclk), | |
806 | .soclk(soclk)); | |
807 | ||
808 | ||
809 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wr_word_en_2_reg ( | |
810 | .scan_in(wr_word_en_2_reg_scanin), | |
811 | .scan_out(wr_word_en_2_reg_scanout), | |
812 | .l1clk ( l1clk_in ), | |
813 | .d ( word_en_bf_l[2] ), | |
814 | .latout_l( word_en_f[2] ), | |
815 | .latout( word_en_f_unused[2] ), | |
816 | .siclk(siclk), | |
817 | .soclk(soclk)); | |
818 | ||
819 | ||
820 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wr_word_en_3_reg ( | |
821 | .scan_in(wr_word_en_3_reg_scanin), | |
822 | .scan_out(wr_word_en_3_reg_scanout), | |
823 | .l1clk ( l1clk_in ), | |
824 | .d ( word_en_bf_l[3] ), | |
825 | .latout_l( word_en_f[3] ), | |
826 | .latout( word_en_f_unused[3] ), | |
827 | .siclk(siclk), | |
828 | .soclk(soclk)); | |
829 | ||
830 | ||
831 | ||
832 | ||
833 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wr_word_en_4_reg ( | |
834 | .scan_in(wr_word_en_4_reg_scanin), | |
835 | .scan_out(wr_word_en_4_reg_scanout), | |
836 | .l1clk ( l1clk_in ), | |
837 | .d ( word_en_bf_l[4] ), | |
838 | .latout_l( word_en_f[4] ), | |
839 | .latout( word_en_f_unused[4] ), | |
840 | .siclk(siclk), | |
841 | .soclk(soclk)); | |
842 | ||
843 | ||
844 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wr_word_en_5_reg ( | |
845 | .scan_in(wr_word_en_5_reg_scanin), | |
846 | .scan_out(wr_word_en_5_reg_scanout), | |
847 | .l1clk ( l1clk_in ), | |
848 | .d ( word_en_bf_l[5] ), | |
849 | .latout_l( word_en_f[5] ), | |
850 | .latout( word_en_f_unused[5] ), | |
851 | .siclk(siclk), | |
852 | .soclk(soclk)); | |
853 | ||
854 | ||
855 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wr_word_en_6_reg ( | |
856 | .scan_in(wr_word_en_6_reg_scanin), | |
857 | .scan_out(wr_word_en_6_reg_scanout), | |
858 | .l1clk ( l1clk_in ), | |
859 | .d ( word_en_bf_l[6] ), | |
860 | .latout_l( word_en_f[6] ), | |
861 | .latout( word_en_f_unused[6] ), | |
862 | .siclk(siclk), | |
863 | .soclk(soclk)); | |
864 | ||
865 | ||
866 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wr_word_en_7_reg ( | |
867 | .scan_in(wr_word_en_7_reg_scanin), | |
868 | .scan_out(wr_word_en_7_reg_scanout), | |
869 | .l1clk ( l1clk_in ), | |
870 | .d ( word_en_bf_l[7] ), | |
871 | .latout_l( word_en_f[7] ), | |
872 | .latout( word_en_f_unused[7] ), | |
873 | .siclk(siclk), | |
874 | .soclk(soclk)); | |
875 | ||
876 | ||
877 | ||
878 | n2_icd_sp_16p5kb_cust_msffi_ctl_macro__fs_1__width_4 quad_en_reg ( | |
879 | .scan_in(quad_en_reg_scanin[3:0]), | |
880 | .scan_out(quad_en_reg_scanout[3:0]), | |
881 | .l1clk(l1clk_in), | |
882 | .din( {ftp_icd_quad_3_en_bf,ftp_icd_quad_2_en_bf,ftp_icd_quad_1_en_bf,ftp_icd_quad_0_en_bf}), | |
883 | .q_l({icd_quad_3_en_l_f,icd_quad_2_en_l_f,icd_quad_1_en_l_f,icd_quad_0_en_l_f}), | |
884 | .siclk(siclk), | |
885 | .soclk(soclk) | |
886 | ); | |
887 | ||
888 | n2_icd_sp_16p5kb_cust_inv_macro__width_4 quad_inv ( | |
889 | .din ({icd_quad_3_en_l_f,icd_quad_2_en_l_f,icd_quad_1_en_l_f,icd_quad_0_en_l_f}) , | |
890 | .dout({icd_quad_3_en_f,icd_quad_2_en_f,icd_quad_1_en_f,icd_quad_0_en_f}) | |
891 | ); | |
892 | ||
893 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wrreq_reg ( | |
894 | .scan_in(wrreq_reg_scanin[0:0]), | |
895 | .scan_out(wrreq_reg_scanout[0:0]), | |
896 | .l1clk(l1clk_in), | |
897 | .d(ic_wr_req_bf_l), | |
898 | .latout_l(wrreq_f), | |
899 | .latout(wrreq_f_l_unused), | |
900 | .siclk(siclk), | |
901 | .soclk(soclk) | |
902 | ); | |
903 | ||
904 | ||
905 | n2_icd_sp_16p5kb_cust_msffi_ctl_macro__width_1 wrreq_reg_b ( | |
906 | .scan_in(wrreq_reg_b_scanin), | |
907 | .scan_out(wrreq_reg_b_scanout), | |
908 | .l1clk ( l1clk_in ), | |
909 | .din ( ftp_ic_wr_req_bf ), | |
910 | .q_l ( wrreq_f_l ), | |
911 | .siclk(siclk), | |
912 | .soclk(soclk)); | |
913 | ||
914 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_1 ftp_access_f_reg ( | |
915 | .scan_in(ftp_access_f_reg_scanin[0:0]), | |
916 | .scan_out(ftp_access_f_reg_scanout[0:0]), | |
917 | .l1clk(l1clk_in), | |
918 | .din(ftp_asi_mbist_access_bf), | |
919 | .dout(asi_access_f), | |
920 | .siclk(siclk), | |
921 | .soclk(soclk) | |
922 | ); | |
923 | ||
924 | ||
925 | n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 rdreq_reg ( | |
926 | .scan_in(rdreq_reg_scanin), | |
927 | .scan_out(rdreq_reg_scanout), | |
928 | .l1clk ( l1clk_in ), | |
929 | .d ( ic_rd_req_bf_l ), | |
930 | .latout ( rdreq_f_l_unused ), | |
931 | .latout_l ( rdreq_f_unused ), | |
932 | .siclk(siclk), | |
933 | .soclk(soclk)); | |
934 | ||
935 | ||
936 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__width_1 rdreq_reg_b ( | |
937 | .scan_in(rdreq_reg_b_scanin), | |
938 | .scan_out(rdreq_reg_b_scanout), | |
939 | .l1clk ( l1clk_in ), | |
940 | .din ( ftp_ic_rd_req_bf ), | |
941 | .dout ( rdreq_f ), | |
942 | .siclk(siclk), | |
943 | .soclk(soclk)); | |
944 | ||
945 | ||
946 | ||
947 | // write data regsiter | |
948 | ||
949 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__stack_66c__width_66 wrdata_reg_lo_1_mux ( | |
950 | .din0({agd_asi_bist_wrdata[32:0],agd_asi_bist_wrdata[32:0]}), | |
951 | .din1(cmu_ic_data[65:0]), | |
952 | .sel0(ftp_asi_mbist_access_bf), | |
953 | .dout(wrdata_in[65:0]) | |
954 | ); | |
955 | ||
956 | ||
957 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q0_0 ( | |
958 | .scan_in(wrdata_q0_0_scanin[32:0]), | |
959 | .scan_out(wrdata_q0_0_scanout[32:0]), | |
960 | .l1clk(l1clk_wr), | |
961 | .din(wrdata_in[32:0]), | |
962 | .dout(wrdata_f[32:0]), | |
963 | .siclk(siclk), | |
964 | .soclk(soclk) | |
965 | ); | |
966 | ||
967 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q1_1 ( | |
968 | .scan_in(wrdata_q1_1_scanin[32:0]), | |
969 | .scan_out(wrdata_q1_1_scanout[32:0]), | |
970 | .l1clk(l1clk_wr), | |
971 | .din(wrdata_in[65:33]), | |
972 | .dout(wrdata_f[65:33]), | |
973 | .siclk(siclk), | |
974 | .soclk(soclk) | |
975 | ); | |
976 | ||
977 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__stack_66c__width_66 wrdata_reg_lo_2_mux ( | |
978 | .din0({agd_asi_bist_wrdata[32:0],agd_asi_bist_wrdata[32:0]}), | |
979 | .din1(cmu_ic_data[131:66]), | |
980 | .sel0(ftp_asi_mbist_access_bf), | |
981 | .dout(wrdata_in[131:66]) | |
982 | ); | |
983 | ||
984 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q2_2 ( | |
985 | .scan_in(wrdata_q2_2_scanin[32:0]), | |
986 | .scan_out(wrdata_q2_2_scanout[32:0]), | |
987 | .l1clk(l1clk_wr), | |
988 | .din(wrdata_in[98:66]), | |
989 | .dout(wrdata_f[98:66]), | |
990 | .siclk(siclk), | |
991 | .soclk(soclk) | |
992 | ); | |
993 | ||
994 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q3_3 ( | |
995 | .scan_in(wrdata_q3_3_scanin[32:0]), | |
996 | .scan_out(wrdata_q3_3_scanout[32:0]), | |
997 | .l1clk(l1clk_wr), | |
998 | .din(wrdata_in[131:99]), | |
999 | .dout(wrdata_f[131:99]), | |
1000 | .siclk(siclk), | |
1001 | .soclk(soclk) | |
1002 | ); | |
1003 | ||
1004 | ||
1005 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__stack_66c__width_66 wrdata_reg_hi_1_mux ( | |
1006 | .din0({agd_asi_bist_wrdata[32:0],agd_asi_bist_wrdata[32:0]}), | |
1007 | .din1(cmu_ic_data[197:132]), | |
1008 | .sel0(ftp_asi_mbist_access_bf), | |
1009 | .dout(wrdata_in[197:132]) | |
1010 | ); | |
1011 | ||
1012 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q0_4 ( | |
1013 | .scan_in(wrdata_q0_4_scanin[32:0]), | |
1014 | .scan_out(wrdata_q0_4_scanout[32:0]), | |
1015 | .l1clk(l1clk_wr), | |
1016 | .din(wrdata_in[164:132]), | |
1017 | .dout(wrdata_f[164:132]), | |
1018 | .siclk(siclk), | |
1019 | .soclk(soclk) | |
1020 | ); | |
1021 | ||
1022 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q1_5 ( | |
1023 | .scan_in(wrdata_q1_5_scanin[32:0]), | |
1024 | .scan_out(wrdata_q1_5_scanout[32:0]), | |
1025 | .l1clk(l1clk_wr), | |
1026 | .din(wrdata_in[197:165]), | |
1027 | .dout(wrdata_f[197:165]), | |
1028 | .siclk(siclk), | |
1029 | .soclk(soclk) | |
1030 | ); | |
1031 | ||
1032 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__stack_66c__width_66 wrdata_reg_hi_2_mux ( | |
1033 | .din0({agd_asi_bist_wrdata[32:0],agd_asi_bist_wrdata[32:0]}), | |
1034 | .din1(cmu_ic_data[263:198]), | |
1035 | .sel0(ftp_asi_mbist_access_bf), | |
1036 | .dout(wrdata_in[263:198]) | |
1037 | ); | |
1038 | ||
1039 | ||
1040 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q2_6 ( | |
1041 | .scan_in(wrdata_q2_6_scanin[32:0]), | |
1042 | .scan_out(wrdata_q2_6_scanout[32:0]), | |
1043 | .l1clk(l1clk_wr), | |
1044 | .din(wrdata_in[230:198]), | |
1045 | .dout(wrdata_f[230:198]), | |
1046 | .siclk(siclk), | |
1047 | .soclk(soclk) | |
1048 | ); | |
1049 | ||
1050 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q3_7 ( | |
1051 | .scan_in(wrdata_q3_7_scanin[32:0]), | |
1052 | .scan_out(wrdata_q3_7_scanout[32:0]), | |
1053 | .l1clk(l1clk_wr), | |
1054 | .din(wrdata_in[263:231]), | |
1055 | .dout(wrdata_f[263:231]), | |
1056 | .siclk(siclk), | |
1057 | .soclk(soclk) | |
1058 | ); | |
1059 | ||
1060 | ||
1061 | ||
1062 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_5 red_d_reg ( | |
1063 | .scan_in(red_d_reg_scanin[4:0]), | |
1064 | .scan_out(red_d_reg_scanout[4:0]), | |
1065 | .l1clk(l1clk_red_in), | |
1066 | .din(red_d_in[4:0]), | |
1067 | .dout(red_d_ff[4:0]), | |
1068 | .siclk(siclk), | |
1069 | .soclk(soclk) | |
1070 | ); | |
1071 | ||
1072 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_2 red_en_reg ( | |
1073 | .scan_in(red_en_reg_scanin[1:0]), | |
1074 | .scan_out(red_en_reg_scanout[1:0]), | |
1075 | .l1clk(l1clk_red_in), | |
1076 | .din(red_en_in[1:0]), | |
1077 | .dout(red_en_ff[1:0]), | |
1078 | .siclk(siclk), | |
1079 | .soclk(soclk) | |
1080 | ); | |
1081 | ||
1082 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_4 rid_reg ( | |
1083 | .scan_in(rid_reg_scanin[3:0]), | |
1084 | .scan_out(rid_reg_scanout[3:0]), | |
1085 | .l1clk(l1clk_red_in), | |
1086 | .din(rid_in[3:0]), | |
1087 | .dout(rid_ff[3:0]), | |
1088 | .siclk(siclk), | |
1089 | .soclk(soclk) | |
1090 | ); | |
1091 | ||
1092 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_1 red_wen_reg ( | |
1093 | .scan_in(red_wen_reg_scanin[0:0]), | |
1094 | .scan_out(red_wen_reg_scanout[0:0]), | |
1095 | .l1clk(l1clk_red_in), | |
1096 | .din(red_wen), | |
1097 | .dout(red_wen_ff_and), | |
1098 | .siclk(siclk), | |
1099 | .soclk(soclk) | |
1100 | ); | |
1101 | ||
1102 | n2_icd_sp_16p5kb_cust_and_macro__ports_2__width_1 red_wen_wrinhib_and_gate ( | |
1103 | .din0(red_wen_ff_and), | |
1104 | .din1(wr_inhibit_in_l), | |
1105 | .dout(red_wen_ff) | |
1106 | ); | |
1107 | ||
1108 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_1 red_arst_reg ( | |
1109 | .scan_in(red_arst_reg_scanin[0:0]), | |
1110 | .scan_out(red_arst_reg_scanout[0:0]), | |
1111 | .l1clk(l1clk_red_in), | |
1112 | .din(red_arst), | |
1113 | .dout(red_arst_ff_and), | |
1114 | .siclk(siclk), | |
1115 | .soclk(soclk) | |
1116 | ); | |
1117 | ||
1118 | n2_icd_sp_16p5kb_cust_and_macro__ports_2__width_1 red_arst_wrinhib_and_gate ( | |
1119 | .din0(red_arst_ff_and), | |
1120 | .din1(wr_inhibit_in_l), | |
1121 | .dout(red_arst_ff) | |
1122 | ); | |
1123 | ||
1124 | ||
1125 | ||
1126 | //////////////////////////////////////////////////// | |
1127 | // C-stage flops and muxes on the input side // | |
1128 | //////////////////////////////////////////////////// | |
1129 | ||
1130 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_8 way_f_reg ( | |
1131 | .scan_in(way_f_reg_scanin[7:0]), | |
1132 | .scan_out(way_f_reg_scanout[7:0]), | |
1133 | .l1clk(l1clk_int), | |
1134 | .din(wrway_dec_bf[7:0]), | |
1135 | .dout(wrway_dec_f[7:0]), | |
1136 | .siclk(siclk), | |
1137 | .soclk(soclk) | |
1138 | ); | |
1139 | ||
1140 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_8 way_c_reg ( | |
1141 | .scan_in(way_c_reg_scanin[7:0]), | |
1142 | .scan_out(way_c_reg_scanout[7:0]), | |
1143 | .l1clk(l1clk_out), | |
1144 | .din(wrway_dec_f[7:0]), | |
1145 | .dout(wrway_dec_c[7:0]), | |
1146 | .siclk(siclk), | |
1147 | .soclk(soclk) | |
1148 | ); | |
1149 | ||
1150 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_1 ftp_access_c_reg ( | |
1151 | .scan_in(ftp_access_c_reg_scanin[0:0]), | |
1152 | .scan_out(ftp_access_c_reg_scanout[0:0]), | |
1153 | .l1clk(l1clk_out), | |
1154 | .din(asi_access_f), | |
1155 | .dout(asi_access_c), | |
1156 | .siclk(siclk), | |
1157 | .soclk(soclk) | |
1158 | ); | |
1159 | ||
1160 | n2_icd_sp_16p5kb_cust_msffi_ctl_macro__width_1 ftp_access_c_dum ( | |
1161 | .scan_in(ftp_access_c_dum_scanin), | |
1162 | .scan_out(ftp_access_c_dum_scanout), | |
1163 | .l1clk ( l1clk_out ), | |
1164 | .din ( asi_access_f ), | |
1165 | .q_l ( asi_access_c_l ), | |
1166 | .siclk(siclk), | |
1167 | .soclk(soclk)); | |
1168 | ||
1169 | n2_icd_sp_16p5kb_cust_inv_macro__width_1 asi_access_c_l_invt ( | |
1170 | .din(asi_access_c_l), | |
1171 | .dout(asi_access_c_l_inv) | |
1172 | ); | |
1173 | ||
1174 | n2_icd_sp_16p5kb_cust_inv_macro__width_1 asi_access_c_invt ( | |
1175 | .din(asi_access_c), | |
1176 | .dout(asi_access_c_inv) | |
1177 | ); | |
1178 | ||
1179 | ||
1180 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_2__stack_50c__width_8 way_sel_mux ( | |
1181 | .din1(wrway_dec_c[7:0]), | |
1182 | .din0(itb_icd_waysel_c[7:0]), | |
1183 | .sel0 ( asi_access_c_inv), | |
1184 | .sel1 ( asi_access_c_l_inv), | |
1185 | .dout( muxed_way_sel_c[7:0] )); | |
1186 | ||
1187 | ||
1188 | ||
1189 | ||
1190 | ||
1191 | ////////////////////////////////////////////////////////////////////////////////////////////// | |
1192 | // assign i4_i0_sel_upper = ~(index_f[4:2] == 3'b000) ; | |
1193 | // assign i5_i1_sel_upper = ~( ~index_f[4] & ~index_f[3] ); | |
1194 | // assign i6_i2_sel_upper = ~((~index_f[4] & ~index_f[3]) | (~index_f[4] & ~index_f[2])); | |
1195 | // assign i7_i3_sel_upper = index_f[4] ; | |
1196 | ////////////////////////////////////////////////////////////////////////////////////////////// | |
1197 | n2_icd_sp_16p5kb_cust_or_macro__ports_3__stack_50c__width_1 i4_i0_sel_upper_or ( | |
1198 | .din0(index_f[4]), | |
1199 | .din1(index_f[3]), | |
1200 | .din2(index_f[2]), | |
1201 | .dout(i4_i0_sel_upper) | |
1202 | ); | |
1203 | ||
1204 | n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 i4_i0_sel_upper_gate_l ( | |
1205 | .din(i4_i0_sel_upper), | |
1206 | .dout(i4_i0_sel_upper_) | |
1207 | ); | |
1208 | ||
1209 | n2_icd_sp_16p5kb_cust_or_macro__ports_2__stack_50c__width_1 i5_i1_sel_upper_or ( | |
1210 | .din0(index_f[4]), | |
1211 | .din1(index_f[3]), | |
1212 | .dout(i5_i1_sel_upper) | |
1213 | ); | |
1214 | ||
1215 | n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 i5_i1_sel_upper_gate_l ( | |
1216 | .din(i5_i1_sel_upper), | |
1217 | .dout(i5_i1_sel_upper_) | |
1218 | ); | |
1219 | ||
1220 | n2_icd_sp_16p5kb_cust_or_macro__ports_2__stack_50c__width_1 i6_i2_sel_upper_or_2_gate ( | |
1221 | .din0(index_f[4]), | |
1222 | .din1(index_f[2]), | |
1223 | .dout(i6_i2_sel_upper_or_2) | |
1224 | ); | |
1225 | ||
1226 | n2_icd_sp_16p5kb_cust_and_macro__ports_2__stack_50c__width_1 i6_i2_sel_upper_and_gate ( | |
1227 | .din0(i6_i2_sel_upper_or_2), | |
1228 | .din1(i5_i1_sel_upper), | |
1229 | .dout(i6_i2_sel_upper) | |
1230 | ); | |
1231 | ||
1232 | n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 i6_i2_sel_upper_gate_l ( | |
1233 | .din(i6_i2_sel_upper), | |
1234 | .dout(i6_i2_sel_upper_) | |
1235 | ); | |
1236 | ||
1237 | n2_icd_sp_16p5kb_cust_buff_macro__stack_50c__width_1 i7_i3_sel_upper_gate ( | |
1238 | .din(index_f[4]), | |
1239 | .dout(i7_i3_sel_upper) | |
1240 | ); | |
1241 | ||
1242 | n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 i7_i3_sel_upper_gate_l ( | |
1243 | .din(i7_i3_sel_upper), | |
1244 | .dout(i7_i3_sel_upper_) | |
1245 | ); | |
1246 | ////////////////////////////////////////////////////////// | |
1247 | // write_enable // | |
1248 | ////////////////////////////////////////////////////////// | |
1249 | ||
1250 | // tisram_msff_macro wr_inh_ff (width=1) ( | |
1251 | // .scan_in(wr_inh_ff_scanin), | |
1252 | // .scan_out(wr_inh_ff_scanout), | |
1253 | // .l1clk ( l1clk_in ), | |
1254 | // .d ( wr_inhibit_in_l ), | |
1255 | // .latout_l( wr_inhibit_unused ), | |
1256 | // .latout( wr_inhibit_l )); | |
1257 | ||
1258 | n2_icd_sp_16p5kb_cust_nand_macro__ports_3__stack_50c__width_8 wr_word_en_nand ( | |
1259 | .din0({8{wr_inhibit_in_l}}), | |
1260 | .din1({8{wrreq_f}}), | |
1261 | .din2(word_en_f[7:0]), | |
1262 | .dout(wr_word_en_f_l[7:0]) | |
1263 | ); | |
1264 | ||
1265 | ||
1266 | ////////////////////////////////////////////////////////// | |
1267 | // Disable reads when quad is not enabled | |
1268 | ////////////////////////////////////////////////////////// | |
1269 | n2_icd_sp_16p5kb_cust_nand_macro__ports_4__stack_50c__width_1 rd_req_q_0_en ( | |
1270 | .din0(icd_quad_0_en_f), | |
1271 | .din1(rdreq_f), | |
1272 | .din2(wrreq_f_l), | |
1273 | .din3(wr_inhibit_in_l), | |
1274 | .dout(rdreq_f_q0_l) | |
1275 | ); | |
1276 | ||
1277 | n2_icd_sp_16p5kb_cust_inv_macro rd_req_q_0_en_inv ( | |
1278 | .din (rdreq_f_q0_l), | |
1279 | .dout (rdreq_f_q0)) ; | |
1280 | ||
1281 | n2_icd_sp_16p5kb_cust_and_macro quad_0_en_qualify ( | |
1282 | .din0 (rdreq_f_q0) , | |
1283 | .din1 (icd_quad_0_en_f) , | |
1284 | .dout (icd_quad_0_en_f_qual)) ; | |
1285 | ||
1286 | ||
1287 | n2_icd_sp_16p5kb_cust_nand_macro__ports_4__stack_50c__width_1 rd_req_q_1_en ( | |
1288 | .din0(icd_quad_1_en_f), | |
1289 | .din1(rdreq_f), | |
1290 | .din2(wrreq_f_l), | |
1291 | .din3(wr_inhibit_in_l), | |
1292 | .dout(rdreq_f_q1_l) | |
1293 | ); | |
1294 | ||
1295 | n2_icd_sp_16p5kb_cust_inv_macro rd_req_q_1_en_inv ( | |
1296 | .din (rdreq_f_q1_l), | |
1297 | .dout (rdreq_f_q1)) ; | |
1298 | ||
1299 | n2_icd_sp_16p5kb_cust_and_macro quad_1_en_qualify ( | |
1300 | .din0 (rdreq_f_q1) , | |
1301 | .din1 (icd_quad_1_en_f) , | |
1302 | .dout (icd_quad_1_en_f_qual)) ; | |
1303 | ||
1304 | ||
1305 | n2_icd_sp_16p5kb_cust_nand_macro__ports_4__stack_50c__width_1 rd_req_q_2_en ( | |
1306 | .din0(icd_quad_2_en_f), | |
1307 | .din1(rdreq_f), | |
1308 | .din2(wrreq_f_l), | |
1309 | .din3(wr_inhibit_in_l), | |
1310 | .dout(rdreq_f_q2_l) | |
1311 | ); | |
1312 | ||
1313 | n2_icd_sp_16p5kb_cust_inv_macro rd_req_q_2_en_inv ( | |
1314 | .din (rdreq_f_q2_l), | |
1315 | .dout (rdreq_f_q2)) ; | |
1316 | ||
1317 | n2_icd_sp_16p5kb_cust_and_macro quad_2_en_qualify ( | |
1318 | .din0 (rdreq_f_q2) , | |
1319 | .din1 (icd_quad_2_en_f) , | |
1320 | .dout (icd_quad_2_en_f_qual)) ; | |
1321 | ||
1322 | ||
1323 | n2_icd_sp_16p5kb_cust_nand_macro__ports_4__stack_50c__width_1 rd_req_q_3_en ( | |
1324 | .din0(icd_quad_3_en_f), | |
1325 | .din1(rdreq_f), | |
1326 | .din2(wrreq_f_l), | |
1327 | .din3(wr_inhibit_in_l), | |
1328 | .dout(rdreq_f_q3_l) | |
1329 | ); | |
1330 | ||
1331 | ||
1332 | n2_icd_sp_16p5kb_cust_inv_macro rd_req_q_3_en_inv ( | |
1333 | .din (rdreq_f_q3_l), | |
1334 | .dout (rdreq_f_q3)) ; | |
1335 | ||
1336 | n2_icd_sp_16p5kb_cust_and_macro quad_3_en_qualify ( | |
1337 | .din0 (rdreq_f_q3) , | |
1338 | .din1 (icd_quad_3_en_f) , | |
1339 | .dout (icd_quad_3_en_f_qual)) ; | |
1340 | ||
1341 | ||
1342 | ////////////////////////////////////////////////////////// | |
1343 | // 4:8 decode // | |
1344 | ////////////////////////////////////////////////////////// | |
1345 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_8 wr_way_decode ( | |
1346 | .din0 (8'b00000001), | |
1347 | .din1 (8'b00000010), | |
1348 | .din2 (8'b00000100), | |
1349 | .din3 (8'b00001000), | |
1350 | .din4 (8'b00010000), | |
1351 | .din5 (8'b00100000), | |
1352 | .din6 (8'b01000000), | |
1353 | .din7 (8'b10000000), | |
1354 | .sel (wrway_f[2:0]), // This changed | |
1355 | .dout (wrway_dec_bf[7:0]) | |
1356 | ); | |
1357 | ||
1358 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_8 wr_way_decode_l ( | |
1359 | .din0 (8'b11111110), | |
1360 | .din1 (8'b11111101), | |
1361 | .din2 (8'b11111011), | |
1362 | .din3 (8'b11110111), | |
1363 | .din4 (8'b11101111), | |
1364 | .din5 (8'b11011111), | |
1365 | .din6 (8'b10111111), | |
1366 | .din7 (8'b01111111), | |
1367 | .sel (wrway_f[2:0]), | |
1368 | .dout (wrway_dec_f_[7:0]) | |
1369 | ); | |
1370 | ||
1371 | ////////////////////////////////////////////////////////// | |
1372 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_8 rid_sel_mux0 ( | |
1373 | .din0 (8'b00000001), | |
1374 | .din1 (8'b00000010), | |
1375 | .din2 (8'b00000100), | |
1376 | .din3 (8'b00001000), | |
1377 | .din4 (8'b00010000), | |
1378 | .din5 (8'b00100000), | |
1379 | .din6 (8'b01000000), | |
1380 | .din7 (8'b10000000), | |
1381 | .sel (rid_ff[2:0]), | |
1382 | .dout (rid_sel_dec[7:0]) | |
1383 | ); | |
1384 | ||
1385 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__width_16 rid_sel_mux1 ( | |
1386 | .din0 ({rid_sel_dec[7:0],8'b00000000}), | |
1387 | .din1 ({8'b00000000,rid_sel_dec[7:0]}), | |
1388 | .sel0 (rid_ff[3]), | |
1389 | .dout (rid_sel[15:0]) | |
1390 | ); | |
1391 | ||
1392 | ||
1393 | ///////////////////////////////////////////////////////////////// | |
1394 | // Instantiate each way ARRAY. // | |
1395 | ///////////////////////////////////////////////////////////////// | |
1396 | // The Icache is divided in four quads. // | |
1397 | // Each quad is made of two Banks. // | |
1398 | // Each quad has two words for all the 8 ways. // | |
1399 | // ----------------------------------------------------------- // | |
1400 | // quad_0 has I0/I4 for ways 7 to 0 // | |
1401 | // quad-1 has I1/I5 for ways 7 to 0 // | |
1402 | // quad-2 has I2/I6 for ways 7 to 0 // | |
1403 | // quad-3 has I3/I7 for ways 7 to 0 // | |
1404 | // ----------------------------------------------------------- // | |
1405 | // Inside quad-0 top bank has ways 3 to 0 // | |
1406 | // Inside quad-0 bottom bank has ways 7 to 4 // | |
1407 | // ----------------------------------------------------------- // | |
1408 | // Other quads are arranged similarly. // | |
1409 | ///////////////////////////////////////////////////////////////// | |
1410 | ||
1411 | ///////////////////////////////////////////////////////////////// | |
1412 | ///////////////////////////////////////////////////////////////// | |
1413 | // quad-0 // | |
1414 | ///////////////////////////////////////////////////////////////// | |
1415 | ////////////////////////////////////////////// | |
1416 | // quad-0 // | |
1417 | ///////////////////////////////////////////// | |
1418 | n2_icd_quad_array quad_0 (.adr_ac_h(index_f[10:5]), | |
1419 | .adr_ac_l(index_f_l[10:5]), | |
1420 | .rd_en_a_l(rdreq_f_q0_l), | |
1421 | .quaden_f_l(icd_quad_0_en_f_lat_l), | |
1422 | .wr_word_en_ac_l({wr_word_en_f_l[4],wr_word_en_f_l[0]}), | |
1423 | .wr_waysel0_ac_l(wrway_dec_f_[7:0]), | |
1424 | .wr_waysel1_ac_l(wrway_dec_f_[7:0]), | |
1425 | .din0_a(wrdata_f[32:0]), | |
1426 | .din1_a(wrdata_f[164:132]), | |
1427 | .dout_wy0_bc(rd_data_w0_i4_or_i0[32:0]), | |
1428 | .dout_wy1_bc(rd_data_w1_i4_or_i0[32:0]), | |
1429 | .dout_wy2_bc(rd_data_w2_i4_or_i0[32:0]), | |
1430 | .dout_wy3_bc(rd_data_w3_i4_or_i0[32:0]), | |
1431 | .dout_wy4_bc(rd_data_w4_i4_or_i0[32:0]), | |
1432 | .dout_wy5_bc(rd_data_w5_i4_or_i0[32:0]), | |
1433 | .dout_wy6_bc(rd_data_w6_i4_or_i0[32:0]), | |
1434 | .dout_wy7_bc(rd_data_w7_i4_or_i0[32:0]), | |
1435 | .reg_d_lft_top(reg_d_q0_w3_w0_lft_d[4:0]) , | |
1436 | .reg_en_lft_top(reg_d_q0_w3_w0_lft_en[1:0]) , | |
1437 | .reg_d_rgt_top(reg_d_q0_w3_w0_rgt_d[4:0]) , | |
1438 | .reg_en_rgt_top(reg_d_q0_w3_w0_rgt_en[1:0]) , | |
1439 | .reg_d_lft_bot(reg_d_q0_w7_w4_lft_d[4:0]) , | |
1440 | .reg_en_lft_bot(reg_d_q0_w7_w4_lft_en[1:0]) , | |
1441 | .reg_d_rgt_bot(reg_d_q0_w7_w4_rgt_d[4:0]) , | |
1442 | .reg_en_rgt_bot(reg_d_q0_w7_w4_rgt_en[1:0]) , | |
1443 | .red_d_ff(red_d_ff[4:0]), | |
1444 | .red_en_ff(red_en_ff[1:0]), | |
1445 | .rid_sel(rid_sel[3:0]) , | |
1446 | .red_wen_ff(red_wen_ff) , | |
1447 | .red_arst_ff(red_arst_ff), | |
1448 | .rd_worden_ac_l({i4_i0_sel_upper_,i4_i0_sel_upper}), | |
1449 | .l1clk_fuse(l1clk_fuse_clk1), | |
1450 | .l1clk(l1clk_free), | |
1451 | .vnw_ary(vnw_ary) | |
1452 | ); | |
1453 | ||
1454 | ||
1455 | ///////////////////////////////////////////////////////////////// | |
1456 | ///////////////////////////////////////////////////////////////// | |
1457 | // quad-1 // | |
1458 | ///////////////////////////////////////////////////////////////// | |
1459 | n2_icd_quad_array quad_1 (.adr_ac_h(index_f[10:5]), | |
1460 | .adr_ac_l(index_f_l[10:5]), | |
1461 | .rd_en_a_l(rdreq_f_q1_l), | |
1462 | .quaden_f_l(icd_quad_1_en_f_lat_l), | |
1463 | .wr_word_en_ac_l({wr_word_en_f_l[5],wr_word_en_f_l[1]}), | |
1464 | .wr_waysel0_ac_l(wrway_dec_f_[7:0]), | |
1465 | .wr_waysel1_ac_l(wrway_dec_f_[7:0]), | |
1466 | .din0_a(wrdata_f[65:33]), | |
1467 | .din1_a(wrdata_f[197:165]), | |
1468 | .dout_wy0_bc(rd_data_w0_i5_or_i1[32:0]), | |
1469 | .dout_wy1_bc(rd_data_w1_i5_or_i1[32:0]), | |
1470 | .dout_wy2_bc(rd_data_w2_i5_or_i1[32:0]), | |
1471 | .dout_wy3_bc(rd_data_w3_i5_or_i1[32:0]), | |
1472 | .dout_wy4_bc(rd_data_w4_i5_or_i1[32:0]), | |
1473 | .dout_wy5_bc(rd_data_w5_i5_or_i1[32:0]), | |
1474 | .dout_wy6_bc(rd_data_w6_i5_or_i1[32:0]), | |
1475 | .dout_wy7_bc(rd_data_w7_i5_or_i1[32:0]), | |
1476 | .reg_d_lft_top(reg_d_q1_w3_w0_lft_d[4:0]) , | |
1477 | .reg_en_lft_top(reg_d_q1_w3_w0_lft_en[1:0]) , | |
1478 | .reg_d_rgt_top(reg_d_q1_w3_w0_rgt_d[4:0]) , | |
1479 | .reg_en_rgt_top(reg_d_q1_w3_w0_rgt_en[1:0]) , | |
1480 | .reg_d_lft_bot(reg_d_q1_w7_w4_lft_d[4:0]) , | |
1481 | .reg_en_lft_bot(reg_d_q1_w7_w4_lft_en[1:0]) , | |
1482 | .reg_d_rgt_bot(reg_d_q1_w7_w4_rgt_d[4:0]) , | |
1483 | .reg_en_rgt_bot(reg_d_q1_w7_w4_rgt_en[1:0]) , | |
1484 | .red_d_ff(red_d_ff[4:0]), | |
1485 | .red_en_ff(red_en_ff[1:0]), | |
1486 | .rid_sel(rid_sel[7:4]) , | |
1487 | .red_wen_ff(red_wen_ff) , | |
1488 | .red_arst_ff(red_arst_ff), | |
1489 | .rd_worden_ac_l({i5_i1_sel_upper_,i5_i1_sel_upper}), | |
1490 | .l1clk_fuse(l1clk_fuse_clk1), | |
1491 | .l1clk(l1clk_free), | |
1492 | .vnw_ary(vnw_ary) | |
1493 | ); | |
1494 | ||
1495 | ||
1496 | ///////////////////////////////////////////////////////////////// | |
1497 | ///////////////////////////////////////////////////////////////// | |
1498 | // quad-2 // | |
1499 | ///////////////////////////////////////////////////////////////// | |
1500 | n2_icd_quad_array quad_2 (.adr_ac_h(index_f[10:5]), | |
1501 | .adr_ac_l(index_f_l[10:5]), | |
1502 | .rd_en_a_l(rdreq_f_q2_l), | |
1503 | .quaden_f_l(icd_quad_2_en_f_lat_l), | |
1504 | .wr_word_en_ac_l({wr_word_en_f_l[6],wr_word_en_f_l[2]}), | |
1505 | .wr_waysel0_ac_l(wrway_dec_f_[7:0]), | |
1506 | .wr_waysel1_ac_l(wrway_dec_f_[7:0]), | |
1507 | .din0_a(wrdata_f[98:66]), | |
1508 | .din1_a(wrdata_f[230:198]), | |
1509 | .dout_wy0_bc(rd_data_w0_i6_or_i2[32:0]), | |
1510 | .dout_wy1_bc(rd_data_w1_i6_or_i2[32:0]), | |
1511 | .dout_wy2_bc(rd_data_w2_i6_or_i2[32:0]), | |
1512 | .dout_wy3_bc(rd_data_w3_i6_or_i2[32:0]), | |
1513 | .dout_wy4_bc(rd_data_w4_i6_or_i2[32:0]), | |
1514 | .dout_wy5_bc(rd_data_w5_i6_or_i2[32:0]), | |
1515 | .dout_wy6_bc(rd_data_w6_i6_or_i2[32:0]), | |
1516 | .dout_wy7_bc(rd_data_w7_i6_or_i2[32:0]), | |
1517 | .reg_d_lft_top(reg_d_q2_w3_w0_lft_d[4:0]) , | |
1518 | .reg_en_lft_top(reg_d_q2_w3_w0_lft_en[1:0]) , | |
1519 | .reg_d_rgt_top(reg_d_q2_w3_w0_rgt_d[4:0]) , | |
1520 | .reg_en_rgt_top(reg_d_q2_w3_w0_rgt_en[1:0]) , | |
1521 | .reg_d_lft_bot(reg_d_q2_w7_w4_lft_d[4:0]) , | |
1522 | .reg_en_lft_bot(reg_d_q2_w7_w4_lft_en[1:0]) , | |
1523 | .reg_d_rgt_bot(reg_d_q2_w7_w4_rgt_d[4:0]) , | |
1524 | .reg_en_rgt_bot(reg_d_q2_w7_w4_rgt_en[1:0]) , | |
1525 | .red_d_ff(red_d_ff[4:0]), | |
1526 | .red_en_ff(red_en_ff[1:0]), | |
1527 | .rid_sel(rid_sel[11:8]) , | |
1528 | .red_wen_ff(red_wen_ff) , | |
1529 | .red_arst_ff(red_arst_ff), | |
1530 | .rd_worden_ac_l({i6_i2_sel_upper_,i6_i2_sel_upper}), | |
1531 | .l1clk_fuse(l1clk_fuse_clk1), | |
1532 | .l1clk(l1clk_free), | |
1533 | .vnw_ary(vnw_ary) | |
1534 | ); | |
1535 | ||
1536 | ||
1537 | ||
1538 | ||
1539 | ///////////////////////////////////////////////////////////////// | |
1540 | ///////////////////////////////////////////////////////////////// | |
1541 | // quad-3 // | |
1542 | ///////////////////////////////////////////////////////////////// | |
1543 | n2_icd_quad_array quad_3 (.adr_ac_h(index_f[10:5]), | |
1544 | .adr_ac_l(index_f_l[10:5]), | |
1545 | .rd_en_a_l(rdreq_f_q3_l), | |
1546 | .quaden_f_l(icd_quad_3_en_f_lat_l), | |
1547 | .wr_word_en_ac_l({wr_word_en_f_l[7],wr_word_en_f_l[3]}), | |
1548 | .wr_waysel0_ac_l(wrway_dec_f_[7:0]), | |
1549 | .wr_waysel1_ac_l(wrway_dec_f_[7:0]), | |
1550 | .din0_a(wrdata_f[131:99]), | |
1551 | .din1_a(wrdata_f[263:231]), | |
1552 | .dout_wy0_bc(rd_data_w0_i7_or_i3[32:0]), | |
1553 | .dout_wy1_bc(rd_data_w1_i7_or_i3[32:0]), | |
1554 | .dout_wy2_bc(rd_data_w2_i7_or_i3[32:0]), | |
1555 | .dout_wy3_bc(rd_data_w3_i7_or_i3[32:0]), | |
1556 | .dout_wy4_bc(rd_data_w4_i7_or_i3[32:0]), | |
1557 | .dout_wy5_bc(rd_data_w5_i7_or_i3[32:0]), | |
1558 | .dout_wy6_bc(rd_data_w6_i7_or_i3[32:0]), | |
1559 | .dout_wy7_bc(rd_data_w7_i7_or_i3[32:0]), | |
1560 | .reg_d_lft_top(reg_d_q3_w3_w0_lft_d[4:0]) , | |
1561 | .reg_en_lft_top(reg_d_q3_w3_w0_lft_en[1:0]) , | |
1562 | .reg_d_rgt_top(reg_d_q3_w3_w0_rgt_d[4:0]) , | |
1563 | .reg_en_rgt_top(reg_d_q3_w3_w0_rgt_en[1:0]) , | |
1564 | .reg_d_lft_bot(reg_d_q3_w7_w4_lft_d[4:0]) , | |
1565 | .reg_en_lft_bot(reg_d_q3_w7_w4_lft_en[1:0]) , | |
1566 | .reg_d_rgt_bot(reg_d_q3_w7_w4_rgt_d[4:0]) , | |
1567 | .reg_en_rgt_bot(reg_d_q3_w7_w4_rgt_en[1:0]) , | |
1568 | .red_d_ff(red_d_ff[4:0]), | |
1569 | .red_en_ff(red_en_ff[1:0]), | |
1570 | .rid_sel(rid_sel[15:12]) , | |
1571 | .red_wen_ff(red_wen_ff) , | |
1572 | .red_arst_ff(red_arst_ff), | |
1573 | .rd_worden_ac_l({i7_i3_sel_upper_,i7_i3_sel_upper}), | |
1574 | .l1clk_fuse(l1clk_fuse_clk1), | |
1575 | .l1clk(l1clk_free), | |
1576 | .vnw_ary(vnw_ary) | |
1577 | ); | |
1578 | ||
1579 | ||
1580 | ||
1581 | ||
1582 | ////////////////////////////////////////////////////////////////////////// | |
1583 | // Mux the instructions in each way to four buses // | |
1584 | ////////////////////////////////////////////////////////////////////////// | |
1585 | ////////////////////////////////////////////////////////////////////////// | |
1586 | // Flop all the way outputs. // | |
1587 | ////////////////////////////////////////////////////////////////////////// | |
1588 | ||
1589 | ////////////////////////////////////////////////// | |
1590 | // way 0 flops // | |
1591 | ////////////////////////////////////////////////// | |
1592 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w0_reg ( | |
1593 | .scan_in(data_bus_0_w0_reg_scanin[32:0]), | |
1594 | .scan_out(data_bus_0_w0_reg_scanout[32:0]), | |
1595 | .l1clk(l1clk_q0_out), | |
1596 | .din(rd_data_w0_i4_or_i0[32:0]), | |
1597 | .dout(data_bus_0_w0_c[32:0]), | |
1598 | .siclk(siclk), | |
1599 | .soclk(soclk) | |
1600 | ); | |
1601 | ||
1602 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w0_reg ( | |
1603 | .scan_in(data_bus_1_w0_reg_scanin[32:0]), | |
1604 | .scan_out(data_bus_1_w0_reg_scanout[32:0]), | |
1605 | .l1clk(l1clk_q1_out), | |
1606 | .din(rd_data_w0_i5_or_i1[32:0]), | |
1607 | .dout(data_bus_1_w0_c[32:0]), | |
1608 | .siclk(siclk), | |
1609 | .soclk(soclk) | |
1610 | ); | |
1611 | ||
1612 | ||
1613 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w0_reg ( | |
1614 | .scan_in(data_bus_2_w0_reg_scanin[32:0]), | |
1615 | .scan_out(data_bus_2_w0_reg_scanout[32:0]), | |
1616 | .l1clk(l1clk_q2_out), | |
1617 | .din(rd_data_w0_i6_or_i2[32:0]), | |
1618 | .dout(data_bus_2_w0_c[32:0]), | |
1619 | .siclk(siclk), | |
1620 | .soclk(soclk) | |
1621 | ); | |
1622 | ||
1623 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w0_reg ( | |
1624 | .scan_in(data_bus_3_w0_reg_scanin[32:0]), | |
1625 | .scan_out(data_bus_3_w0_reg_scanout[32:0]), | |
1626 | .l1clk(l1clk_q3_out), | |
1627 | .din(rd_data_w0_i7_or_i3[32:0]), | |
1628 | .dout(data_bus_3_w0_c[32:0]), | |
1629 | .siclk(siclk), | |
1630 | .soclk(soclk) | |
1631 | ); | |
1632 | ////////////////////////////////////////////////// | |
1633 | // way 1 flops // | |
1634 | ////////////////////////////////////////////////// | |
1635 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w1_reg ( | |
1636 | .scan_in(data_bus_0_w1_reg_scanin[32:0]), | |
1637 | .scan_out(data_bus_0_w1_reg_scanout[32:0]), | |
1638 | .l1clk(l1clk_q0_out), | |
1639 | .din(rd_data_w1_i4_or_i0[32:0]), | |
1640 | .dout(data_bus_0_w1_c[32:0]), | |
1641 | .siclk(siclk), | |
1642 | .soclk(soclk) | |
1643 | ); | |
1644 | ||
1645 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w1_reg ( | |
1646 | .scan_in(data_bus_1_w1_reg_scanin[32:0]), | |
1647 | .scan_out(data_bus_1_w1_reg_scanout[32:0]), | |
1648 | .l1clk(l1clk_q1_out), | |
1649 | .din(rd_data_w1_i5_or_i1[32:0]), | |
1650 | .dout(data_bus_1_w1_c[32:0]), | |
1651 | .siclk(siclk), | |
1652 | .soclk(soclk) | |
1653 | ); | |
1654 | ||
1655 | ||
1656 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w1_reg ( | |
1657 | .scan_in(data_bus_2_w1_reg_scanin[32:0]), | |
1658 | .scan_out(data_bus_2_w1_reg_scanout[32:0]), | |
1659 | .l1clk(l1clk_q2_out), | |
1660 | .din(rd_data_w1_i6_or_i2[32:0]), | |
1661 | .dout(data_bus_2_w1_c[32:0]), | |
1662 | .siclk(siclk), | |
1663 | .soclk(soclk) | |
1664 | ); | |
1665 | ||
1666 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w1_reg ( | |
1667 | .scan_in(data_bus_3_w1_reg_scanin[32:0]), | |
1668 | .scan_out(data_bus_3_w1_reg_scanout[32:0]), | |
1669 | .l1clk(l1clk_q3_out), | |
1670 | .din(rd_data_w1_i7_or_i3[32:0]), | |
1671 | .dout(data_bus_3_w1_c[32:0]), | |
1672 | .siclk(siclk), | |
1673 | .soclk(soclk) | |
1674 | ); | |
1675 | ////////////////////////////////////////////////// | |
1676 | // way 2 flops // | |
1677 | ////////////////////////////////////////////////// | |
1678 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w2_reg ( | |
1679 | .scan_in(data_bus_0_w2_reg_scanin[32:0]), | |
1680 | .scan_out(data_bus_0_w2_reg_scanout[32:0]), | |
1681 | .l1clk(l1clk_q0_out), | |
1682 | .din(rd_data_w2_i4_or_i0[32:0]), | |
1683 | .dout(data_bus_0_w2_c[32:0]), | |
1684 | .siclk(siclk), | |
1685 | .soclk(soclk) | |
1686 | ); | |
1687 | ||
1688 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w2_reg ( | |
1689 | .scan_in(data_bus_1_w2_reg_scanin[32:0]), | |
1690 | .scan_out(data_bus_1_w2_reg_scanout[32:0]), | |
1691 | .l1clk(l1clk_q1_out), | |
1692 | .din(rd_data_w2_i5_or_i1[32:0]), | |
1693 | .dout(data_bus_1_w2_c[32:0]), | |
1694 | .siclk(siclk), | |
1695 | .soclk(soclk) | |
1696 | ); | |
1697 | ||
1698 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w2_reg ( | |
1699 | .scan_in(data_bus_2_w2_reg_scanin[32:0]), | |
1700 | .scan_out(data_bus_2_w2_reg_scanout[32:0]), | |
1701 | .l1clk(l1clk_q2_out), | |
1702 | .din(rd_data_w2_i6_or_i2[32:0]), | |
1703 | .dout(data_bus_2_w2_c[32:0]), | |
1704 | .siclk(siclk), | |
1705 | .soclk(soclk) | |
1706 | ); | |
1707 | ||
1708 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w2_reg ( | |
1709 | .scan_in(data_bus_3_w2_reg_scanin[32:0]), | |
1710 | .scan_out(data_bus_3_w2_reg_scanout[32:0]), | |
1711 | .l1clk(l1clk_q3_out), | |
1712 | .din(rd_data_w2_i7_or_i3[32:0]), | |
1713 | .dout(data_bus_3_w2_c[32:0]), | |
1714 | .siclk(siclk), | |
1715 | .soclk(soclk) | |
1716 | ); | |
1717 | ////////////////////////////////////////////////// | |
1718 | // way 3 flops // | |
1719 | ////////////////////////////////////////////////// | |
1720 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w3_reg ( | |
1721 | .scan_in(data_bus_0_w3_reg_scanin[32:0]), | |
1722 | .scan_out(data_bus_0_w3_reg_scanout[32:0]), | |
1723 | .l1clk(l1clk_q0_out), | |
1724 | .din(rd_data_w3_i4_or_i0[32:0]), | |
1725 | .dout(data_bus_0_w3_c[32:0]), | |
1726 | .siclk(siclk), | |
1727 | .soclk(soclk) | |
1728 | ); | |
1729 | ||
1730 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w3_reg ( | |
1731 | .scan_in(data_bus_1_w3_reg_scanin[32:0]), | |
1732 | .scan_out(data_bus_1_w3_reg_scanout[32:0]), | |
1733 | .l1clk(l1clk_q1_out), | |
1734 | .din(rd_data_w3_i5_or_i1[32:0]), | |
1735 | .dout(data_bus_1_w3_c[32:0]), | |
1736 | .siclk(siclk), | |
1737 | .soclk(soclk) | |
1738 | ); | |
1739 | ||
1740 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w3_reg ( | |
1741 | .scan_in(data_bus_2_w3_reg_scanin[32:0]), | |
1742 | .scan_out(data_bus_2_w3_reg_scanout[32:0]), | |
1743 | .l1clk(l1clk_q2_out), | |
1744 | .din(rd_data_w3_i6_or_i2[32:0]), | |
1745 | .dout(data_bus_2_w3_c[32:0]), | |
1746 | .siclk(siclk), | |
1747 | .soclk(soclk) | |
1748 | ); | |
1749 | ||
1750 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w3_reg ( | |
1751 | .scan_in(data_bus_3_w3_reg_scanin[32:0]), | |
1752 | .scan_out(data_bus_3_w3_reg_scanout[32:0]), | |
1753 | .l1clk(l1clk_q3_out), | |
1754 | .din(rd_data_w3_i7_or_i3[32:0]), | |
1755 | .dout(data_bus_3_w3_c[32:0]), | |
1756 | .siclk(siclk), | |
1757 | .soclk(soclk) | |
1758 | ); | |
1759 | ////////////////////////////////////////////////// | |
1760 | // way 4 flops // | |
1761 | ////////////////////////////////////////////////// | |
1762 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w4_reg ( | |
1763 | .scan_in(data_bus_0_w4_reg_scanin[32:0]), | |
1764 | .scan_out(data_bus_0_w4_reg_scanout[32:0]), | |
1765 | .l1clk(l1clk_q0_out), | |
1766 | .din(rd_data_w4_i4_or_i0[32:0]), | |
1767 | .dout(data_bus_0_w4_c[32:0]), | |
1768 | .siclk(siclk), | |
1769 | .soclk(soclk) | |
1770 | ); | |
1771 | ||
1772 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w4_reg ( | |
1773 | .scan_in(data_bus_1_w4_reg_scanin[32:0]), | |
1774 | .scan_out(data_bus_1_w4_reg_scanout[32:0]), | |
1775 | .l1clk(l1clk_q1_out), | |
1776 | .din(rd_data_w4_i5_or_i1[32:0]), | |
1777 | .dout(data_bus_1_w4_c[32:0]), | |
1778 | .siclk(siclk), | |
1779 | .soclk(soclk) | |
1780 | ); | |
1781 | ||
1782 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w4_reg ( | |
1783 | .scan_in(data_bus_2_w4_reg_scanin[32:0]), | |
1784 | .scan_out(data_bus_2_w4_reg_scanout[32:0]), | |
1785 | .l1clk(l1clk_q2_out), | |
1786 | .din(rd_data_w4_i6_or_i2[32:0]), | |
1787 | .dout(data_bus_2_w4_c[32:0]), | |
1788 | .siclk(siclk), | |
1789 | .soclk(soclk) | |
1790 | ); | |
1791 | ||
1792 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w4_reg ( | |
1793 | .scan_in(data_bus_3_w4_reg_scanin[32:0]), | |
1794 | .scan_out(data_bus_3_w4_reg_scanout[32:0]), | |
1795 | .l1clk(l1clk_q3_out), | |
1796 | .din(rd_data_w4_i7_or_i3[32:0]), | |
1797 | .dout(data_bus_3_w4_c[32:0]), | |
1798 | .siclk(siclk), | |
1799 | .soclk(soclk) | |
1800 | ); | |
1801 | ////////////////////////////////////////////////// | |
1802 | // way 5 flops // | |
1803 | ////////////////////////////////////////////////// | |
1804 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w5_reg ( | |
1805 | .scan_in(data_bus_0_w5_reg_scanin[32:0]), | |
1806 | .scan_out(data_bus_0_w5_reg_scanout[32:0]), | |
1807 | .l1clk(l1clk_q0_out), | |
1808 | .din(rd_data_w5_i4_or_i0[32:0]), | |
1809 | .dout(data_bus_0_w5_c[32:0]), | |
1810 | .siclk(siclk), | |
1811 | .soclk(soclk) | |
1812 | ); | |
1813 | ||
1814 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w5_reg ( | |
1815 | .scan_in(data_bus_1_w5_reg_scanin[32:0]), | |
1816 | .scan_out(data_bus_1_w5_reg_scanout[32:0]), | |
1817 | .l1clk(l1clk_q1_out), | |
1818 | .din(rd_data_w5_i5_or_i1[32:0]), | |
1819 | .dout(data_bus_1_w5_c[32:0]), | |
1820 | .siclk(siclk), | |
1821 | .soclk(soclk) | |
1822 | ); | |
1823 | ||
1824 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w5_reg ( | |
1825 | .scan_in(data_bus_2_w5_reg_scanin[32:0]), | |
1826 | .scan_out(data_bus_2_w5_reg_scanout[32:0]), | |
1827 | .l1clk(l1clk_q2_out), | |
1828 | .din(rd_data_w5_i6_or_i2[32:0]), | |
1829 | .dout(data_bus_2_w5_c[32:0]), | |
1830 | .siclk(siclk), | |
1831 | .soclk(soclk) | |
1832 | ); | |
1833 | ||
1834 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w5_reg ( | |
1835 | .scan_in(data_bus_3_w5_reg_scanin[32:0]), | |
1836 | .scan_out(data_bus_3_w5_reg_scanout[32:0]), | |
1837 | .l1clk(l1clk_q3_out), | |
1838 | .din(rd_data_w5_i7_or_i3[32:0]), | |
1839 | .dout(data_bus_3_w5_c[32:0]), | |
1840 | .siclk(siclk), | |
1841 | .soclk(soclk) | |
1842 | ); | |
1843 | ////////////////////////////////////////////////// | |
1844 | // way 6 flops // | |
1845 | ////////////////////////////////////////////////// | |
1846 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w6_reg ( | |
1847 | .scan_in(data_bus_0_w6_reg_scanin[32:0]), | |
1848 | .scan_out(data_bus_0_w6_reg_scanout[32:0]), | |
1849 | .l1clk(l1clk_q0_out), | |
1850 | .din(rd_data_w6_i4_or_i0[32:0]), | |
1851 | .dout(data_bus_0_w6_c[32:0]), | |
1852 | .siclk(siclk), | |
1853 | .soclk(soclk) | |
1854 | ); | |
1855 | ||
1856 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w6_reg ( | |
1857 | .scan_in(data_bus_1_w6_reg_scanin[32:0]), | |
1858 | .scan_out(data_bus_1_w6_reg_scanout[32:0]), | |
1859 | .l1clk(l1clk_q1_out), | |
1860 | .din(rd_data_w6_i5_or_i1[32:0]), | |
1861 | .dout(data_bus_1_w6_c[32:0]), | |
1862 | .siclk(siclk), | |
1863 | .soclk(soclk) | |
1864 | ); | |
1865 | ||
1866 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w6_reg ( | |
1867 | .scan_in(data_bus_2_w6_reg_scanin[32:0]), | |
1868 | .scan_out(data_bus_2_w6_reg_scanout[32:0]), | |
1869 | .l1clk(l1clk_q2_out), | |
1870 | .din(rd_data_w6_i6_or_i2[32:0]), | |
1871 | .dout(data_bus_2_w6_c[32:0]), | |
1872 | .siclk(siclk), | |
1873 | .soclk(soclk) | |
1874 | ); | |
1875 | ||
1876 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w6_reg ( | |
1877 | .scan_in(data_bus_3_w6_reg_scanin[32:0]), | |
1878 | .scan_out(data_bus_3_w6_reg_scanout[32:0]), | |
1879 | .l1clk(l1clk_q3_out), | |
1880 | .din(rd_data_w6_i7_or_i3[32:0]), | |
1881 | .dout(data_bus_3_w6_c[32:0]), | |
1882 | .siclk(siclk), | |
1883 | .soclk(soclk) | |
1884 | ); | |
1885 | ////////////////////////////////////////////////// | |
1886 | // way 7 flops // | |
1887 | ////////////////////////////////////////////////// | |
1888 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w7_reg ( | |
1889 | .scan_in(data_bus_0_w7_reg_scanin[32:0]), | |
1890 | .scan_out(data_bus_0_w7_reg_scanout[32:0]), | |
1891 | .l1clk(l1clk_q0_out), | |
1892 | .din(rd_data_w7_i4_or_i0[32:0]), | |
1893 | .dout(data_bus_0_w7_c[32:0]), | |
1894 | .siclk(siclk), | |
1895 | .soclk(soclk) | |
1896 | ); | |
1897 | ||
1898 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w7_reg ( | |
1899 | .scan_in(data_bus_1_w7_reg_scanin[32:0]), | |
1900 | .scan_out(data_bus_1_w7_reg_scanout[32:0]), | |
1901 | .l1clk(l1clk_q1_out), | |
1902 | .din(rd_data_w7_i5_or_i1[32:0]), | |
1903 | .dout(data_bus_1_w7_c[32:0]), | |
1904 | .siclk(siclk), | |
1905 | .soclk(soclk) | |
1906 | ); | |
1907 | ||
1908 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w7_reg ( | |
1909 | .scan_in(data_bus_2_w7_reg_scanin[32:0]), | |
1910 | .scan_out(data_bus_2_w7_reg_scanout[32:0]), | |
1911 | .l1clk(l1clk_q2_out), | |
1912 | .din(rd_data_w7_i6_or_i2[32:0]), | |
1913 | .dout(data_bus_2_w7_c[32:0]), | |
1914 | .siclk(siclk), | |
1915 | .soclk(soclk) | |
1916 | ); | |
1917 | ||
1918 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w7_reg ( | |
1919 | .scan_in(data_bus_3_w7_reg_scanin[32:0]), | |
1920 | .scan_out(data_bus_3_w7_reg_scanout[32:0]), | |
1921 | .l1clk(l1clk_q3_out), | |
1922 | .din(rd_data_w7_i7_or_i3[32:0]), | |
1923 | .dout(data_bus_3_w7_c[32:0]), | |
1924 | .siclk(siclk), | |
1925 | .soclk(soclk) | |
1926 | ); | |
1927 | ////////////////////////////////////////////////////////////////////////// | |
1928 | // Muxing ALL ways to get instr 0,1,2,3 based on the way select from // | |
1929 | // Icache tags and TLB. // | |
1930 | // NOTE: These instructions are unordered. // | |
1931 | ////////////////////////////////////////////////////////////////////////// | |
1932 | ||
1933 | ||
1934 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_8__stack_50c__width_33 bus_0_mux ( | |
1935 | .din0({data_bus_0_w0_c[32],data_bus_0_w0_c[31:0]}), | |
1936 | .din1({data_bus_0_w1_c[32],data_bus_0_w1_c[31:0]}), | |
1937 | .din2({data_bus_0_w2_c[32],data_bus_0_w2_c[31:0]}), | |
1938 | .din3({data_bus_0_w3_c[32],data_bus_0_w3_c[31:0]}), | |
1939 | .din4({data_bus_0_w4_c[32],data_bus_0_w4_c[31:0]}), | |
1940 | .din5({data_bus_0_w5_c[32],data_bus_0_w5_c[31:0]}), | |
1941 | .din6({data_bus_0_w6_c[32],data_bus_0_w6_c[31:0]}), | |
1942 | .din7({data_bus_0_w7_c[32],data_bus_0_w7_c[31:0]} ), | |
1943 | .sel0 ( muxed_way_sel_c[0]), | |
1944 | .sel1 ( muxed_way_sel_c[1]), | |
1945 | .sel2 ( muxed_way_sel_c[2]), | |
1946 | .sel3 ( muxed_way_sel_c[3]), | |
1947 | .sel4 ( muxed_way_sel_c[4]), | |
1948 | .sel5 ( muxed_way_sel_c[5]), | |
1949 | .sel6 ( muxed_way_sel_c[6]), | |
1950 | .sel7 ( muxed_way_sel_c[7]), | |
1951 | .dout( icd_bus_0_instr_c[32:0] )); | |
1952 | ||
1953 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_8__stack_50c__width_33 bus_1_mux ( | |
1954 | .din0({data_bus_1_w0_c[32],data_bus_1_w0_c[31:0]}), | |
1955 | .din1({data_bus_1_w1_c[32],data_bus_1_w1_c[31:0]}), | |
1956 | .din2({data_bus_1_w2_c[32],data_bus_1_w2_c[31:0]}), | |
1957 | .din3({data_bus_1_w3_c[32],data_bus_1_w3_c[31:0]}), | |
1958 | .din4({data_bus_1_w4_c[32],data_bus_1_w4_c[31:0]}), | |
1959 | .din5({data_bus_1_w5_c[32],data_bus_1_w5_c[31:0]}), | |
1960 | .din6({data_bus_1_w6_c[32],data_bus_1_w6_c[31:0]}), | |
1961 | .din7({data_bus_1_w7_c[32],data_bus_1_w7_c[31:0]} ), | |
1962 | .sel0 ( muxed_way_sel_c[0]), | |
1963 | .sel1 ( muxed_way_sel_c[1]), | |
1964 | .sel2 ( muxed_way_sel_c[2]), | |
1965 | .sel3 ( muxed_way_sel_c[3]), | |
1966 | .sel4 ( muxed_way_sel_c[4]), | |
1967 | .sel5 ( muxed_way_sel_c[5]), | |
1968 | .sel6 ( muxed_way_sel_c[6]), | |
1969 | .sel7 ( muxed_way_sel_c[7]), | |
1970 | .dout( icd_bus_1_instr_c[32:0] )); | |
1971 | ||
1972 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_8__stack_50c__width_33 bus_2_mux ( | |
1973 | .din0({data_bus_2_w0_c[32],data_bus_2_w0_c[31:0]}), | |
1974 | .din1({data_bus_2_w1_c[32],data_bus_2_w1_c[31:0]}), | |
1975 | .din2({data_bus_2_w2_c[32],data_bus_2_w2_c[31:0]}), | |
1976 | .din3({data_bus_2_w3_c[32],data_bus_2_w3_c[31:0]}), | |
1977 | .din4({data_bus_2_w4_c[32],data_bus_2_w4_c[31:0]}), | |
1978 | .din5({data_bus_2_w5_c[32],data_bus_2_w5_c[31:0]}), | |
1979 | .din6({data_bus_2_w6_c[32],data_bus_2_w6_c[31:0]}), | |
1980 | .din7({data_bus_2_w7_c[32],data_bus_2_w7_c[31:0]} ), | |
1981 | .sel0 ( muxed_way_sel_c[0]), | |
1982 | .sel1 ( muxed_way_sel_c[1]), | |
1983 | .sel2 ( muxed_way_sel_c[2]), | |
1984 | .sel3 ( muxed_way_sel_c[3]), | |
1985 | .sel4 ( muxed_way_sel_c[4]), | |
1986 | .sel5 ( muxed_way_sel_c[5]), | |
1987 | .sel6 ( muxed_way_sel_c[6]), | |
1988 | .sel7 ( muxed_way_sel_c[7]), | |
1989 | .dout( icd_bus_2_instr_c[32:0] )); | |
1990 | ||
1991 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_8__stack_50c__width_33 bus_3_mux ( | |
1992 | .din0({data_bus_3_w0_c[32],data_bus_3_w0_c[31:0]}), | |
1993 | .din1({data_bus_3_w1_c[32],data_bus_3_w1_c[31:0]}), | |
1994 | .din2({data_bus_3_w2_c[32],data_bus_3_w2_c[31:0]}), | |
1995 | .din3({data_bus_3_w3_c[32],data_bus_3_w3_c[31:0]}), | |
1996 | .din4({data_bus_3_w4_c[32],data_bus_3_w4_c[31:0]}), | |
1997 | .din5({data_bus_3_w5_c[32],data_bus_3_w5_c[31:0]}), | |
1998 | .din6({data_bus_3_w6_c[32],data_bus_3_w6_c[31:0]}), | |
1999 | .din7({data_bus_3_w7_c[32],data_bus_3_w7_c[31:0]} ), | |
2000 | .sel0 ( muxed_way_sel_c[0]), | |
2001 | .sel1 ( muxed_way_sel_c[1]), | |
2002 | .sel2 ( muxed_way_sel_c[2]), | |
2003 | .sel3 ( muxed_way_sel_c[3]), | |
2004 | .sel4 ( muxed_way_sel_c[4]), | |
2005 | .sel5 ( muxed_way_sel_c[5]), | |
2006 | .sel6 ( muxed_way_sel_c[6]), | |
2007 | .sel7 ( muxed_way_sel_c[7]), | |
2008 | .dout( icd_bus_3_instr_c[32:0] )); | |
2009 | //////////////////////////////////////////////////////////// | |
2010 | // Redunduncy Data out muxing // | |
2011 | //////////////////////////////////////////////////////////// | |
2012 | ||
2013 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_7 red_data_out_mux0 ( | |
2014 | .din0 ({reg_d_q0_w7_w4_lft_d[4:0],reg_d_q0_w7_w4_lft_en[1:0]}), | |
2015 | .din1 ({reg_d_q0_w7_w4_rgt_d[4:0],reg_d_q0_w7_w4_rgt_en[1:0]}), | |
2016 | .din2 ({reg_d_q0_w3_w0_lft_d[4:0],reg_d_q0_w3_w0_lft_en[1:0]}), | |
2017 | .din3 ({reg_d_q0_w3_w0_rgt_d[4:0],reg_d_q0_w3_w0_rgt_en[1:0]}), | |
2018 | .din4 ({reg_d_q1_w7_w4_lft_d[4:0],reg_d_q1_w7_w4_lft_en[1:0]}), | |
2019 | .din5 ({reg_d_q1_w7_w4_rgt_d[4:0],reg_d_q1_w7_w4_rgt_en[1:0]}), | |
2020 | .din6 ({reg_d_q1_w3_w0_lft_d[4:0],reg_d_q1_w3_w0_lft_en[1:0]}), | |
2021 | .din7 ({reg_d_q1_w3_w0_rgt_d[4:0],reg_d_q1_w3_w0_rgt_en[1:0]}), | |
2022 | .sel (rid_ff[2:0]), | |
2023 | .dout ({reg_d_out_mux_0[4:0],reg_en_out_mux_0[1:0]}) | |
2024 | ); | |
2025 | ||
2026 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_7 red_data_out_mux1 ( | |
2027 | .din0 ({reg_d_q2_w7_w4_lft_d[4:0],reg_d_q2_w7_w4_lft_en[1:0]}), | |
2028 | .din1 ({reg_d_q2_w7_w4_rgt_d[4:0],reg_d_q2_w7_w4_rgt_en[1:0]}), | |
2029 | .din2 ({reg_d_q2_w3_w0_lft_d[4:0],reg_d_q2_w3_w0_lft_en[1:0]}), | |
2030 | .din3 ({reg_d_q2_w3_w0_rgt_d[4:0],reg_d_q2_w3_w0_rgt_en[1:0]}), | |
2031 | .din4 ({reg_d_q3_w7_w4_lft_d[4:0],reg_d_q3_w7_w4_lft_en[1:0]}), | |
2032 | .din5 ({reg_d_q3_w7_w4_rgt_d[4:0],reg_d_q3_w7_w4_rgt_en[1:0]}), | |
2033 | .din6 ({reg_d_q3_w3_w0_lft_d[4:0],reg_d_q3_w3_w0_lft_en[1:0]}), | |
2034 | .din7 ({reg_d_q3_w3_w0_rgt_d[4:0],reg_d_q3_w3_w0_rgt_en[1:0]}), | |
2035 | .sel (rid_ff[2:0]), | |
2036 | .dout ({reg_d_out_mux_1[4:0],reg_en_out_mux_1[1:0]}) | |
2037 | ); | |
2038 | ||
2039 | n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__width_7 red_data_out_mux2 ( | |
2040 | .din0 ({reg_d_out_mux_1[4:0],reg_en_out_mux_1[1:0]}), | |
2041 | .din1 ({reg_d_out_mux_0[4:0],reg_en_out_mux_0[1:0]}), | |
2042 | .sel0 (rid_ff[3]), | |
2043 | .dout ({red_mux_d_out[4:0],red_mux_en_out[1:0]}) | |
2044 | ); | |
2045 | ||
2046 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_5 red_d_out_reg ( | |
2047 | .scan_in(red_d_out_reg_scanin[4:0]), | |
2048 | .scan_out(red_d_out_reg_scanout[4:0]), | |
2049 | .l1clk(l1clk_red_out), | |
2050 | .din(red_mux_d_out[4:0]), | |
2051 | .dout(red_d_out[4:0]), | |
2052 | .siclk(siclk), | |
2053 | .soclk(soclk) | |
2054 | ); | |
2055 | ||
2056 | ||
2057 | n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_2 red_en_out_reg ( | |
2058 | .scan_in(red_en_out_reg_scanin[1:0]), | |
2059 | .scan_out(red_en_out_reg_scanout[1:0]), | |
2060 | .l1clk(l1clk_red_out), | |
2061 | .din(red_mux_en_out[1:0]), | |
2062 | .dout(red_en_out[1:0]), | |
2063 | .siclk(siclk), | |
2064 | .soclk(soclk) | |
2065 | ); | |
2066 | ||
2067 | ||
2068 | supply0 vss; | |
2069 | supply1 vdd; | |
2070 | ||
2071 | assign ftp_access_f_reg_scanin[0]=scan_in; | |
2072 | assign ftp_access_c_reg_scanin[0]=ftp_access_f_reg_scanout; | |
2073 | assign ftp_access_c_dum_scanin=ftp_access_c_reg_scanout[0]; | |
2074 | assign wrdata_q1_5_scanin[32]=ftp_access_c_dum_scanout; | |
2075 | assign wrdata_q1_1_scanin[32]=wrdata_q1_5_scanout[32]; | |
2076 | assign wrdata_q1_5_scanin[31]=wrdata_q1_1_scanout[32]; | |
2077 | assign wrdata_q1_1_scanin[31]=wrdata_q1_5_scanout[31]; | |
2078 | assign wrdata_q1_5_scanin[30]=wrdata_q1_1_scanout[31]; | |
2079 | assign wrdata_q1_1_scanin[30]=wrdata_q1_5_scanout[30]; | |
2080 | assign wrdata_q1_5_scanin[29]=wrdata_q1_1_scanout[30]; | |
2081 | assign wrdata_q1_1_scanin[29]=wrdata_q1_5_scanout[29]; | |
2082 | assign wrdata_q1_5_scanin[28]=wrdata_q1_1_scanout[29]; | |
2083 | assign wrdata_q1_1_scanin[28]=wrdata_q1_5_scanout[28]; | |
2084 | assign wrdata_q1_5_scanin[27]=wrdata_q1_1_scanout[28]; | |
2085 | assign wrdata_q1_1_scanin[27]=wrdata_q1_5_scanout[27]; | |
2086 | assign wrdata_q1_5_scanin[26]=wrdata_q1_1_scanout[27]; | |
2087 | assign wrdata_q1_1_scanin[26]=wrdata_q1_5_scanout[26]; | |
2088 | assign wrdata_q1_5_scanin[25]=wrdata_q1_1_scanout[26]; | |
2089 | assign wrdata_q1_1_scanin[25]=wrdata_q1_5_scanout[25]; | |
2090 | assign wrdata_q1_5_scanin[24]=wrdata_q1_1_scanout[25]; | |
2091 | assign wrdata_q1_1_scanin[24]=wrdata_q1_5_scanout[24]; | |
2092 | assign wrdata_q1_5_scanin[23]=wrdata_q1_1_scanout[24]; | |
2093 | assign wrdata_q1_1_scanin[23]=wrdata_q1_5_scanout[23]; | |
2094 | assign wrdata_q1_5_scanin[22]=wrdata_q1_1_scanout[23]; | |
2095 | assign wrdata_q1_1_scanin[22]=wrdata_q1_5_scanout[22]; | |
2096 | assign wrdata_q1_5_scanin[21]=wrdata_q1_1_scanout[22]; | |
2097 | assign wrdata_q1_1_scanin[21]=wrdata_q1_5_scanout[21]; | |
2098 | assign wrdata_q1_5_scanin[20]=wrdata_q1_1_scanout[21]; | |
2099 | assign wrdata_q1_1_scanin[20]=wrdata_q1_5_scanout[20]; | |
2100 | assign wrdata_q1_5_scanin[19]=wrdata_q1_1_scanout[20]; | |
2101 | assign wrdata_q1_1_scanin[19]=wrdata_q1_5_scanout[19]; | |
2102 | assign wrdata_q1_5_scanin[18]=wrdata_q1_1_scanout[19]; | |
2103 | assign wrdata_q1_1_scanin[18]=wrdata_q1_5_scanout[18]; | |
2104 | assign wrdata_q1_5_scanin[17]=wrdata_q1_1_scanout[18]; | |
2105 | assign wrdata_q1_1_scanin[17]=wrdata_q1_5_scanout[17]; | |
2106 | assign wrdata_q1_5_scanin[16]=wrdata_q1_1_scanout[17]; | |
2107 | assign wrdata_q1_1_scanin[16]=wrdata_q1_5_scanout[16]; | |
2108 | assign wrdata_q1_5_scanin[15]=wrdata_q1_1_scanout[16]; | |
2109 | assign wrdata_q1_1_scanin[15]=wrdata_q1_5_scanout[15]; | |
2110 | assign wrdata_q1_5_scanin[14]=wrdata_q1_1_scanout[15]; | |
2111 | assign wrdata_q1_1_scanin[14]=wrdata_q1_5_scanout[14]; | |
2112 | assign wrdata_q1_5_scanin[13]=wrdata_q1_1_scanout[14]; | |
2113 | assign wrdata_q1_1_scanin[13]=wrdata_q1_5_scanout[13]; | |
2114 | assign wrdata_q1_5_scanin[12]=wrdata_q1_1_scanout[13]; | |
2115 | assign wrdata_q1_1_scanin[12]=wrdata_q1_5_scanout[12]; | |
2116 | assign wrdata_q1_5_scanin[11]=wrdata_q1_1_scanout[12]; | |
2117 | assign wrdata_q1_1_scanin[11]=wrdata_q1_5_scanout[11]; | |
2118 | assign wrdata_q1_5_scanin[10]=wrdata_q1_1_scanout[11]; | |
2119 | assign wrdata_q1_1_scanin[10]=wrdata_q1_5_scanout[10]; | |
2120 | assign wrdata_q1_5_scanin[9]=wrdata_q1_1_scanout[10]; | |
2121 | assign wrdata_q1_1_scanin[9]=wrdata_q1_5_scanout[9]; | |
2122 | assign wrdata_q1_5_scanin[8]=wrdata_q1_1_scanout[9]; | |
2123 | assign wrdata_q1_1_scanin[8]=wrdata_q1_5_scanout[8]; | |
2124 | assign wrdata_q1_5_scanin[7]=wrdata_q1_1_scanout[8]; | |
2125 | assign wrdata_q1_1_scanin[7]=wrdata_q1_5_scanout[7]; | |
2126 | assign wrdata_q1_5_scanin[6]=wrdata_q1_1_scanout[7]; | |
2127 | assign wrdata_q1_1_scanin[6]=wrdata_q1_5_scanout[6]; | |
2128 | assign wrdata_q1_5_scanin[5]=wrdata_q1_1_scanout[6]; | |
2129 | assign wrdata_q1_1_scanin[5]=wrdata_q1_5_scanout[5]; | |
2130 | assign wrdata_q1_5_scanin[4]=wrdata_q1_1_scanout[5]; | |
2131 | assign wrdata_q1_1_scanin[4]=wrdata_q1_5_scanout[4]; | |
2132 | assign wrdata_q1_5_scanin[3]=wrdata_q1_1_scanout[4]; | |
2133 | assign wrdata_q1_1_scanin[3]=wrdata_q1_5_scanout[3]; | |
2134 | assign wrdata_q1_5_scanin[2]=wrdata_q1_1_scanout[3]; | |
2135 | assign wrdata_q1_1_scanin[2]=wrdata_q1_5_scanout[2]; | |
2136 | assign wrdata_q1_5_scanin[1]=wrdata_q1_1_scanout[2]; | |
2137 | assign wrdata_q1_1_scanin[1]=wrdata_q1_5_scanout[1]; | |
2138 | assign wrdata_q1_5_scanin[0]=wrdata_q1_1_scanout[1]; | |
2139 | assign wrdata_q1_1_scanin[0]=wrdata_q1_5_scanout[0]; | |
2140 | ||
2141 | ||
2142 | // ***************************BEGIN SECTION************************* | |
2143 | ||
2144 | assign data_bus_1_w2_reg_scanin[32]=wrdata_q1_1_scanout[0]; | |
2145 | assign data_bus_1_w3_reg_scanin[32]=data_bus_1_w2_reg_scanout[32]; | |
2146 | assign data_bus_1_w6_reg_scanin[32]=data_bus_1_w3_reg_scanout[32]; | |
2147 | assign data_bus_1_w7_reg_scanin[32]=data_bus_1_w6_reg_scanout[32]; | |
2148 | assign data_bus_1_w0_reg_scanin[32]=data_bus_1_w7_reg_scanout[32]; | |
2149 | assign data_bus_1_w1_reg_scanin[32]=data_bus_1_w0_reg_scanout[32]; | |
2150 | assign data_bus_1_w4_reg_scanin[32]=data_bus_1_w1_reg_scanout[32]; | |
2151 | assign data_bus_1_w5_reg_scanin[32]=data_bus_1_w4_reg_scanout[32]; | |
2152 | ||
2153 | assign data_bus_1_w2_reg_scanin[31]=data_bus_1_w5_reg_scanout[32]; | |
2154 | assign data_bus_1_w3_reg_scanin[31]=data_bus_1_w2_reg_scanout[31]; | |
2155 | assign data_bus_1_w6_reg_scanin[31]=data_bus_1_w3_reg_scanout[31]; | |
2156 | assign data_bus_1_w7_reg_scanin[31]=data_bus_1_w6_reg_scanout[31]; | |
2157 | assign data_bus_1_w0_reg_scanin[31]=data_bus_1_w7_reg_scanout[31]; | |
2158 | assign data_bus_1_w1_reg_scanin[31]=data_bus_1_w0_reg_scanout[31]; | |
2159 | assign data_bus_1_w4_reg_scanin[31]=data_bus_1_w1_reg_scanout[31]; | |
2160 | assign data_bus_1_w5_reg_scanin[31]=data_bus_1_w4_reg_scanout[31]; | |
2161 | ||
2162 | assign data_bus_1_w2_reg_scanin[30]=data_bus_1_w5_reg_scanout[31]; | |
2163 | assign data_bus_1_w3_reg_scanin[30]=data_bus_1_w2_reg_scanout[30]; | |
2164 | assign data_bus_1_w6_reg_scanin[30]=data_bus_1_w3_reg_scanout[30]; | |
2165 | assign data_bus_1_w7_reg_scanin[30]=data_bus_1_w6_reg_scanout[30]; | |
2166 | assign data_bus_1_w0_reg_scanin[30]=data_bus_1_w7_reg_scanout[30]; | |
2167 | assign data_bus_1_w1_reg_scanin[30]=data_bus_1_w0_reg_scanout[30]; | |
2168 | assign data_bus_1_w4_reg_scanin[30]=data_bus_1_w1_reg_scanout[30]; | |
2169 | assign data_bus_1_w5_reg_scanin[30]=data_bus_1_w4_reg_scanout[30]; | |
2170 | ||
2171 | assign data_bus_1_w2_reg_scanin[29]=data_bus_1_w5_reg_scanout[30]; | |
2172 | assign data_bus_1_w3_reg_scanin[29]=data_bus_1_w2_reg_scanout[29]; | |
2173 | assign data_bus_1_w6_reg_scanin[29]=data_bus_1_w3_reg_scanout[29]; | |
2174 | assign data_bus_1_w7_reg_scanin[29]=data_bus_1_w6_reg_scanout[29]; | |
2175 | assign data_bus_1_w0_reg_scanin[29]=data_bus_1_w7_reg_scanout[29]; | |
2176 | assign data_bus_1_w1_reg_scanin[29]=data_bus_1_w0_reg_scanout[29]; | |
2177 | assign data_bus_1_w4_reg_scanin[29]=data_bus_1_w1_reg_scanout[29]; | |
2178 | assign data_bus_1_w5_reg_scanin[29]=data_bus_1_w4_reg_scanout[29]; | |
2179 | ||
2180 | assign data_bus_1_w2_reg_scanin[28]=data_bus_1_w5_reg_scanout[29]; | |
2181 | assign data_bus_1_w3_reg_scanin[28]=data_bus_1_w2_reg_scanout[28]; | |
2182 | assign data_bus_1_w6_reg_scanin[28]=data_bus_1_w3_reg_scanout[28]; | |
2183 | assign data_bus_1_w7_reg_scanin[28]=data_bus_1_w6_reg_scanout[28]; | |
2184 | assign data_bus_1_w0_reg_scanin[28]=data_bus_1_w7_reg_scanout[28]; | |
2185 | assign data_bus_1_w1_reg_scanin[28]=data_bus_1_w0_reg_scanout[28]; | |
2186 | assign data_bus_1_w4_reg_scanin[28]=data_bus_1_w1_reg_scanout[28]; | |
2187 | assign data_bus_1_w5_reg_scanin[28]=data_bus_1_w4_reg_scanout[28]; | |
2188 | ||
2189 | assign data_bus_1_w2_reg_scanin[27]=data_bus_1_w5_reg_scanout[28]; | |
2190 | assign data_bus_1_w3_reg_scanin[27]=data_bus_1_w2_reg_scanout[27]; | |
2191 | assign data_bus_1_w6_reg_scanin[27]=data_bus_1_w3_reg_scanout[27]; | |
2192 | assign data_bus_1_w7_reg_scanin[27]=data_bus_1_w6_reg_scanout[27]; | |
2193 | assign data_bus_1_w0_reg_scanin[27]=data_bus_1_w7_reg_scanout[27]; | |
2194 | assign data_bus_1_w1_reg_scanin[27]=data_bus_1_w0_reg_scanout[27]; | |
2195 | assign data_bus_1_w4_reg_scanin[27]=data_bus_1_w1_reg_scanout[27]; | |
2196 | assign data_bus_1_w5_reg_scanin[27]=data_bus_1_w4_reg_scanout[27]; | |
2197 | ||
2198 | assign data_bus_1_w2_reg_scanin[26]=data_bus_1_w5_reg_scanout[27]; | |
2199 | assign data_bus_1_w3_reg_scanin[26]=data_bus_1_w2_reg_scanout[26]; | |
2200 | assign data_bus_1_w6_reg_scanin[26]=data_bus_1_w3_reg_scanout[26]; | |
2201 | assign data_bus_1_w7_reg_scanin[26]=data_bus_1_w6_reg_scanout[26]; | |
2202 | assign data_bus_1_w0_reg_scanin[26]=data_bus_1_w7_reg_scanout[26]; | |
2203 | assign data_bus_1_w1_reg_scanin[26]=data_bus_1_w0_reg_scanout[26]; | |
2204 | assign data_bus_1_w4_reg_scanin[26]=data_bus_1_w1_reg_scanout[26]; | |
2205 | assign data_bus_1_w5_reg_scanin[26]=data_bus_1_w4_reg_scanout[26]; | |
2206 | ||
2207 | assign data_bus_1_w2_reg_scanin[25]=data_bus_1_w5_reg_scanout[26]; | |
2208 | assign data_bus_1_w3_reg_scanin[25]=data_bus_1_w2_reg_scanout[25]; | |
2209 | assign data_bus_1_w6_reg_scanin[25]=data_bus_1_w3_reg_scanout[25]; | |
2210 | assign data_bus_1_w7_reg_scanin[25]=data_bus_1_w6_reg_scanout[25]; | |
2211 | assign data_bus_1_w0_reg_scanin[25]=data_bus_1_w7_reg_scanout[25]; | |
2212 | assign data_bus_1_w1_reg_scanin[25]=data_bus_1_w0_reg_scanout[25]; | |
2213 | assign data_bus_1_w4_reg_scanin[25]=data_bus_1_w1_reg_scanout[25]; | |
2214 | assign data_bus_1_w5_reg_scanin[25]=data_bus_1_w4_reg_scanout[25]; | |
2215 | ||
2216 | assign data_bus_1_w2_reg_scanin[24]=data_bus_1_w5_reg_scanout[25]; | |
2217 | assign data_bus_1_w3_reg_scanin[24]=data_bus_1_w2_reg_scanout[24]; | |
2218 | assign data_bus_1_w6_reg_scanin[24]=data_bus_1_w3_reg_scanout[24]; | |
2219 | assign data_bus_1_w7_reg_scanin[24]=data_bus_1_w6_reg_scanout[24]; | |
2220 | assign data_bus_1_w0_reg_scanin[24]=data_bus_1_w7_reg_scanout[24]; | |
2221 | assign data_bus_1_w1_reg_scanin[24]=data_bus_1_w0_reg_scanout[24]; | |
2222 | assign data_bus_1_w4_reg_scanin[24]=data_bus_1_w1_reg_scanout[24]; | |
2223 | assign data_bus_1_w5_reg_scanin[24]=data_bus_1_w4_reg_scanout[24]; | |
2224 | ||
2225 | assign data_bus_1_w2_reg_scanin[23]=data_bus_1_w5_reg_scanout[24]; | |
2226 | assign data_bus_1_w3_reg_scanin[23]=data_bus_1_w2_reg_scanout[23]; | |
2227 | assign data_bus_1_w6_reg_scanin[23]=data_bus_1_w3_reg_scanout[23]; | |
2228 | assign data_bus_1_w7_reg_scanin[23]=data_bus_1_w6_reg_scanout[23]; | |
2229 | assign data_bus_1_w0_reg_scanin[23]=data_bus_1_w7_reg_scanout[23]; | |
2230 | assign data_bus_1_w1_reg_scanin[23]=data_bus_1_w0_reg_scanout[23]; | |
2231 | assign data_bus_1_w4_reg_scanin[23]=data_bus_1_w1_reg_scanout[23]; | |
2232 | assign data_bus_1_w5_reg_scanin[23]=data_bus_1_w4_reg_scanout[23]; | |
2233 | ||
2234 | assign data_bus_1_w2_reg_scanin[22]=data_bus_1_w5_reg_scanout[23]; | |
2235 | assign data_bus_1_w3_reg_scanin[22]=data_bus_1_w2_reg_scanout[22]; | |
2236 | assign data_bus_1_w6_reg_scanin[22]=data_bus_1_w3_reg_scanout[22]; | |
2237 | assign data_bus_1_w7_reg_scanin[22]=data_bus_1_w6_reg_scanout[22]; | |
2238 | assign data_bus_1_w0_reg_scanin[22]=data_bus_1_w7_reg_scanout[22]; | |
2239 | assign data_bus_1_w1_reg_scanin[22]=data_bus_1_w0_reg_scanout[22]; | |
2240 | assign data_bus_1_w4_reg_scanin[22]=data_bus_1_w1_reg_scanout[22]; | |
2241 | assign data_bus_1_w5_reg_scanin[22]=data_bus_1_w4_reg_scanout[22]; | |
2242 | ||
2243 | assign data_bus_1_w2_reg_scanin[21]=data_bus_1_w5_reg_scanout[22]; | |
2244 | assign data_bus_1_w3_reg_scanin[21]=data_bus_1_w2_reg_scanout[21]; | |
2245 | assign data_bus_1_w6_reg_scanin[21]=data_bus_1_w3_reg_scanout[21]; | |
2246 | assign data_bus_1_w7_reg_scanin[21]=data_bus_1_w6_reg_scanout[21]; | |
2247 | assign data_bus_1_w0_reg_scanin[21]=data_bus_1_w7_reg_scanout[21]; | |
2248 | assign data_bus_1_w1_reg_scanin[21]=data_bus_1_w0_reg_scanout[21]; | |
2249 | assign data_bus_1_w4_reg_scanin[21]=data_bus_1_w1_reg_scanout[21]; | |
2250 | assign data_bus_1_w5_reg_scanin[21]=data_bus_1_w4_reg_scanout[21]; | |
2251 | ||
2252 | assign data_bus_1_w2_reg_scanin[20]=data_bus_1_w5_reg_scanout[21]; | |
2253 | assign data_bus_1_w3_reg_scanin[20]=data_bus_1_w2_reg_scanout[20]; | |
2254 | assign data_bus_1_w6_reg_scanin[20]=data_bus_1_w3_reg_scanout[20]; | |
2255 | assign data_bus_1_w7_reg_scanin[20]=data_bus_1_w6_reg_scanout[20]; | |
2256 | assign data_bus_1_w0_reg_scanin[20]=data_bus_1_w7_reg_scanout[20]; | |
2257 | assign data_bus_1_w1_reg_scanin[20]=data_bus_1_w0_reg_scanout[20]; | |
2258 | assign data_bus_1_w4_reg_scanin[20]=data_bus_1_w1_reg_scanout[20]; | |
2259 | assign data_bus_1_w5_reg_scanin[20]=data_bus_1_w4_reg_scanout[20]; | |
2260 | ||
2261 | assign data_bus_1_w2_reg_scanin[19]=data_bus_1_w5_reg_scanout[20]; | |
2262 | assign data_bus_1_w3_reg_scanin[19]=data_bus_1_w2_reg_scanout[19]; | |
2263 | assign data_bus_1_w6_reg_scanin[19]=data_bus_1_w3_reg_scanout[19]; | |
2264 | assign data_bus_1_w7_reg_scanin[19]=data_bus_1_w6_reg_scanout[19]; | |
2265 | assign data_bus_1_w0_reg_scanin[19]=data_bus_1_w7_reg_scanout[19]; | |
2266 | assign data_bus_1_w1_reg_scanin[19]=data_bus_1_w0_reg_scanout[19]; | |
2267 | assign data_bus_1_w4_reg_scanin[19]=data_bus_1_w1_reg_scanout[19]; | |
2268 | assign data_bus_1_w5_reg_scanin[19]=data_bus_1_w4_reg_scanout[19]; | |
2269 | ||
2270 | assign data_bus_1_w2_reg_scanin[18]=data_bus_1_w5_reg_scanout[19]; | |
2271 | assign data_bus_1_w3_reg_scanin[18]=data_bus_1_w2_reg_scanout[18]; | |
2272 | assign data_bus_1_w6_reg_scanin[18]=data_bus_1_w3_reg_scanout[18]; | |
2273 | assign data_bus_1_w7_reg_scanin[18]=data_bus_1_w6_reg_scanout[18]; | |
2274 | assign data_bus_1_w0_reg_scanin[18]=data_bus_1_w7_reg_scanout[18]; | |
2275 | assign data_bus_1_w1_reg_scanin[18]=data_bus_1_w0_reg_scanout[18]; | |
2276 | assign data_bus_1_w4_reg_scanin[18]=data_bus_1_w1_reg_scanout[18]; | |
2277 | assign data_bus_1_w5_reg_scanin[18]=data_bus_1_w4_reg_scanout[18]; | |
2278 | ||
2279 | assign data_bus_1_w2_reg_scanin[17]=data_bus_1_w5_reg_scanout[18]; | |
2280 | assign data_bus_1_w3_reg_scanin[17]=data_bus_1_w2_reg_scanout[17]; | |
2281 | assign data_bus_1_w6_reg_scanin[17]=data_bus_1_w3_reg_scanout[17]; | |
2282 | assign data_bus_1_w7_reg_scanin[17]=data_bus_1_w6_reg_scanout[17]; | |
2283 | assign data_bus_1_w0_reg_scanin[17]=data_bus_1_w7_reg_scanout[17]; | |
2284 | assign data_bus_1_w1_reg_scanin[17]=data_bus_1_w0_reg_scanout[17]; | |
2285 | assign data_bus_1_w4_reg_scanin[17]=data_bus_1_w1_reg_scanout[17]; | |
2286 | assign data_bus_1_w5_reg_scanin[17]=data_bus_1_w4_reg_scanout[17]; | |
2287 | ||
2288 | assign data_bus_1_w0_reg_scanin[16]=data_bus_1_w5_reg_scanout[17]; | |
2289 | assign data_bus_1_w1_reg_scanin[16]=data_bus_1_w0_reg_scanout[16]; | |
2290 | assign data_bus_1_w4_reg_scanin[16]=data_bus_1_w1_reg_scanout[16]; | |
2291 | assign data_bus_1_w5_reg_scanin[16]=data_bus_1_w4_reg_scanout[16]; | |
2292 | assign data_bus_1_w2_reg_scanin[16]=data_bus_1_w5_reg_scanout[16]; | |
2293 | assign data_bus_1_w3_reg_scanin[16]=data_bus_1_w2_reg_scanout[16]; | |
2294 | assign data_bus_1_w6_reg_scanin[16]=data_bus_1_w3_reg_scanout[16]; | |
2295 | assign data_bus_1_w7_reg_scanin[16]=data_bus_1_w6_reg_scanout[16]; | |
2296 | ||
2297 | assign data_bus_1_w0_reg_scanin[15]=data_bus_1_w7_reg_scanout[16]; | |
2298 | assign data_bus_1_w1_reg_scanin[15]=data_bus_1_w0_reg_scanout[15]; | |
2299 | assign data_bus_1_w4_reg_scanin[15]=data_bus_1_w1_reg_scanout[15]; | |
2300 | assign data_bus_1_w5_reg_scanin[15]=data_bus_1_w4_reg_scanout[15]; | |
2301 | assign data_bus_1_w2_reg_scanin[15]=data_bus_1_w5_reg_scanout[15]; | |
2302 | assign data_bus_1_w3_reg_scanin[15]=data_bus_1_w2_reg_scanout[15]; | |
2303 | assign data_bus_1_w6_reg_scanin[15]=data_bus_1_w3_reg_scanout[15]; | |
2304 | assign data_bus_1_w7_reg_scanin[15]=data_bus_1_w6_reg_scanout[15]; | |
2305 | ||
2306 | assign data_bus_1_w0_reg_scanin[14]=data_bus_1_w7_reg_scanout[15]; | |
2307 | assign data_bus_1_w1_reg_scanin[14]=data_bus_1_w0_reg_scanout[14]; | |
2308 | assign data_bus_1_w4_reg_scanin[14]=data_bus_1_w1_reg_scanout[14]; | |
2309 | assign data_bus_1_w5_reg_scanin[14]=data_bus_1_w4_reg_scanout[14]; | |
2310 | assign data_bus_1_w2_reg_scanin[14]=data_bus_1_w5_reg_scanout[14]; | |
2311 | assign data_bus_1_w3_reg_scanin[14]=data_bus_1_w2_reg_scanout[14]; | |
2312 | assign data_bus_1_w6_reg_scanin[14]=data_bus_1_w3_reg_scanout[14]; | |
2313 | assign data_bus_1_w7_reg_scanin[14]=data_bus_1_w6_reg_scanout[14]; | |
2314 | ||
2315 | assign data_bus_1_w0_reg_scanin[13]=data_bus_1_w7_reg_scanout[14]; | |
2316 | assign data_bus_1_w1_reg_scanin[13]=data_bus_1_w0_reg_scanout[13]; | |
2317 | assign data_bus_1_w4_reg_scanin[13]=data_bus_1_w1_reg_scanout[13]; | |
2318 | assign data_bus_1_w5_reg_scanin[13]=data_bus_1_w4_reg_scanout[13]; | |
2319 | assign data_bus_1_w2_reg_scanin[13]=data_bus_1_w5_reg_scanout[13]; | |
2320 | assign data_bus_1_w3_reg_scanin[13]=data_bus_1_w2_reg_scanout[13]; | |
2321 | assign data_bus_1_w6_reg_scanin[13]=data_bus_1_w3_reg_scanout[13]; | |
2322 | assign data_bus_1_w7_reg_scanin[13]=data_bus_1_w6_reg_scanout[13]; | |
2323 | ||
2324 | assign data_bus_1_w0_reg_scanin[12]=data_bus_1_w7_reg_scanout[13]; | |
2325 | assign data_bus_1_w1_reg_scanin[12]=data_bus_1_w0_reg_scanout[12]; | |
2326 | assign data_bus_1_w4_reg_scanin[12]=data_bus_1_w1_reg_scanout[12]; | |
2327 | assign data_bus_1_w5_reg_scanin[12]=data_bus_1_w4_reg_scanout[12]; | |
2328 | assign data_bus_1_w2_reg_scanin[12]=data_bus_1_w5_reg_scanout[12]; | |
2329 | assign data_bus_1_w3_reg_scanin[12]=data_bus_1_w2_reg_scanout[12]; | |
2330 | assign data_bus_1_w6_reg_scanin[12]=data_bus_1_w3_reg_scanout[12]; | |
2331 | assign data_bus_1_w7_reg_scanin[12]=data_bus_1_w6_reg_scanout[12]; | |
2332 | ||
2333 | assign data_bus_1_w0_reg_scanin[11]=data_bus_1_w7_reg_scanout[12]; | |
2334 | assign data_bus_1_w1_reg_scanin[11]=data_bus_1_w0_reg_scanout[11]; | |
2335 | assign data_bus_1_w4_reg_scanin[11]=data_bus_1_w1_reg_scanout[11]; | |
2336 | assign data_bus_1_w5_reg_scanin[11]=data_bus_1_w4_reg_scanout[11]; | |
2337 | assign data_bus_1_w2_reg_scanin[11]=data_bus_1_w5_reg_scanout[11]; | |
2338 | assign data_bus_1_w3_reg_scanin[11]=data_bus_1_w2_reg_scanout[11]; | |
2339 | assign data_bus_1_w6_reg_scanin[11]=data_bus_1_w3_reg_scanout[11]; | |
2340 | assign data_bus_1_w7_reg_scanin[11]=data_bus_1_w6_reg_scanout[11]; | |
2341 | ||
2342 | assign data_bus_1_w0_reg_scanin[10]=data_bus_1_w7_reg_scanout[11]; | |
2343 | assign data_bus_1_w1_reg_scanin[10]=data_bus_1_w0_reg_scanout[10]; | |
2344 | assign data_bus_1_w4_reg_scanin[10]=data_bus_1_w1_reg_scanout[10]; | |
2345 | assign data_bus_1_w5_reg_scanin[10]=data_bus_1_w4_reg_scanout[10]; | |
2346 | assign data_bus_1_w2_reg_scanin[10]=data_bus_1_w5_reg_scanout[10]; | |
2347 | assign data_bus_1_w3_reg_scanin[10]=data_bus_1_w2_reg_scanout[10]; | |
2348 | assign data_bus_1_w6_reg_scanin[10]=data_bus_1_w3_reg_scanout[10]; | |
2349 | assign data_bus_1_w7_reg_scanin[10]=data_bus_1_w6_reg_scanout[10]; | |
2350 | ||
2351 | assign data_bus_1_w0_reg_scanin[9]=data_bus_1_w7_reg_scanout[10]; | |
2352 | assign data_bus_1_w1_reg_scanin[9]=data_bus_1_w0_reg_scanout[9]; | |
2353 | assign data_bus_1_w4_reg_scanin[9]=data_bus_1_w1_reg_scanout[9]; | |
2354 | assign data_bus_1_w5_reg_scanin[9]=data_bus_1_w4_reg_scanout[9]; | |
2355 | assign data_bus_1_w2_reg_scanin[9]=data_bus_1_w5_reg_scanout[9]; | |
2356 | assign data_bus_1_w3_reg_scanin[9]=data_bus_1_w2_reg_scanout[9]; | |
2357 | assign data_bus_1_w6_reg_scanin[9]=data_bus_1_w3_reg_scanout[9]; | |
2358 | assign data_bus_1_w7_reg_scanin[9]=data_bus_1_w6_reg_scanout[9]; | |
2359 | ||
2360 | assign data_bus_1_w0_reg_scanin[8]=data_bus_1_w7_reg_scanout[9]; | |
2361 | assign data_bus_1_w1_reg_scanin[8]=data_bus_1_w0_reg_scanout[8]; | |
2362 | assign data_bus_1_w4_reg_scanin[8]=data_bus_1_w1_reg_scanout[8]; | |
2363 | assign data_bus_1_w5_reg_scanin[8]=data_bus_1_w4_reg_scanout[8]; | |
2364 | assign data_bus_1_w2_reg_scanin[8]=data_bus_1_w5_reg_scanout[8]; | |
2365 | assign data_bus_1_w3_reg_scanin[8]=data_bus_1_w2_reg_scanout[8]; | |
2366 | assign data_bus_1_w6_reg_scanin[8]=data_bus_1_w3_reg_scanout[8]; | |
2367 | assign data_bus_1_w7_reg_scanin[8]=data_bus_1_w6_reg_scanout[8]; | |
2368 | ||
2369 | assign data_bus_1_w0_reg_scanin[7]=data_bus_1_w7_reg_scanout[8]; | |
2370 | assign data_bus_1_w1_reg_scanin[7]=data_bus_1_w0_reg_scanout[7]; | |
2371 | assign data_bus_1_w4_reg_scanin[7]=data_bus_1_w1_reg_scanout[7]; | |
2372 | assign data_bus_1_w5_reg_scanin[7]=data_bus_1_w4_reg_scanout[7]; | |
2373 | assign data_bus_1_w2_reg_scanin[7]=data_bus_1_w5_reg_scanout[7]; | |
2374 | assign data_bus_1_w3_reg_scanin[7]=data_bus_1_w2_reg_scanout[7]; | |
2375 | assign data_bus_1_w6_reg_scanin[7]=data_bus_1_w3_reg_scanout[7]; | |
2376 | assign data_bus_1_w7_reg_scanin[7]=data_bus_1_w6_reg_scanout[7]; | |
2377 | ||
2378 | assign data_bus_1_w0_reg_scanin[6]=data_bus_1_w7_reg_scanout[7]; | |
2379 | assign data_bus_1_w1_reg_scanin[6]=data_bus_1_w0_reg_scanout[6]; | |
2380 | assign data_bus_1_w4_reg_scanin[6]=data_bus_1_w1_reg_scanout[6]; | |
2381 | assign data_bus_1_w5_reg_scanin[6]=data_bus_1_w4_reg_scanout[6]; | |
2382 | assign data_bus_1_w2_reg_scanin[6]=data_bus_1_w5_reg_scanout[6]; | |
2383 | assign data_bus_1_w3_reg_scanin[6]=data_bus_1_w2_reg_scanout[6]; | |
2384 | assign data_bus_1_w6_reg_scanin[6]=data_bus_1_w3_reg_scanout[6]; | |
2385 | assign data_bus_1_w7_reg_scanin[6]=data_bus_1_w6_reg_scanout[6]; | |
2386 | ||
2387 | assign data_bus_1_w0_reg_scanin[5]=data_bus_1_w7_reg_scanout[6]; | |
2388 | assign data_bus_1_w1_reg_scanin[5]=data_bus_1_w0_reg_scanout[5]; | |
2389 | assign data_bus_1_w4_reg_scanin[5]=data_bus_1_w1_reg_scanout[5]; | |
2390 | assign data_bus_1_w5_reg_scanin[5]=data_bus_1_w4_reg_scanout[5]; | |
2391 | assign data_bus_1_w2_reg_scanin[5]=data_bus_1_w5_reg_scanout[5]; | |
2392 | assign data_bus_1_w3_reg_scanin[5]=data_bus_1_w2_reg_scanout[5]; | |
2393 | assign data_bus_1_w6_reg_scanin[5]=data_bus_1_w3_reg_scanout[5]; | |
2394 | assign data_bus_1_w7_reg_scanin[5]=data_bus_1_w6_reg_scanout[5]; | |
2395 | ||
2396 | assign data_bus_1_w0_reg_scanin[4]=data_bus_1_w7_reg_scanout[5]; | |
2397 | assign data_bus_1_w1_reg_scanin[4]=data_bus_1_w0_reg_scanout[4]; | |
2398 | assign data_bus_1_w4_reg_scanin[4]=data_bus_1_w1_reg_scanout[4]; | |
2399 | assign data_bus_1_w5_reg_scanin[4]=data_bus_1_w4_reg_scanout[4]; | |
2400 | assign data_bus_1_w2_reg_scanin[4]=data_bus_1_w5_reg_scanout[4]; | |
2401 | assign data_bus_1_w3_reg_scanin[4]=data_bus_1_w2_reg_scanout[4]; | |
2402 | assign data_bus_1_w6_reg_scanin[4]=data_bus_1_w3_reg_scanout[4]; | |
2403 | assign data_bus_1_w7_reg_scanin[4]=data_bus_1_w6_reg_scanout[4]; | |
2404 | ||
2405 | assign data_bus_1_w0_reg_scanin[3]=data_bus_1_w7_reg_scanout[4]; | |
2406 | assign data_bus_1_w1_reg_scanin[3]=data_bus_1_w0_reg_scanout[3]; | |
2407 | assign data_bus_1_w4_reg_scanin[3]=data_bus_1_w1_reg_scanout[3]; | |
2408 | assign data_bus_1_w5_reg_scanin[3]=data_bus_1_w4_reg_scanout[3]; | |
2409 | assign data_bus_1_w2_reg_scanin[3]=data_bus_1_w5_reg_scanout[3]; | |
2410 | assign data_bus_1_w3_reg_scanin[3]=data_bus_1_w2_reg_scanout[3]; | |
2411 | assign data_bus_1_w6_reg_scanin[3]=data_bus_1_w3_reg_scanout[3]; | |
2412 | assign data_bus_1_w7_reg_scanin[3]=data_bus_1_w6_reg_scanout[3]; | |
2413 | ||
2414 | assign data_bus_1_w0_reg_scanin[2]=data_bus_1_w7_reg_scanout[3]; | |
2415 | assign data_bus_1_w1_reg_scanin[2]=data_bus_1_w0_reg_scanout[2]; | |
2416 | assign data_bus_1_w4_reg_scanin[2]=data_bus_1_w1_reg_scanout[2]; | |
2417 | assign data_bus_1_w5_reg_scanin[2]=data_bus_1_w4_reg_scanout[2]; | |
2418 | assign data_bus_1_w2_reg_scanin[2]=data_bus_1_w5_reg_scanout[2]; | |
2419 | assign data_bus_1_w3_reg_scanin[2]=data_bus_1_w2_reg_scanout[2]; | |
2420 | assign data_bus_1_w6_reg_scanin[2]=data_bus_1_w3_reg_scanout[2]; | |
2421 | assign data_bus_1_w7_reg_scanin[2]=data_bus_1_w6_reg_scanout[2]; | |
2422 | ||
2423 | assign data_bus_1_w0_reg_scanin[1]=data_bus_1_w7_reg_scanout[2]; | |
2424 | assign data_bus_1_w1_reg_scanin[1]=data_bus_1_w0_reg_scanout[1]; | |
2425 | assign data_bus_1_w4_reg_scanin[1]=data_bus_1_w1_reg_scanout[1]; | |
2426 | assign data_bus_1_w5_reg_scanin[1]=data_bus_1_w4_reg_scanout[1]; | |
2427 | assign data_bus_1_w2_reg_scanin[1]=data_bus_1_w5_reg_scanout[1]; | |
2428 | assign data_bus_1_w3_reg_scanin[1]=data_bus_1_w2_reg_scanout[1]; | |
2429 | assign data_bus_1_w6_reg_scanin[1]=data_bus_1_w3_reg_scanout[1]; | |
2430 | assign data_bus_1_w7_reg_scanin[1]=data_bus_1_w6_reg_scanout[1]; | |
2431 | ||
2432 | assign data_bus_1_w0_reg_scanin[0]=data_bus_1_w7_reg_scanout[1]; | |
2433 | assign data_bus_1_w1_reg_scanin[0]=data_bus_1_w0_reg_scanout[0]; | |
2434 | assign data_bus_1_w4_reg_scanin[0]=data_bus_1_w1_reg_scanout[0]; | |
2435 | assign data_bus_1_w5_reg_scanin[0]=data_bus_1_w4_reg_scanout[0]; | |
2436 | assign data_bus_1_w2_reg_scanin[0]=data_bus_1_w5_reg_scanout[0]; | |
2437 | assign data_bus_1_w3_reg_scanin[0]=data_bus_1_w2_reg_scanout[0]; | |
2438 | assign data_bus_1_w6_reg_scanin[0]=data_bus_1_w3_reg_scanout[0]; | |
2439 | assign data_bus_1_w7_reg_scanin[0]=data_bus_1_w6_reg_scanout[0]; | |
2440 | ||
2441 | ||
2442 | // ***************************END SECTION*************************** | |
2443 | ||
2444 | assign wrdata_q0_4_scanin[32]=data_bus_1_w7_reg_scanout[0]; | |
2445 | assign wrdata_q0_0_scanin[32]=wrdata_q0_4_scanout[32]; | |
2446 | assign wrdata_q0_4_scanin[31]=wrdata_q0_0_scanout[32]; | |
2447 | assign wrdata_q0_0_scanin[31]=wrdata_q0_4_scanout[31]; | |
2448 | assign wrdata_q0_4_scanin[30]=wrdata_q0_0_scanout[31]; | |
2449 | assign wrdata_q0_0_scanin[30]=wrdata_q0_4_scanout[30]; | |
2450 | assign wrdata_q0_4_scanin[29]=wrdata_q0_0_scanout[30]; | |
2451 | assign wrdata_q0_0_scanin[29]=wrdata_q0_4_scanout[29]; | |
2452 | assign wrdata_q0_4_scanin[28]=wrdata_q0_0_scanout[29]; | |
2453 | assign wrdata_q0_0_scanin[28]=wrdata_q0_4_scanout[28]; | |
2454 | assign wrdata_q0_4_scanin[27]=wrdata_q0_0_scanout[28]; | |
2455 | assign wrdata_q0_0_scanin[27]=wrdata_q0_4_scanout[27]; | |
2456 | assign wrdata_q0_4_scanin[26]=wrdata_q0_0_scanout[27]; | |
2457 | assign wrdata_q0_0_scanin[26]=wrdata_q0_4_scanout[26]; | |
2458 | assign wrdata_q0_4_scanin[25]=wrdata_q0_0_scanout[26]; | |
2459 | assign wrdata_q0_0_scanin[25]=wrdata_q0_4_scanout[25]; | |
2460 | assign wrdata_q0_4_scanin[24]=wrdata_q0_0_scanout[25]; | |
2461 | assign wrdata_q0_0_scanin[24]=wrdata_q0_4_scanout[24]; | |
2462 | assign wrdata_q0_4_scanin[23]=wrdata_q0_0_scanout[24]; | |
2463 | assign wrdata_q0_0_scanin[23]=wrdata_q0_4_scanout[23]; | |
2464 | assign wrdata_q0_4_scanin[22]=wrdata_q0_0_scanout[23]; | |
2465 | assign wrdata_q0_0_scanin[22]=wrdata_q0_4_scanout[22]; | |
2466 | assign wrdata_q0_4_scanin[21]=wrdata_q0_0_scanout[22]; | |
2467 | assign wrdata_q0_0_scanin[21]=wrdata_q0_4_scanout[21]; | |
2468 | assign wrdata_q0_4_scanin[20]=wrdata_q0_0_scanout[21]; | |
2469 | assign wrdata_q0_0_scanin[20]=wrdata_q0_4_scanout[20]; | |
2470 | assign wrdata_q0_4_scanin[19]=wrdata_q0_0_scanout[20]; | |
2471 | assign wrdata_q0_0_scanin[19]=wrdata_q0_4_scanout[19]; | |
2472 | assign wrdata_q0_4_scanin[18]=wrdata_q0_0_scanout[19]; | |
2473 | assign wrdata_q0_0_scanin[18]=wrdata_q0_4_scanout[18]; | |
2474 | assign wrdata_q0_4_scanin[17]=wrdata_q0_0_scanout[18]; | |
2475 | assign wrdata_q0_0_scanin[17]=wrdata_q0_4_scanout[17]; | |
2476 | assign wrdata_q0_4_scanin[16]=wrdata_q0_0_scanout[17]; | |
2477 | assign wrdata_q0_0_scanin[16]=wrdata_q0_4_scanout[16]; | |
2478 | assign wrdata_q0_4_scanin[15]=wrdata_q0_0_scanout[16]; | |
2479 | assign wrdata_q0_0_scanin[15]=wrdata_q0_4_scanout[15]; | |
2480 | assign wrdata_q0_4_scanin[14]=wrdata_q0_0_scanout[15]; | |
2481 | assign wrdata_q0_0_scanin[14]=wrdata_q0_4_scanout[14]; | |
2482 | assign wrdata_q0_4_scanin[13]=wrdata_q0_0_scanout[14]; | |
2483 | assign wrdata_q0_0_scanin[13]=wrdata_q0_4_scanout[13]; | |
2484 | assign wrdata_q0_4_scanin[12]=wrdata_q0_0_scanout[13]; | |
2485 | assign wrdata_q0_0_scanin[12]=wrdata_q0_4_scanout[12]; | |
2486 | assign wrdata_q0_4_scanin[11]=wrdata_q0_0_scanout[12]; | |
2487 | assign wrdata_q0_0_scanin[11]=wrdata_q0_4_scanout[11]; | |
2488 | assign wrdata_q0_4_scanin[10]=wrdata_q0_0_scanout[11]; | |
2489 | assign wrdata_q0_0_scanin[10]=wrdata_q0_4_scanout[10]; | |
2490 | assign wrdata_q0_4_scanin[9]=wrdata_q0_0_scanout[10]; | |
2491 | assign wrdata_q0_0_scanin[9]=wrdata_q0_4_scanout[9]; | |
2492 | assign wrdata_q0_4_scanin[8]=wrdata_q0_0_scanout[9]; | |
2493 | assign wrdata_q0_0_scanin[8]=wrdata_q0_4_scanout[8]; | |
2494 | assign wrdata_q0_4_scanin[7]=wrdata_q0_0_scanout[8]; | |
2495 | assign wrdata_q0_0_scanin[7]=wrdata_q0_4_scanout[7]; | |
2496 | assign wrdata_q0_4_scanin[6]=wrdata_q0_0_scanout[7]; | |
2497 | assign wrdata_q0_0_scanin[6]=wrdata_q0_4_scanout[6]; | |
2498 | assign wrdata_q0_4_scanin[5]=wrdata_q0_0_scanout[6]; | |
2499 | assign wrdata_q0_0_scanin[5]=wrdata_q0_4_scanout[5]; | |
2500 | assign wrdata_q0_4_scanin[4]=wrdata_q0_0_scanout[5]; | |
2501 | assign wrdata_q0_0_scanin[4]=wrdata_q0_4_scanout[4]; | |
2502 | assign wrdata_q0_4_scanin[3]=wrdata_q0_0_scanout[4]; | |
2503 | assign wrdata_q0_0_scanin[3]=wrdata_q0_4_scanout[3]; | |
2504 | assign wrdata_q0_4_scanin[2]=wrdata_q0_0_scanout[3]; | |
2505 | assign wrdata_q0_0_scanin[2]=wrdata_q0_4_scanout[2]; | |
2506 | assign wrdata_q0_4_scanin[1]=wrdata_q0_0_scanout[2]; | |
2507 | assign wrdata_q0_0_scanin[1]=wrdata_q0_4_scanout[1]; | |
2508 | assign wrdata_q0_4_scanin[0]=wrdata_q0_0_scanout[1]; | |
2509 | assign wrdata_q0_0_scanin[0]=wrdata_q0_4_scanout[0]; | |
2510 | ||
2511 | // ***************************BEGIN SECTION************************* | |
2512 | ||
2513 | assign data_bus_0_w2_reg_scanin[32]=wrdata_q0_0_scanout[0]; | |
2514 | assign data_bus_0_w3_reg_scanin[32]=data_bus_0_w2_reg_scanout[32]; | |
2515 | assign data_bus_0_w6_reg_scanin[32]=data_bus_0_w3_reg_scanout[32]; | |
2516 | assign data_bus_0_w7_reg_scanin[32]=data_bus_0_w6_reg_scanout[32]; | |
2517 | assign data_bus_0_w0_reg_scanin[32]=data_bus_0_w7_reg_scanout[32]; | |
2518 | assign data_bus_0_w1_reg_scanin[32]=data_bus_0_w0_reg_scanout[32]; | |
2519 | assign data_bus_0_w4_reg_scanin[32]=data_bus_0_w1_reg_scanout[32]; | |
2520 | assign data_bus_0_w5_reg_scanin[32]=data_bus_0_w4_reg_scanout[32]; | |
2521 | ||
2522 | assign data_bus_0_w2_reg_scanin[31]=data_bus_0_w5_reg_scanout[32]; | |
2523 | assign data_bus_0_w3_reg_scanin[31]=data_bus_0_w2_reg_scanout[31]; | |
2524 | assign data_bus_0_w6_reg_scanin[31]=data_bus_0_w3_reg_scanout[31]; | |
2525 | assign data_bus_0_w7_reg_scanin[31]=data_bus_0_w6_reg_scanout[31]; | |
2526 | assign data_bus_0_w0_reg_scanin[31]=data_bus_0_w7_reg_scanout[31]; | |
2527 | assign data_bus_0_w1_reg_scanin[31]=data_bus_0_w0_reg_scanout[31]; | |
2528 | assign data_bus_0_w4_reg_scanin[31]=data_bus_0_w1_reg_scanout[31]; | |
2529 | assign data_bus_0_w5_reg_scanin[31]=data_bus_0_w4_reg_scanout[31]; | |
2530 | ||
2531 | assign data_bus_0_w2_reg_scanin[30]=data_bus_0_w5_reg_scanout[31]; | |
2532 | assign data_bus_0_w3_reg_scanin[30]=data_bus_0_w2_reg_scanout[30]; | |
2533 | assign data_bus_0_w6_reg_scanin[30]=data_bus_0_w3_reg_scanout[30]; | |
2534 | assign data_bus_0_w7_reg_scanin[30]=data_bus_0_w6_reg_scanout[30]; | |
2535 | assign data_bus_0_w0_reg_scanin[30]=data_bus_0_w7_reg_scanout[30]; | |
2536 | assign data_bus_0_w1_reg_scanin[30]=data_bus_0_w0_reg_scanout[30]; | |
2537 | assign data_bus_0_w4_reg_scanin[30]=data_bus_0_w1_reg_scanout[30]; | |
2538 | assign data_bus_0_w5_reg_scanin[30]=data_bus_0_w4_reg_scanout[30]; | |
2539 | ||
2540 | assign data_bus_0_w2_reg_scanin[29]=data_bus_0_w5_reg_scanout[30]; | |
2541 | assign data_bus_0_w3_reg_scanin[29]=data_bus_0_w2_reg_scanout[29]; | |
2542 | assign data_bus_0_w6_reg_scanin[29]=data_bus_0_w3_reg_scanout[29]; | |
2543 | assign data_bus_0_w7_reg_scanin[29]=data_bus_0_w6_reg_scanout[29]; | |
2544 | assign data_bus_0_w0_reg_scanin[29]=data_bus_0_w7_reg_scanout[29]; | |
2545 | assign data_bus_0_w1_reg_scanin[29]=data_bus_0_w0_reg_scanout[29]; | |
2546 | assign data_bus_0_w4_reg_scanin[29]=data_bus_0_w1_reg_scanout[29]; | |
2547 | assign data_bus_0_w5_reg_scanin[29]=data_bus_0_w4_reg_scanout[29]; | |
2548 | ||
2549 | assign data_bus_0_w2_reg_scanin[28]=data_bus_0_w5_reg_scanout[29]; | |
2550 | assign data_bus_0_w3_reg_scanin[28]=data_bus_0_w2_reg_scanout[28]; | |
2551 | assign data_bus_0_w6_reg_scanin[28]=data_bus_0_w3_reg_scanout[28]; | |
2552 | assign data_bus_0_w7_reg_scanin[28]=data_bus_0_w6_reg_scanout[28]; | |
2553 | assign data_bus_0_w0_reg_scanin[28]=data_bus_0_w7_reg_scanout[28]; | |
2554 | assign data_bus_0_w1_reg_scanin[28]=data_bus_0_w0_reg_scanout[28]; | |
2555 | assign data_bus_0_w4_reg_scanin[28]=data_bus_0_w1_reg_scanout[28]; | |
2556 | assign data_bus_0_w5_reg_scanin[28]=data_bus_0_w4_reg_scanout[28]; | |
2557 | ||
2558 | assign data_bus_0_w2_reg_scanin[27]=data_bus_0_w5_reg_scanout[28]; | |
2559 | assign data_bus_0_w3_reg_scanin[27]=data_bus_0_w2_reg_scanout[27]; | |
2560 | assign data_bus_0_w6_reg_scanin[27]=data_bus_0_w3_reg_scanout[27]; | |
2561 | assign data_bus_0_w7_reg_scanin[27]=data_bus_0_w6_reg_scanout[27]; | |
2562 | assign data_bus_0_w0_reg_scanin[27]=data_bus_0_w7_reg_scanout[27]; | |
2563 | assign data_bus_0_w1_reg_scanin[27]=data_bus_0_w0_reg_scanout[27]; | |
2564 | assign data_bus_0_w4_reg_scanin[27]=data_bus_0_w1_reg_scanout[27]; | |
2565 | assign data_bus_0_w5_reg_scanin[27]=data_bus_0_w4_reg_scanout[27]; | |
2566 | ||
2567 | assign data_bus_0_w2_reg_scanin[26]=data_bus_0_w5_reg_scanout[27]; | |
2568 | assign data_bus_0_w3_reg_scanin[26]=data_bus_0_w2_reg_scanout[26]; | |
2569 | assign data_bus_0_w6_reg_scanin[26]=data_bus_0_w3_reg_scanout[26]; | |
2570 | assign data_bus_0_w7_reg_scanin[26]=data_bus_0_w6_reg_scanout[26]; | |
2571 | assign data_bus_0_w0_reg_scanin[26]=data_bus_0_w7_reg_scanout[26]; | |
2572 | assign data_bus_0_w1_reg_scanin[26]=data_bus_0_w0_reg_scanout[26]; | |
2573 | assign data_bus_0_w4_reg_scanin[26]=data_bus_0_w1_reg_scanout[26]; | |
2574 | assign data_bus_0_w5_reg_scanin[26]=data_bus_0_w4_reg_scanout[26]; | |
2575 | ||
2576 | assign data_bus_0_w2_reg_scanin[25]=data_bus_0_w5_reg_scanout[26]; | |
2577 | assign data_bus_0_w3_reg_scanin[25]=data_bus_0_w2_reg_scanout[25]; | |
2578 | assign data_bus_0_w6_reg_scanin[25]=data_bus_0_w3_reg_scanout[25]; | |
2579 | assign data_bus_0_w7_reg_scanin[25]=data_bus_0_w6_reg_scanout[25]; | |
2580 | assign data_bus_0_w0_reg_scanin[25]=data_bus_0_w7_reg_scanout[25]; | |
2581 | assign data_bus_0_w1_reg_scanin[25]=data_bus_0_w0_reg_scanout[25]; | |
2582 | assign data_bus_0_w4_reg_scanin[25]=data_bus_0_w1_reg_scanout[25]; | |
2583 | assign data_bus_0_w5_reg_scanin[25]=data_bus_0_w4_reg_scanout[25]; | |
2584 | ||
2585 | assign data_bus_0_w2_reg_scanin[24]=data_bus_0_w5_reg_scanout[25]; | |
2586 | assign data_bus_0_w3_reg_scanin[24]=data_bus_0_w2_reg_scanout[24]; | |
2587 | assign data_bus_0_w6_reg_scanin[24]=data_bus_0_w3_reg_scanout[24]; | |
2588 | assign data_bus_0_w7_reg_scanin[24]=data_bus_0_w6_reg_scanout[24]; | |
2589 | assign data_bus_0_w0_reg_scanin[24]=data_bus_0_w7_reg_scanout[24]; | |
2590 | assign data_bus_0_w1_reg_scanin[24]=data_bus_0_w0_reg_scanout[24]; | |
2591 | assign data_bus_0_w4_reg_scanin[24]=data_bus_0_w1_reg_scanout[24]; | |
2592 | assign data_bus_0_w5_reg_scanin[24]=data_bus_0_w4_reg_scanout[24]; | |
2593 | ||
2594 | assign data_bus_0_w2_reg_scanin[23]=data_bus_0_w5_reg_scanout[24]; | |
2595 | assign data_bus_0_w3_reg_scanin[23]=data_bus_0_w2_reg_scanout[23]; | |
2596 | assign data_bus_0_w6_reg_scanin[23]=data_bus_0_w3_reg_scanout[23]; | |
2597 | assign data_bus_0_w7_reg_scanin[23]=data_bus_0_w6_reg_scanout[23]; | |
2598 | assign data_bus_0_w0_reg_scanin[23]=data_bus_0_w7_reg_scanout[23]; | |
2599 | assign data_bus_0_w1_reg_scanin[23]=data_bus_0_w0_reg_scanout[23]; | |
2600 | assign data_bus_0_w4_reg_scanin[23]=data_bus_0_w1_reg_scanout[23]; | |
2601 | assign data_bus_0_w5_reg_scanin[23]=data_bus_0_w4_reg_scanout[23]; | |
2602 | ||
2603 | assign data_bus_0_w2_reg_scanin[22]=data_bus_0_w5_reg_scanout[23]; | |
2604 | assign data_bus_0_w3_reg_scanin[22]=data_bus_0_w2_reg_scanout[22]; | |
2605 | assign data_bus_0_w6_reg_scanin[22]=data_bus_0_w3_reg_scanout[22]; | |
2606 | assign data_bus_0_w7_reg_scanin[22]=data_bus_0_w6_reg_scanout[22]; | |
2607 | assign data_bus_0_w0_reg_scanin[22]=data_bus_0_w7_reg_scanout[22]; | |
2608 | assign data_bus_0_w1_reg_scanin[22]=data_bus_0_w0_reg_scanout[22]; | |
2609 | assign data_bus_0_w4_reg_scanin[22]=data_bus_0_w1_reg_scanout[22]; | |
2610 | assign data_bus_0_w5_reg_scanin[22]=data_bus_0_w4_reg_scanout[22]; | |
2611 | ||
2612 | assign data_bus_0_w2_reg_scanin[21]=data_bus_0_w5_reg_scanout[22]; | |
2613 | assign data_bus_0_w3_reg_scanin[21]=data_bus_0_w2_reg_scanout[21]; | |
2614 | assign data_bus_0_w6_reg_scanin[21]=data_bus_0_w3_reg_scanout[21]; | |
2615 | assign data_bus_0_w7_reg_scanin[21]=data_bus_0_w6_reg_scanout[21]; | |
2616 | assign data_bus_0_w0_reg_scanin[21]=data_bus_0_w7_reg_scanout[21]; | |
2617 | assign data_bus_0_w1_reg_scanin[21]=data_bus_0_w0_reg_scanout[21]; | |
2618 | assign data_bus_0_w4_reg_scanin[21]=data_bus_0_w1_reg_scanout[21]; | |
2619 | assign data_bus_0_w5_reg_scanin[21]=data_bus_0_w4_reg_scanout[21]; | |
2620 | ||
2621 | assign data_bus_0_w2_reg_scanin[20]=data_bus_0_w5_reg_scanout[21]; | |
2622 | assign data_bus_0_w3_reg_scanin[20]=data_bus_0_w2_reg_scanout[20]; | |
2623 | assign data_bus_0_w6_reg_scanin[20]=data_bus_0_w3_reg_scanout[20]; | |
2624 | assign data_bus_0_w7_reg_scanin[20]=data_bus_0_w6_reg_scanout[20]; | |
2625 | assign data_bus_0_w0_reg_scanin[20]=data_bus_0_w7_reg_scanout[20]; | |
2626 | assign data_bus_0_w1_reg_scanin[20]=data_bus_0_w0_reg_scanout[20]; | |
2627 | assign data_bus_0_w4_reg_scanin[20]=data_bus_0_w1_reg_scanout[20]; | |
2628 | assign data_bus_0_w5_reg_scanin[20]=data_bus_0_w4_reg_scanout[20]; | |
2629 | ||
2630 | assign data_bus_0_w2_reg_scanin[19]=data_bus_0_w5_reg_scanout[20]; | |
2631 | assign data_bus_0_w3_reg_scanin[19]=data_bus_0_w2_reg_scanout[19]; | |
2632 | assign data_bus_0_w6_reg_scanin[19]=data_bus_0_w3_reg_scanout[19]; | |
2633 | assign data_bus_0_w7_reg_scanin[19]=data_bus_0_w6_reg_scanout[19]; | |
2634 | assign data_bus_0_w0_reg_scanin[19]=data_bus_0_w7_reg_scanout[19]; | |
2635 | assign data_bus_0_w1_reg_scanin[19]=data_bus_0_w0_reg_scanout[19]; | |
2636 | assign data_bus_0_w4_reg_scanin[19]=data_bus_0_w1_reg_scanout[19]; | |
2637 | assign data_bus_0_w5_reg_scanin[19]=data_bus_0_w4_reg_scanout[19]; | |
2638 | ||
2639 | assign data_bus_0_w2_reg_scanin[18]=data_bus_0_w5_reg_scanout[19]; | |
2640 | assign data_bus_0_w3_reg_scanin[18]=data_bus_0_w2_reg_scanout[18]; | |
2641 | assign data_bus_0_w6_reg_scanin[18]=data_bus_0_w3_reg_scanout[18]; | |
2642 | assign data_bus_0_w7_reg_scanin[18]=data_bus_0_w6_reg_scanout[18]; | |
2643 | assign data_bus_0_w0_reg_scanin[18]=data_bus_0_w7_reg_scanout[18]; | |
2644 | assign data_bus_0_w1_reg_scanin[18]=data_bus_0_w0_reg_scanout[18]; | |
2645 | assign data_bus_0_w4_reg_scanin[18]=data_bus_0_w1_reg_scanout[18]; | |
2646 | assign data_bus_0_w5_reg_scanin[18]=data_bus_0_w4_reg_scanout[18]; | |
2647 | ||
2648 | assign data_bus_0_w2_reg_scanin[17]=data_bus_0_w5_reg_scanout[18]; | |
2649 | assign data_bus_0_w3_reg_scanin[17]=data_bus_0_w2_reg_scanout[17]; | |
2650 | assign data_bus_0_w6_reg_scanin[17]=data_bus_0_w3_reg_scanout[17]; | |
2651 | assign data_bus_0_w7_reg_scanin[17]=data_bus_0_w6_reg_scanout[17]; | |
2652 | assign data_bus_0_w0_reg_scanin[17]=data_bus_0_w7_reg_scanout[17]; | |
2653 | assign data_bus_0_w1_reg_scanin[17]=data_bus_0_w0_reg_scanout[17]; | |
2654 | assign data_bus_0_w4_reg_scanin[17]=data_bus_0_w1_reg_scanout[17]; | |
2655 | assign data_bus_0_w5_reg_scanin[17]=data_bus_0_w4_reg_scanout[17]; | |
2656 | ||
2657 | assign data_bus_0_w0_reg_scanin[16]=data_bus_0_w5_reg_scanout[17]; | |
2658 | assign data_bus_0_w1_reg_scanin[16]=data_bus_0_w0_reg_scanout[16]; | |
2659 | assign data_bus_0_w4_reg_scanin[16]=data_bus_0_w1_reg_scanout[16]; | |
2660 | assign data_bus_0_w5_reg_scanin[16]=data_bus_0_w4_reg_scanout[16]; | |
2661 | assign data_bus_0_w2_reg_scanin[16]=data_bus_0_w5_reg_scanout[16]; | |
2662 | assign data_bus_0_w3_reg_scanin[16]=data_bus_0_w2_reg_scanout[16]; | |
2663 | assign data_bus_0_w6_reg_scanin[16]=data_bus_0_w3_reg_scanout[16]; | |
2664 | assign data_bus_0_w7_reg_scanin[16]=data_bus_0_w6_reg_scanout[16]; | |
2665 | ||
2666 | assign data_bus_0_w0_reg_scanin[15]=data_bus_0_w7_reg_scanout[16]; | |
2667 | assign data_bus_0_w1_reg_scanin[15]=data_bus_0_w0_reg_scanout[15]; | |
2668 | assign data_bus_0_w4_reg_scanin[15]=data_bus_0_w1_reg_scanout[15]; | |
2669 | assign data_bus_0_w5_reg_scanin[15]=data_bus_0_w4_reg_scanout[15]; | |
2670 | assign data_bus_0_w2_reg_scanin[15]=data_bus_0_w5_reg_scanout[15]; | |
2671 | assign data_bus_0_w3_reg_scanin[15]=data_bus_0_w2_reg_scanout[15]; | |
2672 | assign data_bus_0_w6_reg_scanin[15]=data_bus_0_w3_reg_scanout[15]; | |
2673 | assign data_bus_0_w7_reg_scanin[15]=data_bus_0_w6_reg_scanout[15]; | |
2674 | ||
2675 | assign data_bus_0_w0_reg_scanin[14]=data_bus_0_w7_reg_scanout[15]; | |
2676 | assign data_bus_0_w1_reg_scanin[14]=data_bus_0_w0_reg_scanout[14]; | |
2677 | assign data_bus_0_w4_reg_scanin[14]=data_bus_0_w1_reg_scanout[14]; | |
2678 | assign data_bus_0_w5_reg_scanin[14]=data_bus_0_w4_reg_scanout[14]; | |
2679 | assign data_bus_0_w2_reg_scanin[14]=data_bus_0_w5_reg_scanout[14]; | |
2680 | assign data_bus_0_w3_reg_scanin[14]=data_bus_0_w2_reg_scanout[14]; | |
2681 | assign data_bus_0_w6_reg_scanin[14]=data_bus_0_w3_reg_scanout[14]; | |
2682 | assign data_bus_0_w7_reg_scanin[14]=data_bus_0_w6_reg_scanout[14]; | |
2683 | ||
2684 | assign data_bus_0_w0_reg_scanin[13]=data_bus_0_w7_reg_scanout[14]; | |
2685 | assign data_bus_0_w1_reg_scanin[13]=data_bus_0_w0_reg_scanout[13]; | |
2686 | assign data_bus_0_w4_reg_scanin[13]=data_bus_0_w1_reg_scanout[13]; | |
2687 | assign data_bus_0_w5_reg_scanin[13]=data_bus_0_w4_reg_scanout[13]; | |
2688 | assign data_bus_0_w2_reg_scanin[13]=data_bus_0_w5_reg_scanout[13]; | |
2689 | assign data_bus_0_w3_reg_scanin[13]=data_bus_0_w2_reg_scanout[13]; | |
2690 | assign data_bus_0_w6_reg_scanin[13]=data_bus_0_w3_reg_scanout[13]; | |
2691 | assign data_bus_0_w7_reg_scanin[13]=data_bus_0_w6_reg_scanout[13]; | |
2692 | ||
2693 | assign data_bus_0_w0_reg_scanin[12]=data_bus_0_w7_reg_scanout[13]; | |
2694 | assign data_bus_0_w1_reg_scanin[12]=data_bus_0_w0_reg_scanout[12]; | |
2695 | assign data_bus_0_w4_reg_scanin[12]=data_bus_0_w1_reg_scanout[12]; | |
2696 | assign data_bus_0_w5_reg_scanin[12]=data_bus_0_w4_reg_scanout[12]; | |
2697 | assign data_bus_0_w2_reg_scanin[12]=data_bus_0_w5_reg_scanout[12]; | |
2698 | assign data_bus_0_w3_reg_scanin[12]=data_bus_0_w2_reg_scanout[12]; | |
2699 | assign data_bus_0_w6_reg_scanin[12]=data_bus_0_w3_reg_scanout[12]; | |
2700 | assign data_bus_0_w7_reg_scanin[12]=data_bus_0_w6_reg_scanout[12]; | |
2701 | ||
2702 | assign data_bus_0_w0_reg_scanin[11]=data_bus_0_w7_reg_scanout[12]; | |
2703 | assign data_bus_0_w1_reg_scanin[11]=data_bus_0_w0_reg_scanout[11]; | |
2704 | assign data_bus_0_w4_reg_scanin[11]=data_bus_0_w1_reg_scanout[11]; | |
2705 | assign data_bus_0_w5_reg_scanin[11]=data_bus_0_w4_reg_scanout[11]; | |
2706 | assign data_bus_0_w2_reg_scanin[11]=data_bus_0_w5_reg_scanout[11]; | |
2707 | assign data_bus_0_w3_reg_scanin[11]=data_bus_0_w2_reg_scanout[11]; | |
2708 | assign data_bus_0_w6_reg_scanin[11]=data_bus_0_w3_reg_scanout[11]; | |
2709 | assign data_bus_0_w7_reg_scanin[11]=data_bus_0_w6_reg_scanout[11]; | |
2710 | ||
2711 | assign data_bus_0_w0_reg_scanin[10]=data_bus_0_w7_reg_scanout[11]; | |
2712 | assign data_bus_0_w1_reg_scanin[10]=data_bus_0_w0_reg_scanout[10]; | |
2713 | assign data_bus_0_w4_reg_scanin[10]=data_bus_0_w1_reg_scanout[10]; | |
2714 | assign data_bus_0_w5_reg_scanin[10]=data_bus_0_w4_reg_scanout[10]; | |
2715 | assign data_bus_0_w2_reg_scanin[10]=data_bus_0_w5_reg_scanout[10]; | |
2716 | assign data_bus_0_w3_reg_scanin[10]=data_bus_0_w2_reg_scanout[10]; | |
2717 | assign data_bus_0_w6_reg_scanin[10]=data_bus_0_w3_reg_scanout[10]; | |
2718 | assign data_bus_0_w7_reg_scanin[10]=data_bus_0_w6_reg_scanout[10]; | |
2719 | ||
2720 | assign data_bus_0_w0_reg_scanin[9]=data_bus_0_w7_reg_scanout[10]; | |
2721 | assign data_bus_0_w1_reg_scanin[9]=data_bus_0_w0_reg_scanout[9]; | |
2722 | assign data_bus_0_w4_reg_scanin[9]=data_bus_0_w1_reg_scanout[9]; | |
2723 | assign data_bus_0_w5_reg_scanin[9]=data_bus_0_w4_reg_scanout[9]; | |
2724 | assign data_bus_0_w2_reg_scanin[9]=data_bus_0_w5_reg_scanout[9]; | |
2725 | assign data_bus_0_w3_reg_scanin[9]=data_bus_0_w2_reg_scanout[9]; | |
2726 | assign data_bus_0_w6_reg_scanin[9]=data_bus_0_w3_reg_scanout[9]; | |
2727 | assign data_bus_0_w7_reg_scanin[9]=data_bus_0_w6_reg_scanout[9]; | |
2728 | ||
2729 | assign data_bus_0_w0_reg_scanin[8]=data_bus_0_w7_reg_scanout[9]; | |
2730 | assign data_bus_0_w1_reg_scanin[8]=data_bus_0_w0_reg_scanout[8]; | |
2731 | assign data_bus_0_w4_reg_scanin[8]=data_bus_0_w1_reg_scanout[8]; | |
2732 | assign data_bus_0_w5_reg_scanin[8]=data_bus_0_w4_reg_scanout[8]; | |
2733 | assign data_bus_0_w2_reg_scanin[8]=data_bus_0_w5_reg_scanout[8]; | |
2734 | assign data_bus_0_w3_reg_scanin[8]=data_bus_0_w2_reg_scanout[8]; | |
2735 | assign data_bus_0_w6_reg_scanin[8]=data_bus_0_w3_reg_scanout[8]; | |
2736 | assign data_bus_0_w7_reg_scanin[8]=data_bus_0_w6_reg_scanout[8]; | |
2737 | ||
2738 | assign data_bus_0_w0_reg_scanin[7]=data_bus_0_w7_reg_scanout[8]; | |
2739 | assign data_bus_0_w1_reg_scanin[7]=data_bus_0_w0_reg_scanout[7]; | |
2740 | assign data_bus_0_w4_reg_scanin[7]=data_bus_0_w1_reg_scanout[7]; | |
2741 | assign data_bus_0_w5_reg_scanin[7]=data_bus_0_w4_reg_scanout[7]; | |
2742 | assign data_bus_0_w2_reg_scanin[7]=data_bus_0_w5_reg_scanout[7]; | |
2743 | assign data_bus_0_w3_reg_scanin[7]=data_bus_0_w2_reg_scanout[7]; | |
2744 | assign data_bus_0_w6_reg_scanin[7]=data_bus_0_w3_reg_scanout[7]; | |
2745 | assign data_bus_0_w7_reg_scanin[7]=data_bus_0_w6_reg_scanout[7]; | |
2746 | ||
2747 | assign data_bus_0_w0_reg_scanin[6]=data_bus_0_w7_reg_scanout[7]; | |
2748 | assign data_bus_0_w1_reg_scanin[6]=data_bus_0_w0_reg_scanout[6]; | |
2749 | assign data_bus_0_w4_reg_scanin[6]=data_bus_0_w1_reg_scanout[6]; | |
2750 | assign data_bus_0_w5_reg_scanin[6]=data_bus_0_w4_reg_scanout[6]; | |
2751 | assign data_bus_0_w2_reg_scanin[6]=data_bus_0_w5_reg_scanout[6]; | |
2752 | assign data_bus_0_w3_reg_scanin[6]=data_bus_0_w2_reg_scanout[6]; | |
2753 | assign data_bus_0_w6_reg_scanin[6]=data_bus_0_w3_reg_scanout[6]; | |
2754 | assign data_bus_0_w7_reg_scanin[6]=data_bus_0_w6_reg_scanout[6]; | |
2755 | ||
2756 | assign data_bus_0_w0_reg_scanin[5]=data_bus_0_w7_reg_scanout[6]; | |
2757 | assign data_bus_0_w1_reg_scanin[5]=data_bus_0_w0_reg_scanout[5]; | |
2758 | assign data_bus_0_w4_reg_scanin[5]=data_bus_0_w1_reg_scanout[5]; | |
2759 | assign data_bus_0_w5_reg_scanin[5]=data_bus_0_w4_reg_scanout[5]; | |
2760 | assign data_bus_0_w2_reg_scanin[5]=data_bus_0_w5_reg_scanout[5]; | |
2761 | assign data_bus_0_w3_reg_scanin[5]=data_bus_0_w2_reg_scanout[5]; | |
2762 | assign data_bus_0_w6_reg_scanin[5]=data_bus_0_w3_reg_scanout[5]; | |
2763 | assign data_bus_0_w7_reg_scanin[5]=data_bus_0_w6_reg_scanout[5]; | |
2764 | ||
2765 | assign data_bus_0_w0_reg_scanin[4]=data_bus_0_w7_reg_scanout[5]; | |
2766 | assign data_bus_0_w1_reg_scanin[4]=data_bus_0_w0_reg_scanout[4]; | |
2767 | assign data_bus_0_w4_reg_scanin[4]=data_bus_0_w1_reg_scanout[4]; | |
2768 | assign data_bus_0_w5_reg_scanin[4]=data_bus_0_w4_reg_scanout[4]; | |
2769 | assign data_bus_0_w2_reg_scanin[4]=data_bus_0_w5_reg_scanout[4]; | |
2770 | assign data_bus_0_w3_reg_scanin[4]=data_bus_0_w2_reg_scanout[4]; | |
2771 | assign data_bus_0_w6_reg_scanin[4]=data_bus_0_w3_reg_scanout[4]; | |
2772 | assign data_bus_0_w7_reg_scanin[4]=data_bus_0_w6_reg_scanout[4]; | |
2773 | ||
2774 | assign data_bus_0_w0_reg_scanin[3]=data_bus_0_w7_reg_scanout[4]; | |
2775 | assign data_bus_0_w1_reg_scanin[3]=data_bus_0_w0_reg_scanout[3]; | |
2776 | assign data_bus_0_w4_reg_scanin[3]=data_bus_0_w1_reg_scanout[3]; | |
2777 | assign data_bus_0_w5_reg_scanin[3]=data_bus_0_w4_reg_scanout[3]; | |
2778 | assign data_bus_0_w2_reg_scanin[3]=data_bus_0_w5_reg_scanout[3]; | |
2779 | assign data_bus_0_w3_reg_scanin[3]=data_bus_0_w2_reg_scanout[3]; | |
2780 | assign data_bus_0_w6_reg_scanin[3]=data_bus_0_w3_reg_scanout[3]; | |
2781 | assign data_bus_0_w7_reg_scanin[3]=data_bus_0_w6_reg_scanout[3]; | |
2782 | ||
2783 | assign data_bus_0_w0_reg_scanin[2]=data_bus_0_w7_reg_scanout[3]; | |
2784 | assign data_bus_0_w1_reg_scanin[2]=data_bus_0_w0_reg_scanout[2]; | |
2785 | assign data_bus_0_w4_reg_scanin[2]=data_bus_0_w1_reg_scanout[2]; | |
2786 | assign data_bus_0_w5_reg_scanin[2]=data_bus_0_w4_reg_scanout[2]; | |
2787 | assign data_bus_0_w2_reg_scanin[2]=data_bus_0_w5_reg_scanout[2]; | |
2788 | assign data_bus_0_w3_reg_scanin[2]=data_bus_0_w2_reg_scanout[2]; | |
2789 | assign data_bus_0_w6_reg_scanin[2]=data_bus_0_w3_reg_scanout[2]; | |
2790 | assign data_bus_0_w7_reg_scanin[2]=data_bus_0_w6_reg_scanout[2]; | |
2791 | ||
2792 | assign data_bus_0_w0_reg_scanin[1]=data_bus_0_w7_reg_scanout[2]; | |
2793 | assign data_bus_0_w1_reg_scanin[1]=data_bus_0_w0_reg_scanout[1]; | |
2794 | assign data_bus_0_w4_reg_scanin[1]=data_bus_0_w1_reg_scanout[1]; | |
2795 | assign data_bus_0_w5_reg_scanin[1]=data_bus_0_w4_reg_scanout[1]; | |
2796 | assign data_bus_0_w2_reg_scanin[1]=data_bus_0_w5_reg_scanout[1]; | |
2797 | assign data_bus_0_w3_reg_scanin[1]=data_bus_0_w2_reg_scanout[1]; | |
2798 | assign data_bus_0_w6_reg_scanin[1]=data_bus_0_w3_reg_scanout[1]; | |
2799 | assign data_bus_0_w7_reg_scanin[1]=data_bus_0_w6_reg_scanout[1]; | |
2800 | ||
2801 | assign data_bus_0_w0_reg_scanin[0]=data_bus_0_w7_reg_scanout[1]; | |
2802 | assign data_bus_0_w1_reg_scanin[0]=data_bus_0_w0_reg_scanout[0]; | |
2803 | assign data_bus_0_w4_reg_scanin[0]=data_bus_0_w1_reg_scanout[0]; | |
2804 | assign data_bus_0_w5_reg_scanin[0]=data_bus_0_w4_reg_scanout[0]; | |
2805 | assign data_bus_0_w2_reg_scanin[0]=data_bus_0_w5_reg_scanout[0]; | |
2806 | assign data_bus_0_w3_reg_scanin[0]=data_bus_0_w2_reg_scanout[0]; | |
2807 | assign data_bus_0_w6_reg_scanin[0]=data_bus_0_w3_reg_scanout[0]; | |
2808 | assign data_bus_0_w7_reg_scanin[0]=data_bus_0_w6_reg_scanout[0]; | |
2809 | ||
2810 | ||
2811 | // ***************************END SECTION*************************** | |
2812 | ||
2813 | ////////////////////////// | |
2814 | // Middle section scan // | |
2815 | ////////////////////////// | |
2816 | ||
2817 | ||
2818 | assign red_en_reg_scanin[0] = data_bus_0_w7_reg_scanout[0]; | |
2819 | assign red_en_reg_scanin[1] = red_en_reg_scanout[0]; | |
2820 | assign red_en_out_reg_scanin[0] = red_en_reg_scanout[1]; | |
2821 | assign red_en_out_reg_scanin[1] = red_en_out_reg_scanout[0]; | |
2822 | assign red_arst_reg_scanin = red_en_out_reg_scanout[1]; | |
2823 | assign red_wen_reg_scanin = red_arst_reg_scanout; | |
2824 | assign red_d_out_reg_scanin[0] = red_wen_reg_scanout; | |
2825 | assign red_d_out_reg_scanin[1] = red_d_out_reg_scanout[0]; | |
2826 | assign red_d_out_reg_scanin[3] = red_d_out_reg_scanout[1]; | |
2827 | assign red_d_out_reg_scanin[2] = red_d_out_reg_scanout[3]; | |
2828 | assign red_d_out_reg_scanin[4] = red_d_out_reg_scanout[2]; | |
2829 | assign rid_reg_scanin[1] = red_d_out_reg_scanout[4]; | |
2830 | assign rid_reg_scanin[0] = rid_reg_scanout[1]; | |
2831 | assign rid_reg_scanin[3] = rid_reg_scanout[0]; | |
2832 | assign rid_reg_scanin[2] = rid_reg_scanout[3]; | |
2833 | assign red_d_reg_scanin[0] = rid_reg_scanout[2]; | |
2834 | assign red_d_reg_scanin[3] = red_d_reg_scanout[0]; | |
2835 | assign red_d_reg_scanin[4] = red_d_reg_scanout[3]; | |
2836 | assign red_d_reg_scanin[1] = red_d_reg_scanout[4]; | |
2837 | assign red_d_reg_scanin[2] = red_d_reg_scanout[1]; | |
2838 | assign quad_en_reg_scanin[2]= red_d_reg_scanout[2]; | |
2839 | assign quad_en_reg_scanin[0]= quad_en_reg_scanout[2]; | |
2840 | assign index_reg_i_scanin = quad_en_reg_scanout[0] ; | |
2841 | assign way_f_reg_scanin[4] = index_reg_i_scanout ; | |
2842 | assign way_f_reg_scanin[5] = way_f_reg_scanout[4] ; | |
2843 | assign way_f_reg_scanin[6] = way_f_reg_scanout[5] ; | |
2844 | assign way_f_reg_scanin[7] = way_f_reg_scanout[6] ; | |
2845 | assign quad_en_1_latch_scanin = way_f_reg_scanout[7] ; | |
2846 | assign quad_en_0_latch_scanin = quad_en_1_latch_scanout ; | |
2847 | assign wr_word_en_5_reg_scanin = quad_en_0_latch_scanout ; | |
2848 | assign wr_word_en_1_reg_scanin = wr_word_en_5_reg_scanout ; | |
2849 | assign wr_word_en_0_reg_scanin = wr_word_en_1_reg_scanout ; | |
2850 | assign wr_word_en_4_reg_scanin = wr_word_en_0_reg_scanout ; | |
2851 | assign wr_word_en_6_reg_scanin = wr_word_en_4_reg_scanout ; | |
2852 | assign wr_word_en_2_reg_scanin = wr_word_en_6_reg_scanout ; | |
2853 | assign wr_word_en_7_reg_scanin = wr_word_en_2_reg_scanout ; | |
2854 | assign wr_word_en_3_reg_scanin = wr_word_en_7_reg_scanout ; | |
2855 | assign quad_en_3_latch_scanin = wr_word_en_3_reg_scanout ; | |
2856 | assign quad_en_2_latch_scanin = quad_en_3_latch_scanout ; | |
2857 | assign way_f_reg_scanin[0] = quad_en_2_latch_scanout ; | |
2858 | assign way_f_reg_scanin[1] = way_f_reg_scanout[0] ; | |
2859 | assign way_f_reg_scanin[2] = way_f_reg_scanout[1] ; | |
2860 | assign way_f_reg_scanin[3] = way_f_reg_scanout[2] ; | |
2861 | assign wrway_0_reg_scanin = way_f_reg_scanout[3] ; | |
2862 | assign wrway_1_reg_scanin = wrway_0_reg_scanout ; | |
2863 | assign wrway_2_reg_scanin = wrway_1_reg_scanout ; | |
2864 | assign wrreq_reg_scanin = wrway_2_reg_scanout ; | |
2865 | assign rdreq_reg_scanin = wrreq_reg_scanout ; | |
2866 | assign quad_en_reg_scanin[3]= rdreq_reg_scanout ; | |
2867 | assign quad_en_reg_scanin[1]= quad_en_reg_scanout[3]; | |
2868 | assign rdreq_reg_b_scanin = quad_en_reg_scanout[1] ; | |
2869 | assign wrreq_reg_b_scanin = rdreq_reg_b_scanout ; | |
2870 | assign way_c_reg_scanin[7] = wrreq_reg_b_scanout ; | |
2871 | assign way_c_reg_scanin[6] = way_c_reg_scanout[7] ; | |
2872 | assign way_c_reg_scanin[5] = way_c_reg_scanout[6] ; | |
2873 | assign way_c_reg_scanin[4] = way_c_reg_scanout[5] ; | |
2874 | assign way_c_reg_scanin[3] = way_c_reg_scanout[4] ; | |
2875 | assign way_c_reg_scanin[2] = way_c_reg_scanout[3] ; | |
2876 | assign way_c_reg_scanin[1] = way_c_reg_scanout[2] ; | |
2877 | assign way_c_reg_scanin[0] = way_c_reg_scanout[1] ; | |
2878 | ||
2879 | ||
2880 | ||
2881 | /////// end of middle section /////////////////// | |
2882 | ||
2883 | assign wrdata_q3_7_scanin[32]=way_c_reg_scanout[0]; | |
2884 | assign wrdata_q3_3_scanin[32]=wrdata_q3_7_scanout[32]; | |
2885 | assign wrdata_q3_7_scanin[31]=wrdata_q3_3_scanout[32]; | |
2886 | assign wrdata_q3_3_scanin[31]=wrdata_q3_7_scanout[31]; | |
2887 | assign wrdata_q3_7_scanin[30]=wrdata_q3_3_scanout[31]; | |
2888 | assign wrdata_q3_3_scanin[30]=wrdata_q3_7_scanout[30]; | |
2889 | assign wrdata_q3_7_scanin[29]=wrdata_q3_3_scanout[30]; | |
2890 | assign wrdata_q3_3_scanin[29]=wrdata_q3_7_scanout[29]; | |
2891 | assign wrdata_q3_7_scanin[28]=wrdata_q3_3_scanout[29]; | |
2892 | assign wrdata_q3_3_scanin[28]=wrdata_q3_7_scanout[28]; | |
2893 | assign wrdata_q3_7_scanin[27]=wrdata_q3_3_scanout[28]; | |
2894 | assign wrdata_q3_3_scanin[27]=wrdata_q3_7_scanout[27]; | |
2895 | assign wrdata_q3_7_scanin[26]=wrdata_q3_3_scanout[27]; | |
2896 | assign wrdata_q3_3_scanin[26]=wrdata_q3_7_scanout[26]; | |
2897 | assign wrdata_q3_7_scanin[25]=wrdata_q3_3_scanout[26]; | |
2898 | assign wrdata_q3_3_scanin[25]=wrdata_q3_7_scanout[25]; | |
2899 | assign wrdata_q3_7_scanin[24]=wrdata_q3_3_scanout[25]; | |
2900 | assign wrdata_q3_3_scanin[24]=wrdata_q3_7_scanout[24]; | |
2901 | assign wrdata_q3_7_scanin[23]=wrdata_q3_3_scanout[24]; | |
2902 | assign wrdata_q3_3_scanin[23]=wrdata_q3_7_scanout[23]; | |
2903 | assign wrdata_q3_7_scanin[22]=wrdata_q3_3_scanout[23]; | |
2904 | assign wrdata_q3_3_scanin[22]=wrdata_q3_7_scanout[22]; | |
2905 | assign wrdata_q3_7_scanin[21]=wrdata_q3_3_scanout[22]; | |
2906 | assign wrdata_q3_3_scanin[21]=wrdata_q3_7_scanout[21]; | |
2907 | assign wrdata_q3_7_scanin[20]=wrdata_q3_3_scanout[21]; | |
2908 | assign wrdata_q3_3_scanin[20]=wrdata_q3_7_scanout[20]; | |
2909 | assign wrdata_q3_7_scanin[19]=wrdata_q3_3_scanout[20]; | |
2910 | assign wrdata_q3_3_scanin[19]=wrdata_q3_7_scanout[19]; | |
2911 | assign wrdata_q3_7_scanin[18]=wrdata_q3_3_scanout[19]; | |
2912 | assign wrdata_q3_3_scanin[18]=wrdata_q3_7_scanout[18]; | |
2913 | assign wrdata_q3_7_scanin[17]=wrdata_q3_3_scanout[18]; | |
2914 | assign wrdata_q3_3_scanin[17]=wrdata_q3_7_scanout[17]; | |
2915 | assign wrdata_q3_7_scanin[16]=wrdata_q3_3_scanout[17]; | |
2916 | assign wrdata_q3_3_scanin[16]=wrdata_q3_7_scanout[16]; | |
2917 | assign wrdata_q3_7_scanin[15]=wrdata_q3_3_scanout[16]; | |
2918 | assign wrdata_q3_3_scanin[15]=wrdata_q3_7_scanout[15]; | |
2919 | assign wrdata_q3_7_scanin[14]=wrdata_q3_3_scanout[15]; | |
2920 | assign wrdata_q3_3_scanin[14]=wrdata_q3_7_scanout[14]; | |
2921 | assign wrdata_q3_7_scanin[13]=wrdata_q3_3_scanout[14]; | |
2922 | assign wrdata_q3_3_scanin[13]=wrdata_q3_7_scanout[13]; | |
2923 | assign wrdata_q3_7_scanin[12]=wrdata_q3_3_scanout[13]; | |
2924 | assign wrdata_q3_3_scanin[12]=wrdata_q3_7_scanout[12]; | |
2925 | assign wrdata_q3_7_scanin[11]=wrdata_q3_3_scanout[12]; | |
2926 | assign wrdata_q3_3_scanin[11]=wrdata_q3_7_scanout[11]; | |
2927 | assign wrdata_q3_7_scanin[10]=wrdata_q3_3_scanout[11]; | |
2928 | assign wrdata_q3_3_scanin[10]=wrdata_q3_7_scanout[10]; | |
2929 | assign wrdata_q3_7_scanin[9]=wrdata_q3_3_scanout[10]; | |
2930 | assign wrdata_q3_3_scanin[9]=wrdata_q3_7_scanout[9]; | |
2931 | assign wrdata_q3_7_scanin[8]=wrdata_q3_3_scanout[9]; | |
2932 | assign wrdata_q3_3_scanin[8]=wrdata_q3_7_scanout[8]; | |
2933 | assign wrdata_q3_7_scanin[7]=wrdata_q3_3_scanout[8]; | |
2934 | assign wrdata_q3_3_scanin[7]=wrdata_q3_7_scanout[7]; | |
2935 | assign wrdata_q3_7_scanin[6]=wrdata_q3_3_scanout[7]; | |
2936 | assign wrdata_q3_3_scanin[6]=wrdata_q3_7_scanout[6]; | |
2937 | assign wrdata_q3_7_scanin[5]=wrdata_q3_3_scanout[6]; | |
2938 | assign wrdata_q3_3_scanin[5]=wrdata_q3_7_scanout[5]; | |
2939 | assign wrdata_q3_7_scanin[4]=wrdata_q3_3_scanout[5]; | |
2940 | assign wrdata_q3_3_scanin[4]=wrdata_q3_7_scanout[4]; | |
2941 | assign wrdata_q3_7_scanin[3]=wrdata_q3_3_scanout[4]; | |
2942 | assign wrdata_q3_3_scanin[3]=wrdata_q3_7_scanout[3]; | |
2943 | assign wrdata_q3_7_scanin[2]=wrdata_q3_3_scanout[3]; | |
2944 | assign wrdata_q3_3_scanin[2]=wrdata_q3_7_scanout[2]; | |
2945 | assign wrdata_q3_7_scanin[1]=wrdata_q3_3_scanout[2]; | |
2946 | assign wrdata_q3_3_scanin[1]=wrdata_q3_7_scanout[1]; | |
2947 | assign wrdata_q3_7_scanin[0]=wrdata_q3_3_scanout[1]; | |
2948 | assign wrdata_q3_3_scanin[0]=wrdata_q3_7_scanout[0]; | |
2949 | ||
2950 | // ***************************BEGIN SECTION************************* | |
2951 | ||
2952 | assign data_bus_3_w2_reg_scanin[32]=wrdata_q3_3_scanout[0]; | |
2953 | assign data_bus_3_w3_reg_scanin[32]=data_bus_3_w2_reg_scanout[32]; | |
2954 | assign data_bus_3_w6_reg_scanin[32]=data_bus_3_w3_reg_scanout[32]; | |
2955 | assign data_bus_3_w7_reg_scanin[32]=data_bus_3_w6_reg_scanout[32]; | |
2956 | assign data_bus_3_w0_reg_scanin[32]=data_bus_3_w7_reg_scanout[32]; | |
2957 | assign data_bus_3_w1_reg_scanin[32]=data_bus_3_w0_reg_scanout[32]; | |
2958 | assign data_bus_3_w4_reg_scanin[32]=data_bus_3_w1_reg_scanout[32]; | |
2959 | assign data_bus_3_w5_reg_scanin[32]=data_bus_3_w4_reg_scanout[32]; | |
2960 | ||
2961 | assign data_bus_3_w2_reg_scanin[31]=data_bus_3_w5_reg_scanout[32]; | |
2962 | assign data_bus_3_w3_reg_scanin[31]=data_bus_3_w2_reg_scanout[31]; | |
2963 | assign data_bus_3_w6_reg_scanin[31]=data_bus_3_w3_reg_scanout[31]; | |
2964 | assign data_bus_3_w7_reg_scanin[31]=data_bus_3_w6_reg_scanout[31]; | |
2965 | assign data_bus_3_w0_reg_scanin[31]=data_bus_3_w7_reg_scanout[31]; | |
2966 | assign data_bus_3_w1_reg_scanin[31]=data_bus_3_w0_reg_scanout[31]; | |
2967 | assign data_bus_3_w4_reg_scanin[31]=data_bus_3_w1_reg_scanout[31]; | |
2968 | assign data_bus_3_w5_reg_scanin[31]=data_bus_3_w4_reg_scanout[31]; | |
2969 | ||
2970 | assign data_bus_3_w2_reg_scanin[30]=data_bus_3_w5_reg_scanout[31]; | |
2971 | assign data_bus_3_w3_reg_scanin[30]=data_bus_3_w2_reg_scanout[30]; | |
2972 | assign data_bus_3_w6_reg_scanin[30]=data_bus_3_w3_reg_scanout[30]; | |
2973 | assign data_bus_3_w7_reg_scanin[30]=data_bus_3_w6_reg_scanout[30]; | |
2974 | assign data_bus_3_w0_reg_scanin[30]=data_bus_3_w7_reg_scanout[30]; | |
2975 | assign data_bus_3_w1_reg_scanin[30]=data_bus_3_w0_reg_scanout[30]; | |
2976 | assign data_bus_3_w4_reg_scanin[30]=data_bus_3_w1_reg_scanout[30]; | |
2977 | assign data_bus_3_w5_reg_scanin[30]=data_bus_3_w4_reg_scanout[30]; | |
2978 | ||
2979 | assign data_bus_3_w2_reg_scanin[29]=data_bus_3_w5_reg_scanout[30]; | |
2980 | assign data_bus_3_w3_reg_scanin[29]=data_bus_3_w2_reg_scanout[29]; | |
2981 | assign data_bus_3_w6_reg_scanin[29]=data_bus_3_w3_reg_scanout[29]; | |
2982 | assign data_bus_3_w7_reg_scanin[29]=data_bus_3_w6_reg_scanout[29]; | |
2983 | assign data_bus_3_w0_reg_scanin[29]=data_bus_3_w7_reg_scanout[29]; | |
2984 | assign data_bus_3_w1_reg_scanin[29]=data_bus_3_w0_reg_scanout[29]; | |
2985 | assign data_bus_3_w4_reg_scanin[29]=data_bus_3_w1_reg_scanout[29]; | |
2986 | assign data_bus_3_w5_reg_scanin[29]=data_bus_3_w4_reg_scanout[29]; | |
2987 | ||
2988 | assign data_bus_3_w2_reg_scanin[28]=data_bus_3_w5_reg_scanout[29]; | |
2989 | assign data_bus_3_w3_reg_scanin[28]=data_bus_3_w2_reg_scanout[28]; | |
2990 | assign data_bus_3_w6_reg_scanin[28]=data_bus_3_w3_reg_scanout[28]; | |
2991 | assign data_bus_3_w7_reg_scanin[28]=data_bus_3_w6_reg_scanout[28]; | |
2992 | assign data_bus_3_w0_reg_scanin[28]=data_bus_3_w7_reg_scanout[28]; | |
2993 | assign data_bus_3_w1_reg_scanin[28]=data_bus_3_w0_reg_scanout[28]; | |
2994 | assign data_bus_3_w4_reg_scanin[28]=data_bus_3_w1_reg_scanout[28]; | |
2995 | assign data_bus_3_w5_reg_scanin[28]=data_bus_3_w4_reg_scanout[28]; | |
2996 | ||
2997 | assign data_bus_3_w2_reg_scanin[27]=data_bus_3_w5_reg_scanout[28]; | |
2998 | assign data_bus_3_w3_reg_scanin[27]=data_bus_3_w2_reg_scanout[27]; | |
2999 | assign data_bus_3_w6_reg_scanin[27]=data_bus_3_w3_reg_scanout[27]; | |
3000 | assign data_bus_3_w7_reg_scanin[27]=data_bus_3_w6_reg_scanout[27]; | |
3001 | assign data_bus_3_w0_reg_scanin[27]=data_bus_3_w7_reg_scanout[27]; | |
3002 | assign data_bus_3_w1_reg_scanin[27]=data_bus_3_w0_reg_scanout[27]; | |
3003 | assign data_bus_3_w4_reg_scanin[27]=data_bus_3_w1_reg_scanout[27]; | |
3004 | assign data_bus_3_w5_reg_scanin[27]=data_bus_3_w4_reg_scanout[27]; | |
3005 | ||
3006 | assign data_bus_3_w2_reg_scanin[26]=data_bus_3_w5_reg_scanout[27]; | |
3007 | assign data_bus_3_w3_reg_scanin[26]=data_bus_3_w2_reg_scanout[26]; | |
3008 | assign data_bus_3_w6_reg_scanin[26]=data_bus_3_w3_reg_scanout[26]; | |
3009 | assign data_bus_3_w7_reg_scanin[26]=data_bus_3_w6_reg_scanout[26]; | |
3010 | assign data_bus_3_w0_reg_scanin[26]=data_bus_3_w7_reg_scanout[26]; | |
3011 | assign data_bus_3_w1_reg_scanin[26]=data_bus_3_w0_reg_scanout[26]; | |
3012 | assign data_bus_3_w4_reg_scanin[26]=data_bus_3_w1_reg_scanout[26]; | |
3013 | assign data_bus_3_w5_reg_scanin[26]=data_bus_3_w4_reg_scanout[26]; | |
3014 | ||
3015 | assign data_bus_3_w2_reg_scanin[25]=data_bus_3_w5_reg_scanout[26]; | |
3016 | assign data_bus_3_w3_reg_scanin[25]=data_bus_3_w2_reg_scanout[25]; | |
3017 | assign data_bus_3_w6_reg_scanin[25]=data_bus_3_w3_reg_scanout[25]; | |
3018 | assign data_bus_3_w7_reg_scanin[25]=data_bus_3_w6_reg_scanout[25]; | |
3019 | assign data_bus_3_w0_reg_scanin[25]=data_bus_3_w7_reg_scanout[25]; | |
3020 | assign data_bus_3_w1_reg_scanin[25]=data_bus_3_w0_reg_scanout[25]; | |
3021 | assign data_bus_3_w4_reg_scanin[25]=data_bus_3_w1_reg_scanout[25]; | |
3022 | assign data_bus_3_w5_reg_scanin[25]=data_bus_3_w4_reg_scanout[25]; | |
3023 | ||
3024 | assign data_bus_3_w2_reg_scanin[24]=data_bus_3_w5_reg_scanout[25]; | |
3025 | assign data_bus_3_w3_reg_scanin[24]=data_bus_3_w2_reg_scanout[24]; | |
3026 | assign data_bus_3_w6_reg_scanin[24]=data_bus_3_w3_reg_scanout[24]; | |
3027 | assign data_bus_3_w7_reg_scanin[24]=data_bus_3_w6_reg_scanout[24]; | |
3028 | assign data_bus_3_w0_reg_scanin[24]=data_bus_3_w7_reg_scanout[24]; | |
3029 | assign data_bus_3_w1_reg_scanin[24]=data_bus_3_w0_reg_scanout[24]; | |
3030 | assign data_bus_3_w4_reg_scanin[24]=data_bus_3_w1_reg_scanout[24]; | |
3031 | assign data_bus_3_w5_reg_scanin[24]=data_bus_3_w4_reg_scanout[24]; | |
3032 | ||
3033 | assign data_bus_3_w2_reg_scanin[23]=data_bus_3_w5_reg_scanout[24]; | |
3034 | assign data_bus_3_w3_reg_scanin[23]=data_bus_3_w2_reg_scanout[23]; | |
3035 | assign data_bus_3_w6_reg_scanin[23]=data_bus_3_w3_reg_scanout[23]; | |
3036 | assign data_bus_3_w7_reg_scanin[23]=data_bus_3_w6_reg_scanout[23]; | |
3037 | assign data_bus_3_w0_reg_scanin[23]=data_bus_3_w7_reg_scanout[23]; | |
3038 | assign data_bus_3_w1_reg_scanin[23]=data_bus_3_w0_reg_scanout[23]; | |
3039 | assign data_bus_3_w4_reg_scanin[23]=data_bus_3_w1_reg_scanout[23]; | |
3040 | assign data_bus_3_w5_reg_scanin[23]=data_bus_3_w4_reg_scanout[23]; | |
3041 | ||
3042 | assign data_bus_3_w2_reg_scanin[22]=data_bus_3_w5_reg_scanout[23]; | |
3043 | assign data_bus_3_w3_reg_scanin[22]=data_bus_3_w2_reg_scanout[22]; | |
3044 | assign data_bus_3_w6_reg_scanin[22]=data_bus_3_w3_reg_scanout[22]; | |
3045 | assign data_bus_3_w7_reg_scanin[22]=data_bus_3_w6_reg_scanout[22]; | |
3046 | assign data_bus_3_w0_reg_scanin[22]=data_bus_3_w7_reg_scanout[22]; | |
3047 | assign data_bus_3_w1_reg_scanin[22]=data_bus_3_w0_reg_scanout[22]; | |
3048 | assign data_bus_3_w4_reg_scanin[22]=data_bus_3_w1_reg_scanout[22]; | |
3049 | assign data_bus_3_w5_reg_scanin[22]=data_bus_3_w4_reg_scanout[22]; | |
3050 | ||
3051 | assign data_bus_3_w2_reg_scanin[21]=data_bus_3_w5_reg_scanout[22]; | |
3052 | assign data_bus_3_w3_reg_scanin[21]=data_bus_3_w2_reg_scanout[21]; | |
3053 | assign data_bus_3_w6_reg_scanin[21]=data_bus_3_w3_reg_scanout[21]; | |
3054 | assign data_bus_3_w7_reg_scanin[21]=data_bus_3_w6_reg_scanout[21]; | |
3055 | assign data_bus_3_w0_reg_scanin[21]=data_bus_3_w7_reg_scanout[21]; | |
3056 | assign data_bus_3_w1_reg_scanin[21]=data_bus_3_w0_reg_scanout[21]; | |
3057 | assign data_bus_3_w4_reg_scanin[21]=data_bus_3_w1_reg_scanout[21]; | |
3058 | assign data_bus_3_w5_reg_scanin[21]=data_bus_3_w4_reg_scanout[21]; | |
3059 | ||
3060 | assign data_bus_3_w2_reg_scanin[20]=data_bus_3_w5_reg_scanout[21]; | |
3061 | assign data_bus_3_w3_reg_scanin[20]=data_bus_3_w2_reg_scanout[20]; | |
3062 | assign data_bus_3_w6_reg_scanin[20]=data_bus_3_w3_reg_scanout[20]; | |
3063 | assign data_bus_3_w7_reg_scanin[20]=data_bus_3_w6_reg_scanout[20]; | |
3064 | assign data_bus_3_w0_reg_scanin[20]=data_bus_3_w7_reg_scanout[20]; | |
3065 | assign data_bus_3_w1_reg_scanin[20]=data_bus_3_w0_reg_scanout[20]; | |
3066 | assign data_bus_3_w4_reg_scanin[20]=data_bus_3_w1_reg_scanout[20]; | |
3067 | assign data_bus_3_w5_reg_scanin[20]=data_bus_3_w4_reg_scanout[20]; | |
3068 | ||
3069 | assign data_bus_3_w2_reg_scanin[19]=data_bus_3_w5_reg_scanout[20]; | |
3070 | assign data_bus_3_w3_reg_scanin[19]=data_bus_3_w2_reg_scanout[19]; | |
3071 | assign data_bus_3_w6_reg_scanin[19]=data_bus_3_w3_reg_scanout[19]; | |
3072 | assign data_bus_3_w7_reg_scanin[19]=data_bus_3_w6_reg_scanout[19]; | |
3073 | assign data_bus_3_w0_reg_scanin[19]=data_bus_3_w7_reg_scanout[19]; | |
3074 | assign data_bus_3_w1_reg_scanin[19]=data_bus_3_w0_reg_scanout[19]; | |
3075 | assign data_bus_3_w4_reg_scanin[19]=data_bus_3_w1_reg_scanout[19]; | |
3076 | assign data_bus_3_w5_reg_scanin[19]=data_bus_3_w4_reg_scanout[19]; | |
3077 | ||
3078 | assign data_bus_3_w2_reg_scanin[18]=data_bus_3_w5_reg_scanout[19]; | |
3079 | assign data_bus_3_w3_reg_scanin[18]=data_bus_3_w2_reg_scanout[18]; | |
3080 | assign data_bus_3_w6_reg_scanin[18]=data_bus_3_w3_reg_scanout[18]; | |
3081 | assign data_bus_3_w7_reg_scanin[18]=data_bus_3_w6_reg_scanout[18]; | |
3082 | assign data_bus_3_w0_reg_scanin[18]=data_bus_3_w7_reg_scanout[18]; | |
3083 | assign data_bus_3_w1_reg_scanin[18]=data_bus_3_w0_reg_scanout[18]; | |
3084 | assign data_bus_3_w4_reg_scanin[18]=data_bus_3_w1_reg_scanout[18]; | |
3085 | assign data_bus_3_w5_reg_scanin[18]=data_bus_3_w4_reg_scanout[18]; | |
3086 | ||
3087 | assign data_bus_3_w2_reg_scanin[17]=data_bus_3_w5_reg_scanout[18]; | |
3088 | assign data_bus_3_w3_reg_scanin[17]=data_bus_3_w2_reg_scanout[17]; | |
3089 | assign data_bus_3_w6_reg_scanin[17]=data_bus_3_w3_reg_scanout[17]; | |
3090 | assign data_bus_3_w7_reg_scanin[17]=data_bus_3_w6_reg_scanout[17]; | |
3091 | assign data_bus_3_w0_reg_scanin[17]=data_bus_3_w7_reg_scanout[17]; | |
3092 | assign data_bus_3_w1_reg_scanin[17]=data_bus_3_w0_reg_scanout[17]; | |
3093 | assign data_bus_3_w4_reg_scanin[17]=data_bus_3_w1_reg_scanout[17]; | |
3094 | assign data_bus_3_w5_reg_scanin[17]=data_bus_3_w4_reg_scanout[17]; | |
3095 | ||
3096 | assign data_bus_3_w0_reg_scanin[16]=data_bus_3_w5_reg_scanout[17]; | |
3097 | assign data_bus_3_w1_reg_scanin[16]=data_bus_3_w0_reg_scanout[16]; | |
3098 | assign data_bus_3_w4_reg_scanin[16]=data_bus_3_w1_reg_scanout[16]; | |
3099 | assign data_bus_3_w5_reg_scanin[16]=data_bus_3_w4_reg_scanout[16]; | |
3100 | assign data_bus_3_w2_reg_scanin[16]=data_bus_3_w5_reg_scanout[16]; | |
3101 | assign data_bus_3_w3_reg_scanin[16]=data_bus_3_w2_reg_scanout[16]; | |
3102 | assign data_bus_3_w6_reg_scanin[16]=data_bus_3_w3_reg_scanout[16]; | |
3103 | assign data_bus_3_w7_reg_scanin[16]=data_bus_3_w6_reg_scanout[16]; | |
3104 | ||
3105 | assign data_bus_3_w0_reg_scanin[15]=data_bus_3_w7_reg_scanout[16]; | |
3106 | assign data_bus_3_w1_reg_scanin[15]=data_bus_3_w0_reg_scanout[15]; | |
3107 | assign data_bus_3_w4_reg_scanin[15]=data_bus_3_w1_reg_scanout[15]; | |
3108 | assign data_bus_3_w5_reg_scanin[15]=data_bus_3_w4_reg_scanout[15]; | |
3109 | assign data_bus_3_w2_reg_scanin[15]=data_bus_3_w5_reg_scanout[15]; | |
3110 | assign data_bus_3_w3_reg_scanin[15]=data_bus_3_w2_reg_scanout[15]; | |
3111 | assign data_bus_3_w6_reg_scanin[15]=data_bus_3_w3_reg_scanout[15]; | |
3112 | assign data_bus_3_w7_reg_scanin[15]=data_bus_3_w6_reg_scanout[15]; | |
3113 | ||
3114 | assign data_bus_3_w0_reg_scanin[14]=data_bus_3_w7_reg_scanout[15]; | |
3115 | assign data_bus_3_w1_reg_scanin[14]=data_bus_3_w0_reg_scanout[14]; | |
3116 | assign data_bus_3_w4_reg_scanin[14]=data_bus_3_w1_reg_scanout[14]; | |
3117 | assign data_bus_3_w5_reg_scanin[14]=data_bus_3_w4_reg_scanout[14]; | |
3118 | assign data_bus_3_w2_reg_scanin[14]=data_bus_3_w5_reg_scanout[14]; | |
3119 | assign data_bus_3_w3_reg_scanin[14]=data_bus_3_w2_reg_scanout[14]; | |
3120 | assign data_bus_3_w6_reg_scanin[14]=data_bus_3_w3_reg_scanout[14]; | |
3121 | assign data_bus_3_w7_reg_scanin[14]=data_bus_3_w6_reg_scanout[14]; | |
3122 | ||
3123 | assign data_bus_3_w0_reg_scanin[13]=data_bus_3_w7_reg_scanout[14]; | |
3124 | assign data_bus_3_w1_reg_scanin[13]=data_bus_3_w0_reg_scanout[13]; | |
3125 | assign data_bus_3_w4_reg_scanin[13]=data_bus_3_w1_reg_scanout[13]; | |
3126 | assign data_bus_3_w5_reg_scanin[13]=data_bus_3_w4_reg_scanout[13]; | |
3127 | assign data_bus_3_w2_reg_scanin[13]=data_bus_3_w5_reg_scanout[13]; | |
3128 | assign data_bus_3_w3_reg_scanin[13]=data_bus_3_w2_reg_scanout[13]; | |
3129 | assign data_bus_3_w6_reg_scanin[13]=data_bus_3_w3_reg_scanout[13]; | |
3130 | assign data_bus_3_w7_reg_scanin[13]=data_bus_3_w6_reg_scanout[13]; | |
3131 | ||
3132 | assign data_bus_3_w0_reg_scanin[12]=data_bus_3_w7_reg_scanout[13]; | |
3133 | assign data_bus_3_w1_reg_scanin[12]=data_bus_3_w0_reg_scanout[12]; | |
3134 | assign data_bus_3_w4_reg_scanin[12]=data_bus_3_w1_reg_scanout[12]; | |
3135 | assign data_bus_3_w5_reg_scanin[12]=data_bus_3_w4_reg_scanout[12]; | |
3136 | assign data_bus_3_w2_reg_scanin[12]=data_bus_3_w5_reg_scanout[12]; | |
3137 | assign data_bus_3_w3_reg_scanin[12]=data_bus_3_w2_reg_scanout[12]; | |
3138 | assign data_bus_3_w6_reg_scanin[12]=data_bus_3_w3_reg_scanout[12]; | |
3139 | assign data_bus_3_w7_reg_scanin[12]=data_bus_3_w6_reg_scanout[12]; | |
3140 | ||
3141 | assign data_bus_3_w0_reg_scanin[11]=data_bus_3_w7_reg_scanout[12]; | |
3142 | assign data_bus_3_w1_reg_scanin[11]=data_bus_3_w0_reg_scanout[11]; | |
3143 | assign data_bus_3_w4_reg_scanin[11]=data_bus_3_w1_reg_scanout[11]; | |
3144 | assign data_bus_3_w5_reg_scanin[11]=data_bus_3_w4_reg_scanout[11]; | |
3145 | assign data_bus_3_w2_reg_scanin[11]=data_bus_3_w5_reg_scanout[11]; | |
3146 | assign data_bus_3_w3_reg_scanin[11]=data_bus_3_w2_reg_scanout[11]; | |
3147 | assign data_bus_3_w6_reg_scanin[11]=data_bus_3_w3_reg_scanout[11]; | |
3148 | assign data_bus_3_w7_reg_scanin[11]=data_bus_3_w6_reg_scanout[11]; | |
3149 | ||
3150 | assign data_bus_3_w0_reg_scanin[10]=data_bus_3_w7_reg_scanout[11]; | |
3151 | assign data_bus_3_w1_reg_scanin[10]=data_bus_3_w0_reg_scanout[10]; | |
3152 | assign data_bus_3_w4_reg_scanin[10]=data_bus_3_w1_reg_scanout[10]; | |
3153 | assign data_bus_3_w5_reg_scanin[10]=data_bus_3_w4_reg_scanout[10]; | |
3154 | assign data_bus_3_w2_reg_scanin[10]=data_bus_3_w5_reg_scanout[10]; | |
3155 | assign data_bus_3_w3_reg_scanin[10]=data_bus_3_w2_reg_scanout[10]; | |
3156 | assign data_bus_3_w6_reg_scanin[10]=data_bus_3_w3_reg_scanout[10]; | |
3157 | assign data_bus_3_w7_reg_scanin[10]=data_bus_3_w6_reg_scanout[10]; | |
3158 | ||
3159 | assign data_bus_3_w0_reg_scanin[9]=data_bus_3_w7_reg_scanout[10]; | |
3160 | assign data_bus_3_w1_reg_scanin[9]=data_bus_3_w0_reg_scanout[9]; | |
3161 | assign data_bus_3_w4_reg_scanin[9]=data_bus_3_w1_reg_scanout[9]; | |
3162 | assign data_bus_3_w5_reg_scanin[9]=data_bus_3_w4_reg_scanout[9]; | |
3163 | assign data_bus_3_w2_reg_scanin[9]=data_bus_3_w5_reg_scanout[9]; | |
3164 | assign data_bus_3_w3_reg_scanin[9]=data_bus_3_w2_reg_scanout[9]; | |
3165 | assign data_bus_3_w6_reg_scanin[9]=data_bus_3_w3_reg_scanout[9]; | |
3166 | assign data_bus_3_w7_reg_scanin[9]=data_bus_3_w6_reg_scanout[9]; | |
3167 | ||
3168 | assign data_bus_3_w0_reg_scanin[8]=data_bus_3_w7_reg_scanout[9]; | |
3169 | assign data_bus_3_w1_reg_scanin[8]=data_bus_3_w0_reg_scanout[8]; | |
3170 | assign data_bus_3_w4_reg_scanin[8]=data_bus_3_w1_reg_scanout[8]; | |
3171 | assign data_bus_3_w5_reg_scanin[8]=data_bus_3_w4_reg_scanout[8]; | |
3172 | assign data_bus_3_w2_reg_scanin[8]=data_bus_3_w5_reg_scanout[8]; | |
3173 | assign data_bus_3_w3_reg_scanin[8]=data_bus_3_w2_reg_scanout[8]; | |
3174 | assign data_bus_3_w6_reg_scanin[8]=data_bus_3_w3_reg_scanout[8]; | |
3175 | assign data_bus_3_w7_reg_scanin[8]=data_bus_3_w6_reg_scanout[8]; | |
3176 | ||
3177 | assign data_bus_3_w0_reg_scanin[7]=data_bus_3_w7_reg_scanout[8]; | |
3178 | assign data_bus_3_w1_reg_scanin[7]=data_bus_3_w0_reg_scanout[7]; | |
3179 | assign data_bus_3_w4_reg_scanin[7]=data_bus_3_w1_reg_scanout[7]; | |
3180 | assign data_bus_3_w5_reg_scanin[7]=data_bus_3_w4_reg_scanout[7]; | |
3181 | assign data_bus_3_w2_reg_scanin[7]=data_bus_3_w5_reg_scanout[7]; | |
3182 | assign data_bus_3_w3_reg_scanin[7]=data_bus_3_w2_reg_scanout[7]; | |
3183 | assign data_bus_3_w6_reg_scanin[7]=data_bus_3_w3_reg_scanout[7]; | |
3184 | assign data_bus_3_w7_reg_scanin[7]=data_bus_3_w6_reg_scanout[7]; | |
3185 | ||
3186 | assign data_bus_3_w0_reg_scanin[6]=data_bus_3_w7_reg_scanout[7]; | |
3187 | assign data_bus_3_w1_reg_scanin[6]=data_bus_3_w0_reg_scanout[6]; | |
3188 | assign data_bus_3_w4_reg_scanin[6]=data_bus_3_w1_reg_scanout[6]; | |
3189 | assign data_bus_3_w5_reg_scanin[6]=data_bus_3_w4_reg_scanout[6]; | |
3190 | assign data_bus_3_w2_reg_scanin[6]=data_bus_3_w5_reg_scanout[6]; | |
3191 | assign data_bus_3_w3_reg_scanin[6]=data_bus_3_w2_reg_scanout[6]; | |
3192 | assign data_bus_3_w6_reg_scanin[6]=data_bus_3_w3_reg_scanout[6]; | |
3193 | assign data_bus_3_w7_reg_scanin[6]=data_bus_3_w6_reg_scanout[6]; | |
3194 | ||
3195 | assign data_bus_3_w0_reg_scanin[5]=data_bus_3_w7_reg_scanout[6]; | |
3196 | assign data_bus_3_w1_reg_scanin[5]=data_bus_3_w0_reg_scanout[5]; | |
3197 | assign data_bus_3_w4_reg_scanin[5]=data_bus_3_w1_reg_scanout[5]; | |
3198 | assign data_bus_3_w5_reg_scanin[5]=data_bus_3_w4_reg_scanout[5]; | |
3199 | assign data_bus_3_w2_reg_scanin[5]=data_bus_3_w5_reg_scanout[5]; | |
3200 | assign data_bus_3_w3_reg_scanin[5]=data_bus_3_w2_reg_scanout[5]; | |
3201 | assign data_bus_3_w6_reg_scanin[5]=data_bus_3_w3_reg_scanout[5]; | |
3202 | assign data_bus_3_w7_reg_scanin[5]=data_bus_3_w6_reg_scanout[5]; | |
3203 | ||
3204 | assign data_bus_3_w0_reg_scanin[4]=data_bus_3_w7_reg_scanout[5]; | |
3205 | assign data_bus_3_w1_reg_scanin[4]=data_bus_3_w0_reg_scanout[4]; | |
3206 | assign data_bus_3_w4_reg_scanin[4]=data_bus_3_w1_reg_scanout[4]; | |
3207 | assign data_bus_3_w5_reg_scanin[4]=data_bus_3_w4_reg_scanout[4]; | |
3208 | assign data_bus_3_w2_reg_scanin[4]=data_bus_3_w5_reg_scanout[4]; | |
3209 | assign data_bus_3_w3_reg_scanin[4]=data_bus_3_w2_reg_scanout[4]; | |
3210 | assign data_bus_3_w6_reg_scanin[4]=data_bus_3_w3_reg_scanout[4]; | |
3211 | assign data_bus_3_w7_reg_scanin[4]=data_bus_3_w6_reg_scanout[4]; | |
3212 | ||
3213 | assign data_bus_3_w0_reg_scanin[3]=data_bus_3_w7_reg_scanout[4]; | |
3214 | assign data_bus_3_w1_reg_scanin[3]=data_bus_3_w0_reg_scanout[3]; | |
3215 | assign data_bus_3_w4_reg_scanin[3]=data_bus_3_w1_reg_scanout[3]; | |
3216 | assign data_bus_3_w5_reg_scanin[3]=data_bus_3_w4_reg_scanout[3]; | |
3217 | assign data_bus_3_w2_reg_scanin[3]=data_bus_3_w5_reg_scanout[3]; | |
3218 | assign data_bus_3_w3_reg_scanin[3]=data_bus_3_w2_reg_scanout[3]; | |
3219 | assign data_bus_3_w6_reg_scanin[3]=data_bus_3_w3_reg_scanout[3]; | |
3220 | assign data_bus_3_w7_reg_scanin[3]=data_bus_3_w6_reg_scanout[3]; | |
3221 | ||
3222 | assign data_bus_3_w0_reg_scanin[2]=data_bus_3_w7_reg_scanout[3]; | |
3223 | assign data_bus_3_w1_reg_scanin[2]=data_bus_3_w0_reg_scanout[2]; | |
3224 | assign data_bus_3_w4_reg_scanin[2]=data_bus_3_w1_reg_scanout[2]; | |
3225 | assign data_bus_3_w5_reg_scanin[2]=data_bus_3_w4_reg_scanout[2]; | |
3226 | assign data_bus_3_w2_reg_scanin[2]=data_bus_3_w5_reg_scanout[2]; | |
3227 | assign data_bus_3_w3_reg_scanin[2]=data_bus_3_w2_reg_scanout[2]; | |
3228 | assign data_bus_3_w6_reg_scanin[2]=data_bus_3_w3_reg_scanout[2]; | |
3229 | assign data_bus_3_w7_reg_scanin[2]=data_bus_3_w6_reg_scanout[2]; | |
3230 | ||
3231 | assign data_bus_3_w0_reg_scanin[1]=data_bus_3_w7_reg_scanout[2]; | |
3232 | assign data_bus_3_w1_reg_scanin[1]=data_bus_3_w0_reg_scanout[1]; | |
3233 | assign data_bus_3_w4_reg_scanin[1]=data_bus_3_w1_reg_scanout[1]; | |
3234 | assign data_bus_3_w5_reg_scanin[1]=data_bus_3_w4_reg_scanout[1]; | |
3235 | assign data_bus_3_w2_reg_scanin[1]=data_bus_3_w5_reg_scanout[1]; | |
3236 | assign data_bus_3_w3_reg_scanin[1]=data_bus_3_w2_reg_scanout[1]; | |
3237 | assign data_bus_3_w6_reg_scanin[1]=data_bus_3_w3_reg_scanout[1]; | |
3238 | assign data_bus_3_w7_reg_scanin[1]=data_bus_3_w6_reg_scanout[1]; | |
3239 | ||
3240 | assign data_bus_3_w0_reg_scanin[0]=data_bus_3_w7_reg_scanout[1]; | |
3241 | assign data_bus_3_w1_reg_scanin[0]=data_bus_3_w0_reg_scanout[0]; | |
3242 | assign data_bus_3_w4_reg_scanin[0]=data_bus_3_w1_reg_scanout[0]; | |
3243 | assign data_bus_3_w5_reg_scanin[0]=data_bus_3_w4_reg_scanout[0]; | |
3244 | assign data_bus_3_w2_reg_scanin[0]=data_bus_3_w5_reg_scanout[0]; | |
3245 | assign data_bus_3_w3_reg_scanin[0]=data_bus_3_w2_reg_scanout[0]; | |
3246 | assign data_bus_3_w6_reg_scanin[0]=data_bus_3_w3_reg_scanout[0]; | |
3247 | assign data_bus_3_w7_reg_scanin[0]=data_bus_3_w6_reg_scanout[0]; | |
3248 | ||
3249 | ||
3250 | // ***************************END SECTION*************************** | |
3251 | assign wrdata_q2_6_scanin[32]=data_bus_3_w7_reg_scanout[0]; | |
3252 | assign wrdata_q2_2_scanin[32]=wrdata_q2_6_scanout[32]; | |
3253 | assign wrdata_q2_6_scanin[31]=wrdata_q2_2_scanout[32]; | |
3254 | assign wrdata_q2_2_scanin[31]=wrdata_q2_6_scanout[31]; | |
3255 | assign wrdata_q2_6_scanin[30]=wrdata_q2_2_scanout[31]; | |
3256 | assign wrdata_q2_2_scanin[30]=wrdata_q2_6_scanout[30]; | |
3257 | assign wrdata_q2_6_scanin[29]=wrdata_q2_2_scanout[30]; | |
3258 | assign wrdata_q2_2_scanin[29]=wrdata_q2_6_scanout[29]; | |
3259 | assign wrdata_q2_6_scanin[28]=wrdata_q2_2_scanout[29]; | |
3260 | assign wrdata_q2_2_scanin[28]=wrdata_q2_6_scanout[28]; | |
3261 | assign wrdata_q2_6_scanin[27]=wrdata_q2_2_scanout[28]; | |
3262 | assign wrdata_q2_2_scanin[27]=wrdata_q2_6_scanout[27]; | |
3263 | assign wrdata_q2_6_scanin[26]=wrdata_q2_2_scanout[27]; | |
3264 | assign wrdata_q2_2_scanin[26]=wrdata_q2_6_scanout[26]; | |
3265 | assign wrdata_q2_6_scanin[25]=wrdata_q2_2_scanout[26]; | |
3266 | assign wrdata_q2_2_scanin[25]=wrdata_q2_6_scanout[25]; | |
3267 | assign wrdata_q2_6_scanin[24]=wrdata_q2_2_scanout[25]; | |
3268 | assign wrdata_q2_2_scanin[24]=wrdata_q2_6_scanout[24]; | |
3269 | assign wrdata_q2_6_scanin[23]=wrdata_q2_2_scanout[24]; | |
3270 | assign wrdata_q2_2_scanin[23]=wrdata_q2_6_scanout[23]; | |
3271 | assign wrdata_q2_6_scanin[22]=wrdata_q2_2_scanout[23]; | |
3272 | assign wrdata_q2_2_scanin[22]=wrdata_q2_6_scanout[22]; | |
3273 | assign wrdata_q2_6_scanin[21]=wrdata_q2_2_scanout[22]; | |
3274 | assign wrdata_q2_2_scanin[21]=wrdata_q2_6_scanout[21]; | |
3275 | assign wrdata_q2_6_scanin[20]=wrdata_q2_2_scanout[21]; | |
3276 | assign wrdata_q2_2_scanin[20]=wrdata_q2_6_scanout[20]; | |
3277 | assign wrdata_q2_6_scanin[19]=wrdata_q2_2_scanout[20]; | |
3278 | assign wrdata_q2_2_scanin[19]=wrdata_q2_6_scanout[19]; | |
3279 | assign wrdata_q2_6_scanin[18]=wrdata_q2_2_scanout[19]; | |
3280 | assign wrdata_q2_2_scanin[18]=wrdata_q2_6_scanout[18]; | |
3281 | assign wrdata_q2_6_scanin[17]=wrdata_q2_2_scanout[18]; | |
3282 | assign wrdata_q2_2_scanin[17]=wrdata_q2_6_scanout[17]; | |
3283 | assign wrdata_q2_6_scanin[16]=wrdata_q2_2_scanout[17]; | |
3284 | assign wrdata_q2_2_scanin[16]=wrdata_q2_6_scanout[16]; | |
3285 | assign wrdata_q2_6_scanin[15]=wrdata_q2_2_scanout[16]; | |
3286 | assign wrdata_q2_2_scanin[15]=wrdata_q2_6_scanout[15]; | |
3287 | assign wrdata_q2_6_scanin[14]=wrdata_q2_2_scanout[15]; | |
3288 | assign wrdata_q2_2_scanin[14]=wrdata_q2_6_scanout[14]; | |
3289 | assign wrdata_q2_6_scanin[13]=wrdata_q2_2_scanout[14]; | |
3290 | assign wrdata_q2_2_scanin[13]=wrdata_q2_6_scanout[13]; | |
3291 | assign wrdata_q2_6_scanin[12]=wrdata_q2_2_scanout[13]; | |
3292 | assign wrdata_q2_2_scanin[12]=wrdata_q2_6_scanout[12]; | |
3293 | assign wrdata_q2_6_scanin[11]=wrdata_q2_2_scanout[12]; | |
3294 | assign wrdata_q2_2_scanin[11]=wrdata_q2_6_scanout[11]; | |
3295 | assign wrdata_q2_6_scanin[10]=wrdata_q2_2_scanout[11]; | |
3296 | assign wrdata_q2_2_scanin[10]=wrdata_q2_6_scanout[10]; | |
3297 | assign wrdata_q2_6_scanin[9]=wrdata_q2_2_scanout[10]; | |
3298 | assign wrdata_q2_2_scanin[9]=wrdata_q2_6_scanout[9]; | |
3299 | assign wrdata_q2_6_scanin[8]=wrdata_q2_2_scanout[9]; | |
3300 | assign wrdata_q2_2_scanin[8]=wrdata_q2_6_scanout[8]; | |
3301 | assign wrdata_q2_6_scanin[7]=wrdata_q2_2_scanout[8]; | |
3302 | assign wrdata_q2_2_scanin[7]=wrdata_q2_6_scanout[7]; | |
3303 | assign wrdata_q2_6_scanin[6]=wrdata_q2_2_scanout[7]; | |
3304 | assign wrdata_q2_2_scanin[6]=wrdata_q2_6_scanout[6]; | |
3305 | assign wrdata_q2_6_scanin[5]=wrdata_q2_2_scanout[6]; | |
3306 | assign wrdata_q2_2_scanin[5]=wrdata_q2_6_scanout[5]; | |
3307 | assign wrdata_q2_6_scanin[4]=wrdata_q2_2_scanout[5]; | |
3308 | assign wrdata_q2_2_scanin[4]=wrdata_q2_6_scanout[4]; | |
3309 | assign wrdata_q2_6_scanin[3]=wrdata_q2_2_scanout[4]; | |
3310 | assign wrdata_q2_2_scanin[3]=wrdata_q2_6_scanout[3]; | |
3311 | assign wrdata_q2_6_scanin[2]=wrdata_q2_2_scanout[3]; | |
3312 | assign wrdata_q2_2_scanin[2]=wrdata_q2_6_scanout[2]; | |
3313 | assign wrdata_q2_6_scanin[1]=wrdata_q2_2_scanout[2]; | |
3314 | assign wrdata_q2_2_scanin[1]=wrdata_q2_6_scanout[1]; | |
3315 | assign wrdata_q2_6_scanin[0]=wrdata_q2_2_scanout[1]; | |
3316 | assign wrdata_q2_2_scanin[0]=wrdata_q2_6_scanout[0]; | |
3317 | ||
3318 | // ***************************BEGIN SECTION************************* | |
3319 | ||
3320 | assign data_bus_2_w2_reg_scanin[32]=wrdata_q2_2_scanout[0]; | |
3321 | assign data_bus_2_w3_reg_scanin[32]=data_bus_2_w2_reg_scanout[32]; | |
3322 | assign data_bus_2_w6_reg_scanin[32]=data_bus_2_w3_reg_scanout[32]; | |
3323 | assign data_bus_2_w7_reg_scanin[32]=data_bus_2_w6_reg_scanout[32]; | |
3324 | assign data_bus_2_w0_reg_scanin[32]=data_bus_2_w7_reg_scanout[32]; | |
3325 | assign data_bus_2_w1_reg_scanin[32]=data_bus_2_w0_reg_scanout[32]; | |
3326 | assign data_bus_2_w4_reg_scanin[32]=data_bus_2_w1_reg_scanout[32]; | |
3327 | assign data_bus_2_w5_reg_scanin[32]=data_bus_2_w4_reg_scanout[32]; | |
3328 | ||
3329 | assign data_bus_2_w2_reg_scanin[31]=data_bus_2_w5_reg_scanout[32]; | |
3330 | assign data_bus_2_w3_reg_scanin[31]=data_bus_2_w2_reg_scanout[31]; | |
3331 | assign data_bus_2_w6_reg_scanin[31]=data_bus_2_w3_reg_scanout[31]; | |
3332 | assign data_bus_2_w7_reg_scanin[31]=data_bus_2_w6_reg_scanout[31]; | |
3333 | assign data_bus_2_w0_reg_scanin[31]=data_bus_2_w7_reg_scanout[31]; | |
3334 | assign data_bus_2_w1_reg_scanin[31]=data_bus_2_w0_reg_scanout[31]; | |
3335 | assign data_bus_2_w4_reg_scanin[31]=data_bus_2_w1_reg_scanout[31]; | |
3336 | assign data_bus_2_w5_reg_scanin[31]=data_bus_2_w4_reg_scanout[31]; | |
3337 | ||
3338 | assign data_bus_2_w2_reg_scanin[30]=data_bus_2_w5_reg_scanout[31]; | |
3339 | assign data_bus_2_w3_reg_scanin[30]=data_bus_2_w2_reg_scanout[30]; | |
3340 | assign data_bus_2_w6_reg_scanin[30]=data_bus_2_w3_reg_scanout[30]; | |
3341 | assign data_bus_2_w7_reg_scanin[30]=data_bus_2_w6_reg_scanout[30]; | |
3342 | assign data_bus_2_w0_reg_scanin[30]=data_bus_2_w7_reg_scanout[30]; | |
3343 | assign data_bus_2_w1_reg_scanin[30]=data_bus_2_w0_reg_scanout[30]; | |
3344 | assign data_bus_2_w4_reg_scanin[30]=data_bus_2_w1_reg_scanout[30]; | |
3345 | assign data_bus_2_w5_reg_scanin[30]=data_bus_2_w4_reg_scanout[30]; | |
3346 | ||
3347 | assign data_bus_2_w2_reg_scanin[29]=data_bus_2_w5_reg_scanout[30]; | |
3348 | assign data_bus_2_w3_reg_scanin[29]=data_bus_2_w2_reg_scanout[29]; | |
3349 | assign data_bus_2_w6_reg_scanin[29]=data_bus_2_w3_reg_scanout[29]; | |
3350 | assign data_bus_2_w7_reg_scanin[29]=data_bus_2_w6_reg_scanout[29]; | |
3351 | assign data_bus_2_w0_reg_scanin[29]=data_bus_2_w7_reg_scanout[29]; | |
3352 | assign data_bus_2_w1_reg_scanin[29]=data_bus_2_w0_reg_scanout[29]; | |
3353 | assign data_bus_2_w4_reg_scanin[29]=data_bus_2_w1_reg_scanout[29]; | |
3354 | assign data_bus_2_w5_reg_scanin[29]=data_bus_2_w4_reg_scanout[29]; | |
3355 | ||
3356 | assign data_bus_2_w2_reg_scanin[28]=data_bus_2_w5_reg_scanout[29]; | |
3357 | assign data_bus_2_w3_reg_scanin[28]=data_bus_2_w2_reg_scanout[28]; | |
3358 | assign data_bus_2_w6_reg_scanin[28]=data_bus_2_w3_reg_scanout[28]; | |
3359 | assign data_bus_2_w7_reg_scanin[28]=data_bus_2_w6_reg_scanout[28]; | |
3360 | assign data_bus_2_w0_reg_scanin[28]=data_bus_2_w7_reg_scanout[28]; | |
3361 | assign data_bus_2_w1_reg_scanin[28]=data_bus_2_w0_reg_scanout[28]; | |
3362 | assign data_bus_2_w4_reg_scanin[28]=data_bus_2_w1_reg_scanout[28]; | |
3363 | assign data_bus_2_w5_reg_scanin[28]=data_bus_2_w4_reg_scanout[28]; | |
3364 | ||
3365 | assign data_bus_2_w2_reg_scanin[27]=data_bus_2_w5_reg_scanout[28]; | |
3366 | assign data_bus_2_w3_reg_scanin[27]=data_bus_2_w2_reg_scanout[27]; | |
3367 | assign data_bus_2_w6_reg_scanin[27]=data_bus_2_w3_reg_scanout[27]; | |
3368 | assign data_bus_2_w7_reg_scanin[27]=data_bus_2_w6_reg_scanout[27]; | |
3369 | assign data_bus_2_w0_reg_scanin[27]=data_bus_2_w7_reg_scanout[27]; | |
3370 | assign data_bus_2_w1_reg_scanin[27]=data_bus_2_w0_reg_scanout[27]; | |
3371 | assign data_bus_2_w4_reg_scanin[27]=data_bus_2_w1_reg_scanout[27]; | |
3372 | assign data_bus_2_w5_reg_scanin[27]=data_bus_2_w4_reg_scanout[27]; | |
3373 | ||
3374 | assign data_bus_2_w2_reg_scanin[26]=data_bus_2_w5_reg_scanout[27]; | |
3375 | assign data_bus_2_w3_reg_scanin[26]=data_bus_2_w2_reg_scanout[26]; | |
3376 | assign data_bus_2_w6_reg_scanin[26]=data_bus_2_w3_reg_scanout[26]; | |
3377 | assign data_bus_2_w7_reg_scanin[26]=data_bus_2_w6_reg_scanout[26]; | |
3378 | assign data_bus_2_w0_reg_scanin[26]=data_bus_2_w7_reg_scanout[26]; | |
3379 | assign data_bus_2_w1_reg_scanin[26]=data_bus_2_w0_reg_scanout[26]; | |
3380 | assign data_bus_2_w4_reg_scanin[26]=data_bus_2_w1_reg_scanout[26]; | |
3381 | assign data_bus_2_w5_reg_scanin[26]=data_bus_2_w4_reg_scanout[26]; | |
3382 | ||
3383 | assign data_bus_2_w2_reg_scanin[25]=data_bus_2_w5_reg_scanout[26]; | |
3384 | assign data_bus_2_w3_reg_scanin[25]=data_bus_2_w2_reg_scanout[25]; | |
3385 | assign data_bus_2_w6_reg_scanin[25]=data_bus_2_w3_reg_scanout[25]; | |
3386 | assign data_bus_2_w7_reg_scanin[25]=data_bus_2_w6_reg_scanout[25]; | |
3387 | assign data_bus_2_w0_reg_scanin[25]=data_bus_2_w7_reg_scanout[25]; | |
3388 | assign data_bus_2_w1_reg_scanin[25]=data_bus_2_w0_reg_scanout[25]; | |
3389 | assign data_bus_2_w4_reg_scanin[25]=data_bus_2_w1_reg_scanout[25]; | |
3390 | assign data_bus_2_w5_reg_scanin[25]=data_bus_2_w4_reg_scanout[25]; | |
3391 | ||
3392 | assign data_bus_2_w2_reg_scanin[24]=data_bus_2_w5_reg_scanout[25]; | |
3393 | assign data_bus_2_w3_reg_scanin[24]=data_bus_2_w2_reg_scanout[24]; | |
3394 | assign data_bus_2_w6_reg_scanin[24]=data_bus_2_w3_reg_scanout[24]; | |
3395 | assign data_bus_2_w7_reg_scanin[24]=data_bus_2_w6_reg_scanout[24]; | |
3396 | assign data_bus_2_w0_reg_scanin[24]=data_bus_2_w7_reg_scanout[24]; | |
3397 | assign data_bus_2_w1_reg_scanin[24]=data_bus_2_w0_reg_scanout[24]; | |
3398 | assign data_bus_2_w4_reg_scanin[24]=data_bus_2_w1_reg_scanout[24]; | |
3399 | assign data_bus_2_w5_reg_scanin[24]=data_bus_2_w4_reg_scanout[24]; | |
3400 | ||
3401 | assign data_bus_2_w2_reg_scanin[23]=data_bus_2_w5_reg_scanout[24]; | |
3402 | assign data_bus_2_w3_reg_scanin[23]=data_bus_2_w2_reg_scanout[23]; | |
3403 | assign data_bus_2_w6_reg_scanin[23]=data_bus_2_w3_reg_scanout[23]; | |
3404 | assign data_bus_2_w7_reg_scanin[23]=data_bus_2_w6_reg_scanout[23]; | |
3405 | assign data_bus_2_w0_reg_scanin[23]=data_bus_2_w7_reg_scanout[23]; | |
3406 | assign data_bus_2_w1_reg_scanin[23]=data_bus_2_w0_reg_scanout[23]; | |
3407 | assign data_bus_2_w4_reg_scanin[23]=data_bus_2_w1_reg_scanout[23]; | |
3408 | assign data_bus_2_w5_reg_scanin[23]=data_bus_2_w4_reg_scanout[23]; | |
3409 | ||
3410 | assign data_bus_2_w2_reg_scanin[22]=data_bus_2_w5_reg_scanout[23]; | |
3411 | assign data_bus_2_w3_reg_scanin[22]=data_bus_2_w2_reg_scanout[22]; | |
3412 | assign data_bus_2_w6_reg_scanin[22]=data_bus_2_w3_reg_scanout[22]; | |
3413 | assign data_bus_2_w7_reg_scanin[22]=data_bus_2_w6_reg_scanout[22]; | |
3414 | assign data_bus_2_w0_reg_scanin[22]=data_bus_2_w7_reg_scanout[22]; | |
3415 | assign data_bus_2_w1_reg_scanin[22]=data_bus_2_w0_reg_scanout[22]; | |
3416 | assign data_bus_2_w4_reg_scanin[22]=data_bus_2_w1_reg_scanout[22]; | |
3417 | assign data_bus_2_w5_reg_scanin[22]=data_bus_2_w4_reg_scanout[22]; | |
3418 | ||
3419 | assign data_bus_2_w2_reg_scanin[21]=data_bus_2_w5_reg_scanout[22]; | |
3420 | assign data_bus_2_w3_reg_scanin[21]=data_bus_2_w2_reg_scanout[21]; | |
3421 | assign data_bus_2_w6_reg_scanin[21]=data_bus_2_w3_reg_scanout[21]; | |
3422 | assign data_bus_2_w7_reg_scanin[21]=data_bus_2_w6_reg_scanout[21]; | |
3423 | assign data_bus_2_w0_reg_scanin[21]=data_bus_2_w7_reg_scanout[21]; | |
3424 | assign data_bus_2_w1_reg_scanin[21]=data_bus_2_w0_reg_scanout[21]; | |
3425 | assign data_bus_2_w4_reg_scanin[21]=data_bus_2_w1_reg_scanout[21]; | |
3426 | assign data_bus_2_w5_reg_scanin[21]=data_bus_2_w4_reg_scanout[21]; | |
3427 | ||
3428 | assign data_bus_2_w2_reg_scanin[20]=data_bus_2_w5_reg_scanout[21]; | |
3429 | assign data_bus_2_w3_reg_scanin[20]=data_bus_2_w2_reg_scanout[20]; | |
3430 | assign data_bus_2_w6_reg_scanin[20]=data_bus_2_w3_reg_scanout[20]; | |
3431 | assign data_bus_2_w7_reg_scanin[20]=data_bus_2_w6_reg_scanout[20]; | |
3432 | assign data_bus_2_w0_reg_scanin[20]=data_bus_2_w7_reg_scanout[20]; | |
3433 | assign data_bus_2_w1_reg_scanin[20]=data_bus_2_w0_reg_scanout[20]; | |
3434 | assign data_bus_2_w4_reg_scanin[20]=data_bus_2_w1_reg_scanout[20]; | |
3435 | assign data_bus_2_w5_reg_scanin[20]=data_bus_2_w4_reg_scanout[20]; | |
3436 | ||
3437 | assign data_bus_2_w2_reg_scanin[19]=data_bus_2_w5_reg_scanout[20]; | |
3438 | assign data_bus_2_w3_reg_scanin[19]=data_bus_2_w2_reg_scanout[19]; | |
3439 | assign data_bus_2_w6_reg_scanin[19]=data_bus_2_w3_reg_scanout[19]; | |
3440 | assign data_bus_2_w7_reg_scanin[19]=data_bus_2_w6_reg_scanout[19]; | |
3441 | assign data_bus_2_w0_reg_scanin[19]=data_bus_2_w7_reg_scanout[19]; | |
3442 | assign data_bus_2_w1_reg_scanin[19]=data_bus_2_w0_reg_scanout[19]; | |
3443 | assign data_bus_2_w4_reg_scanin[19]=data_bus_2_w1_reg_scanout[19]; | |
3444 | assign data_bus_2_w5_reg_scanin[19]=data_bus_2_w4_reg_scanout[19]; | |
3445 | ||
3446 | assign data_bus_2_w2_reg_scanin[18]=data_bus_2_w5_reg_scanout[19]; | |
3447 | assign data_bus_2_w3_reg_scanin[18]=data_bus_2_w2_reg_scanout[18]; | |
3448 | assign data_bus_2_w6_reg_scanin[18]=data_bus_2_w3_reg_scanout[18]; | |
3449 | assign data_bus_2_w7_reg_scanin[18]=data_bus_2_w6_reg_scanout[18]; | |
3450 | assign data_bus_2_w0_reg_scanin[18]=data_bus_2_w7_reg_scanout[18]; | |
3451 | assign data_bus_2_w1_reg_scanin[18]=data_bus_2_w0_reg_scanout[18]; | |
3452 | assign data_bus_2_w4_reg_scanin[18]=data_bus_2_w1_reg_scanout[18]; | |
3453 | assign data_bus_2_w5_reg_scanin[18]=data_bus_2_w4_reg_scanout[18]; | |
3454 | ||
3455 | assign data_bus_2_w2_reg_scanin[17]=data_bus_2_w5_reg_scanout[18]; | |
3456 | assign data_bus_2_w3_reg_scanin[17]=data_bus_2_w2_reg_scanout[17]; | |
3457 | assign data_bus_2_w6_reg_scanin[17]=data_bus_2_w3_reg_scanout[17]; | |
3458 | assign data_bus_2_w7_reg_scanin[17]=data_bus_2_w6_reg_scanout[17]; | |
3459 | assign data_bus_2_w0_reg_scanin[17]=data_bus_2_w7_reg_scanout[17]; | |
3460 | assign data_bus_2_w1_reg_scanin[17]=data_bus_2_w0_reg_scanout[17]; | |
3461 | assign data_bus_2_w4_reg_scanin[17]=data_bus_2_w1_reg_scanout[17]; | |
3462 | assign data_bus_2_w5_reg_scanin[17]=data_bus_2_w4_reg_scanout[17]; | |
3463 | ||
3464 | assign data_bus_2_w0_reg_scanin[16]=data_bus_2_w5_reg_scanout[17]; | |
3465 | assign data_bus_2_w1_reg_scanin[16]=data_bus_2_w0_reg_scanout[16]; | |
3466 | assign data_bus_2_w4_reg_scanin[16]=data_bus_2_w1_reg_scanout[16]; | |
3467 | assign data_bus_2_w5_reg_scanin[16]=data_bus_2_w4_reg_scanout[16]; | |
3468 | assign data_bus_2_w2_reg_scanin[16]=data_bus_2_w5_reg_scanout[16]; | |
3469 | assign data_bus_2_w3_reg_scanin[16]=data_bus_2_w2_reg_scanout[16]; | |
3470 | assign data_bus_2_w6_reg_scanin[16]=data_bus_2_w3_reg_scanout[16]; | |
3471 | assign data_bus_2_w7_reg_scanin[16]=data_bus_2_w6_reg_scanout[16]; | |
3472 | ||
3473 | assign data_bus_2_w0_reg_scanin[15]=data_bus_2_w7_reg_scanout[16]; | |
3474 | assign data_bus_2_w1_reg_scanin[15]=data_bus_2_w0_reg_scanout[15]; | |
3475 | assign data_bus_2_w4_reg_scanin[15]=data_bus_2_w1_reg_scanout[15]; | |
3476 | assign data_bus_2_w5_reg_scanin[15]=data_bus_2_w4_reg_scanout[15]; | |
3477 | assign data_bus_2_w2_reg_scanin[15]=data_bus_2_w5_reg_scanout[15]; | |
3478 | assign data_bus_2_w3_reg_scanin[15]=data_bus_2_w2_reg_scanout[15]; | |
3479 | assign data_bus_2_w6_reg_scanin[15]=data_bus_2_w3_reg_scanout[15]; | |
3480 | assign data_bus_2_w7_reg_scanin[15]=data_bus_2_w6_reg_scanout[15]; | |
3481 | ||
3482 | assign data_bus_2_w0_reg_scanin[14]=data_bus_2_w7_reg_scanout[15]; | |
3483 | assign data_bus_2_w1_reg_scanin[14]=data_bus_2_w0_reg_scanout[14]; | |
3484 | assign data_bus_2_w4_reg_scanin[14]=data_bus_2_w1_reg_scanout[14]; | |
3485 | assign data_bus_2_w5_reg_scanin[14]=data_bus_2_w4_reg_scanout[14]; | |
3486 | assign data_bus_2_w2_reg_scanin[14]=data_bus_2_w5_reg_scanout[14]; | |
3487 | assign data_bus_2_w3_reg_scanin[14]=data_bus_2_w2_reg_scanout[14]; | |
3488 | assign data_bus_2_w6_reg_scanin[14]=data_bus_2_w3_reg_scanout[14]; | |
3489 | assign data_bus_2_w7_reg_scanin[14]=data_bus_2_w6_reg_scanout[14]; | |
3490 | ||
3491 | assign data_bus_2_w0_reg_scanin[13]=data_bus_2_w7_reg_scanout[14]; | |
3492 | assign data_bus_2_w1_reg_scanin[13]=data_bus_2_w0_reg_scanout[13]; | |
3493 | assign data_bus_2_w4_reg_scanin[13]=data_bus_2_w1_reg_scanout[13]; | |
3494 | assign data_bus_2_w5_reg_scanin[13]=data_bus_2_w4_reg_scanout[13]; | |
3495 | assign data_bus_2_w2_reg_scanin[13]=data_bus_2_w5_reg_scanout[13]; | |
3496 | assign data_bus_2_w3_reg_scanin[13]=data_bus_2_w2_reg_scanout[13]; | |
3497 | assign data_bus_2_w6_reg_scanin[13]=data_bus_2_w3_reg_scanout[13]; | |
3498 | assign data_bus_2_w7_reg_scanin[13]=data_bus_2_w6_reg_scanout[13]; | |
3499 | ||
3500 | assign data_bus_2_w0_reg_scanin[12]=data_bus_2_w7_reg_scanout[13]; | |
3501 | assign data_bus_2_w1_reg_scanin[12]=data_bus_2_w0_reg_scanout[12]; | |
3502 | assign data_bus_2_w4_reg_scanin[12]=data_bus_2_w1_reg_scanout[12]; | |
3503 | assign data_bus_2_w5_reg_scanin[12]=data_bus_2_w4_reg_scanout[12]; | |
3504 | assign data_bus_2_w2_reg_scanin[12]=data_bus_2_w5_reg_scanout[12]; | |
3505 | assign data_bus_2_w3_reg_scanin[12]=data_bus_2_w2_reg_scanout[12]; | |
3506 | assign data_bus_2_w6_reg_scanin[12]=data_bus_2_w3_reg_scanout[12]; | |
3507 | assign data_bus_2_w7_reg_scanin[12]=data_bus_2_w6_reg_scanout[12]; | |
3508 | ||
3509 | assign data_bus_2_w0_reg_scanin[11]=data_bus_2_w7_reg_scanout[12]; | |
3510 | assign data_bus_2_w1_reg_scanin[11]=data_bus_2_w0_reg_scanout[11]; | |
3511 | assign data_bus_2_w4_reg_scanin[11]=data_bus_2_w1_reg_scanout[11]; | |
3512 | assign data_bus_2_w5_reg_scanin[11]=data_bus_2_w4_reg_scanout[11]; | |
3513 | assign data_bus_2_w2_reg_scanin[11]=data_bus_2_w5_reg_scanout[11]; | |
3514 | assign data_bus_2_w3_reg_scanin[11]=data_bus_2_w2_reg_scanout[11]; | |
3515 | assign data_bus_2_w6_reg_scanin[11]=data_bus_2_w3_reg_scanout[11]; | |
3516 | assign data_bus_2_w7_reg_scanin[11]=data_bus_2_w6_reg_scanout[11]; | |
3517 | ||
3518 | assign data_bus_2_w0_reg_scanin[10]=data_bus_2_w7_reg_scanout[11]; | |
3519 | assign data_bus_2_w1_reg_scanin[10]=data_bus_2_w0_reg_scanout[10]; | |
3520 | assign data_bus_2_w4_reg_scanin[10]=data_bus_2_w1_reg_scanout[10]; | |
3521 | assign data_bus_2_w5_reg_scanin[10]=data_bus_2_w4_reg_scanout[10]; | |
3522 | assign data_bus_2_w2_reg_scanin[10]=data_bus_2_w5_reg_scanout[10]; | |
3523 | assign data_bus_2_w3_reg_scanin[10]=data_bus_2_w2_reg_scanout[10]; | |
3524 | assign data_bus_2_w6_reg_scanin[10]=data_bus_2_w3_reg_scanout[10]; | |
3525 | assign data_bus_2_w7_reg_scanin[10]=data_bus_2_w6_reg_scanout[10]; | |
3526 | ||
3527 | assign data_bus_2_w0_reg_scanin[9]=data_bus_2_w7_reg_scanout[10]; | |
3528 | assign data_bus_2_w1_reg_scanin[9]=data_bus_2_w0_reg_scanout[9]; | |
3529 | assign data_bus_2_w4_reg_scanin[9]=data_bus_2_w1_reg_scanout[9]; | |
3530 | assign data_bus_2_w5_reg_scanin[9]=data_bus_2_w4_reg_scanout[9]; | |
3531 | assign data_bus_2_w2_reg_scanin[9]=data_bus_2_w5_reg_scanout[9]; | |
3532 | assign data_bus_2_w3_reg_scanin[9]=data_bus_2_w2_reg_scanout[9]; | |
3533 | assign data_bus_2_w6_reg_scanin[9]=data_bus_2_w3_reg_scanout[9]; | |
3534 | assign data_bus_2_w7_reg_scanin[9]=data_bus_2_w6_reg_scanout[9]; | |
3535 | ||
3536 | assign data_bus_2_w0_reg_scanin[8]=data_bus_2_w7_reg_scanout[9]; | |
3537 | assign data_bus_2_w1_reg_scanin[8]=data_bus_2_w0_reg_scanout[8]; | |
3538 | assign data_bus_2_w4_reg_scanin[8]=data_bus_2_w1_reg_scanout[8]; | |
3539 | assign data_bus_2_w5_reg_scanin[8]=data_bus_2_w4_reg_scanout[8]; | |
3540 | assign data_bus_2_w2_reg_scanin[8]=data_bus_2_w5_reg_scanout[8]; | |
3541 | assign data_bus_2_w3_reg_scanin[8]=data_bus_2_w2_reg_scanout[8]; | |
3542 | assign data_bus_2_w6_reg_scanin[8]=data_bus_2_w3_reg_scanout[8]; | |
3543 | assign data_bus_2_w7_reg_scanin[8]=data_bus_2_w6_reg_scanout[8]; | |
3544 | ||
3545 | assign data_bus_2_w0_reg_scanin[7]=data_bus_2_w7_reg_scanout[8]; | |
3546 | assign data_bus_2_w1_reg_scanin[7]=data_bus_2_w0_reg_scanout[7]; | |
3547 | assign data_bus_2_w4_reg_scanin[7]=data_bus_2_w1_reg_scanout[7]; | |
3548 | assign data_bus_2_w5_reg_scanin[7]=data_bus_2_w4_reg_scanout[7]; | |
3549 | assign data_bus_2_w2_reg_scanin[7]=data_bus_2_w5_reg_scanout[7]; | |
3550 | assign data_bus_2_w3_reg_scanin[7]=data_bus_2_w2_reg_scanout[7]; | |
3551 | assign data_bus_2_w6_reg_scanin[7]=data_bus_2_w3_reg_scanout[7]; | |
3552 | assign data_bus_2_w7_reg_scanin[7]=data_bus_2_w6_reg_scanout[7]; | |
3553 | ||
3554 | assign data_bus_2_w0_reg_scanin[6]=data_bus_2_w7_reg_scanout[7]; | |
3555 | assign data_bus_2_w1_reg_scanin[6]=data_bus_2_w0_reg_scanout[6]; | |
3556 | assign data_bus_2_w4_reg_scanin[6]=data_bus_2_w1_reg_scanout[6]; | |
3557 | assign data_bus_2_w5_reg_scanin[6]=data_bus_2_w4_reg_scanout[6]; | |
3558 | assign data_bus_2_w2_reg_scanin[6]=data_bus_2_w5_reg_scanout[6]; | |
3559 | assign data_bus_2_w3_reg_scanin[6]=data_bus_2_w2_reg_scanout[6]; | |
3560 | assign data_bus_2_w6_reg_scanin[6]=data_bus_2_w3_reg_scanout[6]; | |
3561 | assign data_bus_2_w7_reg_scanin[6]=data_bus_2_w6_reg_scanout[6]; | |
3562 | ||
3563 | assign data_bus_2_w0_reg_scanin[5]=data_bus_2_w7_reg_scanout[6]; | |
3564 | assign data_bus_2_w1_reg_scanin[5]=data_bus_2_w0_reg_scanout[5]; | |
3565 | assign data_bus_2_w4_reg_scanin[5]=data_bus_2_w1_reg_scanout[5]; | |
3566 | assign data_bus_2_w5_reg_scanin[5]=data_bus_2_w4_reg_scanout[5]; | |
3567 | assign data_bus_2_w2_reg_scanin[5]=data_bus_2_w5_reg_scanout[5]; | |
3568 | assign data_bus_2_w3_reg_scanin[5]=data_bus_2_w2_reg_scanout[5]; | |
3569 | assign data_bus_2_w6_reg_scanin[5]=data_bus_2_w3_reg_scanout[5]; | |
3570 | assign data_bus_2_w7_reg_scanin[5]=data_bus_2_w6_reg_scanout[5]; | |
3571 | ||
3572 | assign data_bus_2_w0_reg_scanin[4]=data_bus_2_w7_reg_scanout[5]; | |
3573 | assign data_bus_2_w1_reg_scanin[4]=data_bus_2_w0_reg_scanout[4]; | |
3574 | assign data_bus_2_w4_reg_scanin[4]=data_bus_2_w1_reg_scanout[4]; | |
3575 | assign data_bus_2_w5_reg_scanin[4]=data_bus_2_w4_reg_scanout[4]; | |
3576 | assign data_bus_2_w2_reg_scanin[4]=data_bus_2_w5_reg_scanout[4]; | |
3577 | assign data_bus_2_w3_reg_scanin[4]=data_bus_2_w2_reg_scanout[4]; | |
3578 | assign data_bus_2_w6_reg_scanin[4]=data_bus_2_w3_reg_scanout[4]; | |
3579 | assign data_bus_2_w7_reg_scanin[4]=data_bus_2_w6_reg_scanout[4]; | |
3580 | ||
3581 | assign data_bus_2_w0_reg_scanin[3]=data_bus_2_w7_reg_scanout[4]; | |
3582 | assign data_bus_2_w1_reg_scanin[3]=data_bus_2_w0_reg_scanout[3]; | |
3583 | assign data_bus_2_w4_reg_scanin[3]=data_bus_2_w1_reg_scanout[3]; | |
3584 | assign data_bus_2_w5_reg_scanin[3]=data_bus_2_w4_reg_scanout[3]; | |
3585 | assign data_bus_2_w2_reg_scanin[3]=data_bus_2_w5_reg_scanout[3]; | |
3586 | assign data_bus_2_w3_reg_scanin[3]=data_bus_2_w2_reg_scanout[3]; | |
3587 | assign data_bus_2_w6_reg_scanin[3]=data_bus_2_w3_reg_scanout[3]; | |
3588 | assign data_bus_2_w7_reg_scanin[3]=data_bus_2_w6_reg_scanout[3]; | |
3589 | ||
3590 | assign data_bus_2_w0_reg_scanin[2]=data_bus_2_w7_reg_scanout[3]; | |
3591 | assign data_bus_2_w1_reg_scanin[2]=data_bus_2_w0_reg_scanout[2]; | |
3592 | assign data_bus_2_w4_reg_scanin[2]=data_bus_2_w1_reg_scanout[2]; | |
3593 | assign data_bus_2_w5_reg_scanin[2]=data_bus_2_w4_reg_scanout[2]; | |
3594 | assign data_bus_2_w2_reg_scanin[2]=data_bus_2_w5_reg_scanout[2]; | |
3595 | assign data_bus_2_w3_reg_scanin[2]=data_bus_2_w2_reg_scanout[2]; | |
3596 | assign data_bus_2_w6_reg_scanin[2]=data_bus_2_w3_reg_scanout[2]; | |
3597 | assign data_bus_2_w7_reg_scanin[2]=data_bus_2_w6_reg_scanout[2]; | |
3598 | ||
3599 | assign data_bus_2_w0_reg_scanin[1]=data_bus_2_w7_reg_scanout[2]; | |
3600 | assign data_bus_2_w1_reg_scanin[1]=data_bus_2_w0_reg_scanout[1]; | |
3601 | assign data_bus_2_w4_reg_scanin[1]=data_bus_2_w1_reg_scanout[1]; | |
3602 | assign data_bus_2_w5_reg_scanin[1]=data_bus_2_w4_reg_scanout[1]; | |
3603 | assign data_bus_2_w2_reg_scanin[1]=data_bus_2_w5_reg_scanout[1]; | |
3604 | assign data_bus_2_w3_reg_scanin[1]=data_bus_2_w2_reg_scanout[1]; | |
3605 | assign data_bus_2_w6_reg_scanin[1]=data_bus_2_w3_reg_scanout[1]; | |
3606 | assign data_bus_2_w7_reg_scanin[1]=data_bus_2_w6_reg_scanout[1]; | |
3607 | ||
3608 | assign data_bus_2_w0_reg_scanin[0]=data_bus_2_w7_reg_scanout[1]; | |
3609 | assign data_bus_2_w1_reg_scanin[0]=data_bus_2_w0_reg_scanout[0]; | |
3610 | assign data_bus_2_w4_reg_scanin[0]=data_bus_2_w1_reg_scanout[0]; | |
3611 | assign data_bus_2_w5_reg_scanin[0]=data_bus_2_w4_reg_scanout[0]; | |
3612 | assign data_bus_2_w2_reg_scanin[0]=data_bus_2_w5_reg_scanout[0]; | |
3613 | assign data_bus_2_w3_reg_scanin[0]=data_bus_2_w2_reg_scanout[0]; | |
3614 | assign data_bus_2_w6_reg_scanin[0]=data_bus_2_w3_reg_scanout[0]; | |
3615 | assign data_bus_2_w7_reg_scanin[0]=data_bus_2_w6_reg_scanout[0]; | |
3616 | ||
3617 | assign scan_out =data_bus_2_w7_reg_scanout[0]; | |
3618 | ||
3619 | // ***************************END SECTION*************************** | |
3620 | ||
3621 | ||
3622 | `ifndef FPGA | |
3623 | // synopsys translate_on | |
3624 | `endif | |
3625 | ||
3626 | endmodule | |
3627 | ||
3628 | ||
3629 | ||
3630 | ||
3631 | ||
3632 | ||
3633 | // any PARAMS parms go into naming of macro | |
3634 | ||
3635 | module n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro ( | |
3636 | l2clk, | |
3637 | l1en, | |
3638 | pce_ov, | |
3639 | stop, | |
3640 | se, | |
3641 | l1clk); | |
3642 | ||
3643 | ||
3644 | input l2clk; | |
3645 | input l1en; | |
3646 | input pce_ov; | |
3647 | input stop; | |
3648 | input se; | |
3649 | output l1clk; | |
3650 | ||
3651 | ||
3652 | ||
3653 | ||
3654 | ||
3655 | cl_sc1_l1hdr_8x c_0 ( | |
3656 | ||
3657 | ||
3658 | .l2clk(l2clk), | |
3659 | .pce(l1en), | |
3660 | .l1clk(l1clk), | |
3661 | .se(se), | |
3662 | .pce_ov(pce_ov), | |
3663 | .stop(stop) | |
3664 | ); | |
3665 | ||
3666 | ||
3667 | ||
3668 | endmodule | |
3669 | ||
3670 | ||
3671 | ||
3672 | ||
3673 | ||
3674 | ||
3675 | ||
3676 | ||
3677 | ||
3678 | // | |
3679 | // invert macro | |
3680 | // | |
3681 | // | |
3682 | ||
3683 | ||
3684 | ||
3685 | ||
3686 | ||
3687 | module n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_9 ( | |
3688 | din, | |
3689 | dout); | |
3690 | input [8:0] din; | |
3691 | output [8:0] dout; | |
3692 | ||
3693 | ||
3694 | ||
3695 | ||
3696 | ||
3697 | ||
3698 | inv #(9) d0_0 ( | |
3699 | .in(din[8:0]), | |
3700 | .out(dout[8:0]) | |
3701 | ); | |
3702 | ||
3703 | ||
3704 | ||
3705 | ||
3706 | ||
3707 | ||
3708 | ||
3709 | ||
3710 | ||
3711 | endmodule | |
3712 | ||
3713 | ||
3714 | ||
3715 | ||
3716 | ||
3717 | // | |
3718 | // invert macro | |
3719 | // | |
3720 | // | |
3721 | ||
3722 | ||
3723 | ||
3724 | ||
3725 | ||
3726 | module n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_3 ( | |
3727 | din, | |
3728 | dout); | |
3729 | input [2:0] din; | |
3730 | output [2:0] dout; | |
3731 | ||
3732 | ||
3733 | ||
3734 | ||
3735 | ||
3736 | ||
3737 | inv #(3) d0_0 ( | |
3738 | .in(din[2:0]), | |
3739 | .out(dout[2:0]) | |
3740 | ); | |
3741 | ||
3742 | ||
3743 | ||
3744 | ||
3745 | ||
3746 | ||
3747 | ||
3748 | ||
3749 | ||
3750 | endmodule | |
3751 | ||
3752 | ||
3753 | ||
3754 | ||
3755 | ||
3756 | // | |
3757 | // invert macro | |
3758 | // | |
3759 | // | |
3760 | ||
3761 | ||
3762 | ||
3763 | ||
3764 | ||
3765 | module n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_8 ( | |
3766 | din, | |
3767 | dout); | |
3768 | input [7:0] din; | |
3769 | output [7:0] dout; | |
3770 | ||
3771 | ||
3772 | ||
3773 | ||
3774 | ||
3775 | ||
3776 | inv #(8) d0_0 ( | |
3777 | .in(din[7:0]), | |
3778 | .out(dout[7:0]) | |
3779 | ); | |
3780 | ||
3781 | ||
3782 | ||
3783 | ||
3784 | ||
3785 | ||
3786 | ||
3787 | ||
3788 | ||
3789 | endmodule | |
3790 | ||
3791 | ||
3792 | ||
3793 | ||
3794 | ||
3795 | // | |
3796 | // invert macro | |
3797 | // | |
3798 | // | |
3799 | ||
3800 | ||
3801 | ||
3802 | ||
3803 | ||
3804 | module n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 ( | |
3805 | din, | |
3806 | dout); | |
3807 | input [0:0] din; | |
3808 | output [0:0] dout; | |
3809 | ||
3810 | ||
3811 | ||
3812 | ||
3813 | ||
3814 | ||
3815 | inv #(1) d0_0 ( | |
3816 | .in(din[0:0]), | |
3817 | .out(dout[0:0]) | |
3818 | ); | |
3819 | ||
3820 | ||
3821 | ||
3822 | ||
3823 | ||
3824 | ||
3825 | ||
3826 | ||
3827 | ||
3828 | endmodule | |
3829 | ||
3830 | ||
3831 | ||
3832 | ||
3833 | ||
3834 | // | |
3835 | // invert macro | |
3836 | // | |
3837 | // | |
3838 | ||
3839 | ||
3840 | ||
3841 | ||
3842 | ||
3843 | module n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_4 ( | |
3844 | din, | |
3845 | dout); | |
3846 | input [3:0] din; | |
3847 | output [3:0] dout; | |
3848 | ||
3849 | ||
3850 | ||
3851 | ||
3852 | ||
3853 | ||
3854 | inv #(4) d0_0 ( | |
3855 | .in(din[3:0]), | |
3856 | .out(dout[3:0]) | |
3857 | ); | |
3858 | ||
3859 | ||
3860 | ||
3861 | ||
3862 | ||
3863 | ||
3864 | ||
3865 | ||
3866 | ||
3867 | endmodule | |
3868 | ||
3869 | ||
3870 | ||
3871 | ||
3872 | ||
3873 | // | |
3874 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
3875 | // | |
3876 | // | |
3877 | ||
3878 | ||
3879 | ||
3880 | ||
3881 | ||
3882 | module n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 ( | |
3883 | d, | |
3884 | scan_in, | |
3885 | l1clk, | |
3886 | siclk, | |
3887 | soclk, | |
3888 | scan_out, | |
3889 | latout, | |
3890 | latout_l); | |
3891 | input [0:0] d; | |
3892 | input scan_in; | |
3893 | input l1clk; | |
3894 | input siclk; | |
3895 | input soclk; | |
3896 | output scan_out; | |
3897 | output [0:0] latout; | |
3898 | output [0:0] latout_l; | |
3899 | ||
3900 | ||
3901 | ||
3902 | ||
3903 | ||
3904 | ||
3905 | tisram_msff #(1) d0_0 ( | |
3906 | .d(d[0:0]), | |
3907 | .si(scan_in), | |
3908 | .so(scan_out), | |
3909 | .l1clk(l1clk), | |
3910 | .siclk(siclk), | |
3911 | .soclk(soclk), | |
3912 | .latout(latout[0:0]), | |
3913 | .latout_l(latout_l[0:0]) | |
3914 | ); | |
3915 | ||
3916 | ||
3917 | ||
3918 | ||
3919 | ||
3920 | ||
3921 | ||
3922 | ||
3923 | ||
3924 | ||
3925 | ||
3926 | ||
3927 | //place::generic_place($width,$stack,$left); | |
3928 | ||
3929 | endmodule | |
3930 | ||
3931 | ||
3932 | ||
3933 | ||
3934 | ||
3935 | // | |
3936 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
3937 | // | |
3938 | // | |
3939 | ||
3940 | ||
3941 | ||
3942 | ||
3943 | ||
3944 | module n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_9 ( | |
3945 | d, | |
3946 | scan_in, | |
3947 | l1clk, | |
3948 | siclk, | |
3949 | soclk, | |
3950 | scan_out, | |
3951 | latout, | |
3952 | latout_l); | |
3953 | wire [7:0] so; | |
3954 | ||
3955 | input [8:0] d; | |
3956 | input scan_in; | |
3957 | input l1clk; | |
3958 | input siclk; | |
3959 | input soclk; | |
3960 | output scan_out; | |
3961 | output [8:0] latout; | |
3962 | output [8:0] latout_l; | |
3963 | ||
3964 | ||
3965 | ||
3966 | ||
3967 | ||
3968 | ||
3969 | tisram_msff #(9) d0_0 ( | |
3970 | .d(d[8:0]), | |
3971 | .si({scan_in,so[7:0]}), | |
3972 | .so({so[7:0],scan_out}), | |
3973 | .l1clk(l1clk), | |
3974 | .siclk(siclk), | |
3975 | .soclk(soclk), | |
3976 | .latout(latout[8:0]), | |
3977 | .latout_l(latout_l[8:0]) | |
3978 | ); | |
3979 | ||
3980 | ||
3981 | ||
3982 | ||
3983 | ||
3984 | ||
3985 | ||
3986 | ||
3987 | ||
3988 | ||
3989 | ||
3990 | ||
3991 | //place::generic_place($width,$stack,$left); | |
3992 | ||
3993 | endmodule | |
3994 | ||
3995 | ||
3996 | ||
3997 | ||
3998 | ||
3999 | ||
4000 | ||
4001 | ||
4002 | ||
4003 | // any PARAMS parms go into naming of macro | |
4004 | ||
4005 | module n2_icd_sp_16p5kb_cust_msffi_ctl_macro__fs_1__width_4 ( | |
4006 | din, | |
4007 | l1clk, | |
4008 | scan_in, | |
4009 | siclk, | |
4010 | soclk, | |
4011 | q_l, | |
4012 | scan_out); | |
4013 | input [3:0] din; | |
4014 | input l1clk; | |
4015 | input [3:0] scan_in; | |
4016 | ||
4017 | ||
4018 | input siclk; | |
4019 | input soclk; | |
4020 | ||
4021 | output [3:0] q_l; | |
4022 | output [3:0] scan_out; | |
4023 | ||
4024 | ||
4025 | ||
4026 | ||
4027 | ||
4028 | ||
4029 | msffi #(4) d0_0 ( | |
4030 | .l1clk(l1clk), | |
4031 | .siclk(siclk), | |
4032 | .soclk(soclk), | |
4033 | .d(din[3:0]), | |
4034 | .si(scan_in[3:0]), | |
4035 | .so(scan_out[3:0]), | |
4036 | .q_l(q_l[3:0]) | |
4037 | ); | |
4038 | ||
4039 | ||
4040 | ||
4041 | ||
4042 | ||
4043 | ||
4044 | ||
4045 | ||
4046 | ||
4047 | ||
4048 | ||
4049 | ||
4050 | endmodule | |
4051 | ||
4052 | ||
4053 | ||
4054 | ||
4055 | ||
4056 | ||
4057 | ||
4058 | ||
4059 | ||
4060 | // | |
4061 | // invert macro | |
4062 | // | |
4063 | // | |
4064 | ||
4065 | ||
4066 | ||
4067 | ||
4068 | ||
4069 | module n2_icd_sp_16p5kb_cust_inv_macro__width_4 ( | |
4070 | din, | |
4071 | dout); | |
4072 | input [3:0] din; | |
4073 | output [3:0] dout; | |
4074 | ||
4075 | ||
4076 | ||
4077 | ||
4078 | ||
4079 | ||
4080 | inv #(4) d0_0 ( | |
4081 | .in(din[3:0]), | |
4082 | .out(dout[3:0]) | |
4083 | ); | |
4084 | ||
4085 | ||
4086 | ||
4087 | ||
4088 | ||
4089 | ||
4090 | ||
4091 | ||
4092 | ||
4093 | endmodule | |
4094 | ||
4095 | ||
4096 | ||
4097 | ||
4098 | ||
4099 | ||
4100 | ||
4101 | ||
4102 | ||
4103 | // any PARAMS parms go into naming of macro | |
4104 | ||
4105 | module n2_icd_sp_16p5kb_cust_msffi_ctl_macro__width_1 ( | |
4106 | din, | |
4107 | l1clk, | |
4108 | scan_in, | |
4109 | siclk, | |
4110 | soclk, | |
4111 | q_l, | |
4112 | scan_out); | |
4113 | input [0:0] din; | |
4114 | input l1clk; | |
4115 | input scan_in; | |
4116 | ||
4117 | ||
4118 | input siclk; | |
4119 | input soclk; | |
4120 | ||
4121 | output [0:0] q_l; | |
4122 | output scan_out; | |
4123 | ||
4124 | ||
4125 | ||
4126 | ||
4127 | ||
4128 | ||
4129 | msffi #(1) d0_0 ( | |
4130 | .l1clk(l1clk), | |
4131 | .siclk(siclk), | |
4132 | .soclk(soclk), | |
4133 | .d(din[0:0]), | |
4134 | .si(scan_in), | |
4135 | .so(scan_out), | |
4136 | .q_l(q_l[0:0]) | |
4137 | ); | |
4138 | ||
4139 | ||
4140 | ||
4141 | ||
4142 | ||
4143 | ||
4144 | ||
4145 | ||
4146 | ||
4147 | ||
4148 | ||
4149 | ||
4150 | endmodule | |
4151 | ||
4152 | ||
4153 | ||
4154 | ||
4155 | ||
4156 | ||
4157 | ||
4158 | ||
4159 | ||
4160 | ||
4161 | ||
4162 | ||
4163 | ||
4164 | // any PARAMS parms go into naming of macro | |
4165 | ||
4166 | module n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_1 ( | |
4167 | din, | |
4168 | l1clk, | |
4169 | scan_in, | |
4170 | siclk, | |
4171 | soclk, | |
4172 | dout, | |
4173 | scan_out); | |
4174 | wire [0:0] fdin; | |
4175 | ||
4176 | input [0:0] din; | |
4177 | input l1clk; | |
4178 | input [0:0] scan_in; | |
4179 | ||
4180 | ||
4181 | input siclk; | |
4182 | input soclk; | |
4183 | ||
4184 | output [0:0] dout; | |
4185 | output [0:0] scan_out; | |
4186 | assign fdin[0:0] = din[0:0]; | |
4187 | ||
4188 | ||
4189 | ||
4190 | ||
4191 | ||
4192 | ||
4193 | dff #(1) d0_0 ( | |
4194 | .l1clk(l1clk), | |
4195 | .siclk(siclk), | |
4196 | .soclk(soclk), | |
4197 | .d(fdin[0:0]), | |
4198 | .si(scan_in[0:0]), | |
4199 | .so(scan_out[0:0]), | |
4200 | .q(dout[0:0]) | |
4201 | ); | |
4202 | ||
4203 | ||
4204 | ||
4205 | ||
4206 | ||
4207 | ||
4208 | ||
4209 | ||
4210 | ||
4211 | ||
4212 | ||
4213 | ||
4214 | endmodule | |
4215 | ||
4216 | ||
4217 | ||
4218 | ||
4219 | ||
4220 | ||
4221 | ||
4222 | ||
4223 | ||
4224 | ||
4225 | ||
4226 | ||
4227 | ||
4228 | // any PARAMS parms go into naming of macro | |
4229 | ||
4230 | module n2_icd_sp_16p5kb_cust_msff_ctl_macro__width_1 ( | |
4231 | din, | |
4232 | l1clk, | |
4233 | scan_in, | |
4234 | siclk, | |
4235 | soclk, | |
4236 | dout, | |
4237 | scan_out); | |
4238 | wire [0:0] fdin; | |
4239 | ||
4240 | input [0:0] din; | |
4241 | input l1clk; | |
4242 | input scan_in; | |
4243 | ||
4244 | ||
4245 | input siclk; | |
4246 | input soclk; | |
4247 | ||
4248 | output [0:0] dout; | |
4249 | output scan_out; | |
4250 | assign fdin[0:0] = din[0:0]; | |
4251 | ||
4252 | ||
4253 | ||
4254 | ||
4255 | ||
4256 | ||
4257 | dff #(1) d0_0 ( | |
4258 | .l1clk(l1clk), | |
4259 | .siclk(siclk), | |
4260 | .soclk(soclk), | |
4261 | .d(fdin[0:0]), | |
4262 | .si(scan_in), | |
4263 | .so(scan_out), | |
4264 | .q(dout[0:0]) | |
4265 | ); | |
4266 | ||
4267 | ||
4268 | ||
4269 | ||
4270 | ||
4271 | ||
4272 | ||
4273 | ||
4274 | ||
4275 | ||
4276 | ||
4277 | ||
4278 | endmodule | |
4279 | ||
4280 | ||
4281 | ||
4282 | ||
4283 | ||
4284 | ||
4285 | ||
4286 | ||
4287 | ||
4288 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4289 | // also for pass-gate with decoder | |
4290 | ||
4291 | ||
4292 | ||
4293 | ||
4294 | ||
4295 | // any PARAMS parms go into naming of macro | |
4296 | ||
4297 | module n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__stack_66c__width_66 ( | |
4298 | din0, | |
4299 | din1, | |
4300 | sel0, | |
4301 | dout); | |
4302 | wire psel0; | |
4303 | wire psel1; | |
4304 | ||
4305 | input [65:0] din0; | |
4306 | input [65:0] din1; | |
4307 | input sel0; | |
4308 | output [65:0] dout; | |
4309 | ||
4310 | ||
4311 | ||
4312 | ||
4313 | ||
4314 | cl_dp1_penc2_8x c0_0 ( | |
4315 | .sel0(sel0), | |
4316 | .psel0(psel0), | |
4317 | .psel1(psel1) | |
4318 | ); | |
4319 | ||
4320 | mux2s #(66) d0_0 ( | |
4321 | .sel0(psel0), | |
4322 | .sel1(psel1), | |
4323 | .in0(din0[65:0]), | |
4324 | .in1(din1[65:0]), | |
4325 | .dout(dout[65:0]) | |
4326 | ); | |
4327 | ||
4328 | ||
4329 | ||
4330 | ||
4331 | ||
4332 | ||
4333 | ||
4334 | ||
4335 | ||
4336 | ||
4337 | ||
4338 | ||
4339 | ||
4340 | endmodule | |
4341 | ||
4342 | ||
4343 | ||
4344 | ||
4345 | ||
4346 | ||
4347 | // any PARAMS parms go into naming of macro | |
4348 | ||
4349 | module n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 ( | |
4350 | din, | |
4351 | l1clk, | |
4352 | scan_in, | |
4353 | siclk, | |
4354 | soclk, | |
4355 | dout, | |
4356 | scan_out); | |
4357 | wire [32:0] fdin; | |
4358 | ||
4359 | input [32:0] din; | |
4360 | input l1clk; | |
4361 | input [32:0] scan_in; | |
4362 | ||
4363 | ||
4364 | input siclk; | |
4365 | input soclk; | |
4366 | ||
4367 | output [32:0] dout; | |
4368 | output [32:0] scan_out; | |
4369 | assign fdin[32:0] = din[32:0]; | |
4370 | ||
4371 | ||
4372 | ||
4373 | ||
4374 | ||
4375 | ||
4376 | dff #(33) d0_0 ( | |
4377 | .l1clk(l1clk), | |
4378 | .siclk(siclk), | |
4379 | .soclk(soclk), | |
4380 | .d(fdin[32:0]), | |
4381 | .si(scan_in[32:0]), | |
4382 | .so(scan_out[32:0]), | |
4383 | .q(dout[32:0]) | |
4384 | ); | |
4385 | ||
4386 | ||
4387 | ||
4388 | ||
4389 | ||
4390 | ||
4391 | ||
4392 | ||
4393 | ||
4394 | ||
4395 | ||
4396 | ||
4397 | endmodule | |
4398 | ||
4399 | ||
4400 | ||
4401 | ||
4402 | ||
4403 | ||
4404 | ||
4405 | ||
4406 | ||
4407 | ||
4408 | ||
4409 | ||
4410 | ||
4411 | // any PARAMS parms go into naming of macro | |
4412 | ||
4413 | module n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_5 ( | |
4414 | din, | |
4415 | l1clk, | |
4416 | scan_in, | |
4417 | siclk, | |
4418 | soclk, | |
4419 | dout, | |
4420 | scan_out); | |
4421 | wire [4:0] fdin; | |
4422 | ||
4423 | input [4:0] din; | |
4424 | input l1clk; | |
4425 | input [4:0] scan_in; | |
4426 | ||
4427 | ||
4428 | input siclk; | |
4429 | input soclk; | |
4430 | ||
4431 | output [4:0] dout; | |
4432 | output [4:0] scan_out; | |
4433 | assign fdin[4:0] = din[4:0]; | |
4434 | ||
4435 | ||
4436 | ||
4437 | ||
4438 | ||
4439 | ||
4440 | dff #(5) d0_0 ( | |
4441 | .l1clk(l1clk), | |
4442 | .siclk(siclk), | |
4443 | .soclk(soclk), | |
4444 | .d(fdin[4:0]), | |
4445 | .si(scan_in[4:0]), | |
4446 | .so(scan_out[4:0]), | |
4447 | .q(dout[4:0]) | |
4448 | ); | |
4449 | ||
4450 | ||
4451 | ||
4452 | ||
4453 | ||
4454 | ||
4455 | ||
4456 | ||
4457 | ||
4458 | ||
4459 | ||
4460 | ||
4461 | endmodule | |
4462 | ||
4463 | ||
4464 | ||
4465 | ||
4466 | ||
4467 | ||
4468 | ||
4469 | ||
4470 | ||
4471 | ||
4472 | ||
4473 | ||
4474 | ||
4475 | // any PARAMS parms go into naming of macro | |
4476 | ||
4477 | module n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_2 ( | |
4478 | din, | |
4479 | l1clk, | |
4480 | scan_in, | |
4481 | siclk, | |
4482 | soclk, | |
4483 | dout, | |
4484 | scan_out); | |
4485 | wire [1:0] fdin; | |
4486 | ||
4487 | input [1:0] din; | |
4488 | input l1clk; | |
4489 | input [1:0] scan_in; | |
4490 | ||
4491 | ||
4492 | input siclk; | |
4493 | input soclk; | |
4494 | ||
4495 | output [1:0] dout; | |
4496 | output [1:0] scan_out; | |
4497 | assign fdin[1:0] = din[1:0]; | |
4498 | ||
4499 | ||
4500 | ||
4501 | ||
4502 | ||
4503 | ||
4504 | dff #(2) d0_0 ( | |
4505 | .l1clk(l1clk), | |
4506 | .siclk(siclk), | |
4507 | .soclk(soclk), | |
4508 | .d(fdin[1:0]), | |
4509 | .si(scan_in[1:0]), | |
4510 | .so(scan_out[1:0]), | |
4511 | .q(dout[1:0]) | |
4512 | ); | |
4513 | ||
4514 | ||
4515 | ||
4516 | ||
4517 | ||
4518 | ||
4519 | ||
4520 | ||
4521 | ||
4522 | ||
4523 | ||
4524 | ||
4525 | endmodule | |
4526 | ||
4527 | ||
4528 | ||
4529 | ||
4530 | ||
4531 | ||
4532 | ||
4533 | ||
4534 | ||
4535 | ||
4536 | ||
4537 | ||
4538 | ||
4539 | // any PARAMS parms go into naming of macro | |
4540 | ||
4541 | module n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_4 ( | |
4542 | din, | |
4543 | l1clk, | |
4544 | scan_in, | |
4545 | siclk, | |
4546 | soclk, | |
4547 | dout, | |
4548 | scan_out); | |
4549 | wire [3:0] fdin; | |
4550 | ||
4551 | input [3:0] din; | |
4552 | input l1clk; | |
4553 | input [3:0] scan_in; | |
4554 | ||
4555 | ||
4556 | input siclk; | |
4557 | input soclk; | |
4558 | ||
4559 | output [3:0] dout; | |
4560 | output [3:0] scan_out; | |
4561 | assign fdin[3:0] = din[3:0]; | |
4562 | ||
4563 | ||
4564 | ||
4565 | ||
4566 | ||
4567 | ||
4568 | dff #(4) d0_0 ( | |
4569 | .l1clk(l1clk), | |
4570 | .siclk(siclk), | |
4571 | .soclk(soclk), | |
4572 | .d(fdin[3:0]), | |
4573 | .si(scan_in[3:0]), | |
4574 | .so(scan_out[3:0]), | |
4575 | .q(dout[3:0]) | |
4576 | ); | |
4577 | ||
4578 | ||
4579 | ||
4580 | ||
4581 | ||
4582 | ||
4583 | ||
4584 | ||
4585 | ||
4586 | ||
4587 | ||
4588 | ||
4589 | endmodule | |
4590 | ||
4591 | ||
4592 | ||
4593 | ||
4594 | ||
4595 | ||
4596 | ||
4597 | ||
4598 | ||
4599 | // | |
4600 | // and macro for ports = 2,3,4 | |
4601 | // | |
4602 | // | |
4603 | ||
4604 | ||
4605 | ||
4606 | ||
4607 | ||
4608 | module n2_icd_sp_16p5kb_cust_and_macro__ports_2__width_1 ( | |
4609 | din0, | |
4610 | din1, | |
4611 | dout); | |
4612 | input [0:0] din0; | |
4613 | input [0:0] din1; | |
4614 | output [0:0] dout; | |
4615 | ||
4616 | ||
4617 | ||
4618 | ||
4619 | ||
4620 | ||
4621 | and2 #(1) d0_0 ( | |
4622 | .in0(din0[0:0]), | |
4623 | .in1(din1[0:0]), | |
4624 | .out(dout[0:0]) | |
4625 | ); | |
4626 | ||
4627 | ||
4628 | ||
4629 | ||
4630 | ||
4631 | ||
4632 | ||
4633 | ||
4634 | ||
4635 | endmodule | |
4636 | ||
4637 | ||
4638 | ||
4639 | ||
4640 | ||
4641 | ||
4642 | ||
4643 | ||
4644 | ||
4645 | // any PARAMS parms go into naming of macro | |
4646 | ||
4647 | module n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_8 ( | |
4648 | din, | |
4649 | l1clk, | |
4650 | scan_in, | |
4651 | siclk, | |
4652 | soclk, | |
4653 | dout, | |
4654 | scan_out); | |
4655 | wire [7:0] fdin; | |
4656 | ||
4657 | input [7:0] din; | |
4658 | input l1clk; | |
4659 | input [7:0] scan_in; | |
4660 | ||
4661 | ||
4662 | input siclk; | |
4663 | input soclk; | |
4664 | ||
4665 | output [7:0] dout; | |
4666 | output [7:0] scan_out; | |
4667 | assign fdin[7:0] = din[7:0]; | |
4668 | ||
4669 | ||
4670 | ||
4671 | ||
4672 | ||
4673 | ||
4674 | dff #(8) d0_0 ( | |
4675 | .l1clk(l1clk), | |
4676 | .siclk(siclk), | |
4677 | .soclk(soclk), | |
4678 | .d(fdin[7:0]), | |
4679 | .si(scan_in[7:0]), | |
4680 | .so(scan_out[7:0]), | |
4681 | .q(dout[7:0]) | |
4682 | ); | |
4683 | ||
4684 | ||
4685 | ||
4686 | ||
4687 | ||
4688 | ||
4689 | ||
4690 | ||
4691 | ||
4692 | ||
4693 | ||
4694 | ||
4695 | endmodule | |
4696 | ||
4697 | ||
4698 | ||
4699 | ||
4700 | ||
4701 | ||
4702 | ||
4703 | ||
4704 | ||
4705 | // | |
4706 | // invert macro | |
4707 | // | |
4708 | // | |
4709 | ||
4710 | ||
4711 | ||
4712 | ||
4713 | ||
4714 | module n2_icd_sp_16p5kb_cust_inv_macro__width_1 ( | |
4715 | din, | |
4716 | dout); | |
4717 | input [0:0] din; | |
4718 | output [0:0] dout; | |
4719 | ||
4720 | ||
4721 | ||
4722 | ||
4723 | ||
4724 | ||
4725 | inv #(1) d0_0 ( | |
4726 | .in(din[0:0]), | |
4727 | .out(dout[0:0]) | |
4728 | ); | |
4729 | ||
4730 | ||
4731 | ||
4732 | ||
4733 | ||
4734 | ||
4735 | ||
4736 | ||
4737 | ||
4738 | endmodule | |
4739 | ||
4740 | ||
4741 | ||
4742 | ||
4743 | ||
4744 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4745 | // also for pass-gate with decoder | |
4746 | ||
4747 | ||
4748 | ||
4749 | ||
4750 | ||
4751 | // any PARAMS parms go into naming of macro | |
4752 | ||
4753 | module n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_2__stack_50c__width_8 ( | |
4754 | din0, | |
4755 | sel0, | |
4756 | din1, | |
4757 | sel1, | |
4758 | dout); | |
4759 | wire buffout0; | |
4760 | wire buffout1; | |
4761 | ||
4762 | input [7:0] din0; | |
4763 | input sel0; | |
4764 | input [7:0] din1; | |
4765 | input sel1; | |
4766 | output [7:0] dout; | |
4767 | ||
4768 | ||
4769 | ||
4770 | ||
4771 | ||
4772 | cl_dp1_muxbuff2_8x c0_0 ( | |
4773 | .in0(sel0), | |
4774 | .in1(sel1), | |
4775 | .out0(buffout0), | |
4776 | .out1(buffout1) | |
4777 | ); | |
4778 | mux2s #(8) d0_0 ( | |
4779 | .sel0(buffout0), | |
4780 | .sel1(buffout1), | |
4781 | .in0(din0[7:0]), | |
4782 | .in1(din1[7:0]), | |
4783 | .dout(dout[7:0]) | |
4784 | ); | |
4785 | ||
4786 | ||
4787 | ||
4788 | ||
4789 | ||
4790 | ||
4791 | ||
4792 | ||
4793 | ||
4794 | ||
4795 | ||
4796 | ||
4797 | ||
4798 | endmodule | |
4799 | ||
4800 | ||
4801 | // | |
4802 | // or macro for ports = 2,3 | |
4803 | // | |
4804 | // | |
4805 | ||
4806 | ||
4807 | ||
4808 | ||
4809 | ||
4810 | module n2_icd_sp_16p5kb_cust_or_macro__ports_3__stack_50c__width_1 ( | |
4811 | din0, | |
4812 | din1, | |
4813 | din2, | |
4814 | dout); | |
4815 | input [0:0] din0; | |
4816 | input [0:0] din1; | |
4817 | input [0:0] din2; | |
4818 | output [0:0] dout; | |
4819 | ||
4820 | ||
4821 | ||
4822 | ||
4823 | ||
4824 | ||
4825 | or3 #(1) d0_0 ( | |
4826 | .in0(din0[0:0]), | |
4827 | .in1(din1[0:0]), | |
4828 | .in2(din2[0:0]), | |
4829 | .out(dout[0:0]) | |
4830 | ); | |
4831 | ||
4832 | ||
4833 | ||
4834 | ||
4835 | ||
4836 | ||
4837 | ||
4838 | ||
4839 | ||
4840 | endmodule | |
4841 | ||
4842 | ||
4843 | ||
4844 | ||
4845 | ||
4846 | // | |
4847 | // or macro for ports = 2,3 | |
4848 | // | |
4849 | // | |
4850 | ||
4851 | ||
4852 | ||
4853 | ||
4854 | ||
4855 | module n2_icd_sp_16p5kb_cust_or_macro__ports_2__stack_50c__width_1 ( | |
4856 | din0, | |
4857 | din1, | |
4858 | dout); | |
4859 | input [0:0] din0; | |
4860 | input [0:0] din1; | |
4861 | output [0:0] dout; | |
4862 | ||
4863 | ||
4864 | ||
4865 | ||
4866 | ||
4867 | ||
4868 | or2 #(1) d0_0 ( | |
4869 | .in0(din0[0:0]), | |
4870 | .in1(din1[0:0]), | |
4871 | .out(dout[0:0]) | |
4872 | ); | |
4873 | ||
4874 | ||
4875 | ||
4876 | ||
4877 | ||
4878 | ||
4879 | ||
4880 | ||
4881 | ||
4882 | endmodule | |
4883 | ||
4884 | ||
4885 | ||
4886 | ||
4887 | ||
4888 | // | |
4889 | // and macro for ports = 2,3,4 | |
4890 | // | |
4891 | // | |
4892 | ||
4893 | ||
4894 | ||
4895 | ||
4896 | ||
4897 | module n2_icd_sp_16p5kb_cust_and_macro__ports_2__stack_50c__width_1 ( | |
4898 | din0, | |
4899 | din1, | |
4900 | dout); | |
4901 | input [0:0] din0; | |
4902 | input [0:0] din1; | |
4903 | output [0:0] dout; | |
4904 | ||
4905 | ||
4906 | ||
4907 | ||
4908 | ||
4909 | ||
4910 | and2 #(1) d0_0 ( | |
4911 | .in0(din0[0:0]), | |
4912 | .in1(din1[0:0]), | |
4913 | .out(dout[0:0]) | |
4914 | ); | |
4915 | ||
4916 | ||
4917 | ||
4918 | ||
4919 | ||
4920 | ||
4921 | ||
4922 | ||
4923 | ||
4924 | endmodule | |
4925 | ||
4926 | ||
4927 | ||
4928 | ||
4929 | ||
4930 | // | |
4931 | // buff macro | |
4932 | // | |
4933 | // | |
4934 | ||
4935 | ||
4936 | ||
4937 | ||
4938 | ||
4939 | module n2_icd_sp_16p5kb_cust_buff_macro__stack_50c__width_1 ( | |
4940 | din, | |
4941 | dout); | |
4942 | input [0:0] din; | |
4943 | output [0:0] dout; | |
4944 | ||
4945 | ||
4946 | ||
4947 | ||
4948 | ||
4949 | ||
4950 | buff #(1) d0_0 ( | |
4951 | .in(din[0:0]), | |
4952 | .out(dout[0:0]) | |
4953 | ); | |
4954 | ||
4955 | ||
4956 | ||
4957 | ||
4958 | ||
4959 | ||
4960 | ||
4961 | ||
4962 | endmodule | |
4963 | ||
4964 | ||
4965 | ||
4966 | ||
4967 | ||
4968 | // | |
4969 | // nand macro for ports = 2,3,4 | |
4970 | // | |
4971 | // | |
4972 | ||
4973 | ||
4974 | ||
4975 | ||
4976 | ||
4977 | module n2_icd_sp_16p5kb_cust_nand_macro__ports_3__stack_50c__width_8 ( | |
4978 | din0, | |
4979 | din1, | |
4980 | din2, | |
4981 | dout); | |
4982 | input [7:0] din0; | |
4983 | input [7:0] din1; | |
4984 | input [7:0] din2; | |
4985 | output [7:0] dout; | |
4986 | ||
4987 | ||
4988 | ||
4989 | ||
4990 | ||
4991 | ||
4992 | nand3 #(8) d0_0 ( | |
4993 | .in0(din0[7:0]), | |
4994 | .in1(din1[7:0]), | |
4995 | .in2(din2[7:0]), | |
4996 | .out(dout[7:0]) | |
4997 | ); | |
4998 | ||
4999 | ||
5000 | ||
5001 | ||
5002 | ||
5003 | ||
5004 | ||
5005 | ||
5006 | ||
5007 | endmodule | |
5008 | ||
5009 | ||
5010 | ||
5011 | ||
5012 | ||
5013 | // | |
5014 | // nand macro for ports = 2,3,4 | |
5015 | // | |
5016 | // | |
5017 | ||
5018 | ||
5019 | ||
5020 | ||
5021 | ||
5022 | module n2_icd_sp_16p5kb_cust_nand_macro__ports_4__stack_50c__width_1 ( | |
5023 | din0, | |
5024 | din1, | |
5025 | din2, | |
5026 | din3, | |
5027 | dout); | |
5028 | input [0:0] din0; | |
5029 | input [0:0] din1; | |
5030 | input [0:0] din2; | |
5031 | input [0:0] din3; | |
5032 | output [0:0] dout; | |
5033 | ||
5034 | ||
5035 | ||
5036 | ||
5037 | ||
5038 | ||
5039 | nand4 #(1) d0_0 ( | |
5040 | .in0(din0[0:0]), | |
5041 | .in1(din1[0:0]), | |
5042 | .in2(din2[0:0]), | |
5043 | .in3(din3[0:0]), | |
5044 | .out(dout[0:0]) | |
5045 | ); | |
5046 | ||
5047 | ||
5048 | ||
5049 | ||
5050 | ||
5051 | ||
5052 | ||
5053 | ||
5054 | ||
5055 | endmodule | |
5056 | ||
5057 | ||
5058 | ||
5059 | ||
5060 | ||
5061 | // | |
5062 | // invert macro | |
5063 | // | |
5064 | // | |
5065 | ||
5066 | ||
5067 | ||
5068 | ||
5069 | ||
5070 | module n2_icd_sp_16p5kb_cust_inv_macro ( | |
5071 | din, | |
5072 | dout); | |
5073 | input [0:0] din; | |
5074 | output [0:0] dout; | |
5075 | ||
5076 | ||
5077 | ||
5078 | ||
5079 | ||
5080 | ||
5081 | inv #(1) d0_0 ( | |
5082 | .in(din[0:0]), | |
5083 | .out(dout[0:0]) | |
5084 | ); | |
5085 | ||
5086 | ||
5087 | ||
5088 | ||
5089 | ||
5090 | ||
5091 | ||
5092 | ||
5093 | ||
5094 | endmodule | |
5095 | ||
5096 | ||
5097 | ||
5098 | ||
5099 | ||
5100 | // | |
5101 | // and macro for ports = 2,3,4 | |
5102 | // | |
5103 | // | |
5104 | ||
5105 | ||
5106 | ||
5107 | ||
5108 | ||
5109 | module n2_icd_sp_16p5kb_cust_and_macro ( | |
5110 | din0, | |
5111 | din1, | |
5112 | dout); | |
5113 | input [0:0] din0; | |
5114 | input [0:0] din1; | |
5115 | output [0:0] dout; | |
5116 | ||
5117 | ||
5118 | ||
5119 | ||
5120 | ||
5121 | ||
5122 | and2 #(1) d0_0 ( | |
5123 | .in0(din0[0:0]), | |
5124 | .in1(din1[0:0]), | |
5125 | .out(dout[0:0]) | |
5126 | ); | |
5127 | ||
5128 | ||
5129 | ||
5130 | ||
5131 | ||
5132 | ||
5133 | ||
5134 | ||
5135 | ||
5136 | endmodule | |
5137 | ||
5138 | ||
5139 | ||
5140 | ||
5141 | ||
5142 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
5143 | // also for pass-gate with decoder | |
5144 | ||
5145 | ||
5146 | ||
5147 | ||
5148 | ||
5149 | // any PARAMS parms go into naming of macro | |
5150 | ||
5151 | module n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_8 ( | |
5152 | din0, | |
5153 | din1, | |
5154 | din2, | |
5155 | din3, | |
5156 | din4, | |
5157 | din5, | |
5158 | din6, | |
5159 | din7, | |
5160 | sel, | |
5161 | dout); | |
5162 | wire psel0; | |
5163 | wire psel1; | |
5164 | wire psel2; | |
5165 | wire psel3; | |
5166 | wire psel4; | |
5167 | wire psel5; | |
5168 | wire psel6; | |
5169 | wire psel7; | |
5170 | ||
5171 | input [7:0] din0; | |
5172 | input [7:0] din1; | |
5173 | input [7:0] din2; | |
5174 | input [7:0] din3; | |
5175 | input [7:0] din4; | |
5176 | input [7:0] din5; | |
5177 | input [7:0] din6; | |
5178 | input [7:0] din7; | |
5179 | input [2:0] sel; | |
5180 | output [7:0] dout; | |
5181 | ||
5182 | ||
5183 | ||
5184 | ||
5185 | ||
5186 | cl_dp1_pdec8_8x c0_0 ( | |
5187 | .test(1'b1), | |
5188 | .sel0(sel[0]), | |
5189 | .sel1(sel[1]), | |
5190 | .sel2(sel[2]), | |
5191 | .psel0(psel0), | |
5192 | .psel1(psel1), | |
5193 | .psel2(psel2), | |
5194 | .psel3(psel3), | |
5195 | .psel4(psel4), | |
5196 | .psel5(psel5), | |
5197 | .psel6(psel6), | |
5198 | .psel7(psel7) | |
5199 | ); | |
5200 | ||
5201 | mux8s #(8) d0_0 ( | |
5202 | .sel0(psel0), | |
5203 | .sel1(psel1), | |
5204 | .sel2(psel2), | |
5205 | .sel3(psel3), | |
5206 | .sel4(psel4), | |
5207 | .sel5(psel5), | |
5208 | .sel6(psel6), | |
5209 | .sel7(psel7), | |
5210 | .in0(din0[7:0]), | |
5211 | .in1(din1[7:0]), | |
5212 | .in2(din2[7:0]), | |
5213 | .in3(din3[7:0]), | |
5214 | .in4(din4[7:0]), | |
5215 | .in5(din5[7:0]), | |
5216 | .in6(din6[7:0]), | |
5217 | .in7(din7[7:0]), | |
5218 | .dout(dout[7:0]) | |
5219 | ); | |
5220 | ||
5221 | ||
5222 | ||
5223 | ||
5224 | ||
5225 | ||
5226 | ||
5227 | ||
5228 | ||
5229 | ||
5230 | ||
5231 | ||
5232 | ||
5233 | endmodule | |
5234 | ||
5235 | ||
5236 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
5237 | // also for pass-gate with decoder | |
5238 | ||
5239 | ||
5240 | ||
5241 | ||
5242 | ||
5243 | // any PARAMS parms go into naming of macro | |
5244 | ||
5245 | module n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__width_16 ( | |
5246 | din0, | |
5247 | din1, | |
5248 | sel0, | |
5249 | dout); | |
5250 | wire psel0; | |
5251 | wire psel1; | |
5252 | ||
5253 | input [15:0] din0; | |
5254 | input [15:0] din1; | |
5255 | input sel0; | |
5256 | output [15:0] dout; | |
5257 | ||
5258 | ||
5259 | ||
5260 | ||
5261 | ||
5262 | cl_dp1_penc2_8x c0_0 ( | |
5263 | .sel0(sel0), | |
5264 | .psel0(psel0), | |
5265 | .psel1(psel1) | |
5266 | ); | |
5267 | ||
5268 | mux2s #(16) d0_0 ( | |
5269 | .sel0(psel0), | |
5270 | .sel1(psel1), | |
5271 | .in0(din0[15:0]), | |
5272 | .in1(din1[15:0]), | |
5273 | .dout(dout[15:0]) | |
5274 | ); | |
5275 | ||
5276 | ||
5277 | ||
5278 | ||
5279 | ||
5280 | ||
5281 | ||
5282 | ||
5283 | ||
5284 | ||
5285 | ||
5286 | ||
5287 | ||
5288 | endmodule | |
5289 | ||
5290 | ||
5291 | module n2_icd_quad_array ( | |
5292 | adr_ac_h, | |
5293 | adr_ac_l, | |
5294 | rd_en_a_l, | |
5295 | quaden_f_l, | |
5296 | wr_word_en_ac_l, | |
5297 | wr_waysel0_ac_l, | |
5298 | wr_waysel1_ac_l, | |
5299 | din0_a, | |
5300 | din1_a, | |
5301 | red_d_ff, | |
5302 | red_en_ff, | |
5303 | rid_sel, | |
5304 | red_arst_ff, | |
5305 | red_wen_ff, | |
5306 | rd_worden_ac_l, | |
5307 | l1clk, | |
5308 | l1clk_fuse, | |
5309 | vnw_ary, | |
5310 | dout_wy0_bc, | |
5311 | dout_wy1_bc, | |
5312 | dout_wy2_bc, | |
5313 | dout_wy3_bc, | |
5314 | dout_wy4_bc, | |
5315 | dout_wy5_bc, | |
5316 | dout_wy6_bc, | |
5317 | dout_wy7_bc, | |
5318 | reg_d_lft_top, | |
5319 | reg_en_lft_top, | |
5320 | reg_d_rgt_top, | |
5321 | reg_en_rgt_top, | |
5322 | reg_d_lft_bot, | |
5323 | reg_en_lft_bot, | |
5324 | reg_d_rgt_bot, | |
5325 | reg_en_rgt_bot) ; | |
5326 | wire [3:0] red_write; | |
5327 | wire [4:0] reg_d_lft_top_in; | |
5328 | wire [1:0] reg_en_lft_top_in; | |
5329 | wire [4:0] reg_d_rgt_top_in; | |
5330 | wire [1:0] reg_en_rgt_top_in; | |
5331 | wire [4:0] reg_d_lft_bot_in; | |
5332 | wire [1:0] reg_en_lft_bot_in; | |
5333 | wire [4:0] reg_d_rgt_bot_in; | |
5334 | wire [1:0] reg_en_rgt_bot_in; | |
5335 | ||
5336 | ||
5337 | ||
5338 | input [10:5] adr_ac_h; | |
5339 | input [10:5] adr_ac_l; | |
5340 | input rd_en_a_l; | |
5341 | input quaden_f_l; | |
5342 | input [1:0] wr_word_en_ac_l; | |
5343 | input [7:0] wr_waysel0_ac_l; | |
5344 | input [7:0] wr_waysel1_ac_l; | |
5345 | input [32:0] din0_a; | |
5346 | input [32:0] din1_a; | |
5347 | input [4:0] red_d_ff; | |
5348 | input [1:0] red_en_ff; | |
5349 | input [3:0] rid_sel; | |
5350 | input red_arst_ff; | |
5351 | input red_wen_ff; | |
5352 | input [1:0] rd_worden_ac_l; | |
5353 | input l1clk; | |
5354 | input l1clk_fuse; | |
5355 | input vnw_ary; | |
5356 | ||
5357 | output [32:0] dout_wy0_bc; | |
5358 | output [32:0] dout_wy1_bc; | |
5359 | output [32:0] dout_wy2_bc; | |
5360 | output [32:0] dout_wy3_bc; | |
5361 | output [32:0] dout_wy4_bc; | |
5362 | output [32:0] dout_wy5_bc; | |
5363 | output [32:0] dout_wy6_bc; | |
5364 | output [32:0] dout_wy7_bc; | |
5365 | ||
5366 | output [4:0] reg_d_lft_top ; | |
5367 | output [1:0] reg_en_lft_top ; | |
5368 | output [4:0] reg_d_rgt_top ; | |
5369 | output [1:0] reg_en_rgt_top ; | |
5370 | output [4:0] reg_d_lft_bot ; | |
5371 | output [1:0] reg_en_lft_bot ; | |
5372 | output [4:0] reg_d_rgt_bot ; | |
5373 | output [1:0] reg_en_rgt_bot ; | |
5374 | ||
5375 | reg [4:0] reg_d_lft_top ; | |
5376 | reg [1:0] reg_en_lft_top ; | |
5377 | reg [4:0] reg_d_rgt_top ; | |
5378 | reg [1:0] reg_en_rgt_top ; | |
5379 | reg [4:0] reg_d_lft_bot ; | |
5380 | reg [1:0] reg_en_lft_bot ; | |
5381 | reg [4:0] reg_d_rgt_bot ; | |
5382 | reg [1:0] reg_en_rgt_bot ; | |
5383 | ||
5384 | ////////////////////////////////////////// | |
5385 | // top bank // | |
5386 | ////////////////////////////////////////// | |
5387 | n2_icd_bank w3_to_w0_bank(.adr_ac_h(adr_ac_h[10:5]), | |
5388 | .adr_ac_l(adr_ac_l[10:5]), | |
5389 | .rd_en_a_l(rd_en_a_l), | |
5390 | .quaden_f_l(quaden_f_l), | |
5391 | .wr_word_en_ac_l(wr_word_en_ac_l[1:0]), | |
5392 | .wr_waysel0_ac_l(wr_waysel0_ac_l[3:0]), | |
5393 | .wr_waysel1_ac_l(wr_waysel1_ac_l[3:0]), | |
5394 | .din0_a(din0_a[32:0]), | |
5395 | .din1_a(din1_a[32:0]), | |
5396 | .dout_wy0_bc(dout_wy0_bc[32:0]), | |
5397 | .dout_wy1_bc(dout_wy1_bc[32:0]), | |
5398 | .dout_wy2_bc(dout_wy2_bc[32:0]), | |
5399 | .dout_wy3_bc(dout_wy3_bc[32:0]), | |
5400 | .reg_d_lft(reg_d_lft_top[4:0]), | |
5401 | .reg_en_lft(reg_en_lft_top[1:0]), | |
5402 | .reg_d_rgt(reg_d_rgt_top[4:0]), | |
5403 | .reg_en_rgt(reg_en_rgt_top[1:0]), | |
5404 | .rd_worden_ac_l(rd_worden_ac_l[1:0]), | |
5405 | .l1clk(l1clk), | |
5406 | .vnw_ary(vnw_ary) | |
5407 | ); | |
5408 | ||
5409 | ||
5410 | ////////////////////////////////////////// | |
5411 | // bottom bank // | |
5412 | ////////////////////////////////////////// | |
5413 | n2_icd_bank w7_to_w4_bank(.adr_ac_h(adr_ac_h[10:5]), | |
5414 | .adr_ac_l(adr_ac_l[10:5]), | |
5415 | .rd_en_a_l(rd_en_a_l), | |
5416 | .quaden_f_l(quaden_f_l), | |
5417 | .wr_word_en_ac_l(wr_word_en_ac_l[1:0]), | |
5418 | .wr_waysel0_ac_l(wr_waysel0_ac_l[7:4]), | |
5419 | .wr_waysel1_ac_l(wr_waysel1_ac_l[7:4]), | |
5420 | .din0_a(din0_a[32:0]), | |
5421 | .din1_a(din1_a[32:0]), | |
5422 | .dout_wy0_bc(dout_wy4_bc[32:0]), | |
5423 | .dout_wy1_bc(dout_wy5_bc[32:0]), | |
5424 | .dout_wy2_bc(dout_wy6_bc[32:0]), | |
5425 | .dout_wy3_bc(dout_wy7_bc[32:0]), | |
5426 | .reg_d_lft(reg_d_lft_bot[4:0]), | |
5427 | .reg_en_lft(reg_en_lft_bot[1:0]), | |
5428 | .reg_d_rgt(reg_d_rgt_bot[4:0]), | |
5429 | .reg_en_rgt(reg_en_rgt_bot[1:0]), | |
5430 | .rd_worden_ac_l(rd_worden_ac_l[1:0]), | |
5431 | .l1clk(l1clk), | |
5432 | .vnw_ary(vnw_ary) | |
5433 | ); | |
5434 | ||
5435 | ||
5436 | assign red_write[3:0] = ({4{red_wen_ff}} & rid_sel[3:0]) ; | |
5437 | assign reg_d_lft_top_in[4:0] = (red_arst_ff) ? 5'b00000 : | |
5438 | (red_write[2]) ? red_d_ff[4:0] : reg_d_lft_top[4:0] ; | |
5439 | assign reg_en_lft_top_in[1:0] = (red_arst_ff) ? 2'b00 : | |
5440 | (red_write[2]) ? red_en_ff[1:0] : reg_en_lft_top[1:0]; | |
5441 | ||
5442 | assign reg_d_rgt_top_in[4:0] = (red_arst_ff) ? 5'b00000 : | |
5443 | (red_write[3]) ? red_d_ff[4:0] : reg_d_rgt_top[4:0] ; | |
5444 | assign reg_en_rgt_top_in[1:0] = (red_arst_ff) ? 2'b00 : | |
5445 | (red_write[3]) ? red_en_ff[1:0] : reg_en_rgt_top[1:0]; | |
5446 | ||
5447 | assign reg_d_lft_bot_in[4:0] = (red_arst_ff) ? 5'b00000 : | |
5448 | (red_write[0]) ? red_d_ff[4:0] : reg_d_lft_bot[4:0] ; | |
5449 | assign reg_en_lft_bot_in[1:0] = (red_arst_ff) ? 2'b00 : | |
5450 | (red_write[0]) ? red_en_ff[1:0] : reg_en_lft_bot[1:0]; | |
5451 | ||
5452 | assign reg_d_rgt_bot_in[4:0] = (red_arst_ff) ? 5'b00000 : | |
5453 | (red_write[1]) ? red_d_ff[4:0] : reg_d_rgt_bot[4:0] ; | |
5454 | assign reg_en_rgt_bot_in[1:0] = (red_arst_ff) ? 2'b00 : | |
5455 | (red_write[1]) ? red_en_ff[1:0] : reg_en_rgt_bot[1:0]; | |
5456 | ||
5457 | ||
5458 | ||
5459 | //always @(posedge l1clk) begin | |
5460 | always @(l1clk_fuse or red_arst_ff or red_wen_ff) begin | |
5461 | ||
5462 | // this is a b-latch so need to update when red_wen_ff or red_arst_ff changes | |
5463 | // red_wen_ff or red_arst_ff can change in b-phase b/c of wr_inhibit signal | |
5464 | if (~l1clk_fuse) begin | |
5465 | reg_d_lft_top[4:0] <= reg_d_lft_top_in[4:0] ; | |
5466 | reg_en_lft_top[1:0] <= reg_en_lft_top_in[1:0] ; | |
5467 | reg_d_rgt_top[4:0] <= reg_d_rgt_top_in[4:0] ; | |
5468 | reg_en_rgt_top[1:0] <= reg_en_rgt_top_in[1:0] ; | |
5469 | reg_d_lft_bot[4:0] <= reg_d_lft_bot_in[4:0] ; | |
5470 | reg_en_lft_bot[1:0] <= reg_en_lft_bot_in[1:0] ; | |
5471 | reg_d_rgt_bot[4:0] <= reg_d_rgt_bot_in[4:0] ; | |
5472 | reg_en_rgt_bot[1:0] <= reg_en_rgt_bot_in[1:0] ; | |
5473 | end | |
5474 | ||
5475 | end | |
5476 | ||
5477 | ||
5478 | endmodule | |
5479 | ||
5480 | ||
5481 | module n2_icd_bank ( | |
5482 | adr_ac_h, | |
5483 | adr_ac_l, | |
5484 | rd_en_a_l, | |
5485 | quaden_f_l, | |
5486 | wr_word_en_ac_l, | |
5487 | wr_waysel0_ac_l, | |
5488 | wr_waysel1_ac_l, | |
5489 | din0_a, | |
5490 | din1_a, | |
5491 | rd_worden_ac_l, | |
5492 | l1clk, | |
5493 | vnw_ary, | |
5494 | reg_d_lft, | |
5495 | reg_d_rgt, | |
5496 | reg_en_lft, | |
5497 | reg_en_rgt, | |
5498 | dout_wy0_bc, | |
5499 | dout_wy1_bc, | |
5500 | dout_wy2_bc, | |
5501 | dout_wy3_bc); | |
5502 | wire [16:0] din0_a_rev; | |
5503 | wire [16:0] din1_a_rev; | |
5504 | wire [16:0] dout_wy0_bc_rev; | |
5505 | wire [16:0] dout_wy1_bc_rev; | |
5506 | wire [16:0] dout_wy2_bc_rev; | |
5507 | wire [16:0] dout_wy3_bc_rev; | |
5508 | ||
5509 | ||
5510 | input [5:0] adr_ac_h ; | |
5511 | input [5:0] adr_ac_l ; | |
5512 | input rd_en_a_l ; | |
5513 | input quaden_f_l ; | |
5514 | input [1:0] wr_word_en_ac_l ; | |
5515 | input [3:0] wr_waysel0_ac_l ; | |
5516 | input [3:0] wr_waysel1_ac_l ; | |
5517 | input [32:0] din0_a ; | |
5518 | input [32:0] din1_a ; | |
5519 | input [1:0] rd_worden_ac_l ; | |
5520 | input l1clk ; | |
5521 | ||
5522 | input vnw_ary; | |
5523 | ||
5524 | input [4:0] reg_d_lft; | |
5525 | input [4:0] reg_d_rgt; | |
5526 | input [1:0] reg_en_lft; | |
5527 | input [1:0] reg_en_rgt; | |
5528 | ||
5529 | output [32:0] dout_wy0_bc ; | |
5530 | output [32:0] dout_wy1_bc ; | |
5531 | output [32:0] dout_wy2_bc ; | |
5532 | output [32:0] dout_wy3_bc ; | |
5533 | ||
5534 | ||
5535 | ||
5536 | assign din0_a_rev[16:0] = {din0_a[0],din0_a[1],din0_a[2],din0_a[3],din0_a[4],din0_a[5],din0_a[6],din0_a[7],din0_a[8], | |
5537 | din0_a[9],din0_a[10],din0_a[11],din0_a[12],din0_a[13],din0_a[14],din0_a[15],din0_a[16]}; | |
5538 | assign din1_a_rev[16:0] = {din1_a[0],din1_a[1],din1_a[2],din1_a[3],din1_a[4],din1_a[5],din1_a[6],din1_a[7],din1_a[8], | |
5539 | din1_a[9],din1_a[10],din1_a[11],din1_a[12],din1_a[13],din1_a[14],din1_a[15],din1_a[16]}; | |
5540 | ||
5541 | n2_icd_lft_sb_array left_sb_array ( | |
5542 | ||
5543 | .adr_ac_h (adr_ac_h[5:0]), | |
5544 | .adr_ac_l (adr_ac_l[5:0]), | |
5545 | .rd_en_a_l (rd_en_a_l), | |
5546 | .quaden_f_l (quaden_f_l), | |
5547 | .wr_word_en_ac_l (wr_word_en_ac_l[1:0]) , | |
5548 | .wr_waysel0_ac_l (wr_waysel0_ac_l[3:0]), | |
5549 | .wr_waysel1_ac_l (wr_waysel1_ac_l[3:0]), | |
5550 | .din0_a (din0_a_rev[16:0]), | |
5551 | .din1_a (din1_a_rev[16:0]), | |
5552 | .rd_worden_ac_l (rd_worden_ac_l[1:0]), | |
5553 | .l1clk (l1clk), | |
5554 | ||
5555 | .reg_d_lft (reg_d_lft[4:0]), | |
5556 | .reg_en_lft (reg_en_lft[1:0]), | |
5557 | ||
5558 | .dout_wy0_bc (dout_wy0_bc_rev[16:0]), | |
5559 | .dout_wy1_bc (dout_wy1_bc_rev[16:0]), | |
5560 | .dout_wy2_bc (dout_wy2_bc_rev[16:0]), | |
5561 | .dout_wy3_bc (dout_wy3_bc_rev[16:0]), | |
5562 | .vnw_ary(vnw_ary) ) ; | |
5563 | ||
5564 | assign dout_wy0_bc[16:0] = {dout_wy0_bc_rev[0],dout_wy0_bc_rev[1],dout_wy0_bc_rev[2],dout_wy0_bc_rev[3], | |
5565 | dout_wy0_bc_rev[4], dout_wy0_bc_rev[5],dout_wy0_bc_rev[6],dout_wy0_bc_rev[7], | |
5566 | dout_wy0_bc_rev[8],dout_wy0_bc_rev[9], dout_wy0_bc_rev[10],dout_wy0_bc_rev[11], | |
5567 | dout_wy0_bc_rev[12],dout_wy0_bc_rev[13],dout_wy0_bc_rev[14], dout_wy0_bc_rev[15],dout_wy0_bc_rev[16]}; | |
5568 | ||
5569 | assign dout_wy1_bc[16:0] = {dout_wy1_bc_rev[0],dout_wy1_bc_rev[1],dout_wy1_bc_rev[2],dout_wy1_bc_rev[3], | |
5570 | dout_wy1_bc_rev[4],dout_wy1_bc_rev[5],dout_wy1_bc_rev[6],dout_wy1_bc_rev[7], | |
5571 | dout_wy1_bc_rev[8],dout_wy1_bc_rev[9],dout_wy1_bc_rev[10],dout_wy1_bc_rev[11], | |
5572 | dout_wy1_bc_rev[12],dout_wy1_bc_rev[13],dout_wy1_bc_rev[14],dout_wy1_bc_rev[15],dout_wy1_bc_rev[16]}; | |
5573 | ||
5574 | assign dout_wy2_bc[16:0] = {dout_wy2_bc_rev[0],dout_wy2_bc_rev[1],dout_wy2_bc_rev[2],dout_wy2_bc_rev[3], | |
5575 | dout_wy2_bc_rev[4],dout_wy2_bc_rev[5],dout_wy2_bc_rev[6],dout_wy2_bc_rev[7], | |
5576 | dout_wy2_bc_rev[8],dout_wy2_bc_rev[9],dout_wy2_bc_rev[10],dout_wy2_bc_rev[11], | |
5577 | dout_wy2_bc_rev[12],dout_wy2_bc_rev[13],dout_wy2_bc_rev[14],dout_wy2_bc_rev[15],dout_wy2_bc_rev[16]}; | |
5578 | ||
5579 | assign dout_wy3_bc[16:0] = {dout_wy3_bc_rev[0],dout_wy3_bc_rev[1],dout_wy3_bc_rev[2],dout_wy3_bc_rev[3], | |
5580 | dout_wy3_bc_rev[4],dout_wy3_bc_rev[5],dout_wy3_bc_rev[6],dout_wy3_bc_rev[7], | |
5581 | dout_wy3_bc_rev[8],dout_wy3_bc_rev[9],dout_wy3_bc_rev[10],dout_wy3_bc_rev[11], | |
5582 | dout_wy3_bc_rev[12],dout_wy3_bc_rev[13],dout_wy3_bc_rev[14],dout_wy3_bc_rev[15],dout_wy3_bc_rev[16]}; | |
5583 | ||
5584 | n2_icd_rgt_sb_array right_sb_array ( | |
5585 | ||
5586 | .adr_ac_h (adr_ac_h[5:0]), | |
5587 | .adr_ac_l (adr_ac_l[5:0]), | |
5588 | .rd_en_a_l (rd_en_a_l), | |
5589 | .quaden_f_l (quaden_f_l), | |
5590 | .wr_word_en_ac_l (wr_word_en_ac_l[1:0]) , | |
5591 | .wr_waysel0_ac_l (wr_waysel0_ac_l[3:0]), | |
5592 | .wr_waysel1_ac_l (wr_waysel1_ac_l[3:0]), | |
5593 | .din0_a (din0_a[32:17]), | |
5594 | .din1_a (din1_a[32:17]), | |
5595 | .rd_worden_ac_l (rd_worden_ac_l[1:0]), | |
5596 | .l1clk (l1clk), | |
5597 | ||
5598 | .reg_d_rgt (reg_d_rgt[4:0]), | |
5599 | .reg_en_rgt (reg_en_rgt[1:0]), | |
5600 | ||
5601 | .dout_wy0_bc (dout_wy0_bc[32:17]), | |
5602 | .dout_wy1_bc (dout_wy1_bc[32:17]), | |
5603 | .dout_wy2_bc (dout_wy2_bc[32:17]), | |
5604 | .dout_wy3_bc (dout_wy3_bc[32:17]), | |
5605 | .vnw_ary(vnw_ary) ) ; | |
5606 | ||
5607 | ||
5608 | supply0 vss; | |
5609 | supply1 vdd; | |
5610 | endmodule | |
5611 | ||
5612 | ||
5613 | `ifndef FPGA | |
5614 | ||
5615 | module n2_icd_lft_sb_array ( | |
5616 | adr_ac_h, | |
5617 | adr_ac_l, | |
5618 | rd_en_a_l, | |
5619 | quaden_f_l, | |
5620 | wr_word_en_ac_l, | |
5621 | wr_waysel0_ac_l, | |
5622 | wr_waysel1_ac_l, | |
5623 | din0_a, | |
5624 | din1_a, | |
5625 | rd_worden_ac_l, | |
5626 | l1clk, | |
5627 | reg_d_lft, | |
5628 | reg_en_lft, | |
5629 | vnw_ary, | |
5630 | dout_wy0_bc, | |
5631 | dout_wy1_bc, | |
5632 | dout_wy2_bc, | |
5633 | dout_wy3_bc); | |
5634 | wire [135:0] word_write_en; | |
5635 | wire [135:0] way_write_en; | |
5636 | wire [135:0] data_in; | |
5637 | wire rd_worden_ac_l_unused; | |
5638 | wire [5:0] adr_ac_l_unused; | |
5639 | ||
5640 | ||
5641 | input [5:0] adr_ac_h ; | |
5642 | input [5:0] adr_ac_l ; | |
5643 | input rd_en_a_l ; | |
5644 | input quaden_f_l ; | |
5645 | input [1:0] wr_word_en_ac_l ; | |
5646 | input [3:0] wr_waysel0_ac_l ; | |
5647 | input [3:0] wr_waysel1_ac_l ; | |
5648 | input [16:0] din0_a ; | |
5649 | input [16:0] din1_a ; | |
5650 | input [1:0] rd_worden_ac_l ; | |
5651 | input l1clk ; | |
5652 | ||
5653 | input [4:0] reg_d_lft; | |
5654 | input [1:0] reg_en_lft; | |
5655 | ||
5656 | input vnw_ary; | |
5657 | ||
5658 | output [16:0] dout_wy0_bc ; | |
5659 | output [16:0] dout_wy1_bc ; | |
5660 | output [16:0] dout_wy2_bc ; | |
5661 | output [16:0] dout_wy3_bc ; | |
5662 | ||
5663 | ||
5664 | reg [143:0] mem[63:0] ; | |
5665 | ||
5666 | ||
5667 | reg [143:0] local_dout; | |
5668 | reg [135:0] old_data; | |
5669 | reg [143:0] wr_data; | |
5670 | reg [135:0] dout; | |
5671 | wire [143:0] temp; | |
5672 | wire [135:0] din; | |
5673 | ||
5674 | reg [16:0] dout_wy0_bc ; | |
5675 | reg [16:0] dout_wy1_bc ; | |
5676 | reg [16:0] dout_wy2_bc ; | |
5677 | reg [16:0] dout_wy3_bc ; | |
5678 | ||
5679 | reg [16:0] way3_word0 ; | |
5680 | reg [16:0] way3_word1 ; | |
5681 | reg [16:0] way2_word0 ; | |
5682 | reg [16:0] way2_word1 ; | |
5683 | reg [16:0] way1_word0 ; | |
5684 | reg [16:0] way1_word1 ; | |
5685 | reg [16:0] way0_word0 ; | |
5686 | reg [16:0] way0_word1 ; | |
5687 | reg [31:0] n_reg1; | |
5688 | reg [31:0] n_reg2; | |
5689 | reg [31:0] n_reg3; | |
5690 | reg word_0_read; | |
5691 | integer n; | |
5692 | ||
5693 | `ifndef NOINITMEM | |
5694 | // Emulate reset | |
5695 | integer i; | |
5696 | initial begin | |
5697 | for (i=0; i<64; i=i+1) begin | |
5698 | mem [i] = {144{1'b0}}; | |
5699 | end | |
5700 | local_dout = {144{1'b0}}; | |
5701 | end | |
5702 | `endif | |
5703 | ||
5704 | ||
5705 | ||
5706 | // assign word_0_read = ~rd_worden_ac_l[0] & ~rd_en_a_l ; | |
5707 | // assign red_value[4:0] = reg_d_lft[4:0] & {5{reg_en_lft[1] & reg_en_lft[0]}}; | |
5708 | assign temp[143:0] = mem[adr_ac_h[5:0]] ; | |
5709 | ||
5710 | //////////////////////////////// | |
5711 | // Redunduncy Read shifter | |
5712 | //////////////////////////////// | |
5713 | always @(reg_en_lft[1:0] or reg_d_lft or temp ) begin | |
5714 | for (n = 0; n < 136; n = n + 1 ) begin | |
5715 | n_reg1 = n; | |
5716 | if (reg_en_lft[1] & reg_en_lft[0] & ( reg_d_lft >= 5'b00000) & (reg_d_lft <= 5'b10000)) begin | |
5717 | if ( n_reg1[9:0] >= ((reg_d_lft + 5'h1) * 5'b01000)) | |
5718 | old_data[n] = temp[n+8] ; | |
5719 | else | |
5720 | old_data[n] = temp[n] ; | |
5721 | end else | |
5722 | old_data[n] = temp[n+8] ; | |
5723 | end | |
5724 | end | |
5725 | ||
5726 | assign word_write_en[135:0] = {68{~wr_word_en_ac_l[0], ~wr_word_en_ac_l[1]}} ; | |
5727 | assign way_write_en[135:0] = {17{~wr_waysel0_ac_l[3] , ~wr_waysel1_ac_l[3] ,~wr_waysel0_ac_l[2] , ~wr_waysel1_ac_l[2], | |
5728 | ~wr_waysel0_ac_l[1] , ~wr_waysel1_ac_l[1] ,~wr_waysel0_ac_l[0] , ~wr_waysel1_ac_l[0] }} ; | |
5729 | ||
5730 | assign data_in[135:0] = {din0_a[16],din1_a[16] , din0_a[16],din1_a[16] , din0_a[16],din1_a[16] , din0_a[16],din1_a[16], // 135:128 | |
5731 | din0_a[15],din1_a[15] , din0_a[15],din1_a[15] , din0_a[15],din1_a[15] , din0_a[15],din1_a[15], // 127:120 | |
5732 | din0_a[14],din1_a[14] , din0_a[14],din1_a[14] , din0_a[14],din1_a[14] , din0_a[14],din1_a[14], // 119:112 | |
5733 | din0_a[13],din1_a[13] , din0_a[13],din1_a[13] , din0_a[13],din1_a[13] , din0_a[13],din1_a[13], // 111:104 | |
5734 | din0_a[12],din1_a[12] , din0_a[12],din1_a[12] , din0_a[12],din1_a[12] , din0_a[12],din1_a[12], // 103:096 | |
5735 | din0_a[11],din1_a[11] , din0_a[11],din1_a[11] , din0_a[11],din1_a[11] , din0_a[11],din1_a[11], // 095:088 | |
5736 | din0_a[10],din1_a[10] , din0_a[10],din1_a[10] , din0_a[10],din1_a[10] , din0_a[10],din1_a[10], // 087:080 | |
5737 | din0_a[9],din1_a[9] , din0_a[9],din1_a[9] , din0_a[9],din1_a[9] , din0_a[9],din1_a[9], // 079:072 | |
5738 | din0_a[8],din1_a[8] , din0_a[8],din1_a[8] , din0_a[8],din1_a[8] , din0_a[8],din1_a[8], // 071:064 | |
5739 | din0_a[7],din1_a[7] , din0_a[7],din1_a[7] , din0_a[7],din1_a[7] , din0_a[7],din1_a[7], // 063:056 | |
5740 | din0_a[6],din1_a[6] , din0_a[6],din1_a[6] , din0_a[6],din1_a[6] , din0_a[6],din1_a[6], // 055:048 | |
5741 | din0_a[5],din1_a[5] , din0_a[5],din1_a[5] , din0_a[5],din1_a[5] , din0_a[5],din1_a[5], // 047:040 | |
5742 | din0_a[4],din1_a[4] , din0_a[4],din1_a[4] , din0_a[4],din1_a[4] , din0_a[4],din1_a[4], // 039:032 | |
5743 | din0_a[3],din1_a[3] , din0_a[3],din1_a[3] , din0_a[3],din1_a[3] , din0_a[3],din1_a[3], // 031:024 | |
5744 | din0_a[2],din1_a[2] , din0_a[2],din1_a[2] , din0_a[2],din1_a[2] , din0_a[2],din1_a[2], // 023:016 | |
5745 | din0_a[1],din1_a[1] , din0_a[1],din1_a[1] , din0_a[1],din1_a[1] , din0_a[1],din1_a[1], // 015:008 | |
5746 | din0_a[0],din1_a[0] , din0_a[0],din1_a[0] , din0_a[0],din1_a[0] , din0_a[0],din1_a[0]};// 007:000 | |
5747 | ||
5748 | ||
5749 | assign din[135:0] = ( way_write_en[135:0] & word_write_en[135:0] & data_in[135:0] ) | | |
5750 | ( ~(way_write_en[135:0] & word_write_en[135:0]) & old_data[135:0] ) ; | |
5751 | ||
5752 | ||
5753 | //////////////////////////////// | |
5754 | // Redunduncy write shifter | |
5755 | //////////////////////////////// | |
5756 | ||
5757 | always @(reg_en_lft[1:0] or reg_d_lft or din ) begin | |
5758 | for (n = 0; n < 144; n = n + 1 ) begin | |
5759 | n_reg2 = n; | |
5760 | if (reg_en_lft[1] & reg_en_lft[0] & ( reg_d_lft >= 5'b00000) & (reg_d_lft <= 5'b10000)) begin | |
5761 | if ( n_reg2[9:0] < ((reg_d_lft + 5'h1) * 5'b01000 )) | |
5762 | wr_data[n] = din[n] ; | |
5763 | else begin | |
5764 | if ( n_reg2[9:0] < ((reg_d_lft + 5'h2) * 5'b01000 )) | |
5765 | wr_data[n] = 1'bx ; | |
5766 | else | |
5767 | wr_data[n] = din[n-8] ; | |
5768 | end | |
5769 | end else begin | |
5770 | if (n < 8 ) | |
5771 | wr_data[n] = 1'bx ; | |
5772 | else | |
5773 | wr_data[n] = din[n-8] ; | |
5774 | end | |
5775 | end | |
5776 | end | |
5777 | ||
5778 | ////////////////////// | |
5779 | // Read/write array | |
5780 | ////////////////////// | |
5781 | ||
5782 | always @ (l1clk or wr_data[143:0] or wr_word_en_ac_l[1:0] or adr_ac_h[5:0] or quaden_f_l or vnw_ary) begin | |
5783 | if (l1clk & ~quaden_f_l & (~wr_word_en_ac_l[1] | ~wr_word_en_ac_l[0]) & vnw_ary) begin | |
5784 | mem[adr_ac_h] <= wr_data[143:0] ; | |
5785 | ||
5786 | ||
5787 | end // end if | |
5788 | end // end always | |
5789 | ||
5790 | ||
5791 | ||
5792 | always @(l1clk or rd_en_a_l or reg_en_lft[1:0] or reg_d_lft or adr_ac_h[5:0] or rd_worden_ac_l[0] or vnw_ary) begin | |
5793 | if (l1clk | rd_en_a_l) begin | |
5794 | dout_wy0_bc[16:0] <= 17'h0; | |
5795 | dout_wy1_bc[16:0] <= 17'h0; | |
5796 | dout_wy2_bc[16:0] <= 17'h0; | |
5797 | dout_wy3_bc[16:0] <= 17'h0; | |
5798 | word_0_read <= ~rd_worden_ac_l[0]; | |
5799 | local_dout[143:0] <= rd_en_a_l ? 144'h0 : mem[adr_ac_h[5:0]]; | |
5800 | end | |
5801 | if (~l1clk & ~rd_en_a_l & vnw_ary) begin | |
5802 | ||
5803 | ||
5804 | ||
5805 | ||
5806 | ||
5807 | //////////////////////////////// | |
5808 | // Redunduncy Read shifter | |
5809 | //////////////////////////////// | |
5810 | ||
5811 | for (n = 0; n < 136; n = n + 1 ) begin | |
5812 | n_reg3 = n; | |
5813 | if (reg_en_lft[1] & reg_en_lft[0] & ( reg_d_lft >= 5'b00000) & (reg_d_lft <= 5'b10000)) begin | |
5814 | if ( n_reg3[9:0] >= ((reg_d_lft + 5'h1) * 5'b01000)) | |
5815 | dout[n] = local_dout[n+8] ; | |
5816 | else | |
5817 | dout[n] = local_dout[n] ; | |
5818 | end else | |
5819 | dout[n] = local_dout[n+8] ; | |
5820 | end | |
5821 | /////////////end redundacy shifter /////////////////// | |
5822 | ||
5823 | way3_word0[16:0] = {dout[135], dout[127], dout[119] , dout[111], | |
5824 | dout[103], dout[95], dout[87] , dout[79], | |
5825 | dout[71], dout[63], dout[55] , dout[47], | |
5826 | dout[39], dout[31], dout[23] , dout[15], | |
5827 | dout[7] } ; | |
5828 | ||
5829 | way3_word1[16:0] = {dout[134], dout[126], dout[118] , dout[110], | |
5830 | dout[102], dout[94], dout[86] , dout[78], | |
5831 | dout[70], dout[62], dout[54] , dout[46], | |
5832 | dout[38], dout[30], dout[22] , dout[14], | |
5833 | dout[6] } ; | |
5834 | ||
5835 | way2_word0[16:0] = {dout[133], dout[125], dout[117] , dout[109], | |
5836 | dout[101], dout[93], dout[85] , dout[77], | |
5837 | dout[69], dout[61], dout[53] , dout[45], | |
5838 | dout[37], dout[29], dout[21] , dout[13], | |
5839 | dout[5] } ; | |
5840 | ||
5841 | way2_word1[16:0] = {dout[132], dout[124], dout[116] , dout[108], | |
5842 | dout[100], dout[92], dout[84] , dout[76], | |
5843 | dout[68], dout[60], dout[52] , dout[44], | |
5844 | dout[36], dout[28], dout[20] , dout[12], | |
5845 | dout[4] } ; | |
5846 | ||
5847 | way1_word0[16:0] = {dout[131], dout[123], dout[115] , dout[107], | |
5848 | dout[99], dout[91], dout[83] , dout[75], | |
5849 | dout[67], dout[59], dout[51] , dout[43], | |
5850 | dout[35], dout[27], dout[19] , dout[11], | |
5851 | dout[3] } ; | |
5852 | ||
5853 | way1_word1[16:0] = {dout[130], dout[122], dout[114] , dout[106], | |
5854 | dout[98], dout[90], dout[82] , dout[74], | |
5855 | dout[66], dout[58], dout[50] , dout[42], | |
5856 | dout[34], dout[26], dout[18] , dout[10], | |
5857 | dout[2] } ; | |
5858 | ||
5859 | way0_word0[16:0] = {dout[129], dout[121], dout[113] , dout[105], | |
5860 | dout[97], dout[89], dout[81] , dout[73], | |
5861 | dout[65], dout[57], dout[49] , dout[41], | |
5862 | dout[33], dout[25], dout[17] , dout[9], | |
5863 | dout[1] } ; | |
5864 | ||
5865 | way0_word1[16:0] = {dout[128], dout[120], dout[112] , dout[104], | |
5866 | dout[96], dout[88], dout[80] , dout[72], | |
5867 | dout[64], dout[56], dout[48] , dout[40], | |
5868 | dout[32], dout[24], dout[16] , dout[8], | |
5869 | dout[0] } ; | |
5870 | ||
5871 | /////////////////////// | |
5872 | // rd_data column mux | |
5873 | /////////////////////// | |
5874 | dout_wy0_bc[16:0] <= word_0_read ? way0_word0[16:0] : way0_word1[16:0] ; | |
5875 | dout_wy1_bc[16:0] <= word_0_read ? way1_word0[16:0] : way1_word1[16:0] ; | |
5876 | dout_wy2_bc[16:0] <= word_0_read ? way2_word0[16:0] : way2_word1[16:0] ; | |
5877 | dout_wy3_bc[16:0] <= word_0_read ? way3_word0[16:0] : way3_word1[16:0] ; | |
5878 | ||
5879 | end // if (~rd_en_a_l) | |
5880 | end // always | |
5881 | ||
5882 | // Precharge | |
5883 | // always @ (posedge l1clk) begin | |
5884 | // // local_dout[143:0] = 144'h0; | |
5885 | // dout_wy0_bc[16:0] <= 17'h0; | |
5886 | // dout_wy1_bc[16:0] <= 17'h0; | |
5887 | // dout_wy2_bc[16:0] <= 17'h0; | |
5888 | // dout_wy3_bc[16:0] <= 17'h0; | |
5889 | // end | |
5890 | ||
5891 | //////////////////////////////// | |
5892 | // Redunduncy Read shifter | |
5893 | //////////////////////////////// | |
5894 | // always @(red_value or local_dout ) begin | |
5895 | // for (n = 0; n < 144; n = n + 1 ) begin | |
5896 | // if ( n >= (red_value * 8 )) | |
5897 | // dout[n] = local_dout[n+8] ; | |
5898 | // else | |
5899 | // dout[n] = local_dout[n] ; | |
5900 | // end | |
5901 | // end | |
5902 | ||
5903 | assign rd_worden_ac_l_unused = rd_worden_ac_l[1] ; | |
5904 | assign adr_ac_l_unused[5:0] = adr_ac_l[5:0] ; | |
5905 | ||
5906 | ||
5907 | supply0 vss; | |
5908 | supply1 vdd; | |
5909 | endmodule | |
5910 | `endif // `ifndef FPGA | |
5911 | ||
5912 | `ifdef FPGA | |
5913 | ||
5914 | module n2_icd_lft_sb_array(adr_ac_h, adr_ac_l, rd_en_a_l, quaden_f_l, | |
5915 | wr_word_en_ac_l, wr_waysel0_ac_l, wr_waysel1_ac_l, din0_a, din1_a, | |
5916 | rd_worden_ac_l, l1clk, reg_d_lft, reg_en_lft, vnw_ary, dout_wy0_bc, | |
5917 | dout_wy1_bc, dout_wy2_bc, dout_wy3_bc); | |
5918 | ||
5919 | input [5:0] adr_ac_h; | |
5920 | input [5:0] adr_ac_l; | |
5921 | input rd_en_a_l; | |
5922 | input quaden_f_l; | |
5923 | input [1:0] wr_word_en_ac_l; | |
5924 | input [3:0] wr_waysel0_ac_l; | |
5925 | input [3:0] wr_waysel1_ac_l; | |
5926 | input [16:0] din0_a; | |
5927 | input [16:0] din1_a; | |
5928 | input [1:0] rd_worden_ac_l; | |
5929 | input l1clk; | |
5930 | input [4:0] reg_d_lft; | |
5931 | input [1:0] reg_en_lft; | |
5932 | input vnw_ary; | |
5933 | output [16:0] dout_wy0_bc; | |
5934 | output [16:0] dout_wy1_bc; | |
5935 | output [16:0] dout_wy2_bc; | |
5936 | output [16:0] dout_wy3_bc; | |
5937 | ||
5938 | wire [135:0] word_write_en; | |
5939 | wire [135:0] way_write_en; | |
5940 | wire [135:0] data_in; | |
5941 | wire rd_worden_ac_l_unused; | |
5942 | wire [5:0] adr_ac_l_unused; | |
5943 | ||
5944 | reg [143:0] mem[63:0]; | |
5945 | reg [143:0] local_dout; | |
5946 | reg [135:0] old_data; | |
5947 | reg [143:0] wr_data; | |
5948 | reg [135:0] dout; | |
5949 | wire [143:0] temp; | |
5950 | wire [135:0] din; | |
5951 | reg [16:0] dout_wy0_bc; | |
5952 | reg [16:0] dout_wy1_bc; | |
5953 | reg [16:0] dout_wy2_bc; | |
5954 | reg [16:0] dout_wy3_bc; | |
5955 | reg [16:0] way3_word0; | |
5956 | reg [16:0] way3_word1; | |
5957 | reg [16:0] way2_word0; | |
5958 | reg [16:0] way2_word1; | |
5959 | reg [16:0] way1_word0; | |
5960 | reg [16:0] way1_word1; | |
5961 | reg [16:0] way0_word0; | |
5962 | reg [16:0] way0_word1; | |
5963 | reg [31:0] n_reg1; | |
5964 | reg [31:0] n_reg2; | |
5965 | reg [31:0] n_reg3; | |
5966 | reg word_0_read; | |
5967 | integer n; | |
5968 | integer i; | |
5969 | supply0 vss; | |
5970 | supply1 vdd; | |
5971 | ||
5972 | assign temp[143:0] = mem[adr_ac_h[5:0]]; | |
5973 | assign word_write_en[135:0] = {68 {(~wr_word_en_ac_l[0]), | |
5974 | (~wr_word_en_ac_l[1])}}; | |
5975 | assign way_write_en[135:0] = {17 {(~wr_waysel0_ac_l[3]), | |
5976 | (~wr_waysel1_ac_l[3]), (~wr_waysel0_ac_l[2]), | |
5977 | (~wr_waysel1_ac_l[2]), (~wr_waysel0_ac_l[1]), | |
5978 | (~wr_waysel1_ac_l[1]), (~wr_waysel0_ac_l[0]), | |
5979 | (~wr_waysel1_ac_l[0])}}; | |
5980 | assign data_in[135:0] = {din0_a[16], din1_a[16], din0_a[16], din1_a[16], | |
5981 | din0_a[16], din1_a[16], din0_a[16], din1_a[16], din0_a[15], | |
5982 | din1_a[15], din0_a[15], din1_a[15], din0_a[15], din1_a[15], | |
5983 | din0_a[15], din1_a[15], din0_a[14], din1_a[14], din0_a[14], | |
5984 | din1_a[14], din0_a[14], din1_a[14], din0_a[14], din1_a[14], | |
5985 | din0_a[13], din1_a[13], din0_a[13], din1_a[13], din0_a[13], | |
5986 | din1_a[13], din0_a[13], din1_a[13], din0_a[12], din1_a[12], | |
5987 | din0_a[12], din1_a[12], din0_a[12], din1_a[12], din0_a[12], | |
5988 | din1_a[12], din0_a[11], din1_a[11], din0_a[11], din1_a[11], | |
5989 | din0_a[11], din1_a[11], din0_a[11], din1_a[11], din0_a[10], | |
5990 | din1_a[10], din0_a[10], din1_a[10], din0_a[10], din1_a[10], | |
5991 | din0_a[10], din1_a[10], din0_a[9], din1_a[9], din0_a[9], | |
5992 | din1_a[9], din0_a[9], din1_a[9], din0_a[9], din1_a[9], | |
5993 | din0_a[8], din1_a[8], din0_a[8], din1_a[8], din0_a[8], | |
5994 | din1_a[8], din0_a[8], din1_a[8], din0_a[7], din1_a[7], | |
5995 | din0_a[7], din1_a[7], din0_a[7], din1_a[7], din0_a[7], | |
5996 | din1_a[7], din0_a[6], din1_a[6], din0_a[6], din1_a[6], | |
5997 | din0_a[6], din1_a[6], din0_a[6], din1_a[6], din0_a[5], | |
5998 | din1_a[5], din0_a[5], din1_a[5], din0_a[5], din1_a[5], | |
5999 | din0_a[5], din1_a[5], din0_a[4], din1_a[4], din0_a[4], | |
6000 | din1_a[4], din0_a[4], din1_a[4], din0_a[4], din1_a[4], | |
6001 | din0_a[3], din1_a[3], din0_a[3], din1_a[3], din0_a[3], | |
6002 | din1_a[3], din0_a[3], din1_a[3], din0_a[2], din1_a[2], | |
6003 | din0_a[2], din1_a[2], din0_a[2], din1_a[2], din0_a[2], | |
6004 | din1_a[2], din0_a[1], din1_a[1], din0_a[1], din1_a[1], | |
6005 | din0_a[1], din1_a[1], din0_a[1], din1_a[1], din0_a[0], | |
6006 | din1_a[0], din0_a[0], din1_a[0], din0_a[0], din1_a[0], | |
6007 | din0_a[0], din1_a[0]}; | |
6008 | assign din[135:0] = (((way_write_en[135:0] & word_write_en[135:0]) & | |
6009 | data_in[135:0]) | ((~(way_write_en[135:0] & word_write_en[135:0] | |
6010 | )) & old_data[135:0])); | |
6011 | assign rd_worden_ac_l_unused = rd_worden_ac_l[1]; | |
6012 | assign adr_ac_l_unused[5:0] = adr_ac_l[5:0]; | |
6013 | ||
6014 | initial begin | |
6015 | for (i = 0; (i < 64); i = (i + 1)) begin | |
6016 | mem[i] = {144 {1'b0}}; | |
6017 | end | |
6018 | local_dout = {144 {1'b0}}; | |
6019 | end | |
6020 | always @(reg_en_lft[1:0] or reg_d_lft or temp) begin | |
6021 | for (n = 0; (n < 136); n = (n + 1)) begin | |
6022 | n_reg1 = n; | |
6023 | if (((reg_en_lft[1] & reg_en_lft[0]) & (reg_d_lft >= 5'b0)) & ( | |
6024 | reg_d_lft <= 5'b10000)) begin | |
6025 | if (n_reg1[9:0] >= ((reg_d_lft + 5'b1) * 5'b01000)) begin | |
6026 | old_data[n] = temp[(n + 8)]; | |
6027 | end | |
6028 | else begin | |
6029 | old_data[n] = temp[n]; | |
6030 | end | |
6031 | end | |
6032 | else begin | |
6033 | old_data[n] = temp[(n + 8)]; | |
6034 | end | |
6035 | end | |
6036 | end | |
6037 | always @(reg_en_lft[1:0] or reg_d_lft or din) begin | |
6038 | for (n = 0; (n < 144); n = (n + 1)) begin | |
6039 | n_reg2 = n; | |
6040 | if (((reg_en_lft[1] & reg_en_lft[0]) & (reg_d_lft >= 5'b0)) & ( | |
6041 | reg_d_lft <= 5'b10000)) begin | |
6042 | if (n_reg2[9:0] < ((reg_d_lft + 5'b1) * 5'b01000)) begin | |
6043 | wr_data[n] = din[n]; | |
6044 | end | |
6045 | else | |
6046 | begin | |
6047 | if (n_reg2[9:0] < ((reg_d_lft + 5'b00010) * 5'b01000)) begin | |
6048 | wr_data[n] = 1'bx; | |
6049 | end | |
6050 | else begin | |
6051 | wr_data[n] = din[(n - 8)]; | |
6052 | end | |
6053 | end | |
6054 | end | |
6055 | else | |
6056 | begin | |
6057 | if (n < 8) begin | |
6058 | wr_data[n] = 1'bx; | |
6059 | end | |
6060 | else begin | |
6061 | wr_data[n] = din[(n - 8)]; | |
6062 | end | |
6063 | end | |
6064 | end | |
6065 | end | |
6066 | ||
6067 | always @(l1clk or wr_data[143:0] or wr_word_en_ac_l[1:0] or | |
6068 | adr_ac_h[5:0] or quaden_f_l or vnw_ary) begin | |
6069 | if (((l1clk & (~quaden_f_l)) & ((~wr_word_en_ac_l[1]) | (~ | |
6070 | wr_word_en_ac_l[0]))) & vnw_ary) begin | |
6071 | mem[adr_ac_h] <= wr_data[143:0]; | |
6072 | end | |
6073 | end | |
6074 | always @(l1clk or adr_ac_h[5:0] or rd_worden_ac_l[0]) begin | |
6075 | if (l1clk) begin | |
6076 | word_0_read <= (~rd_worden_ac_l[0]); | |
6077 | local_dout[143:0] <= mem[adr_ac_h[5:0]]; | |
6078 | end | |
6079 | end | |
6080 | ||
6081 | always @(negedge l1clk) begin | |
6082 | if (~rd_en_a_l) begin | |
6083 | for (n = 0; (n < 136); n = (n + 1)) begin | |
6084 | n_reg3 = n; | |
6085 | if (((reg_en_lft[1] & reg_en_lft[0]) & (reg_d_lft >= 5'b0)) & ( | |
6086 | reg_d_lft <= 5'b10000)) begin | |
6087 | if (n_reg3[9:0] >= ((reg_d_lft + 5'b1) * 5'b01000)) begin | |
6088 | dout[n] = local_dout[(n + 8)]; | |
6089 | end | |
6090 | else begin | |
6091 | dout[n] = local_dout[n]; | |
6092 | end | |
6093 | end | |
6094 | else begin | |
6095 | dout[n] = local_dout[(n + 8)]; | |
6096 | end | |
6097 | end | |
6098 | way3_word0[16:0] = {dout[135], dout[127], dout[119], dout[111], | |
6099 | dout[103], dout[95], dout[87], dout[79], dout[71], dout[63], | |
6100 | dout[55], dout[47], dout[39], dout[31], dout[23], dout[15], | |
6101 | dout[7]}; | |
6102 | way3_word1[16:0] = {dout[134], dout[126], dout[118], dout[110], | |
6103 | dout[102], dout[94], dout[86], dout[78], dout[70], dout[62], | |
6104 | dout[54], dout[46], dout[38], dout[30], dout[22], dout[14], | |
6105 | dout[6]}; | |
6106 | way2_word0[16:0] = {dout[133], dout[125], dout[117], dout[109], | |
6107 | dout[101], dout[93], dout[85], dout[77], dout[69], dout[61], | |
6108 | dout[53], dout[45], dout[37], dout[29], dout[21], dout[13], | |
6109 | dout[5]}; | |
6110 | way2_word1[16:0] = {dout[132], dout[124], dout[116], dout[108], | |
6111 | dout[100], dout[92], dout[84], dout[76], dout[68], dout[60], | |
6112 | dout[52], dout[44], dout[36], dout[28], dout[20], dout[12], | |
6113 | dout[4]}; | |
6114 | way1_word0[16:0] = {dout[131], dout[123], dout[115], dout[107], | |
6115 | dout[99], dout[91], dout[83], dout[75], dout[67], dout[59], | |
6116 | dout[51], dout[43], dout[35], dout[27], dout[19], dout[11], | |
6117 | dout[3]}; | |
6118 | way1_word1[16:0] = {dout[130], dout[122], dout[114], dout[106], | |
6119 | dout[98], dout[90], dout[82], dout[74], dout[66], dout[58], | |
6120 | dout[50], dout[42], dout[34], dout[26], dout[18], dout[10], | |
6121 | dout[2]}; | |
6122 | way0_word0[16:0] = {dout[129], dout[121], dout[113], dout[105], | |
6123 | dout[97], dout[89], dout[81], dout[73], dout[65], dout[57], | |
6124 | dout[49], dout[41], dout[33], dout[25], dout[17], dout[9], | |
6125 | dout[1]}; | |
6126 | way0_word1[16:0] = {dout[128], dout[120], dout[112], dout[104], | |
6127 | dout[96], dout[88], dout[80], dout[72], dout[64], dout[56], | |
6128 | dout[48], dout[40], dout[32], dout[24], dout[16], dout[8], | |
6129 | dout[0]}; | |
6130 | dout_wy0_bc[16:0] <= (word_0_read ? way0_word0[16:0] : | |
6131 | way0_word1[16:0]); | |
6132 | dout_wy1_bc[16:0] <= (word_0_read ? way1_word0[16:0] : | |
6133 | way1_word1[16:0]); | |
6134 | dout_wy2_bc[16:0] <= (word_0_read ? way2_word0[16:0] : | |
6135 | way2_word1[16:0]); | |
6136 | dout_wy3_bc[16:0] <= (word_0_read ? way3_word0[16:0] : | |
6137 | way3_word1[16:0]); | |
6138 | end | |
6139 | end | |
6140 | endmodule | |
6141 | ||
6142 | `endif // `ifdef FPGA | |
6143 | ||
6144 | ||
6145 | ||
6146 | ||
6147 | ||
6148 | ||
6149 | `ifndef FPGA | |
6150 | module n2_icd_rgt_sb_array ( | |
6151 | adr_ac_h, | |
6152 | adr_ac_l, | |
6153 | rd_en_a_l, | |
6154 | quaden_f_l, | |
6155 | wr_word_en_ac_l, | |
6156 | wr_waysel0_ac_l, | |
6157 | wr_waysel1_ac_l, | |
6158 | din0_a, | |
6159 | din1_a, | |
6160 | rd_worden_ac_l, | |
6161 | l1clk, | |
6162 | vnw_ary, | |
6163 | reg_d_rgt, | |
6164 | reg_en_rgt, | |
6165 | dout_wy0_bc, | |
6166 | dout_wy1_bc, | |
6167 | dout_wy2_bc, | |
6168 | dout_wy3_bc); | |
6169 | wire [127:0] word_write_en; | |
6170 | wire [127:0] way_write_en; | |
6171 | wire [127:0] data_in; | |
6172 | wire rd_worden_ac_l_unused; | |
6173 | wire [5:0] adr_ac_l_unused; | |
6174 | ||
6175 | ||
6176 | input [5:0] adr_ac_h ; | |
6177 | input [5:0] adr_ac_l ; | |
6178 | input rd_en_a_l ; | |
6179 | input quaden_f_l ; | |
6180 | input [1:0] wr_word_en_ac_l ; | |
6181 | input [3:0] wr_waysel0_ac_l ; | |
6182 | input [3:0] wr_waysel1_ac_l ; | |
6183 | input [32:17] din0_a ; | |
6184 | input [32:17] din1_a ; | |
6185 | input [1:0] rd_worden_ac_l ; | |
6186 | input l1clk ; | |
6187 | ||
6188 | input vnw_ary; | |
6189 | ||
6190 | input [4:0] reg_d_rgt; | |
6191 | input [1:0] reg_en_rgt; | |
6192 | ||
6193 | output [15:0] dout_wy0_bc ; | |
6194 | output [15:0] dout_wy1_bc ; | |
6195 | output [15:0] dout_wy2_bc ; | |
6196 | output [15:0] dout_wy3_bc ; | |
6197 | ||
6198 | ||
6199 | ||
6200 | ||
6201 | reg [135:0] mem[63:0] ; | |
6202 | ||
6203 | ||
6204 | reg [135:0] local_dout; | |
6205 | reg [127:0] old_data; | |
6206 | reg [135:0] wr_data; | |
6207 | reg [127:0] dout; | |
6208 | wire [135:0] temp; | |
6209 | wire [127:0] din; | |
6210 | ||
6211 | reg [15:0] dout_wy0_bc ; | |
6212 | reg [15:0] dout_wy1_bc ; | |
6213 | reg [15:0] dout_wy2_bc ; | |
6214 | reg [15:0] dout_wy3_bc ; | |
6215 | ||
6216 | reg [15:0] way3_word0 ; | |
6217 | reg [15:0] way3_word1 ; | |
6218 | reg [15:0] way2_word0 ; | |
6219 | reg [15:0] way2_word1 ; | |
6220 | reg [15:0] way1_word0 ; | |
6221 | reg [15:0] way1_word1 ; | |
6222 | reg [15:0] way0_word0 ; | |
6223 | reg [15:0] way0_word1 ; | |
6224 | reg [31:0] n_reg1; | |
6225 | reg [31:0] n_reg2; | |
6226 | reg [31:0] n_reg3; | |
6227 | reg word_0_read ; | |
6228 | ||
6229 | integer n; | |
6230 | ||
6231 | ||
6232 | `ifndef NOINITMEM | |
6233 | // Emulate reset | |
6234 | integer i; | |
6235 | initial begin | |
6236 | for (i=0; i<64; i=i+1) begin | |
6237 | mem [i] = {136{1'b0}}; | |
6238 | end | |
6239 | local_dout = {136{1'b0}}; | |
6240 | end | |
6241 | `endif | |
6242 | ||
6243 | ||
6244 | // assign word_0_read = ~rd_worden_ac_l[0] & ~rd_en_a_l ; | |
6245 | // assign red_value[4:0] = reg_d_rgt[4:0] & {5{reg_en_rgt[1] & reg_en_rgt[0]}}; | |
6246 | assign temp[135:0] = mem[adr_ac_h[5:0]] ; | |
6247 | ||
6248 | //////////////////////////////// | |
6249 | // Redunduncy Read shifter | |
6250 | //////////////////////////////// | |
6251 | always @(reg_en_rgt[1:0] or reg_d_rgt or temp ) begin | |
6252 | for (n = 0; n < 128; n = n + 1 ) begin | |
6253 | n_reg1 = n; | |
6254 | if (reg_en_rgt[1] & reg_en_rgt[0] & ( reg_d_rgt >= 5'b00000) & (reg_d_rgt <= 5'b01111)) begin | |
6255 | if ( n_reg1[9:0] >= ((reg_d_rgt + 5'h1) * 5'b01000)) | |
6256 | old_data[n] = temp[n+8] ; | |
6257 | else | |
6258 | old_data[n] = temp[n] ; | |
6259 | end else | |
6260 | old_data[n] = temp[n+8] ; | |
6261 | end | |
6262 | end | |
6263 | ||
6264 | assign word_write_en[127:0] = {64{~wr_word_en_ac_l[0], ~wr_word_en_ac_l[1]}} ; | |
6265 | assign way_write_en[127:0] = {16{~wr_waysel0_ac_l[0] , ~wr_waysel1_ac_l[0] ,~wr_waysel0_ac_l[1] , ~wr_waysel1_ac_l[1], | |
6266 | ~wr_waysel0_ac_l[2] , ~wr_waysel1_ac_l[2] ,~wr_waysel0_ac_l[3] , ~wr_waysel1_ac_l[3] }} ; | |
6267 | ||
6268 | assign data_in[127:0] = {din0_a[32],din1_a[32] , din0_a[32],din1_a[32] , din0_a[32],din1_a[32] , din0_a[32],din1_a[32], // 127:120 | |
6269 | din0_a[31],din1_a[31] , din0_a[31],din1_a[31] , din0_a[31],din1_a[31] , din0_a[31],din1_a[31], // 119:112 | |
6270 | din0_a[30],din1_a[30] , din0_a[30],din1_a[30] , din0_a[30],din1_a[30] , din0_a[30],din1_a[30], // 111:104 | |
6271 | din0_a[29],din1_a[29] , din0_a[29],din1_a[29] , din0_a[29],din1_a[29] , din0_a[29],din1_a[29], // 103:096 | |
6272 | din0_a[28],din1_a[28] , din0_a[28],din1_a[28] , din0_a[28],din1_a[28] , din0_a[28],din1_a[28], // 095:088 | |
6273 | din0_a[27],din1_a[27] , din0_a[27],din1_a[27] , din0_a[27],din1_a[27] , din0_a[27],din1_a[27], // 087:080 | |
6274 | din0_a[26],din1_a[26] , din0_a[26],din1_a[26] , din0_a[26],din1_a[26] , din0_a[26],din1_a[26], // 079:072 | |
6275 | din0_a[25],din1_a[25] , din0_a[25],din1_a[25] , din0_a[25],din1_a[25] , din0_a[25],din1_a[25], // 071:064 | |
6276 | din0_a[24],din1_a[24] , din0_a[24],din1_a[24] , din0_a[24],din1_a[24] , din0_a[24],din1_a[24], // 063:056 | |
6277 | din0_a[23],din1_a[23] , din0_a[23],din1_a[23] , din0_a[23],din1_a[23] , din0_a[23],din1_a[23], // 055:048 | |
6278 | din0_a[22],din1_a[22] , din0_a[22],din1_a[22] , din0_a[22],din1_a[22] , din0_a[22],din1_a[22], // 047:040 | |
6279 | din0_a[21],din1_a[21] , din0_a[21],din1_a[21] , din0_a[21],din1_a[21] , din0_a[21],din1_a[21], // 039:032 | |
6280 | din0_a[20],din1_a[20] , din0_a[20],din1_a[20] , din0_a[20],din1_a[20] , din0_a[20],din1_a[20], // 031:024 | |
6281 | din0_a[19],din1_a[19] , din0_a[19],din1_a[19] , din0_a[19],din1_a[19] , din0_a[19],din1_a[19], // 023:016 | |
6282 | din0_a[18],din1_a[18] , din0_a[18],din1_a[18] , din0_a[18],din1_a[18] , din0_a[18],din1_a[18], // 015:008 | |
6283 | din0_a[17],din1_a[17] , din0_a[17],din1_a[17] , din0_a[17],din1_a[17] , din0_a[17],din1_a[17]};// 007:000 | |
6284 | ||
6285 | ||
6286 | assign din[127:0] = ( way_write_en[127:0] & word_write_en[127:0] & data_in[127:0] ) | | |
6287 | ( ~(way_write_en[127:0] & word_write_en[127:0]) & old_data[127:0] ) ; | |
6288 | ||
6289 | //////////////////////////////// | |
6290 | // Redunduncy write shifter | |
6291 | //////////////////////////////// | |
6292 | always @(reg_en_rgt[1:0] or reg_d_rgt or din ) begin | |
6293 | for (n = 0; n < 136; n = n + 1 ) begin | |
6294 | n_reg2 = n; | |
6295 | if (reg_en_rgt[1] & reg_en_rgt[0] & ( reg_d_rgt >= 5'b00000) & (reg_d_rgt <= 5'b01111)) begin | |
6296 | if ( n_reg2[9:0] < ((reg_d_rgt + 5'h1) * 5'b01000 )) | |
6297 | wr_data[n] = din[n] ; | |
6298 | else begin | |
6299 | if ( n_reg2[9:0] < ((reg_d_rgt + 5'h2) * 5'b01000 )) | |
6300 | wr_data[n] = 1'bx ; | |
6301 | else | |
6302 | wr_data[n] = din[n-8] ; | |
6303 | end | |
6304 | end else begin | |
6305 | if (n < 8) | |
6306 | wr_data[n] = 1'bx ; | |
6307 | else | |
6308 | wr_data[n] = din[n-8] ; | |
6309 | end | |
6310 | end | |
6311 | end | |
6312 | ||
6313 | ////////////////////// | |
6314 | // Read/write array | |
6315 | ////////////////////// | |
6316 | ||
6317 | ||
6318 | always @ (l1clk or wr_data[135:0] or wr_word_en_ac_l[1:0] or adr_ac_h[5:0] or quaden_f_l or vnw_ary) begin | |
6319 | if (l1clk & ~quaden_f_l & (~wr_word_en_ac_l[1] | ~wr_word_en_ac_l[0]) & vnw_ary) begin | |
6320 | mem[adr_ac_h] <= wr_data[135:0] ; | |
6321 | ||
6322 | ||
6323 | end // end if | |
6324 | end // end always | |
6325 | ||
6326 | ||
6327 | ||
6328 | ||
6329 | always @(l1clk or rd_en_a_l or reg_en_rgt[1:0] or reg_d_rgt or adr_ac_h[5:0] or rd_worden_ac_l[0] or vnw_ary) begin | |
6330 | if (l1clk | rd_en_a_l) begin | |
6331 | dout_wy0_bc[15:0] <= 16'h0; | |
6332 | dout_wy1_bc[15:0] <= 16'h0; | |
6333 | dout_wy2_bc[15:0] <= 16'h0; | |
6334 | dout_wy3_bc[15:0] <= 16'h0; | |
6335 | word_0_read <= ~rd_worden_ac_l[0]; | |
6336 | local_dout[135:0] <= rd_en_a_l ? 136'h0 : mem[adr_ac_h[5:0]]; | |
6337 | end | |
6338 | if (~l1clk & ~rd_en_a_l & vnw_ary) begin | |
6339 | ||
6340 | ||
6341 | ||
6342 | ||
6343 | ||
6344 | ||
6345 | //////////////////////////////// | |
6346 | // Redunduncy Read shifter | |
6347 | //////////////////////////////// | |
6348 | for (n = 0; n < 128; n = n + 1 ) begin | |
6349 | n_reg3 = n; | |
6350 | if (reg_en_rgt[1] & reg_en_rgt[0] & ( reg_d_rgt >= 5'b00000) & (reg_d_rgt <= 5'b01111)) begin | |
6351 | if ( n_reg3[9:0] >= ((reg_d_rgt + 5'h1) * 5'b01000)) | |
6352 | dout[n] = local_dout[n+8] ; | |
6353 | else | |
6354 | dout[n] = local_dout[n] ; | |
6355 | end else | |
6356 | dout[n] = local_dout[n+8] ; | |
6357 | end | |
6358 | /////////////////////// | |
6359 | // rd_data column mux | |
6360 | /////////////////////// | |
6361 | ||
6362 | way0_word0[15:0] = {dout[127], dout[119] , dout[111], dout[103], | |
6363 | dout[95], dout[87] , dout[79], dout[71], | |
6364 | dout[63], dout[55] , dout[47], dout[39], | |
6365 | dout[31], dout[23] , dout[15], dout[7] } ; | |
6366 | ||
6367 | way0_word1[15:0] = {dout[126], dout[118] , dout[110], dout[102], | |
6368 | dout[94], dout[86] , dout[78], dout[70], | |
6369 | dout[62], dout[54] , dout[46], dout[38], | |
6370 | dout[30], dout[22] , dout[14], dout[6] } ; | |
6371 | ||
6372 | way1_word0[15:0] = {dout[125], dout[117] , dout[109], dout[101], | |
6373 | dout[93], dout[85] , dout[77], dout[69], | |
6374 | dout[61], dout[53] , dout[45], dout[37], | |
6375 | dout[29], dout[21] , dout[13], dout[5] } ; | |
6376 | ||
6377 | way1_word1[15:0] = {dout[124], dout[116] , dout[108], dout[100], | |
6378 | dout[92], dout[84] , dout[76], dout[68], | |
6379 | dout[60], dout[52] , dout[44], dout[36], | |
6380 | dout[28], dout[20] , dout[12], dout[4] } ; | |
6381 | ||
6382 | way2_word0[15:0] = {dout[123], dout[115] , dout[107], dout[99], | |
6383 | dout[91], dout[83] , dout[75], dout[67], | |
6384 | dout[59], dout[51] , dout[43], dout[35], | |
6385 | dout[27], dout[19] , dout[11], dout[3] } ; | |
6386 | ||
6387 | way2_word1[15:0] = {dout[122], dout[114] , dout[106], dout[98], | |
6388 | dout[90], dout[82] , dout[74], dout[66], | |
6389 | dout[58], dout[50] , dout[42], dout[34], | |
6390 | dout[26], dout[18] , dout[10], dout[2] } ; | |
6391 | ||
6392 | way3_word0[15:0] = {dout[121], dout[113] , dout[105], dout[97], | |
6393 | dout[89], dout[81] , dout[73], dout[65], | |
6394 | dout[57], dout[49] , dout[41], dout[33], | |
6395 | dout[25], dout[17] , dout[9], dout[1] } ; | |
6396 | ||
6397 | way3_word1[15:0] = {dout[120], dout[112] , dout[104], dout[96], | |
6398 | dout[88], dout[80] , dout[72], dout[64], | |
6399 | dout[56], dout[48] , dout[40], dout[32], | |
6400 | dout[24], dout[16] , dout[8], dout[0] } ; | |
6401 | ||
6402 | dout_wy0_bc[15:0] <= word_0_read ? way0_word0[15:0] : way0_word1[15:0] ; | |
6403 | dout_wy1_bc[15:0] <= word_0_read ? way1_word0[15:0] : way1_word1[15:0] ; | |
6404 | dout_wy2_bc[15:0] <= word_0_read ? way2_word0[15:0] : way2_word1[15:0] ; | |
6405 | dout_wy3_bc[15:0] <= word_0_read ? way3_word0[15:0] : way3_word1[15:0] ; | |
6406 | ||
6407 | end // if (~rd_en_a_l) | |
6408 | end // always | |
6409 | ||
6410 | // Precharge | |
6411 | // always @ (posedge l1clk) begin | |
6412 | // local_dout[135:0] = 136'h0; | |
6413 | // dout_wy0_bc[15:0] <= 16'b0; | |
6414 | // dout_wy1_bc[15:0] <= 16'b0; | |
6415 | // dout_wy2_bc[15:0] <= 16'b0; | |
6416 | // dout_wy3_bc[15:0] <= 16'b0; | |
6417 | //end | |
6418 | ||
6419 | //////////////////////////////// | |
6420 | // Redunduncy Read shifter | |
6421 | //////////////////////////////// | |
6422 | // always @(red_value or local_dout ) begin | |
6423 | // for (n = 0; n < 136; n = n + 1 ) begin | |
6424 | // if ( n >= (red_value * 8 )) | |
6425 | // dout[n] = local_dout[n+8] ; | |
6426 | // else | |
6427 | // dout[n] = local_dout[n] ; | |
6428 | // end | |
6429 | // end | |
6430 | ||
6431 | assign rd_worden_ac_l_unused = rd_worden_ac_l[1] ; | |
6432 | assign adr_ac_l_unused[5:0] = adr_ac_l[5:0] ; | |
6433 | ||
6434 | ||
6435 | supply0 vss; | |
6436 | supply1 vdd; | |
6437 | endmodule | |
6438 | `endif // `ifndef FPGA | |
6439 | ||
6440 | `ifdef FPGA | |
6441 | ||
6442 | module n2_icd_rgt_sb_array(adr_ac_h, adr_ac_l, rd_en_a_l, quaden_f_l, | |
6443 | wr_word_en_ac_l, wr_waysel0_ac_l, wr_waysel1_ac_l, din0_a, din1_a, | |
6444 | rd_worden_ac_l, l1clk, vnw_ary, reg_d_rgt, reg_en_rgt, dout_wy0_bc, | |
6445 | dout_wy1_bc, dout_wy2_bc, dout_wy3_bc); | |
6446 | ||
6447 | input [5:0] adr_ac_h; | |
6448 | input [5:0] adr_ac_l; | |
6449 | input rd_en_a_l; | |
6450 | input quaden_f_l; | |
6451 | input [1:0] wr_word_en_ac_l; | |
6452 | input [3:0] wr_waysel0_ac_l; | |
6453 | input [3:0] wr_waysel1_ac_l; | |
6454 | input [32:17] din0_a; | |
6455 | input [32:17] din1_a; | |
6456 | input [1:0] rd_worden_ac_l; | |
6457 | input l1clk; | |
6458 | input vnw_ary; | |
6459 | input [4:0] reg_d_rgt; | |
6460 | input [1:0] reg_en_rgt; | |
6461 | output [15:0] dout_wy0_bc; | |
6462 | output [15:0] dout_wy1_bc; | |
6463 | output [15:0] dout_wy2_bc; | |
6464 | output [15:0] dout_wy3_bc; | |
6465 | ||
6466 | wire [127:0] word_write_en; | |
6467 | wire [127:0] way_write_en; | |
6468 | wire [127:0] data_in; | |
6469 | wire rd_worden_ac_l_unused; | |
6470 | wire [5:0] adr_ac_l_unused; | |
6471 | ||
6472 | reg [135:0] mem[63:0]; | |
6473 | reg [135:0] local_dout; | |
6474 | reg [127:0] old_data; | |
6475 | reg [135:0] wr_data; | |
6476 | reg [127:0] dout; | |
6477 | wire [135:0] temp; | |
6478 | wire [127:0] din; | |
6479 | reg [15:0] dout_wy0_bc; | |
6480 | reg [15:0] dout_wy1_bc; | |
6481 | reg [15:0] dout_wy2_bc; | |
6482 | reg [15:0] dout_wy3_bc; | |
6483 | reg [15:0] way3_word0; | |
6484 | reg [15:0] way3_word1; | |
6485 | reg [15:0] way2_word0; | |
6486 | reg [15:0] way2_word1; | |
6487 | reg [15:0] way1_word0; | |
6488 | reg [15:0] way1_word1; | |
6489 | reg [15:0] way0_word0; | |
6490 | reg [15:0] way0_word1; | |
6491 | reg [31:0] n_reg1; | |
6492 | reg [31:0] n_reg2; | |
6493 | reg [31:0] n_reg3; | |
6494 | reg word_0_read; | |
6495 | integer n; | |
6496 | integer i; | |
6497 | supply0 vss; | |
6498 | supply1 vdd; | |
6499 | ||
6500 | assign temp[135:0] = mem[adr_ac_h[5:0]]; | |
6501 | assign word_write_en[127:0] = {64 {(~wr_word_en_ac_l[0]), | |
6502 | (~wr_word_en_ac_l[1])}}; | |
6503 | assign way_write_en[127:0] = {16 {(~wr_waysel0_ac_l[0]), | |
6504 | (~wr_waysel1_ac_l[0]), (~wr_waysel0_ac_l[1]), | |
6505 | (~wr_waysel1_ac_l[1]), (~wr_waysel0_ac_l[2]), | |
6506 | (~wr_waysel1_ac_l[2]), (~wr_waysel0_ac_l[3]), | |
6507 | (~wr_waysel1_ac_l[3])}}; | |
6508 | assign data_in[127:0] = {din0_a[32], din1_a[32], din0_a[32], din1_a[32], | |
6509 | din0_a[32], din1_a[32], din0_a[32], din1_a[32], din0_a[31], | |
6510 | din1_a[31], din0_a[31], din1_a[31], din0_a[31], din1_a[31], | |
6511 | din0_a[31], din1_a[31], din0_a[30], din1_a[30], din0_a[30], | |
6512 | din1_a[30], din0_a[30], din1_a[30], din0_a[30], din1_a[30], | |
6513 | din0_a[29], din1_a[29], din0_a[29], din1_a[29], din0_a[29], | |
6514 | din1_a[29], din0_a[29], din1_a[29], din0_a[28], din1_a[28], | |
6515 | din0_a[28], din1_a[28], din0_a[28], din1_a[28], din0_a[28], | |
6516 | din1_a[28], din0_a[27], din1_a[27], din0_a[27], din1_a[27], | |
6517 | din0_a[27], din1_a[27], din0_a[27], din1_a[27], din0_a[26], | |
6518 | din1_a[26], din0_a[26], din1_a[26], din0_a[26], din1_a[26], | |
6519 | din0_a[26], din1_a[26], din0_a[25], din1_a[25], din0_a[25], | |
6520 | din1_a[25], din0_a[25], din1_a[25], din0_a[25], din1_a[25], | |
6521 | din0_a[24], din1_a[24], din0_a[24], din1_a[24], din0_a[24], | |
6522 | din1_a[24], din0_a[24], din1_a[24], din0_a[23], din1_a[23], | |
6523 | din0_a[23], din1_a[23], din0_a[23], din1_a[23], din0_a[23], | |
6524 | din1_a[23], din0_a[22], din1_a[22], din0_a[22], din1_a[22], | |
6525 | din0_a[22], din1_a[22], din0_a[22], din1_a[22], din0_a[21], | |
6526 | din1_a[21], din0_a[21], din1_a[21], din0_a[21], din1_a[21], | |
6527 | din0_a[21], din1_a[21], din0_a[20], din1_a[20], din0_a[20], | |
6528 | din1_a[20], din0_a[20], din1_a[20], din0_a[20], din1_a[20], | |
6529 | din0_a[19], din1_a[19], din0_a[19], din1_a[19], din0_a[19], | |
6530 | din1_a[19], din0_a[19], din1_a[19], din0_a[18], din1_a[18], | |
6531 | din0_a[18], din1_a[18], din0_a[18], din1_a[18], din0_a[18], | |
6532 | din1_a[18], din0_a[17], din1_a[17], din0_a[17], din1_a[17], | |
6533 | din0_a[17], din1_a[17], din0_a[17], din1_a[17]}; | |
6534 | assign din[127:0] = (((way_write_en[127:0] & word_write_en[127:0]) & | |
6535 | data_in[127:0]) | ((~(way_write_en[127:0] & word_write_en[127:0] | |
6536 | )) & old_data[127:0])); | |
6537 | assign rd_worden_ac_l_unused = rd_worden_ac_l[1]; | |
6538 | assign adr_ac_l_unused[5:0] = adr_ac_l[5:0]; | |
6539 | ||
6540 | initial begin | |
6541 | for (i = 0; (i < 64); i = (i + 1)) begin | |
6542 | mem[i] = {136 {1'b0}}; | |
6543 | end | |
6544 | local_dout = {136 {1'b0}}; | |
6545 | end | |
6546 | always @(reg_en_rgt[1:0] or reg_d_rgt or temp) begin | |
6547 | for (n = 0; (n < 128); n = (n + 1)) begin | |
6548 | n_reg1 = n; | |
6549 | if (((reg_en_rgt[1] & reg_en_rgt[0]) & (reg_d_rgt >= 5'b0)) & ( | |
6550 | reg_d_rgt <= 5'b01111)) begin | |
6551 | if (n_reg1[9:0] >= ((reg_d_rgt + 5'b1) * 5'b01000)) begin | |
6552 | old_data[n] = temp[(n + 8)]; | |
6553 | end | |
6554 | else begin | |
6555 | old_data[n] = temp[n]; | |
6556 | end | |
6557 | end | |
6558 | else begin | |
6559 | old_data[n] = temp[(n + 8)]; | |
6560 | end | |
6561 | end | |
6562 | end | |
6563 | always @(reg_en_rgt[1:0] or reg_d_rgt or din) begin | |
6564 | for (n = 0; (n < 136); n = (n + 1)) begin | |
6565 | n_reg2 = n; | |
6566 | if (((reg_en_rgt[1] & reg_en_rgt[0]) & (reg_d_rgt >= 5'b0)) & ( | |
6567 | reg_d_rgt <= 5'b01111)) begin | |
6568 | if (n_reg2[9:0] < ((reg_d_rgt + 5'b1) * 5'b01000)) begin | |
6569 | wr_data[n] = din[n]; | |
6570 | end | |
6571 | else | |
6572 | begin | |
6573 | if (n_reg2[9:0] < ((reg_d_rgt + 5'b00010) * 5'b01000)) begin | |
6574 | wr_data[n] = 1'bx; | |
6575 | end | |
6576 | else begin | |
6577 | wr_data[n] = din[(n - 8)]; | |
6578 | end | |
6579 | end | |
6580 | end | |
6581 | else | |
6582 | begin | |
6583 | if (n < 8) begin | |
6584 | wr_data[n] = 1'bx; | |
6585 | end | |
6586 | else begin | |
6587 | wr_data[n] = din[(n - 8)]; | |
6588 | end | |
6589 | end | |
6590 | end | |
6591 | end | |
6592 | ||
6593 | ||
6594 | always @(l1clk or wr_data[135:0] or wr_word_en_ac_l[1:0] or | |
6595 | adr_ac_h[5:0] or quaden_f_l or vnw_ary) begin | |
6596 | if (((l1clk & (~quaden_f_l)) & ((~wr_word_en_ac_l[1]) | (~ | |
6597 | wr_word_en_ac_l[0]))) & vnw_ary) begin | |
6598 | mem[adr_ac_h] <= wr_data[135:0]; | |
6599 | end | |
6600 | end | |
6601 | always @(l1clk or adr_ac_h[5:0] or rd_worden_ac_l[0]) begin | |
6602 | if (l1clk) begin | |
6603 | word_0_read <= (~rd_worden_ac_l[0]); | |
6604 | local_dout[135:0] <= mem[adr_ac_h[5:0]]; | |
6605 | end | |
6606 | end | |
6607 | ||
6608 | always @(negedge l1clk) begin | |
6609 | if (~rd_en_a_l) begin | |
6610 | for (n = 0; (n < 128); n = (n + 1)) begin | |
6611 | n_reg3 = n; | |
6612 | if (((reg_en_rgt[1] & reg_en_rgt[0]) & (reg_d_rgt >= 5'b0)) & ( | |
6613 | reg_d_rgt <= 5'b01111)) begin | |
6614 | if (n_reg3[9:0] >= ((reg_d_rgt + 5'b1) * 5'b01000)) begin | |
6615 | dout[n] = local_dout[(n + 8)]; | |
6616 | end | |
6617 | else begin | |
6618 | dout[n] = local_dout[n]; | |
6619 | end | |
6620 | end | |
6621 | else begin | |
6622 | dout[n] = local_dout[(n + 8)]; | |
6623 | end | |
6624 | end | |
6625 | way0_word0[15:0] = {dout[127], dout[119], dout[111], dout[103], | |
6626 | dout[95], dout[87], dout[79], dout[71], dout[63], dout[55], | |
6627 | dout[47], dout[39], dout[31], dout[23], dout[15], dout[7]}; | |
6628 | way0_word1[15:0] = {dout[126], dout[118], dout[110], dout[102], | |
6629 | dout[94], dout[86], dout[78], dout[70], dout[62], dout[54], | |
6630 | dout[46], dout[38], dout[30], dout[22], dout[14], dout[6]}; | |
6631 | way1_word0[15:0] = {dout[125], dout[117], dout[109], dout[101], | |
6632 | dout[93], dout[85], dout[77], dout[69], dout[61], dout[53], | |
6633 | dout[45], dout[37], dout[29], dout[21], dout[13], dout[5]}; | |
6634 | way1_word1[15:0] = {dout[124], dout[116], dout[108], dout[100], | |
6635 | dout[92], dout[84], dout[76], dout[68], dout[60], dout[52], | |
6636 | dout[44], dout[36], dout[28], dout[20], dout[12], dout[4]}; | |
6637 | way2_word0[15:0] = {dout[123], dout[115], dout[107], dout[99], | |
6638 | dout[91], dout[83], dout[75], dout[67], dout[59], dout[51], | |
6639 | dout[43], dout[35], dout[27], dout[19], dout[11], dout[3]}; | |
6640 | way2_word1[15:0] = {dout[122], dout[114], dout[106], dout[98], | |
6641 | dout[90], dout[82], dout[74], dout[66], dout[58], dout[50], | |
6642 | dout[42], dout[34], dout[26], dout[18], dout[10], dout[2]}; | |
6643 | way3_word0[15:0] = {dout[121], dout[113], dout[105], dout[97], | |
6644 | dout[89], dout[81], dout[73], dout[65], dout[57], dout[49], | |
6645 | dout[41], dout[33], dout[25], dout[17], dout[9], dout[1]}; | |
6646 | way3_word1[15:0] = {dout[120], dout[112], dout[104], dout[96], | |
6647 | dout[88], dout[80], dout[72], dout[64], dout[56], dout[48], | |
6648 | dout[40], dout[32], dout[24], dout[16], dout[8], dout[0]}; | |
6649 | dout_wy0_bc[15:0] <= (word_0_read ? way0_word0[15:0] : | |
6650 | way0_word1[15:0]); | |
6651 | dout_wy1_bc[15:0] <= (word_0_read ? way1_word0[15:0] : | |
6652 | way1_word1[15:0]); | |
6653 | dout_wy2_bc[15:0] <= (word_0_read ? way2_word0[15:0] : | |
6654 | way2_word1[15:0]); | |
6655 | dout_wy3_bc[15:0] <= (word_0_read ? way3_word0[15:0] : | |
6656 | way3_word1[15:0]); | |
6657 | end | |
6658 | end | |
6659 | endmodule | |
6660 | ||
6661 | `endif // `ifdef FPGA | |
6662 | ||
6663 | ||
6664 | ||
6665 | ||
6666 | ||
6667 | ||
6668 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
6669 | // also for pass-gate with decoder | |
6670 | ||
6671 | ||
6672 | ||
6673 | ||
6674 | ||
6675 | // any PARAMS parms go into naming of macro | |
6676 | ||
6677 | module n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_8__stack_50c__width_33 ( | |
6678 | din0, | |
6679 | sel0, | |
6680 | din1, | |
6681 | sel1, | |
6682 | din2, | |
6683 | sel2, | |
6684 | din3, | |
6685 | sel3, | |
6686 | din4, | |
6687 | sel4, | |
6688 | din5, | |
6689 | sel5, | |
6690 | din6, | |
6691 | sel6, | |
6692 | din7, | |
6693 | sel7, | |
6694 | dout); | |
6695 | wire buffout0; | |
6696 | wire buffout1; | |
6697 | wire buffout2; | |
6698 | wire buffout3; | |
6699 | wire buffout4; | |
6700 | wire buffout5; | |
6701 | wire buffout6; | |
6702 | wire buffout7; | |
6703 | ||
6704 | input [32:0] din0; | |
6705 | input sel0; | |
6706 | input [32:0] din1; | |
6707 | input sel1; | |
6708 | input [32:0] din2; | |
6709 | input sel2; | |
6710 | input [32:0] din3; | |
6711 | input sel3; | |
6712 | input [32:0] din4; | |
6713 | input sel4; | |
6714 | input [32:0] din5; | |
6715 | input sel5; | |
6716 | input [32:0] din6; | |
6717 | input sel6; | |
6718 | input [32:0] din7; | |
6719 | input sel7; | |
6720 | output [32:0] dout; | |
6721 | ||
6722 | ||
6723 | ||
6724 | ||
6725 | ||
6726 | cl_dp1_muxbuff8_8x c0_0 ( | |
6727 | .in0(sel0), | |
6728 | .in1(sel1), | |
6729 | .in2(sel2), | |
6730 | .in3(sel3), | |
6731 | .in4(sel4), | |
6732 | .in5(sel5), | |
6733 | .in6(sel6), | |
6734 | .in7(sel7), | |
6735 | .out0(buffout0), | |
6736 | .out1(buffout1), | |
6737 | .out2(buffout2), | |
6738 | .out3(buffout3), | |
6739 | .out4(buffout4), | |
6740 | .out5(buffout5), | |
6741 | .out6(buffout6), | |
6742 | .out7(buffout7) | |
6743 | ); | |
6744 | mux8s #(33) d0_0 ( | |
6745 | .sel0(buffout0), | |
6746 | .sel1(buffout1), | |
6747 | .sel2(buffout2), | |
6748 | .sel3(buffout3), | |
6749 | .sel4(buffout4), | |
6750 | .sel5(buffout5), | |
6751 | .sel6(buffout6), | |
6752 | .sel7(buffout7), | |
6753 | .in0(din0[32:0]), | |
6754 | .in1(din1[32:0]), | |
6755 | .in2(din2[32:0]), | |
6756 | .in3(din3[32:0]), | |
6757 | .in4(din4[32:0]), | |
6758 | .in5(din5[32:0]), | |
6759 | .in6(din6[32:0]), | |
6760 | .in7(din7[32:0]), | |
6761 | .dout(dout[32:0]) | |
6762 | ); | |
6763 | ||
6764 | ||
6765 | ||
6766 | ||
6767 | ||
6768 | ||
6769 | ||
6770 | ||
6771 | ||
6772 | ||
6773 | ||
6774 | ||
6775 | ||
6776 | endmodule | |
6777 | ||
6778 | ||
6779 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
6780 | // also for pass-gate with decoder | |
6781 | ||
6782 | ||
6783 | ||
6784 | ||
6785 | ||
6786 | // any PARAMS parms go into naming of macro | |
6787 | ||
6788 | module n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_7 ( | |
6789 | din0, | |
6790 | din1, | |
6791 | din2, | |
6792 | din3, | |
6793 | din4, | |
6794 | din5, | |
6795 | din6, | |
6796 | din7, | |
6797 | sel, | |
6798 | dout); | |
6799 | wire psel0; | |
6800 | wire psel1; | |
6801 | wire psel2; | |
6802 | wire psel3; | |
6803 | wire psel4; | |
6804 | wire psel5; | |
6805 | wire psel6; | |
6806 | wire psel7; | |
6807 | ||
6808 | input [6:0] din0; | |
6809 | input [6:0] din1; | |
6810 | input [6:0] din2; | |
6811 | input [6:0] din3; | |
6812 | input [6:0] din4; | |
6813 | input [6:0] din5; | |
6814 | input [6:0] din6; | |
6815 | input [6:0] din7; | |
6816 | input [2:0] sel; | |
6817 | output [6:0] dout; | |
6818 | ||
6819 | ||
6820 | ||
6821 | ||
6822 | ||
6823 | cl_dp1_pdec8_8x c0_0 ( | |
6824 | .test(1'b1), | |
6825 | .sel0(sel[0]), | |
6826 | .sel1(sel[1]), | |
6827 | .sel2(sel[2]), | |
6828 | .psel0(psel0), | |
6829 | .psel1(psel1), | |
6830 | .psel2(psel2), | |
6831 | .psel3(psel3), | |
6832 | .psel4(psel4), | |
6833 | .psel5(psel5), | |
6834 | .psel6(psel6), | |
6835 | .psel7(psel7) | |
6836 | ); | |
6837 | ||
6838 | mux8s #(7) d0_0 ( | |
6839 | .sel0(psel0), | |
6840 | .sel1(psel1), | |
6841 | .sel2(psel2), | |
6842 | .sel3(psel3), | |
6843 | .sel4(psel4), | |
6844 | .sel5(psel5), | |
6845 | .sel6(psel6), | |
6846 | .sel7(psel7), | |
6847 | .in0(din0[6:0]), | |
6848 | .in1(din1[6:0]), | |
6849 | .in2(din2[6:0]), | |
6850 | .in3(din3[6:0]), | |
6851 | .in4(din4[6:0]), | |
6852 | .in5(din5[6:0]), | |
6853 | .in6(din6[6:0]), | |
6854 | .in7(din7[6:0]), | |
6855 | .dout(dout[6:0]) | |
6856 | ); | |
6857 | ||
6858 | ||
6859 | ||
6860 | ||
6861 | ||
6862 | ||
6863 | ||
6864 | ||
6865 | ||
6866 | ||
6867 | ||
6868 | ||
6869 | ||
6870 | endmodule | |
6871 | ||
6872 | ||
6873 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
6874 | // also for pass-gate with decoder | |
6875 | ||
6876 | ||
6877 | ||
6878 | ||
6879 | ||
6880 | // any PARAMS parms go into naming of macro | |
6881 | ||
6882 | module n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__width_7 ( | |
6883 | din0, | |
6884 | din1, | |
6885 | sel0, | |
6886 | dout); | |
6887 | wire psel0; | |
6888 | wire psel1; | |
6889 | ||
6890 | input [6:0] din0; | |
6891 | input [6:0] din1; | |
6892 | input sel0; | |
6893 | output [6:0] dout; | |
6894 | ||
6895 | ||
6896 | ||
6897 | ||
6898 | ||
6899 | cl_dp1_penc2_8x c0_0 ( | |
6900 | .sel0(sel0), | |
6901 | .psel0(psel0), | |
6902 | .psel1(psel1) | |
6903 | ); | |
6904 | ||
6905 | mux2s #(7) d0_0 ( | |
6906 | .sel0(psel0), | |
6907 | .sel1(psel1), | |
6908 | .in0(din0[6:0]), | |
6909 | .in1(din1[6:0]), | |
6910 | .dout(dout[6:0]) | |
6911 | ); | |
6912 | ||
6913 | ||
6914 | ||
6915 | ||
6916 | ||
6917 | ||
6918 | ||
6919 | ||
6920 | ||
6921 | ||
6922 | ||
6923 | ||
6924 | ||
6925 | endmodule | |
6926 |