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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / libs / tisram / soc / n2_l2d_sp_512kb_cust_l / n2_l2d_sp_512kb_cust / rtl / n2_l2d_quad_cust.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: n2_l2d_quad_cust.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module n2_l2d_quad_cust (
36 waysel_c3_0,
37 wayerr_c3_0,
38 set_c3_0,
39 coloff_c3_0,
40 coloff_c4_l_0,
41 coloff_c5_0,
42 rd_wr_c3_0,
43 readen_c5_0,
44 worden_c3_0,
45 l2clk,
46 tcu_pce_ov_0,
47 pce_0,
48 se_0,
49 tcu_clk_stop_0,
50 wrdlo0_b_l,
51 wrdhi0_b_l,
52 wrdlo1_b_l,
53 wrdhi1_b_l,
54 ldoutlo0_b,
55 ldouthi0_b,
56 ldoutlo1_b,
57 ldouthi1_b,
58 fuse_l2d_data_in_00,
59 fuse_l2d_rid_00,
60 fuse_l2d_wren_00,
61 fuse_l2d_reset_00_l,
62 fdout_00,
63 fuse_l2d_data_in_01,
64 fuse_l2d_rid_01,
65 fuse_l2d_wren_01,
66 fuse_l2d_reset_01_l,
67 fdout_01,
68 fuse_l2d_data_in_10,
69 fuse_l2d_rid_10,
70 fuse_l2d_wren_10,
71 fuse_l2d_reset_10_l,
72 fdout_10,
73 fuse_l2d_data_in_11,
74 fuse_l2d_rid_11,
75 fuse_l2d_wren_11,
76 fuse_l2d_reset_11_l,
77 fdout_11,
78 waysel_c3_1,
79 wayerr_c3_1,
80 set_c3_1,
81 coloff_c3_1,
82 coloff_c4_l_1,
83 coloff_c5_1,
84 rd_wr_c3_1,
85 readen_c5_1,
86 worden_c3_1,
87 tcu_pce_ov_1,
88 pce_1,
89 se_1,
90 tcu_clk_stop_1,
91 wee_l_0,
92 wee_l_1,
93 tstmodclk_l_0,
94 tstmodclk_l_1,
95 vnw_ary);
96wire [9:0] left_red_top_d_00;
97wire [9:0] left_red_top_d_01;
98wire [38:0] ldoutlo0_b_top;
99wire [38:0] ldouthi0_b_top;
100wire [38:0] ldoutlo1_b_top;
101wire [38:0] ldouthi1_b_top;
102wire [9:0] right_red_top_d_00;
103wire [9:0] right_red_top_d_01;
104
105
106input [15:0] waysel_c3_0; // way_sel
107input wayerr_c3_0; // way_sel error
108input [8:0] set_c3_0; // set
109input coloff_c3_0; // col_offset
110input coloff_c4_l_0; // NEW(one stage+inv)
111input [1:0] coloff_c5_0; // NEW(two stage)
112input rd_wr_c3_0; // wr_en
113input readen_c5_0; // NEW(two stage)
114input [3:0] worden_c3_0; // word_en
115input l2clk; // l2clk
116input tcu_pce_ov_0; // tcu_pce_ov
117input pce_0; // NEW
118input se_0;
119input tcu_clk_stop_0; // NEW
120input [38:0] wrdlo0_b_l; // decc_in(c3-bphase)
121input [38:0] wrdhi0_b_l; // decc_in(c3-bphase)
122input [38:0] wrdlo1_b_l; // decc_in(c3-bphase)
123input [38:0] wrdhi1_b_l; // decc_in(c3-bphase)
124output [38:0] ldoutlo0_b; // decc_c52-b
125output [38:0] ldouthi0_b; // decc_c52-b
126output [38:0] ldoutlo1_b; // decc_c52-b
127output [38:0] ldouthi1_b; // decc_c52-b
128
129input [9:0] fuse_l2d_data_in_00;
130input [4:0] fuse_l2d_rid_00;
131input fuse_l2d_wren_00;
132input fuse_l2d_reset_00_l;
133output [9:0] fdout_00;
134input [9:0] fuse_l2d_data_in_01;
135input [4:0] fuse_l2d_rid_01;
136input fuse_l2d_wren_01;
137input fuse_l2d_reset_01_l;
138output [9:0] fdout_01;
139input [9:0] fuse_l2d_data_in_10;
140input [4:0] fuse_l2d_rid_10;
141input fuse_l2d_wren_10;
142input fuse_l2d_reset_10_l;
143output [9:0] fdout_10;
144input [9:0] fuse_l2d_data_in_11;
145input [4:0] fuse_l2d_rid_11;
146input fuse_l2d_wren_11;
147input fuse_l2d_reset_11_l;
148output [9:0] fdout_11;
149
150input [15:0] waysel_c3_1; // way_sel
151input wayerr_c3_1; // way_sel error
152input [8:0] set_c3_1; // set
153input coloff_c3_1; // col_offset
154input coloff_c4_l_1; // NEW(one stage+inv)
155input [1:0] coloff_c5_1; // NEW(two stage)
156input rd_wr_c3_1; // wr_en
157input readen_c5_1; // NEW(two stage)
158input [3:0] worden_c3_1; // word_en
159input tcu_pce_ov_1; // tcu_pce_ov
160input pce_1; // NEW
161input se_1;
162input tcu_clk_stop_1; // NEW
163input wee_l_0; // NEW
164input wee_l_1; // NEW
165input tstmodclk_l_0;
166input tstmodclk_l_1;
167input vnw_ary; // NEW
168
169
170n2_l2d_32kb_cust way07_00
171 (
172 .waysel_c3 (waysel_c3_0[7:0]),
173 .waysel_err_c3 (wayerr_c3_0),
174 .set_c3 (set_c3_0[8:0]),
175 .coloff_c3 (coloff_c3_0),
176 .coloff_c4_l (coloff_c4_l_0),
177 .coloff_c5 (coloff_c5_0[1:0]),
178 .rd_wr_c3 (rd_wr_c3_0),
179 .readen_c5 (readen_c5_0),
180 .l2clk (l2clk),
181 .fuse_l2d_data_in_00 (fuse_l2d_data_in_00[9:0]),
182 .fuse_l2d_rid_00 (fuse_l2d_rid_00[2:0]),
183 .fuse_l2d_wren_00 (fuse_l2d_wren_00),
184 .fuse_l2d_reset_00_l (fuse_l2d_reset_00_l),
185 .sel_quad_00 (fuse_l2d_rid_00[4]),
186 .fuse_l2d_data_in_01 (fuse_l2d_data_in_01[9:0]),
187 .fuse_l2d_rid_01 (fuse_l2d_rid_01[2:0]),
188 .fuse_l2d_wren_01 (fuse_l2d_wren_01),
189 .fuse_l2d_reset_01_l (fuse_l2d_reset_01_l),
190 .sel_quad_01 (fuse_l2d_rid_01[4]),
191 .red_d_out_00 (left_red_top_d_00[9:0]),
192 .red_d_out_01 (left_red_top_d_01[9:0]),
193 .red_top_d_00 (10'b0),
194 .red_top_d_01 (10'b0),
195 .tcu_pce_ov (tcu_pce_ov_0),
196 .tcu_pce (pce_0),
197 .se (se_0),
198 .tcu_clk_stop (tcu_clk_stop_0),
199 .wrd0lo_b_l (wrdlo0_b_l[19:0]),
200 .wrd0hi_b_l (wrdhi0_b_l[19:0]),
201 .wrd1lo_b_l (wrdlo1_b_l[18:0]),
202 .wrd1hi_b_l (wrdhi1_b_l[18:0]),
203 .ldin0lo_b (20'b0),
204 .ldin0hi_b (20'b0),
205 .ldin1lo_b (19'b0),
206 .ldin1hi_b (19'b0),
207 .worden_c3 (worden_c3_0[3:0]),
208 .tstmodclk_l (tstmodclk_l_0),
209 .wee_l (wee_l_0),
210 .ldout0lo_b00 (ldoutlo0_b_top[19:0]),
211 .ldout0hi_b00 (ldouthi0_b_top[19:0]),
212 .ldout1lo_b00 (ldoutlo1_b_top[18:0]),
213 .ldout1hi_b00 (ldouthi1_b_top[18:0]),
214 .vnw_ary (vnw_ary)
215 );
216
217n2_l2d_32kb_cust way158_00
218 (
219 .waysel_c3 (waysel_c3_0[15:8]),
220 .waysel_err_c3 (wayerr_c3_0),
221 .set_c3 (set_c3_0[8:0]),
222 .coloff_c3 (coloff_c3_0),
223 .coloff_c4_l (coloff_c4_l_0),
224 .coloff_c5 (coloff_c5_0[1:0]),
225 .rd_wr_c3 (rd_wr_c3_0),
226 .readen_c5 (readen_c5_0),
227 .l2clk (l2clk),
228 .fuse_l2d_data_in_00 (fuse_l2d_data_in_00[9:0]),
229 .fuse_l2d_rid_00 (fuse_l2d_rid_00[2:0]),
230 .fuse_l2d_wren_00 (fuse_l2d_wren_00),
231 .fuse_l2d_reset_00_l (fuse_l2d_reset_00_l),
232 .sel_quad_00 (fuse_l2d_rid_00[3]),
233 .fuse_l2d_data_in_01 (fuse_l2d_data_in_01[9:0]),
234 .fuse_l2d_rid_01 (fuse_l2d_rid_01[2:0]),
235 .fuse_l2d_wren_01 (fuse_l2d_wren_01),
236 .fuse_l2d_reset_01_l (fuse_l2d_reset_01_l),
237 .sel_quad_01 (fuse_l2d_rid_01[3]),
238 .red_d_out_00 (fdout_00[9:0]),
239 .red_d_out_01 (fdout_01[9:0]),
240 .red_top_d_00 (left_red_top_d_00[9:0]),
241 .red_top_d_01 (left_red_top_d_01[9:0]),
242 .tcu_pce_ov (tcu_pce_ov_0),
243 .tcu_pce (pce_0),
244 .se (se_0),
245 .tcu_clk_stop (tcu_clk_stop_0),
246 .worden_c3 (worden_c3_0[3:0]),
247 .tstmodclk_l (tstmodclk_l_0),
248 .wee_l (wee_l_0),
249 .wrd0lo_b_l (wrdlo0_b_l[19:0]),
250 .wrd0hi_b_l (wrdhi0_b_l[19:0]),
251 .wrd1lo_b_l (wrdlo1_b_l[18:0]),
252 .wrd1hi_b_l (wrdhi1_b_l[18:0]),
253 .ldin0lo_b (ldoutlo0_b_top[19:0]),
254 .ldin0hi_b (ldouthi0_b_top[19:0]),
255 .ldin1lo_b (ldoutlo1_b_top[18:0]),
256 .ldin1hi_b (ldouthi1_b_top[18:0]),
257 .ldout0lo_b00 (ldoutlo0_b[19:0]),
258 .ldout0hi_b00 (ldouthi0_b[19:0]),
259 .ldout1lo_b00 (ldoutlo1_b[18:0]),
260 .ldout1hi_b00 (ldouthi1_b[18:0]),
261 .vnw_ary (vnw_ary)
262 );
263
264
265n2_l2d_32kb_cust way70_01
266 (
267 .waysel_c3 (waysel_c3_1[7:0]),
268 .waysel_err_c3 (wayerr_c3_1),
269 .set_c3 (set_c3_1[8:0]),
270 .coloff_c3 (coloff_c3_1),
271 .coloff_c4_l (coloff_c4_l_1),
272 .coloff_c5 ({coloff_c5_1[0],coloff_c5_1[1]}),
273 .rd_wr_c3 (rd_wr_c3_1),
274 .readen_c5 (readen_c5_1),
275 .l2clk (l2clk),
276 .fuse_l2d_data_in_00 (fuse_l2d_data_in_10[9:0]),
277 .fuse_l2d_rid_00 (fuse_l2d_rid_10[2:0]),
278 .fuse_l2d_wren_00 (fuse_l2d_wren_10),
279 .fuse_l2d_reset_00_l (fuse_l2d_reset_10_l),
280 .sel_quad_00 (fuse_l2d_rid_10[4]),
281 .fuse_l2d_data_in_01 (fuse_l2d_data_in_11[9:0]),
282 .fuse_l2d_rid_01 (fuse_l2d_rid_11[2:0]),
283 .fuse_l2d_wren_01 (fuse_l2d_wren_11),
284 .fuse_l2d_reset_01_l (fuse_l2d_reset_11_l),
285 .sel_quad_01 (fuse_l2d_rid_11[4]),
286 .red_d_out_00 (right_red_top_d_00[9:0]),
287 .red_d_out_01 (right_red_top_d_01[9:0]),
288 .red_top_d_00 (10'b0),
289 .red_top_d_01 (10'b0),
290 .tcu_pce_ov (tcu_pce_ov_1),
291 .tcu_pce (pce_1),
292 .se (se_1),
293 .tcu_clk_stop (tcu_clk_stop_1),
294 .wrd0lo_b_l (wrdlo1_b_l[38:19]),
295 .wrd0hi_b_l (wrdhi1_b_l[38:19]),
296 .wrd1lo_b_l (wrdlo0_b_l[38:20]),
297 .wrd1hi_b_l (wrdhi0_b_l[38:20]),
298 .ldin0lo_b (20'b0),
299 .ldin0hi_b (20'b0),
300 .ldin1lo_b (19'b0),
301 .ldin1hi_b (19'b0),
302 .worden_c3 (worden_c3_1[3:0]),
303 .tstmodclk_l (tstmodclk_l_1),
304 .wee_l (wee_l_1),
305 .ldout0lo_b00 (ldoutlo1_b_top[38:19]),
306 .ldout0hi_b00 (ldouthi1_b_top[38:19]),
307 .ldout1lo_b00 (ldoutlo0_b_top[38:20]),
308 .ldout1hi_b00 (ldouthi0_b_top[38:20]),
309 .vnw_ary (vnw_ary)
310 );
311
312n2_l2d_32kb_cust way158_01
313 (
314 .waysel_c3 (waysel_c3_1[15:8]),
315 .waysel_err_c3 (wayerr_c3_1),
316 .set_c3 (set_c3_1[8:0]),
317 .coloff_c3 (coloff_c3_1),
318 .coloff_c4_l (coloff_c4_l_1),
319 .coloff_c5 ({coloff_c5_1[0],coloff_c5_1[1]}),
320 .rd_wr_c3 (rd_wr_c3_1),
321 .readen_c5 (readen_c5_1),
322 .l2clk (l2clk),
323 .fuse_l2d_data_in_00 (fuse_l2d_data_in_10[9:0]),
324 .fuse_l2d_rid_00 (fuse_l2d_rid_10[2:0]),
325 .fuse_l2d_wren_00 (fuse_l2d_wren_10),
326 .fuse_l2d_reset_00_l (fuse_l2d_reset_10_l),
327 .sel_quad_00 (fuse_l2d_rid_10[3]),
328 .fuse_l2d_data_in_01 (fuse_l2d_data_in_11[9:0]),
329 .fuse_l2d_rid_01 (fuse_l2d_rid_11[2:0]),
330 .fuse_l2d_wren_01 (fuse_l2d_wren_11),
331 .fuse_l2d_reset_01_l (fuse_l2d_reset_11_l),
332 .sel_quad_01 (fuse_l2d_rid_11[3]),
333 .red_d_out_00 (fdout_10[9:0]),
334 .red_d_out_01 (fdout_11[9:0]),
335 .red_top_d_00 (right_red_top_d_00[9:0]),
336 .red_top_d_01 (right_red_top_d_01[9:0]),
337 .tcu_pce_ov (tcu_pce_ov_1),
338 .tcu_pce (pce_1),
339 .se (se_1),
340 .tcu_clk_stop (tcu_clk_stop_1),
341 .wrd0lo_b_l (wrdlo1_b_l[38:19]),
342 .wrd0hi_b_l (wrdhi1_b_l[38:19]),
343 .wrd1lo_b_l (wrdlo0_b_l[38:20]),
344 .wrd1hi_b_l (wrdhi0_b_l[38:20]),
345 .ldin0lo_b (ldoutlo1_b_top[38:19]),
346 .ldin0hi_b (ldouthi1_b_top[38:19]),
347 .ldin1lo_b (ldoutlo0_b_top[38:20]),
348 .ldin1hi_b (ldouthi0_b_top[38:20]),
349 .worden_c3 (worden_c3_1[3:0]),
350 .tstmodclk_l (tstmodclk_l_1),
351 .wee_l (wee_l_1),
352 .ldout0lo_b00 (ldoutlo1_b[38:19]),
353 .ldout0hi_b00 (ldouthi1_b[38:19]),
354 .ldout1lo_b00 (ldoutlo0_b[38:20]),
355 .ldout1hi_b00 (ldouthi0_b[38:20]),
356 .vnw_ary (vnw_ary)
357 );
358
359
360endmodule
361
362
363module n2_l2d_32kb_cust (
364 waysel_c3,
365 waysel_err_c3,
366 set_c3,
367 coloff_c3,
368 coloff_c4_l,
369 coloff_c5,
370 rd_wr_c3,
371 readen_c5,
372 l2clk,
373 fuse_l2d_data_in_00,
374 fuse_l2d_rid_00,
375 fuse_l2d_wren_00,
376 fuse_l2d_reset_00_l,
377 sel_quad_00,
378 red_d_out_00,
379 fuse_l2d_data_in_01,
380 fuse_l2d_rid_01,
381 fuse_l2d_wren_01,
382 fuse_l2d_reset_01_l,
383 sel_quad_01,
384 red_d_out_01,
385 red_top_d_00,
386 red_top_d_01,
387 tcu_pce_ov,
388 tcu_pce,
389 se,
390 tcu_clk_stop,
391 wrd0lo_b_l,
392 wrd0hi_b_l,
393 wrd1lo_b_l,
394 wrd1hi_b_l,
395 ldin0lo_b,
396 ldin0hi_b,
397 ldin1lo_b,
398 ldin1hi_b,
399 worden_c3,
400 tstmodclk_l,
401 wee_l,
402 vnw_ary,
403 ldout0lo_b00,
404 ldout0hi_b00,
405 ldout1lo_b00,
406 ldout1hi_b00);
407wire [7:0] waysel_top_c4;
408wire [8:0] set_top_c3b;
409wire coloff_top_c3b_l;
410wire writeen_top_c3b;
411wire [3:0] worden_top_c3b;
412wire l1clk;
413wire [9:0] red_addr_top_01;
414wire [77:0] cred;
415wire [19:0] sat_lo0_bc_l;
416wire [19:0] sat_hi0_bc_l;
417wire [18:0] sat_lo1_bc_l;
418wire [18:0] sat_hi1_bc_l;
419wire [7:0] waysel_bot_c4;
420wire [8:0] set_bot_c3b;
421wire coloff_bot_c3b_l;
422wire writeen_bot_c3b;
423wire [3:0] worden_bot_c3b;
424wire [9:0] red_addr_bot_00;
425wire [19:0] sab_lo0_bc_l;
426wire [19:0] sab_hi0_bc_l;
427wire [18:0] sab_lo1_bc_l;
428wire [18:0] sab_hi1_bc_l;
429
430
431
432input [7:0] waysel_c3;
433input waysel_err_c3;
434input [8:0] set_c3;
435input coloff_c3;
436input coloff_c4_l; // check if 1 bit
437input [1:0] coloff_c5; // check if 1 bit
438input rd_wr_c3;
439input readen_c5;
440input l2clk;
441
442
443input [9:0] fuse_l2d_data_in_00;
444input [2:0] fuse_l2d_rid_00;
445input fuse_l2d_wren_00;
446input fuse_l2d_reset_00_l;
447input sel_quad_00;
448output [9:0] red_d_out_00;
449
450input [9:0] fuse_l2d_data_in_01;
451input [2:0] fuse_l2d_rid_01;
452input fuse_l2d_wren_01;
453input fuse_l2d_reset_01_l;
454input sel_quad_01;
455output [9:0] red_d_out_01;
456
457input [9:0] red_top_d_00;
458input [9:0] red_top_d_01;
459
460input tcu_pce_ov;
461input tcu_pce;
462input se;
463input tcu_clk_stop;
464input [19:0] wrd0lo_b_l;
465input [19:0] wrd0hi_b_l;
466input [18:0] wrd1lo_b_l;
467input [18:0] wrd1hi_b_l;
468input [19:0] ldin0lo_b;
469input [19:0] ldin0hi_b;
470input [18:0] ldin1lo_b;
471input [18:0] ldin1hi_b;
472input [3:0] worden_c3;
473input tstmodclk_l;
474input wee_l;
475input vnw_ary; //NEW
476
477output [19:0] ldout0lo_b00;
478output [19:0] ldout0hi_b00;
479output [18:0] ldout1lo_b00;
480output [18:0] ldout1hi_b00;
481
482
483n2_l2d_16kb_cust set_top
484 (
485 .waysel_c4 (waysel_top_c4[7:0]),
486 .waysel_err_c3 (waysel_err_c3),
487 .set_c3b (set_top_c3b[8:0]),
488 .coloff_c3b_l (coloff_top_c3b_l),
489 .coloff_c4_l (coloff_c4_l),
490 .coloff_c5 (coloff_c5[1:0]),
491 .wen_c3b (writeen_top_c3b),
492 .readen_c5 (readen_c5),
493 .worden_c3b (worden_top_c3b[3:0]),
494 .l1clk (l1clk),
495 .wrd_lo0_b_l (wrd0lo_b_l[19:0]),
496 .wrd_hi0_b_l (wrd0hi_b_l[19:0]),
497 .wrd_lo1_b_l (wrd1lo_b_l[18:0]),
498 .wrd_hi1_b_l (wrd1hi_b_l[18:0]),
499// .bnken_lat (bnken_lat),
500 .red_adr (red_addr_top_01[9:0]),
501 .cred (cred[77:0]),
502// .fuse_l2d_reset (fuse_l2d_reset_00_l_buf),
503 .saout_lo0_bc_l (sat_lo0_bc_l[19:0]),
504 .saout_hi0_bc_l (sat_hi0_bc_l[19:0]),
505 .saout_lo1_bc_l (sat_lo1_bc_l[18:0]),
506 .saout_hi1_bc_l (sat_hi1_bc_l[18:0]),
507 .tstmodclk_l (tstmodclk_l), //NEW
508 .wee_l (wee_l), //NEW
509 .vnw_ary (vnw_ary) //NEW
510 );
511
512n2_l2d_16kb_cust set_bot
513 (
514 .waysel_c4 (waysel_bot_c4[7:0]),
515 .waysel_err_c3 (waysel_err_c3),
516 .set_c3b (set_bot_c3b[8:0]),
517 .coloff_c3b_l (coloff_bot_c3b_l),
518 .coloff_c4_l (coloff_c4_l),
519 .coloff_c5 (coloff_c5[1:0]),
520 .wen_c3b (writeen_bot_c3b),
521 .readen_c5 (readen_c5),
522 .worden_c3b (worden_bot_c3b[3:0]),
523 .l1clk (l1clk),
524 .wrd_lo0_b_l (wrd0lo_b_l[19:0]),
525 .wrd_hi0_b_l (wrd0hi_b_l[19:0]),
526 .wrd_lo1_b_l (wrd1lo_b_l[18:0]),
527 .wrd_hi1_b_l (wrd1hi_b_l[18:0]),
528 .red_adr (red_addr_bot_00[9:0]),
529// .bnken_lat (),
530 .cred (cred[77:0]),
531// .fuse_l2d_reset (fuse_l2d_reset_01_l_buf),
532 .saout_lo0_bc_l (sab_lo0_bc_l[19:0]),
533 .saout_hi0_bc_l (sab_hi0_bc_l[19:0]),
534 .saout_lo1_bc_l (sab_lo1_bc_l[18:0]),
535 .saout_hi1_bc_l (sab_hi1_bc_l[18:0]),
536 .tstmodclk_l (tstmodclk_l), //NEW
537 .wee_l (wee_l), //NEW
538 .vnw_ary (vnw_ary) //NEW
539 );
540
541
542n2_l2d_dmux78_cust data_mux
543 (
544 .waysel_c3 (waysel_c3[7:0]), // should be 15:0
545 .set_c3 (set_c3[8:0]),
546 .coloff_c3 (coloff_c3),
547// .coloff_c4_l (coloff_c4_l),
548// .coloff_c5 (coloff_c5[1:0]),
549 .rd_wr_c3 (rd_wr_c3),
550// .readen_c5 (readen_c5),
551 .worden_c3 (worden_c3[3:0]),
552 .l2clk (l2clk),
553 .tcu_pce_ov (tcu_pce_ov),
554 .tcu_pce (tcu_pce),
555 .se (se),
556 .tcu_clk_stop (tcu_clk_stop),
557 .waysel_top_c4 (waysel_top_c4[7:0]),
558 .waysel_bot_c4 (waysel_bot_c4[7:0]),
559 .set_top_c3b (set_top_c3b[8:0]),
560 .set_bot_c3b (set_bot_c3b[8:0]),
561// .coloff_top_c3b_l (coloff_top_c3b_l),
562// .coloff_bot_c3b_l (coloff_bot_c3b_l),
563// .coloff_top_c4_l (coloff_top_c4_l),
564// .coloff_bot_c4_l (coloff_bot_c4_l),
565// .coloff_top_c5 (coloff_top_c5),
566// .coloff_bot_c5 (coloff_bot_c5),
567 .writeen_top_c3b (writeen_top_c3b),
568 .writeen_bot_c3b (writeen_bot_c3b),
569// .readen_top_c5 (readen_top_c5),
570// .readen_bot_c5 (readen_bot_c5),
571 .l1clk (l1clk),
572 .worden_top_c3b (worden_top_c3b[3:0]),
573 .worden_bot_c3b (worden_bot_c3b[3:0]),
574 .sat_lo0_bc_l (sat_lo0_bc_l[19:0]),
575 .sat_hi0_bc_l (sat_hi0_bc_l[19:0]),
576 .sat_lo1_bc_l (sat_lo1_bc_l[18:0]),
577 .sat_hi1_bc_l (sat_hi1_bc_l[18:0]),
578 .sab_lo0_bc_l (sab_lo0_bc_l[19:0]),
579 .sab_hi0_bc_l (sab_hi0_bc_l[19:0]),
580 .sab_lo1_bc_l (sab_lo1_bc_l[18:0]),
581 .sab_hi1_bc_l (sab_hi1_bc_l[18:0]),
582 .ldin0lo_b (ldin0lo_b[19:0]),
583 .ldin0hi_b (ldin0hi_b[19:0]),
584 .ldin1lo_b (ldin1lo_b[18:0]),
585 .ldin1hi_b (ldin1hi_b[18:0]),
586// .bnken_lat (bnken_lat),
587 .ldout0lo_b (ldout0lo_b00[19:0]),
588 .ldout1lo_b (ldout1lo_b00[18:0]),
589 .ldout0hi_b (ldout0hi_b00[19:0]),
590 .ldout1hi_b (ldout1hi_b00[18:0]),
591 .red_d_out_00 (red_d_out_00[9:0]),
592 .red_d_in_00 (fuse_l2d_data_in_00[9:0]),
593 .fuse_l2d_rid_00 (fuse_l2d_rid_00[2:0]),
594 .fuse_l2d_wren_00 (fuse_l2d_wren_00),
595 .fuse_l2d_reset_00_l (fuse_l2d_reset_00_l),
596 .sel_quad_00 (sel_quad_00),
597 .red_d_out_01 (red_d_out_01[9:0]),
598 .red_top_d_00 (red_top_d_00[9:0]),
599 .red_top_d_01 (red_top_d_01[9:0]),
600 .red_d_in_01 (fuse_l2d_data_in_01[9:0]),
601 .fuse_l2d_rid_01 (fuse_l2d_rid_01[2:0]),
602 .fuse_l2d_wren_01 (fuse_l2d_wren_01),
603 .fuse_l2d_reset_01_l (fuse_l2d_reset_01_l),
604 .sel_quad_01 (sel_quad_01),
605 .cred (cred[77:0]),
606// .fuse_l2d_reset_00_l_buf (fuse_l2d_reset_00_l_buf),
607// .fuse_l2d_reset_01_l_buf (fuse_l2d_reset_01_l_buf),
608 .red_addr_top (red_addr_top_01),
609 .red_addr_bot (red_addr_bot_00),
610 .coloff_c4_l(coloff_c4_l),
611 .coloff_top_c3b_l(coloff_top_c3b_l),
612 .coloff_bot_c3b_l(coloff_bot_c3b_l)
613 );
614
615endmodule
616
617
618
619
620module n2_l2d_16kb_cust (
621 waysel_c4,
622 waysel_err_c3,
623 set_c3b,
624 coloff_c3b_l,
625 coloff_c4_l,
626 coloff_c5,
627 wen_c3b,
628 readen_c5,
629 worden_c3b,
630 l1clk,
631 wrd_lo0_b_l,
632 wrd_lo1_b_l,
633 wrd_hi0_b_l,
634 wrd_hi1_b_l,
635 red_adr,
636 cred,
637 tstmodclk_l,
638 wee_l,
639 vnw_ary,
640 saout_lo0_bc_l,
641 saout_lo1_bc_l,
642 saout_hi0_bc_l,
643 saout_hi1_bc_l);
644wire coloff_c3b_l_unused;
645wire bank_select;
646wire coloff_c4;
647wire [7:0] set_c4;
648wire [1:0] spare_word_enable;
649wire select_red_odd;
650wire select_red_even;
651
652
653
654input [7:0] waysel_c4;
655input waysel_err_c3; // Active when multiple way sel is on
656input [8:0] set_c3b; // After b-latch
657input coloff_c3b_l; // After b-latch+inv
658input coloff_c4_l; // stage+inv
659input [1:0] coloff_c5; // 2-stage
660input wen_c3b; // Write-enable, after b-latch
661input readen_c5; //
662input [3:0] worden_c3b; // After b-latch
663input l1clk; // After l1clk hdr
664input [19:0] wrd_lo0_b_l; //
665input [18:0] wrd_lo1_b_l; //
666input [19:0] wrd_hi0_b_l; //
667input [18:0] wrd_hi1_b_l; //
668input [9:0] red_adr; // Redudancy address
669input [77:0] cred; // Redudancy address
670input tstmodclk_l; //NEW
671input wee_l; //NEW
672input vnw_ary; //NEW
673
674//output bnken_lat; // Address latch enable (1.5cycle)
675output [19:0] saout_lo0_bc_l; // C5bc output from senseamp
676output [18:0] saout_lo1_bc_l; // C5bc output from senseamp
677output [19:0] saout_hi0_bc_l; // C5bc output from senseamp
678output [18:0] saout_hi1_bc_l; // C5bc output from senseamp
679
680//reg rd_data_out_sel_c5b;
681//reg select_read_data_c5b;
682reg select_read_data_c5b_hi_rgt;
683reg select_read_data_c5b_hi_lft;
684reg select_read_data_c5b_lo_rgt;
685reg select_read_data_c5b_lo_lft;
686reg select_read_data_all_c5b;
687reg select_read_red_all_c5b;
688
689//reg select_read_red_c5b;
690reg select_read_red_c5b_hi_rgt;
691reg select_read_red_c5b_hi_lft;
692reg select_read_red_c5b_lo_rgt;
693reg select_read_red_c5b_lo_lft;
694
695//reg bnken_lat;
696
697reg [19:0] saout_lo0_bc_l; // C5bc output from senseamp
698reg [18:0] saout_lo1_bc_l; // C5bc output from senseamp
699reg [19:0] saout_hi0_bc_l; // C5bc output from senseamp
700reg [18:0] saout_hi1_bc_l; // C5bc output from senseamp
701
702reg [79:0] read_data;
703wire [79:0] rd_data;
704wire [79:0] wr_data;
705reg rd_spare_0,rd_spare_1;
706wire wr_spare_0,wr_spare_1;
707
708wire [19:0] saout_hi0_b_out_l, saout_lo0_b_out_l;
709wire [18:0] saout_hi1_b_out_l, saout_lo1_b_out_l;
710wire [19:0] red_lo0_b_out_l;
711wire [18:0] red_lo1_b_out_l;
712wire [19:0] red_hi0_b_out_l;
713wire [18:0] red_hi1_b_out_l;
714
715wire [1:0] coloff_c5_rgt;
716wire [1:0] coloff_c5_lft;
717wire red_sel_rgt;
718wire red_sel_lft;
719
720
721
722
723reg [19:0] mem_lo0_way0 [255:0];
724reg [18:0] mem_lo1_way0 [255:0];
725reg [19:0] mem_hi0_way0 [255:0];
726reg [18:0] mem_hi1_way0 [255:0];
727reg [255:0] mem_way0_spare_0;
728reg [255:0] mem_way0_spare_1;
729
730reg [19:0] mem_lo0_way1 [255:0];
731reg [18:0] mem_lo1_way1 [255:0];
732reg [19:0] mem_hi0_way1 [255:0];
733reg [18:0] mem_hi1_way1 [255:0];
734reg [255:0] mem_way1_spare_0;
735reg [255:0] mem_way1_spare_1;
736
737reg [19:0] mem_lo0_way2 [255:0];
738reg [18:0] mem_lo1_way2 [255:0];
739reg [19:0] mem_hi0_way2 [255:0];
740reg [18:0] mem_hi1_way2 [255:0];
741reg [255:0] mem_way2_spare_0;
742reg [255:0] mem_way2_spare_1;
743
744
745reg [19:0] mem_lo0_way3 [255:0];
746reg [18:0] mem_lo1_way3 [255:0];
747reg [19:0] mem_hi0_way3 [255:0];
748reg [18:0] mem_hi1_way3 [255:0];
749reg [255:0] mem_way3_spare_0;
750reg [255:0] mem_way3_spare_1;
751
752
753reg [19:0] mem_lo0_way4 [255:0];
754reg [18:0] mem_lo1_way4 [255:0];
755reg [19:0] mem_hi0_way4 [255:0];
756reg [18:0] mem_hi1_way4 [255:0];
757reg [255:0] mem_way4_spare_0;
758reg [255:0] mem_way4_spare_1;
759
760
761reg [19:0] mem_lo0_way5 [255:0];
762reg [18:0] mem_lo1_way5 [255:0];
763reg [19:0] mem_hi0_way5 [255:0];
764reg [18:0] mem_hi1_way5 [255:0];
765reg [255:0] mem_way5_spare_0;
766reg [255:0] mem_way5_spare_1;
767
768
769reg [19:0] mem_lo0_way6 [255:0];
770reg [18:0] mem_lo1_way6 [255:0];
771reg [19:0] mem_hi0_way6 [255:0];
772reg [18:0] mem_hi1_way6 [255:0];
773reg [255:0] mem_way6_spare_0;
774reg [255:0] mem_way6_spare_1;
775
776
777reg [19:0] mem_lo0_way7 [255:0];
778reg [18:0] mem_lo1_way7 [255:0];
779reg [19:0] mem_hi0_way7 [255:0];
780reg [18:0] mem_hi1_way7 [255:0];
781reg [255:0] mem_way7_spare_0;
782reg [255:0] mem_way7_spare_1;
783
784//reg bnken_lat_c52;
785reg [19:0] saout_lo0_bc; // C5bc output from senseamp
786reg [18:0] saout_lo1_bc; // C5bc output from senseamp
787reg [19:0] saout_hi0_bc; // C5bc output from senseamp
788reg [18:0] saout_hi1_bc; // C5bc output from senseamp
789
790
791//reg [19:0] saout_lo0_bc_d; // C5bc output from senseamp
792//reg [18:0] saout_lo1_bc_d; // C5bc output from senseamp
793//reg [19:0] saout_hi0_bc_d; // C5bc output from senseamp
794//reg [18:0] saout_hi1_bc_d; // C5bc output from senseamp
795
796//reg set_banken_lat, reset_banken_lat;
797
798reg [19:0] saout_lo0_bc_c5b_l;
799reg [18:0] saout_lo1_bc_c5b_l;
800reg [19:0] saout_hi0_bc_c5b_l;
801reg [18:0] saout_hi1_bc_c5b_l;
802
803reg [19:0] saout_lo0_bc_d_l;
804reg [18:0] saout_lo1_bc_d_l;
805reg [19:0] saout_hi0_bc_d_l;
806reg [18:0] saout_hi1_bc_d_l;
807
808
809assign coloff_c3b_l_unused = coloff_c3b_l;
810
811
812//always@(posedge l1clk)
813//begin
814// if(~coloff_c3b_l)
815// set_banken_lat <= 1'b1;
816// else set_banken_lat <= 1'b0;
817//end
818//
819//always@(negedge l1clk)
820//begin
821// if(coloff_c4_l)
822// reset_banken_lat <= 1'b1;
823// else reset_banken_lat <= 1'b0;
824//end
825//
826//always@(set_banken_lat or reset_banken_lat)
827//begin
828// if(set_banken_lat )
829// bnken_lat <= 1'b1;
830// else if(reset_banken_lat )
831// bnken_lat <= 1'b0;
832//end
833
834
835reg [7:0] waysel_c5;
836reg [8:0] index_c4;
837reg [8:0] set_c5;
838reg wen_c4;
839reg [3:0] worden_c4;
840
841
842
843reg bank_select_c5;
844reg waysel_err_c3b, waysel_err_c4,waysel_err_c5;
845
846always@(l1clk or coloff_c4_l)
847begin
848 if(~l1clk & coloff_c4_l)
849 waysel_err_c3b <= waysel_err_c3;
850end
851
852
853
854
855
856always@(posedge l1clk)
857begin
858 waysel_err_c4 <= waysel_err_c3b;
859 waysel_err_c5 <= waysel_err_c4;
860 waysel_c5[7:0] <= waysel_c4[7:0];
861 index_c4[8:0] <= set_c3b[8:0];
862 set_c5[8:0] <= index_c4[8:0];
863 worden_c4[3:0] <= worden_c3b[3:0];
864 wen_c4 <= wen_c3b;
865 bank_select_c5 <= bank_select;
866end
867
868
869assign coloff_c4 = ~coloff_c4_l;
870assign bank_select = index_c4[8];
871
872//reg [19:0] saout_lo0_bc_c5b;
873//reg [18:0] saout_lo1_bc_c5b;
874//reg [19:0] saout_hi0_bc_c5b;
875//reg [18:0] saout_hi1_bc_c5b;
876
877
878
879
880
881
882assign set_c4[7:0] = index_c4[7:0];
883wire [19:0] wrd_lo0_a;
884wire [19:0] wrd_hi0_a;
885wire [18:0] wrd_lo1_a;
886wire [18:0] wrd_hi1_a;
887
888reg [19:0] wrd_lo0_a_reg;
889reg [19:0] wrd_hi0_a_reg;
890reg [18:0] wrd_lo1_a_reg;
891reg [18:0] wrd_hi1_a_reg;
892
893
894always@(posedge l1clk)
895begin
896wrd_lo0_a_reg[19:0] <= ~wrd_lo0_b_l[19:0];
897wrd_hi0_a_reg[19:0] <= ~wrd_hi0_b_l[19:0];
898wrd_lo1_a_reg[18:0] <= ~wrd_lo1_b_l[18:0];
899wrd_hi1_a_reg[18:0] <= ~wrd_hi1_b_l[18:0];
900end
901
902
903
904// COL redudancy
905
906//reg [255:0] red_reg1;
907//reg [255:0] red_reg2;
908
909wire [79:0] cred_mod;
910
911
912assign cred_mod[79:0] = {cred[77:59],1'b0,cred[58:19],1'b0,cred[18:0]};
913
914
915//assign spare_word_enable[1] = cred_mod[19] ? worden_c4[3] : worden_c4[2];
916//assign spare_word_enable[0] = cred_mod[59] ? worden_c4[3] : worden_c4[2];
917
918
919assign wr_data[19:0] =
920{wr_spare_0, wrd_lo1_a_reg[4], wrd_hi0_a_reg[4],wrd_lo0_a_reg[4],
921wrd_hi1_a_reg[3], wrd_lo1_a_reg[3], wrd_hi0_a_reg[3],wrd_lo0_a_reg[3],
922wrd_hi1_a_reg[2], wrd_lo1_a_reg[2], wrd_hi0_a_reg[2],wrd_lo0_a_reg[2],
923wrd_hi1_a_reg[1], wrd_lo1_a_reg[1], wrd_hi0_a_reg[1],wrd_lo0_a_reg[1],
924wrd_hi1_a_reg[0], wrd_lo1_a_reg[0], wrd_hi0_a_reg[0],wrd_lo0_a_reg[0]};
925
926assign wr_data[39:20] = {
927 wrd_lo1_a_reg[9], wrd_hi0_a_reg[9],wrd_lo0_a_reg[9],
928wrd_hi1_a_reg[8], wrd_lo1_a_reg[8], wrd_hi0_a_reg[8],wrd_lo0_a_reg[8],
929wrd_hi1_a_reg[7], wrd_lo1_a_reg[7], wrd_hi0_a_reg[7],wrd_lo0_a_reg[7],
930wrd_hi1_a_reg[6], wrd_lo1_a_reg[6], wrd_hi0_a_reg[6],wrd_lo0_a_reg[6],
931wrd_hi1_a_reg[5], wrd_lo1_a_reg[5], wrd_hi0_a_reg[5],wrd_lo0_a_reg[5], wrd_hi1_a_reg[4]};
932
933
934assign wr_data[59:40] = {
935wrd_lo1_a_reg[14], wrd_hi0_a_reg[14],wrd_lo0_a_reg[14],
936wrd_hi1_a_reg[13], wrd_lo1_a_reg[13], wrd_hi0_a_reg[13],wrd_lo0_a_reg[13],
937wrd_hi1_a_reg[12], wrd_lo1_a_reg[12], wrd_hi0_a_reg[12],wrd_lo0_a_reg[12],
938wrd_hi1_a_reg[11], wrd_lo1_a_reg[11], wrd_hi0_a_reg[11],wrd_lo0_a_reg[11],
939wrd_hi1_a_reg[10], wrd_lo1_a_reg[10], wrd_hi0_a_reg[10],wrd_lo0_a_reg[10], wrd_hi1_a_reg[9]};
940
941assign wr_data[79:60] = {
942wrd_hi0_a_reg[19], wrd_lo0_a_reg[19],
943wrd_hi1_a_reg[18], wrd_lo1_a_reg[18], wrd_hi0_a_reg[18],wrd_lo0_a_reg[18],
944wrd_hi1_a_reg[17], wrd_lo1_a_reg[17], wrd_hi0_a_reg[17],wrd_lo0_a_reg[17],
945wrd_hi1_a_reg[16], wrd_lo1_a_reg[16], wrd_hi0_a_reg[16],wrd_lo0_a_reg[16],
946wrd_hi1_a_reg[15], wrd_lo1_a_reg[15], wrd_hi0_a_reg[15],wrd_lo0_a_reg[15], wrd_hi1_a_reg[14],wr_spare_1};
947
948
949integer i;
950reg [80:0] data;
951
952always@(cred_mod or wr_data)
953begin
954if (~cred_mod[0]) begin
955 data[0] = wr_data[0];
956end
957
958for(i=0; i<18; i=i+1)
959begin
960 data[i+1] = cred_mod[i] ? wr_data[i] : wr_data[i+1];
961end
962
963data[19] = cred_mod[18] ? wr_data[18] : cred_mod[20] ? wr_data[20] : 1'b0;
964
965for(i=21;i<40;i=i+1)
966begin
967 data[i-1] = cred_mod[i] ? wr_data[i] : wr_data[i-1];
968end
969
970
971if (~cred_mod[39]) begin
972 data[39] = wr_data[39];
973end
974
975if (~cred_mod[40]) begin
976 data[40] = wr_data[40];
977end
978
979for(i=40;i<59;i=i+1)
980begin
981 data[i+1] = cred_mod[i] ? wr_data[i] : wr_data[i+1];
982end
983
984data[60] = cred_mod[59] ? wr_data[59] : cred_mod[61] ? wr_data[61] : 1'b0;
985
986for(i=62;i<80;i=i+1)
987begin
988 data[i-1] = cred_mod[i] ? wr_data[i] : wr_data[i-1];
989end
990
991if (~cred_mod[79]) begin
992 data[79] = wr_data[79];
993end
994
995end
996
997
998assign { wrd_hi0_a[19], wrd_lo0_a[19],
999wrd_hi1_a[18], wrd_lo1_a[18], wrd_hi0_a[18],wrd_lo0_a[18],
1000wrd_hi1_a[17], wrd_lo1_a[17], wrd_hi0_a[17],wrd_lo0_a[17],
1001wrd_hi1_a[16], wrd_lo1_a[16], wrd_hi0_a[16],wrd_lo0_a[16],
1002wrd_hi1_a[15], wrd_lo1_a[15], wrd_hi0_a[15],wrd_lo0_a[15],
1003wrd_hi1_a[14],wr_spare_1} = data[79:60];
1004
1005assign {
1006wrd_lo1_a[14], wrd_hi0_a[14],wrd_lo0_a[14],
1007wrd_hi1_a[13], wrd_lo1_a[13], wrd_hi0_a[13],wrd_lo0_a[13],
1008wrd_hi1_a[12], wrd_lo1_a[12], wrd_hi0_a[12],wrd_lo0_a[12],
1009wrd_hi1_a[11], wrd_lo1_a[11], wrd_hi0_a[11],wrd_lo0_a[11],
1010wrd_hi1_a[10], wrd_lo1_a[10], wrd_hi0_a[10],wrd_lo0_a[10],wrd_hi1_a[9]} = data[59:40];
1011
1012assign {
1013wrd_lo1_a[9], wrd_hi0_a[9],wrd_lo0_a[9],
1014wrd_hi1_a[8], wrd_lo1_a[8], wrd_hi0_a[8],wrd_lo0_a[8],
1015wrd_hi1_a[7], wrd_lo1_a[7], wrd_hi0_a[7],wrd_lo0_a[7],
1016wrd_hi1_a[6], wrd_lo1_a[6], wrd_hi0_a[6],wrd_lo0_a[6],
1017wrd_hi1_a[5], wrd_lo1_a[5], wrd_hi0_a[5],wrd_lo0_a[5], wrd_hi1_a[4]} = data[39:20];
1018
1019assign {
1020wr_spare_0, wrd_lo1_a[4], wrd_hi0_a[4],wrd_lo0_a[4],
1021wrd_hi1_a[3], wrd_lo1_a[3], wrd_hi0_a[3],wrd_lo0_a[3],
1022wrd_hi1_a[2], wrd_lo1_a[2], wrd_hi0_a[2],wrd_lo0_a[2],
1023wrd_hi1_a[1], wrd_lo1_a[1], wrd_hi0_a[1],wrd_lo0_a[1],
1024wrd_hi1_a[0], wrd_lo1_a[0], wrd_hi0_a[0],wrd_lo0_a[0]} = data[19:0];
1025
1026
1027
1028wire [79:0] worden_data;
1029wire [19:0] worden_lo0;
1030wire [19:0] worden_hi0;
1031wire [18:0] worden_lo1;
1032wire [18:0] worden_hi1;
1033
1034
1035assign worden_data[19:0] =
1036{spare_word_enable[0], worden_c4[2], worden_c4[1],worden_c4[0],
1037worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
1038worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
1039worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
1040worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0]};
1041
1042assign worden_data[39:20] = {
1043 worden_c4[2], worden_c4[1],worden_c4[0],
1044worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
1045worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
1046worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
1047worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], worden_c4[3]};
1048
1049
1050assign worden_data[59:40] = {
1051 worden_c4[2], worden_c4[1],worden_c4[0],
1052worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
1053worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
1054worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
1055worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], worden_c4[3]};
1056
1057assign worden_data[79:60] = {
1058 worden_c4[1],worden_c4[0],
1059worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
1060worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
1061worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
1062worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], worden_c4[3],spare_word_enable[1]};
1063
1064reg [79:0] worden_shift;
1065
1066
1067
1068always@(cred_mod or worden_data or wen_c4 or coloff_c4)
1069begin
1070if (wen_c4 & coloff_c4)
1071begin
1072if (~cred_mod[0]) begin
1073 worden_shift[0] = worden_data[0];
1074end
1075
1076for(i=0; i<18; i=i+1)
1077begin
1078 worden_shift[i+1] = cred_mod[i] ? worden_data[i] : ~cred_mod[i+1] ? worden_data[i+1] : 1'b0;
1079end
1080
1081worden_shift[19] = cred_mod[18] ? worden_data[18] : cred_mod[20] ? worden_data[20] : 1'b0;
1082
1083for(i=21;i<40;i=i+1)
1084begin
1085 worden_shift[i-1] = cred_mod[i] ? worden_data[i] : ~cred_mod[i-1] ? worden_data[i-1] : 1'b0;
1086end
1087
1088
1089if (~cred_mod[39]) begin
1090 worden_shift[39] = worden_data[39];
1091end
1092
1093if (~cred_mod[40]) begin
1094 worden_shift[40] = worden_data[40];
1095end
1096
1097for(i=40;i<59;i=i+1)
1098begin
1099 worden_shift[i+1] = cred_mod[i] ? worden_data[i] : ~cred_mod[i+1] ? worden_data[i+1] : 1'b0;
1100end
1101
1102worden_shift[60] = cred_mod[59] ? worden_data[59] : cred_mod[61] ? worden_data[61] : 1'b0;
1103
1104for(i=62;i<80;i=i+1)
1105begin
1106 worden_shift[i-1] = cred_mod[i] ? worden_data[i] : ~cred_mod[i-1] ? worden_data[i-1] : 1'b0;
1107end
1108
1109if (~cred_mod[79]) begin
1110 worden_shift[79] = worden_data[79];
1111end
1112
1113end
1114else worden_shift[79:0] = 80'b0;
1115
1116end
1117
1118
1119assign { worden_hi0[19], worden_lo0[19],
1120worden_hi1[18], worden_lo1[18], worden_hi0[18],worden_lo0[18],
1121worden_hi1[17], worden_lo1[17], worden_hi0[17],worden_lo0[17],
1122worden_hi1[16], worden_lo1[16], worden_hi0[16],worden_lo0[16],
1123worden_hi1[15], worden_lo1[15], worden_hi0[15],worden_lo0[15],
1124worden_hi1[14],spare_word_enable[1]} = worden_shift[79:60];
1125
1126assign {
1127worden_lo1[14], worden_hi0[14],worden_lo0[14],
1128worden_hi1[13], worden_lo1[13], worden_hi0[13],worden_lo0[13],
1129worden_hi1[12], worden_lo1[12], worden_hi0[12],worden_lo0[12],
1130worden_hi1[11], worden_lo1[11], worden_hi0[11],worden_lo0[11],
1131worden_hi1[10], worden_lo1[10], worden_hi0[10],worden_lo0[10],worden_hi1[9]} = worden_shift[59:40];
1132
1133assign {
1134worden_lo1[9], worden_hi0[9],worden_lo0[9],
1135worden_hi1[8], worden_lo1[8], worden_hi0[8],worden_lo0[8],
1136worden_hi1[7], worden_lo1[7], worden_hi0[7],worden_lo0[7],
1137worden_hi1[6], worden_lo1[6], worden_hi0[6],worden_lo0[6],
1138worden_hi1[5], worden_lo1[5], worden_hi0[5],worden_lo0[5], worden_hi1[4]} = worden_shift[39:20];
1139
1140assign {
1141spare_word_enable[0], worden_lo1[4], worden_hi0[4],worden_lo0[4],
1142worden_hi1[3], worden_lo1[3], worden_hi0[3],worden_lo0[3],
1143worden_hi1[2], worden_lo1[2], worden_hi0[2],worden_lo0[2],
1144worden_hi1[1], worden_lo1[1], worden_hi0[1],worden_lo0[1],
1145worden_hi1[0], worden_lo1[0], worden_hi0[0],worden_lo0[0]} = worden_shift[19:0];
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164always@(l1clk or wen_c4 or set_c4 or waysel_c4 or waysel_err_c4 or worden_c4 or wrd_lo0_a or
1165 wrd_hi0_a or wrd_lo1_a or wrd_hi1_a or coloff_c4 or bank_select or wr_spare_0 or
1166 wr_spare_1 or wee_l or worden_hi0 or worden_lo0 or worden_lo1 or worden_hi1 or spare_word_enable
1167 or vnw_ary)
1168begin
1169
1170////////////////////////////////////////////////////////////////
1171// Read all entries for a given set
1172////////////////////////////////////////////////////////////////
1173
1174////////////////////////////////////////////////////////////////
1175// Write data computation
1176////////////////////////////////////////////////////////////////
1177
1178///////////////////////////////////////////////////////////////
1179// Write to memory
1180//////////////////////////////////////////////////////////////
1181
1182
1183
1184 #0
1185
1186
1187//if(wen_c4 & ~waysel_err_c4 & bank_select & coloff_c4 & (|worden_c4))
1188if(~l1clk & wee_l & wen_c4 & ~waysel_err_c4 & bank_select & coloff_c4 & (|worden_c4) & vnw_ary)
1189begin
1190 if(waysel_c4[0])
1191 begin
1192 mem_lo0_way0[set_c4] = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way0[set_c4]);
1193 mem_hi0_way0[set_c4] = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way0[set_c4]);
1194 mem_lo1_way0[set_c4] = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way0[set_c4]);
1195 mem_hi1_way0[set_c4] = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way0[set_c4]);
1196 mem_way0_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way0_spare_0[set_c4]);
1197 mem_way0_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way0_spare_1[set_c4]);
1198 end
1199 else if(waysel_c4[1])
1200 begin
1201 mem_lo0_way1[set_c4] = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way1[set_c4]);
1202 mem_hi0_way1[set_c4] = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way1[set_c4]);
1203 mem_lo1_way1[set_c4] = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way1[set_c4]);
1204 mem_hi1_way1[set_c4] = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way1[set_c4]);
1205 mem_way1_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way1_spare_0[set_c4]);
1206 mem_way1_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way1_spare_1[set_c4]);
1207 end
1208 else if(waysel_c4[2])
1209 begin
1210 mem_lo0_way2[set_c4] = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way2[set_c4]);
1211 mem_lo1_way2[set_c4] = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way2[set_c4]);
1212 mem_hi0_way2[set_c4] = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way2[set_c4]);
1213 mem_hi1_way2[set_c4] = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way2[set_c4]);
1214 mem_way2_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way2_spare_0[set_c4]);
1215 mem_way2_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way2_spare_1[set_c4]);
1216 end
1217 else if(waysel_c4[3])
1218 begin
1219 mem_lo0_way3[set_c4] = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way3[set_c4]);
1220 mem_lo1_way3[set_c4] = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way3[set_c4]);
1221 mem_hi0_way3[set_c4] = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way3[set_c4]);
1222 mem_hi1_way3[set_c4] = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way3[set_c4]);
1223 mem_way3_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way3_spare_0[set_c4]);
1224 mem_way3_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way3_spare_1[set_c4]);
1225 end
1226 else if(waysel_c4[4])
1227 begin
1228 mem_lo0_way4[set_c4] = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way4[set_c4]);
1229 mem_lo1_way4[set_c4] = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way4[set_c4]);
1230 mem_hi0_way4[set_c4] = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way4[set_c4]);
1231 mem_hi1_way4[set_c4] = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way4[set_c4]);
1232 mem_way4_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way4_spare_0[set_c4]);
1233 mem_way4_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way4_spare_1[set_c4]);
1234 end
1235 else if(waysel_c4[5])
1236 begin
1237 mem_lo0_way5[set_c4] =(worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way5[set_c4]);
1238 mem_lo1_way5[set_c4] =(worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way5[set_c4]);
1239 mem_hi0_way5[set_c4] =(worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way5[set_c4]);
1240 mem_hi1_way5[set_c4] =(worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way5[set_c4]);
1241 mem_way5_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way5_spare_0[set_c4]);
1242 mem_way5_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way5_spare_1[set_c4]);
1243 end
1244 else if(waysel_c4[6])
1245 begin
1246 mem_lo0_way6[set_c4] =(worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way6[set_c4]);
1247 mem_lo1_way6[set_c4] =(worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way6[set_c4]);
1248 mem_hi0_way6[set_c4] =(worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way6[set_c4]);
1249 mem_hi1_way6[set_c4] =(worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way6[set_c4]);
1250 mem_way6_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way6_spare_0[set_c4]);
1251 mem_way6_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way6_spare_1[set_c4]);
1252 end
1253 else if(waysel_c4[7])
1254 begin
1255 mem_lo0_way7[set_c4] =(worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way7[set_c4]);
1256 mem_lo1_way7[set_c4] =(worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way7[set_c4]);
1257 mem_hi0_way7[set_c4] =(worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way7[set_c4]);
1258 mem_hi1_way7[set_c4] =(worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way7[set_c4]);
1259 mem_way7_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way7_spare_0[set_c4]);
1260 mem_way7_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way7_spare_1[set_c4]);
1261 end
1262 end
1263end
1264
1265//always@(waysel_c4 or set_c4 or bnken_lat )
1266always@(waysel_c4 or set_c4 or coloff_c4_l or vnw_ary)
1267
1268begin
1269
1270
1271 #0
1272
1273if(~coloff_c4_l & vnw_ary)
1274begin
1275 if(waysel_c4[0])
1276 begin
1277 saout_lo0_bc[19:0] <= mem_lo0_way0[set_c4];
1278 saout_lo1_bc[18:0] <= mem_lo1_way0[set_c4];
1279 saout_hi0_bc[19:0] <= mem_hi0_way0[set_c4];
1280 saout_hi1_bc[18:0] <= mem_hi1_way0[set_c4];
1281 rd_spare_0 <= mem_way0_spare_0[set_c4];
1282 rd_spare_1 <= mem_way0_spare_1[set_c4];
1283 end
1284 else if(waysel_c4[1])
1285 begin
1286 saout_lo0_bc[19:0] <= mem_lo0_way1[set_c4];
1287 saout_lo1_bc[18:0] <= mem_lo1_way1[set_c4];
1288 saout_hi0_bc[19:0] <= mem_hi0_way1[set_c4];
1289 saout_hi1_bc[18:0] <= mem_hi1_way1[set_c4];
1290 rd_spare_0 <= mem_way1_spare_0[set_c4];
1291 rd_spare_1 <= mem_way1_spare_1[set_c4];
1292 end
1293 else if(waysel_c4[2])
1294 begin
1295 saout_lo0_bc[19:0] <= mem_lo0_way2[set_c4];
1296 saout_lo1_bc[18:0] <= mem_lo1_way2[set_c4];
1297 saout_hi0_bc[19:0] <= mem_hi0_way2[set_c4];
1298 saout_hi1_bc[18:0] <= mem_hi1_way2[set_c4];
1299 rd_spare_0 <= mem_way2_spare_0[set_c4];
1300 rd_spare_1 <= mem_way2_spare_1[set_c4];
1301 end
1302 else if(waysel_c4[3])
1303 begin
1304 saout_lo0_bc[19:0] <= mem_lo0_way3[set_c4];
1305 saout_lo1_bc[18:0] <= mem_lo1_way3[set_c4];
1306 saout_hi0_bc[19:0] <= mem_hi0_way3[set_c4];
1307 saout_hi1_bc[18:0] <= mem_hi1_way3[set_c4];
1308 rd_spare_0 <= mem_way3_spare_0[set_c4];
1309 rd_spare_1 <= mem_way3_spare_1[set_c4];
1310 end
1311 else if(waysel_c4[4])
1312 begin
1313 saout_lo0_bc[19:0] <= mem_lo0_way4[set_c4];
1314 saout_lo1_bc[18:0] <= mem_lo1_way4[set_c4];
1315 saout_hi0_bc[19:0] <= mem_hi0_way4[set_c4];
1316 saout_hi1_bc[18:0] <= mem_hi1_way4[set_c4];
1317 rd_spare_0 <= mem_way4_spare_0[set_c4];
1318 rd_spare_1 <= mem_way4_spare_1[set_c4];
1319 end
1320 else if(waysel_c4[5])
1321 begin
1322 saout_lo0_bc[19:0] <= mem_lo0_way5[set_c4];
1323 saout_lo1_bc[18:0] <= mem_lo1_way5[set_c4];
1324 saout_hi0_bc[19:0] <= mem_hi0_way5[set_c4];
1325 saout_hi1_bc[18:0] <= mem_hi1_way5[set_c4];
1326 rd_spare_0 <= mem_way5_spare_0[set_c4];
1327 rd_spare_1 <= mem_way5_spare_1[set_c4];
1328 end
1329 else if(waysel_c4[6])
1330 begin
1331 saout_lo0_bc[19:0] <= mem_lo0_way6[set_c4];
1332 saout_lo1_bc[18:0] <= mem_lo1_way6[set_c4];
1333 saout_hi0_bc[19:0] <= mem_hi0_way6[set_c4];
1334 saout_hi1_bc[18:0] <= mem_hi1_way6[set_c4];
1335 rd_spare_0 <= mem_way6_spare_0[set_c4];
1336 rd_spare_1 <= mem_way6_spare_1[set_c4];
1337 end
1338 else if(waysel_c4[7])
1339 begin
1340 saout_lo0_bc[19:0] <= mem_lo0_way7[set_c4];
1341 saout_lo1_bc[18:0] <= mem_lo1_way7[set_c4];
1342 saout_hi0_bc[19:0] <= mem_hi0_way7[set_c4];
1343 saout_hi1_bc[18:0] <= mem_hi1_way7[set_c4];
1344 rd_spare_0 <= mem_way7_spare_0[set_c4];
1345 rd_spare_1 <= mem_way7_spare_1[set_c4];
1346 end
1347end
1348end
1349
1350
1351// READ
1352// Data is read out of the above array in c4 and gets registered and latched
1353// to become a c5b signal which gets muxed and goes to dmux
1354
1355
1356reg rd_spare_0_d_l,rd_spare_1_d_l;
1357reg rdd_spare_0,rdd_spare_1;
1358reg tstmodclk_c3b_l;
1359always@(posedge l1clk)
1360begin
1361 saout_lo0_bc_d_l[19:0] <= ~saout_lo0_bc[19:0];
1362 saout_lo1_bc_d_l[18:0] <= ~saout_lo1_bc[18:0];
1363 saout_hi0_bc_d_l[19:0] <= ~saout_hi0_bc[19:0];
1364 saout_hi1_bc_d_l[18:0] <= ~saout_hi1_bc[18:0];
1365 rd_spare_0_d_l <= ~rd_spare_0;
1366 rd_spare_1_d_l <= ~rd_spare_1;
1367end
1368
1369always@(negedge l1clk)
1370begin
1371 saout_lo0_bc_c5b_l[19:0] <= saout_lo0_bc_d_l[19:0];
1372 saout_lo1_bc_c5b_l[18:0] <= saout_lo1_bc_d_l[18:0];
1373 saout_hi0_bc_c5b_l[19:0] <= saout_hi0_bc_d_l[19:0];
1374 saout_hi1_bc_c5b_l[18:0] <= saout_hi1_bc_d_l[18:0];
1375 rdd_spare_0 <= rd_spare_0_d_l;
1376 rdd_spare_1 <= rd_spare_1_d_l;
1377 tstmodclk_c3b_l <= tstmodclk_l;
1378end
1379
1380
1381assign rd_data[19:0] =
1382 {rdd_spare_0, saout_lo1_bc_c5b_l[4], saout_hi0_bc_c5b_l[4],saout_lo0_bc_c5b_l[4],
1383 saout_hi1_bc_c5b_l[3], saout_lo1_bc_c5b_l[3], saout_hi0_bc_c5b_l[3],saout_lo0_bc_c5b_l[3],
1384 saout_hi1_bc_c5b_l[2], saout_lo1_bc_c5b_l[2], saout_hi0_bc_c5b_l[2],saout_lo0_bc_c5b_l[2],
1385 saout_hi1_bc_c5b_l[1], saout_lo1_bc_c5b_l[1], saout_hi0_bc_c5b_l[1],saout_lo0_bc_c5b_l[1],
1386 saout_hi1_bc_c5b_l[0], saout_lo1_bc_c5b_l[0], saout_hi0_bc_c5b_l[0],saout_lo0_bc_c5b_l[0]};
1387
1388 assign rd_data[39:20] = {
1389 saout_lo1_bc_c5b_l[9], saout_hi0_bc_c5b_l[9],saout_lo0_bc_c5b_l[9],
1390 saout_hi1_bc_c5b_l[8], saout_lo1_bc_c5b_l[8], saout_hi0_bc_c5b_l[8],saout_lo0_bc_c5b_l[8],
1391 saout_hi1_bc_c5b_l[7], saout_lo1_bc_c5b_l[7], saout_hi0_bc_c5b_l[7],saout_lo0_bc_c5b_l[7],
1392 saout_hi1_bc_c5b_l[6], saout_lo1_bc_c5b_l[6], saout_hi0_bc_c5b_l[6],saout_lo0_bc_c5b_l[6],
1393 saout_hi1_bc_c5b_l[5], saout_lo1_bc_c5b_l[5], saout_hi0_bc_c5b_l[5],saout_lo0_bc_c5b_l[5], saout_hi1_bc_c5b_l[4]};
1394
1395
1396 assign rd_data[59:40] = {
1397 saout_lo1_bc_c5b_l[14], saout_hi0_bc_c5b_l[14],saout_lo0_bc_c5b_l[14],
1398 saout_hi1_bc_c5b_l[13], saout_lo1_bc_c5b_l[13], saout_hi0_bc_c5b_l[13],saout_lo0_bc_c5b_l[13],
1399 saout_hi1_bc_c5b_l[12], saout_lo1_bc_c5b_l[12], saout_hi0_bc_c5b_l[12],saout_lo0_bc_c5b_l[12],
1400 saout_hi1_bc_c5b_l[11], saout_lo1_bc_c5b_l[11], saout_hi0_bc_c5b_l[11],saout_lo0_bc_c5b_l[11],
1401 saout_hi1_bc_c5b_l[10], saout_lo1_bc_c5b_l[10], saout_hi0_bc_c5b_l[10],saout_lo0_bc_c5b_l[10], saout_hi1_bc_c5b_l[9]};
1402
1403 assign rd_data[79:60] = {
1404 saout_hi0_bc_c5b_l[19], saout_lo0_bc_c5b_l[19],
1405 saout_hi1_bc_c5b_l[18], saout_lo1_bc_c5b_l[18], saout_hi0_bc_c5b_l[18],saout_lo0_bc_c5b_l[18],
1406 saout_hi1_bc_c5b_l[17], saout_lo1_bc_c5b_l[17], saout_hi0_bc_c5b_l[17],saout_lo0_bc_c5b_l[17],
1407 saout_hi1_bc_c5b_l[16], saout_lo1_bc_c5b_l[16], saout_hi0_bc_c5b_l[16],saout_lo0_bc_c5b_l[16],
1408 saout_hi1_bc_c5b_l[15], saout_lo1_bc_c5b_l[15], saout_hi0_bc_c5b_l[15],saout_lo0_bc_c5b_l[15], saout_hi1_bc_c5b_l[14],rdd_spare_1};
1409
1410
1411 always@(cred_mod or rd_data)
1412 begin
1413
1414 for(i=0;i<19;i=i+1)
1415 begin
1416 read_data[i] = cred_mod[i] ? rd_data[i+1] : rd_data[i];
1417 end
1418
1419 for(i=20;i<40;i=i+1)
1420 begin
1421 read_data[i] = cred_mod[i] ? rd_data[i-1] : rd_data[i];
1422 end
1423
1424
1425 for(i=40;i<60;i=i+1)
1426 begin
1427 read_data[i] = cred_mod[i] ? rd_data[i+1] : rd_data[i];
1428 end
1429
1430 for(i=61;i<80;i=i+1)
1431 begin
1432 read_data[i] = cred_mod[i] ? rd_data[i-1] : rd_data[i];
1433 end
1434
1435 end
1436
1437
1438
1439 assign { saout_hi0_b_out_l[19], saout_lo0_b_out_l[19],
1440 saout_hi1_b_out_l[18], saout_lo1_b_out_l[18], saout_hi0_b_out_l[18],saout_lo0_b_out_l[18],
1441 saout_hi1_b_out_l[17], saout_lo1_b_out_l[17], saout_hi0_b_out_l[17],saout_lo0_b_out_l[17],
1442 saout_hi1_b_out_l[16], saout_lo1_b_out_l[16], saout_hi0_b_out_l[16],saout_lo0_b_out_l[16],
1443 saout_hi1_b_out_l[15], saout_lo1_b_out_l[15], saout_hi0_b_out_l[15],saout_lo0_b_out_l[15],
1444 saout_hi1_b_out_l[14]} = read_data[79:61];
1445
1446 assign {saout_lo1_b_out_l[14], saout_hi0_b_out_l[14],saout_lo0_b_out_l[14],
1447 saout_hi1_b_out_l[13], saout_lo1_b_out_l[13], saout_hi0_b_out_l[13],saout_lo0_b_out_l[13],
1448 saout_hi1_b_out_l[12], saout_lo1_b_out_l[12], saout_hi0_b_out_l[12],saout_lo0_b_out_l[12],
1449 saout_hi1_b_out_l[11], saout_lo1_b_out_l[11], saout_hi0_b_out_l[11],saout_lo0_b_out_l[11],
1450 saout_hi1_b_out_l[10], saout_lo1_b_out_l[10], saout_hi0_b_out_l[10],saout_lo0_b_out_l[10],
1451 saout_hi1_b_out_l[9]} = read_data[59:40];
1452
1453 assign { saout_lo1_b_out_l[9], saout_hi0_b_out_l[9],saout_lo0_b_out_l[9],
1454 saout_hi1_b_out_l[8], saout_lo1_b_out_l[8], saout_hi0_b_out_l[8],saout_lo0_b_out_l[8],
1455 saout_hi1_b_out_l[7], saout_lo1_b_out_l[7], saout_hi0_b_out_l[7],saout_lo0_b_out_l[7],
1456 saout_hi1_b_out_l[6], saout_lo1_b_out_l[6], saout_hi0_b_out_l[6],saout_lo0_b_out_l[6],
1457 saout_hi1_b_out_l[5], saout_lo1_b_out_l[5], saout_hi0_b_out_l[5],saout_lo0_b_out_l[5],
1458 saout_hi1_b_out_l[4]} = read_data[39:20];
1459
1460 assign {saout_lo1_b_out_l[4], saout_hi0_b_out_l[4],saout_lo0_b_out_l[4],
1461 saout_hi1_b_out_l[3], saout_lo1_b_out_l[3], saout_hi0_b_out_l[3],saout_lo0_b_out_l[3],
1462 saout_hi1_b_out_l[2], saout_lo1_b_out_l[2], saout_hi0_b_out_l[2],saout_lo0_b_out_l[2],
1463 saout_hi1_b_out_l[1], saout_lo1_b_out_l[1], saout_hi0_b_out_l[1],saout_lo0_b_out_l[1],
1464 saout_hi1_b_out_l[0], saout_lo1_b_out_l[0], saout_hi0_b_out_l[0],saout_lo0_b_out_l[0]} = read_data[18:0];
1465
1466assign red_sel_rgt = |cred[19:18];
1467assign red_sel_lft = |cred[59:58];
1468
1469assign coloff_c5_rgt[1] = coloff_c5[1] | red_sel_rgt & coloff_c5[0];
1470assign coloff_c5_rgt[0] = coloff_c5[0] | red_sel_rgt & coloff_c5[1];
1471assign coloff_c5_lft[1] = coloff_c5[1] | red_sel_lft & coloff_c5[0];
1472assign coloff_c5_lft[0] = coloff_c5[0] | red_sel_lft & coloff_c5[1];
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484always@(negedge l1clk)
1485begin
1486select_read_data_all_c5b <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5) & (|coloff_c5) & readen_c5 & wee_l & ~waysel_err_c4);
1487select_read_red_all_c5b <=(bank_select_c5 & (select_red_odd | select_red_even) & (|waysel_c5) & (|coloff_c5) & readen_c5 & wee_l & ~waysel_err_c4);
1488
1489select_read_data_c5b_hi_rgt <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5) & wee_l) &
1490 (readen_c5 & coloff_c5_rgt[1] & ~waysel_err_c5);
1491select_read_data_c5b_hi_lft <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5) & wee_l) &
1492 (readen_c5 & coloff_c5_lft[1] & ~waysel_err_c5);
1493select_read_data_c5b_lo_rgt <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5) & wee_l) &
1494 (readen_c5 & coloff_c5_rgt[0] & ~waysel_err_c5);
1495select_read_data_c5b_lo_lft <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5) & wee_l) &
1496 (readen_c5 & coloff_c5_lft[0] & ~waysel_err_c5);
1497select_read_red_c5b_hi_rgt <=(bank_select_c5 & (select_red_odd | select_red_even) & (|waysel_c5) & wee_l) &
1498 (readen_c5 & coloff_c5_rgt[1] & ~waysel_err_c5);
1499select_read_red_c5b_hi_lft <=(bank_select_c5 & (select_red_odd | select_red_even) & (|waysel_c5) & wee_l) &
1500 (readen_c5 & coloff_c5_lft[1] & ~waysel_err_c5);
1501select_read_red_c5b_lo_rgt <=(bank_select_c5 & (select_red_odd | select_red_even) & (|waysel_c5) & wee_l) &
1502 (readen_c5 & coloff_c5_rgt[0] & ~waysel_err_c5);
1503select_read_red_c5b_lo_lft <=(bank_select_c5 & (select_red_odd | select_red_even) & (|waysel_c5) & wee_l) &
1504 (readen_c5 & coloff_c5_lft[0] & ~waysel_err_c5);
1505end
1506
1507
1508//assign saout_lo0_bc_l[19:0] = select_read_data_c5b ? saout_lo0_bc_c5b_l[19:0] :
1509// select_read_red_c5b ? red_lo0_out[19:0] : 20'hFFFFF;
1510//assign saout_lo1_bc_l[18:0] = select_read_data_c5b ? saout_lo1_bc_c5b_l[18:0] :
1511// select_read_red_c5b ? red_lo1_out[18:0] : 19'h7FFFF;
1512//assign saout_hi0_bc_l[19:0] = select_read_data_c5b ? saout_hi0_bc_c5b_l[19:0] :
1513// select_read_red_c5b ? red_hi0_out[19:0] : 20'hFFFFF;
1514//assign saout_hi1_bc_l[18:0] = select_read_data_c5b ? saout_hi1_bc_c5b_l[18:0] :
1515// select_read_red_c5b ? red_hi1_out[18:0] : 19'h7FFFF;
1516//
1517always@(select_read_red_c5b_lo_rgt or select_read_red_c5b_lo_lft or select_read_red_c5b_hi_rgt or select_read_red_c5b_hi_lft or
1518 select_read_data_c5b_lo_rgt or select_read_data_c5b_lo_lft or select_read_data_c5b_hi_rgt or select_read_data_c5b_hi_lft
1519 or red_lo0_b_out_l or red_hi0_b_out_l or red_lo1_b_out_l or saout_hi1_b_out_l
1520 or saout_lo0_b_out_l or red_hi0_b_out_l or saout_lo1_b_out_l or saout_hi1_b_out_l or tstmodclk_c3b_l or l1clk)
1521begin
1522
1523if(tstmodclk_c3b_l)
1524begin
1525saout_lo0_bc_l[9:0] = select_read_red_c5b_lo_rgt ? red_lo0_b_out_l[9:0] :
1526 select_read_data_c5b_lo_rgt ? saout_lo0_b_out_l[9:0] : 10'h3FF;
1527saout_lo0_bc_l[19:10] = select_read_red_c5b_lo_lft ? red_lo0_b_out_l[19:10] :
1528 select_read_data_c5b_lo_lft ? saout_lo0_b_out_l[19:10] : 10'h3FF;
1529saout_hi0_bc_l[9:0] = select_read_red_c5b_lo_rgt ? red_hi0_b_out_l[9:0] :
1530 select_read_data_c5b_lo_rgt ? saout_hi0_b_out_l[9:0] : 10'h3FF;
1531saout_hi0_bc_l[19:10] = select_read_red_c5b_lo_lft ? red_hi0_b_out_l[19:10] :
1532 select_read_data_c5b_lo_lft ? saout_hi0_b_out_l[19:10] : 10'h3FF;
1533saout_lo1_bc_l[9:0] = select_read_red_c5b_hi_rgt ? red_lo1_b_out_l[9:0] :
1534 select_read_data_c5b_hi_rgt ? saout_lo1_b_out_l[9:0] : 10'h3FF;
1535saout_lo1_bc_l[18:10] = select_read_red_c5b_hi_lft ? red_lo1_b_out_l[18:10] :
1536 select_read_data_c5b_hi_lft ? saout_lo1_b_out_l[18:10] : 9'h1FF;
1537saout_hi1_bc_l[8:0] = select_read_red_c5b_hi_rgt ? red_hi1_b_out_l[8:0] :
1538 select_read_data_c5b_hi_rgt ? saout_hi1_b_out_l[8:0] : 9'h1FF;
1539saout_hi1_bc_l[18:9] = select_read_red_c5b_hi_lft ? red_hi1_b_out_l[18:9] :
1540 select_read_data_c5b_hi_lft ? saout_hi1_b_out_l[18:9] : 10'h3FF;
1541end
1542else
1543begin
1544saout_lo0_bc_l[19:0] = select_read_red_all_c5b ? red_lo0_b_out_l[19:0] :
1545 select_read_data_all_c5b ? saout_lo0_b_out_l[19:0] : 20'bx;
1546saout_hi0_bc_l[19:0] = select_read_red_all_c5b ? red_hi0_b_out_l[19:0] :
1547 select_read_data_all_c5b ? saout_hi0_b_out_l[19:0] : 20'bx;
1548saout_lo1_bc_l[18:0] = select_read_red_all_c5b ? red_lo1_b_out_l[18:0] :
1549 select_read_data_all_c5b ? saout_lo1_b_out_l[18:0] : 19'bx;
1550saout_hi1_bc_l[18:0] = select_read_red_all_c5b ? red_hi1_b_out_l[18:0] :
1551 select_read_data_all_c5b ? saout_hi1_b_out_l[18:0] : 19'bx;
1552
1553//saout_lo0_bc_l[19:0] = select_read_data_all_c5b ? saout_lo0_bc_c5b_l[19:0] : 20'hFFFFF;
1554//saout_lo1_bc_l[18:0] = select_read_data_all_c5b ? saout_lo1_bc_c5b_l[18:0] : 19'hFFFFF;
1555//saout_hi0_bc_l[19:0] = select_read_data_all_c5b ? saout_hi0_bc_c5b_l[19:0] : 20'hFFFFF;
1556//saout_hi1_bc_l[18:0] = select_read_data_all_c5b ? saout_hi1_bc_c5b_l[18:0] : 19'hFFFFF;
1557end
1558end
1559
1560
1561//assign repair_saout_lo0_bc_l[9:0] =
1562//select_read_red_c5b_lo_rgt ? red_lo0_b_out_l[9:0] : select_read_data_c5b_lo_rgt ? saout_lo0_b_out_l[9:0] : 10'h3FF ;
1563//assign repair_saout_lo0_bc_l[19:10] =
1564//select_read_red_c5b_lo_lft ? red_lo0_b_out_l[19:10] : select_read_data_c5b_lo_lft ? saout_lo0_b_out_l[19:10] : 10'h3FF ;
1565//assign repair_saout_hi0_bc_l[9:0] =
1566//select_read_red_c5b_lo_rgt ? red_hi0_b_out_l[9:0] : select_read_data_c5b_lo_rgt ? saout_hi0_b_out_l[9:0] : 10'h3FF ;
1567//assign repair_saout_hi0_bc_l[19:10] =
1568//select_read_red_c5b_lo_lft ? red_hi0_b_out_l[19:10] : select_read_data_c5b_lo_lft ? saout_hi0_b_out_l[19:10] : 10'h3FF ;
1569//assign repair_saout_lo1_bc_l[9:0] =
1570//select_read_red_c5b_hi_rgt ? red_lo1_b_out_l[9:0] : select_read_data_c5b_hi_rgt ? saout_lo1_b_out_l[9:0] : 10'h3FF ;
1571//assign repair_saout_lo1_bc_l[18:10] =
1572//select_read_red_c5b_hi_lft ? red_lo1_b_out_l[18:10] : select_read_data_c5b_hi_lft ? saout_lo1_b_out_l[18:10] : 9'h1FF ;
1573//assign repair_saout_hi1_bc_l[8:0] =
1574//select_read_red_c5b_hi_rgt ? red_hi1_b_out_l[8:0] : select_read_data_c5b_hi_rgt ? saout_hi1_b_out_l[8:0] : 9'h1FF ;
1575//assign repair_saout_hi1_bc_l[18:9] =
1576//select_read_red_c5b_hi_lft ? red_hi1_b_out_l[18:9] : select_read_data_c5b_hi_lft ? saout_hi1_b_out_l[18:9] : 10'h3FF ;
1577//
1578//
1579//assign norepair_saout_lo0_bc_l[19:0] = select_read_data_all_c5b ? saout_lo0_bc_c5b_l[19:0] : 20'hFFFFF;
1580//assign norepair_saout_lo1_bc_l[18:0] = select_read_data_all_c5b ? saout_lo1_bc_c5b_l[18:0] : 19'hFFFFF;
1581//assign norepair_saout_hi0_bc_l[19:0] = select_read_data_all_c5b ? saout_hi0_bc_c5b_l[19:0] : 20'hFFFFF;
1582//assign norepair_saout_hi1_bc_l[18:0] = select_read_data_all_c5b ? saout_hi1_bc_c5b_l[18:0] : 19'hFFFFF;
1583//
1584//`endif
1585//
1586//`ifdef AXIS_SMEM
1587//
1588// always@(negedge l1clk)
1589// begin
1590// axis_saout_lo0_bc[19:0] = saout_lo0_bc[19:0];
1591// axis_saout_lo1_bc[18:0] = saout_lo1_bc[18:0];
1592// axis_saout_hi0_bc[19:0] = saout_hi0_bc[19:0];
1593// axis_saout_hi1_bc[18:0] = saout_hi1_bc[18:0];
1594// end
1595// assign saout_lo0_bc_l[19:0] = axis_select_read_data_c5b ? axis_saout_lo0_bc[19:0] : 20'hFFFFF;
1596// assign saout_lo1_bc_l[18:0] = axis_select_read_data_c5b ? axis_saout_lo1_bc[18:0] : 19'h7FFFF;
1597// assign saout_hi0_bc_l[19:0] = axis_select_read_data_c5b ? axis_saout_hi0_bc[19:0] : 20'hFFFFF;
1598// assign saout_hi1_bc_l[18:0] = axis_select_read_data_c5b ? axis_saout_hi1_bc[18:0] : 19'h7FFFF;
1599//
1600//`else
1601//assign saout_lo0_bc_l[19:0] = ~tstmodclk_c3b_l ? repair_saout_lo0_bc_l[19:0] : norepair_saout_lo0_bc_l[19:0];
1602//assign saout_lo1_bc_l[18:0] = ~tstmodclk_c3b_l ? repair_saout_lo1_bc_l[18:0] : norepair_saout_lo1_bc_l[18:0];
1603//assign saout_hi0_bc_l[19:0] = ~tstmodclk_c3b_l ? repair_saout_hi0_bc_l[19:0] : norepair_saout_hi0_bc_l[19:0];
1604//assign saout_hi1_bc_l[18:0] = ~tstmodclk_c3b_l ? repair_saout_hi1_bc_l[18:0] : norepair_saout_hi1_bc_l[18:0];
1605
1606///////////////////////////////////////////////////////////////////////////////////////////////
1607
1608// REDUDANCY
1609
1610reg [19:0] red_lo0_odd_0;
1611reg [18:0] red_lo1_odd_0;
1612reg [19:0] red_hi0_odd_0;
1613reg [18:0] red_hi1_odd_0;
1614reg [19:0] red_lo0_even_0;
1615reg [18:0] red_lo1_even_0;
1616reg [19:0] red_hi0_even_0;
1617reg [18:0] red_hi1_even_0;
1618reg redrow_way0_spare_odd_0;
1619reg redrow_way0_spare_even_0;
1620reg redrow_way0_spare_odd_1;
1621reg redrow_way0_spare_even_1;
1622
1623reg [19:0] red_lo0_odd_1;
1624reg [18:0] red_lo1_odd_1;
1625reg [19:0] red_hi0_odd_1;
1626reg [18:0] red_hi1_odd_1;
1627reg [19:0] red_lo0_even_1;
1628reg [18:0] red_lo1_even_1;
1629reg [19:0] red_hi0_even_1;
1630reg [18:0] red_hi1_even_1;
1631reg redrow_way1_spare_odd_0;
1632reg redrow_way1_spare_even_0;
1633reg redrow_way1_spare_odd_1;
1634reg redrow_way1_spare_even_1;
1635
1636reg [19:0] red_lo0_odd_2;
1637reg [18:0] red_lo1_odd_2;
1638reg [19:0] red_hi0_odd_2;
1639reg [18:0] red_hi1_odd_2;
1640reg [19:0] red_lo0_even_2;
1641reg [18:0] red_lo1_even_2;
1642reg [19:0] red_hi0_even_2;
1643reg [18:0] red_hi1_even_2;
1644reg redrow_way2_spare_odd_0;
1645reg redrow_way2_spare_even_0;
1646reg redrow_way2_spare_odd_1;
1647reg redrow_way2_spare_even_1;
1648
1649reg [19:0] red_lo0_odd_3;
1650reg [18:0] red_lo1_odd_3;
1651reg [19:0] red_hi0_odd_3;
1652reg [18:0] red_hi1_odd_3;
1653reg [19:0] red_lo0_even_3;
1654reg [18:0] red_lo1_even_3;
1655reg [19:0] red_hi0_even_3;
1656reg [18:0] red_hi1_even_3;
1657reg redrow_way3_spare_odd_0;
1658reg redrow_way3_spare_even_0;
1659reg redrow_way3_spare_odd_1;
1660reg redrow_way3_spare_even_1;
1661
1662reg [19:0] red_lo0_odd_4;
1663reg [18:0] red_lo1_odd_4;
1664reg [19:0] red_hi0_odd_4;
1665reg [18:0] red_hi1_odd_4;
1666reg [19:0] red_lo0_even_4;
1667reg [18:0] red_lo1_even_4;
1668reg [19:0] red_hi0_even_4;
1669reg [18:0] red_hi1_even_4;
1670reg redrow_way4_spare_odd_0;
1671reg redrow_way4_spare_even_0;
1672reg redrow_way4_spare_odd_1;
1673reg redrow_way4_spare_even_1;
1674
1675reg [19:0] red_lo0_odd_5;
1676reg [18:0] red_lo1_odd_5;
1677reg [19:0] red_hi0_odd_5;
1678reg [18:0] red_hi1_odd_5;
1679reg [19:0] red_lo0_even_5;
1680reg [18:0] red_lo1_even_5;
1681reg [19:0] red_hi0_even_5;
1682reg [18:0] red_hi1_even_5;
1683reg redrow_way5_spare_odd_0;
1684reg redrow_way5_spare_even_0;
1685reg redrow_way5_spare_odd_1;
1686reg redrow_way5_spare_even_1;
1687
1688reg [19:0] red_lo0_odd_6;
1689reg [18:0] red_lo1_odd_6;
1690reg [19:0] red_hi0_odd_6;
1691reg [18:0] red_hi1_odd_6;
1692reg [19:0] red_lo0_even_6;
1693reg [18:0] red_lo1_even_6;
1694reg [19:0] red_hi0_even_6;
1695reg [18:0] red_hi1_even_6;
1696reg redrow_way6_spare_odd_0;
1697reg redrow_way6_spare_even_0;
1698reg redrow_way6_spare_odd_1;
1699reg redrow_way6_spare_even_1;
1700
1701reg [19:0] red_lo0_odd_7;
1702reg [18:0] red_lo1_odd_7;
1703reg [19:0] red_hi0_odd_7;
1704reg [18:0] red_hi1_odd_7;
1705reg [19:0] red_lo0_even_7;
1706reg [18:0] red_lo1_even_7;
1707reg [19:0] red_hi0_even_7;
1708reg [18:0] red_hi1_even_7;
1709reg redrow_way7_spare_odd_0;
1710reg redrow_way7_spare_even_0;
1711reg redrow_way7_spare_odd_1;
1712reg redrow_way7_spare_even_1;
1713
1714
1715
1716reg [19:0] red_lo0_out_bc;
1717reg [18:0] red_lo1_out_bc;
1718reg [19:0] red_hi0_out_bc;
1719reg [18:0] red_hi1_out_bc;
1720reg redrow_rd_spare_0;
1721reg redrow_rd_spare_1;
1722
1723reg [19:0] red_lo0_out_bc_d_l;
1724reg [18:0] red_lo1_out_bc_d_l;
1725reg [19:0] red_hi0_out_bc_d_l;
1726reg [18:0] red_hi1_out_bc_d_l;
1727reg redrow_rd_spare_0_d_l;
1728reg redrow_rd_spare_1_d_l;
1729
1730reg [19:0] red_lo0_bc_c5b_l;
1731reg [19:0] red_hi0_bc_c5b_l;
1732reg [18:0] red_lo1_bc_c5b_l;
1733reg [18:0] red_hi1_bc_c5b_l;
1734reg redrow_rdd_spare_0;
1735reg redrow_rdd_spare_1;
1736
1737wire [79:0] red_rd_data;
1738reg [79:0] red_read_data;
1739
1740// Folloing 2 assigns detects a red index to hit with incoming index
1741// and assert. While writing and reading the way info is looked at
1742
1743assign select_red_odd = (red_adr[9:8] == 2'b11) & (red_adr[7:1] == set_c3b[7:1])
1744 & set_c3b[0] & red_adr[0];
1745assign select_red_even = (red_adr[9:8] == 2'b11) & (red_adr[7:1] == set_c3b[7:1])
1746 & ~set_c3b[0] & ~red_adr[0];
1747
1748
1749always@(wee_l or l1clk or wen_c4 or set_c4 or waysel_c4 or waysel_err_c4 or bank_select or coloff_c4 or worden_c4 or
1750 select_red_odd or select_red_even or worden_lo0 or worden_hi0 or worden_lo1 or worden_hi1 or wrd_lo0_a
1751 or wrd_hi0_a or wrd_lo1_a or wrd_hi1_a or wr_spare_0 or wr_spare_1 or spare_word_enable or vnw_ary)
1752begin
1753// Odd row to be written
1754if(~l1clk & wee_l & wen_c4 & select_red_odd & ~waysel_err_c4 & bank_select & coloff_c4 & (|worden_c4) & vnw_ary)
1755 begin
1756 if(waysel_c4[0])
1757 begin
1758 red_lo0_odd_0 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_0);
1759 red_hi0_odd_0 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_0);
1760 red_lo1_odd_0 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_0);
1761 red_hi1_odd_0 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_0);
1762 redrow_way0_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way0_spare_odd_0);
1763 redrow_way0_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way0_spare_odd_1);
1764 end
1765 else if(waysel_c4[1])
1766 begin
1767 red_lo0_odd_1 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_1);
1768 red_hi0_odd_1 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_1);
1769 red_lo1_odd_1 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_1);
1770 red_hi1_odd_1 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_1);
1771 redrow_way1_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way1_spare_odd_0);
1772 redrow_way1_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way1_spare_odd_1);
1773 end
1774 else if(waysel_c4[2])
1775 begin
1776 red_lo0_odd_2 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_2);
1777 red_hi0_odd_2 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_2);
1778 red_lo1_odd_2 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_2);
1779 red_hi1_odd_2 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_2);
1780 redrow_way2_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way2_spare_odd_0);
1781 redrow_way2_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way2_spare_odd_1);
1782 end
1783 else if(waysel_c4[3])
1784 begin
1785 red_lo0_odd_3 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_3);
1786 red_hi0_odd_3 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_3);
1787 red_lo1_odd_3 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_3);
1788 red_hi1_odd_3 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_3);
1789 redrow_way3_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way3_spare_odd_0);
1790 redrow_way3_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way3_spare_odd_1);
1791 end
1792 else if(waysel_c4[4])
1793 begin
1794 red_lo0_odd_4 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_4);
1795 red_hi0_odd_4 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_4);
1796 red_lo1_odd_4 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_4);
1797 red_hi1_odd_4 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_4);
1798 redrow_way4_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way4_spare_odd_0);
1799 redrow_way4_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way4_spare_odd_1);
1800 end
1801 else if(waysel_c4[5])
1802 begin
1803 red_lo0_odd_5 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_5);
1804 red_hi0_odd_5 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_5);
1805 red_lo1_odd_5 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_5);
1806 red_hi1_odd_5 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_5);
1807 redrow_way5_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way5_spare_odd_0);
1808 redrow_way5_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way5_spare_odd_1);
1809 end
1810 else if(waysel_c4[6])
1811 begin
1812 red_lo0_odd_6 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_6);
1813 red_hi0_odd_6 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_6);
1814 red_lo1_odd_6 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_6);
1815 red_hi1_odd_6 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_6);
1816 redrow_way6_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way6_spare_odd_0);
1817 redrow_way6_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way6_spare_odd_1);
1818 end
1819 else if(waysel_c4[7])
1820 begin
1821 red_lo0_odd_7 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_7);
1822 red_hi0_odd_7 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_7);
1823 red_lo1_odd_7 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_7);
1824 red_hi1_odd_7 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_7);
1825 redrow_way7_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way7_spare_odd_0);
1826 redrow_way7_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way7_spare_odd_1);
1827 end
1828 end
1829
1830
1831// Even rows to be written
1832if(~l1clk & wee_l & wen_c4 & select_red_even & ~waysel_err_c4 & bank_select & coloff_c4 & (|worden_c4) & vnw_ary)
1833 begin
1834 if(waysel_c4[0])
1835 begin
1836 red_lo0_even_0 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_0);
1837 red_hi0_even_0 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_0);
1838 red_lo1_even_0 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_0);
1839 red_hi1_even_0 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_0);
1840 redrow_way0_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way0_spare_even_0);
1841 redrow_way0_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way0_spare_even_1);
1842 end
1843 else if(waysel_c4[1])
1844 begin
1845 red_lo0_even_1 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_1);
1846 red_hi0_even_1 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_1);
1847 red_lo1_even_1 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_1);
1848 red_hi1_even_1 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_1);
1849 redrow_way1_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way1_spare_even_0);
1850 redrow_way1_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way1_spare_even_1);
1851 end
1852 else if(waysel_c4[2])
1853 begin
1854 red_lo0_even_2 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_2);
1855 red_hi0_even_2 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_2);
1856 red_lo1_even_2 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_2);
1857 red_hi1_even_2 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_2);
1858 redrow_way2_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way2_spare_even_0);
1859 redrow_way2_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way2_spare_even_1);
1860 end
1861 else if(waysel_c4[3])
1862 begin
1863 red_lo0_even_3 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_3);
1864 red_hi0_even_3 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_3);
1865 red_lo1_even_3 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_3);
1866 red_hi1_even_3 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_3);
1867 redrow_way3_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way3_spare_even_0);
1868 redrow_way3_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way3_spare_even_1);
1869 end
1870 else if(waysel_c4[4])
1871 begin
1872 red_lo0_even_4 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_4);
1873 red_hi0_even_4 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_4);
1874 red_lo1_even_4 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_4);
1875 red_hi1_even_4 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_4);
1876 redrow_way4_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way4_spare_even_0);
1877 redrow_way4_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way4_spare_even_1);
1878 end
1879 else if(waysel_c4[5])
1880 begin
1881 red_lo0_even_5 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_5);
1882 red_hi0_even_5 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_5);
1883 red_lo1_even_5 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_5);
1884 red_hi1_even_5 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_5);
1885 redrow_way5_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way5_spare_even_0);
1886 redrow_way5_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way5_spare_even_1);
1887 end
1888 else if(waysel_c4[6])
1889 begin
1890 red_lo0_even_6 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_6);
1891 red_hi0_even_6 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_6);
1892 red_lo1_even_6 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_6);
1893 red_hi1_even_6 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_6);
1894 redrow_way6_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way6_spare_even_0);
1895 redrow_way6_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way6_spare_even_1);
1896 end
1897 else if(waysel_c4[7])
1898 begin
1899 red_lo0_even_7 <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_7);
1900 red_hi0_even_7 <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_7);
1901 red_lo1_even_7 <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_7);
1902 red_hi1_even_7 <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_7);
1903 redrow_way7_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way7_spare_even_0);
1904 redrow_way7_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way7_spare_even_1);
1905 end
1906end
1907end
1908
1909// read out
1910always@(waysel_c4 or coloff_c4_l or set_c4 or vnw_ary)
1911begin
1912if(~coloff_c4_l & vnw_ary)
1913 begin
1914 if(waysel_c4[0])
1915 begin
1916 red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_0 : red_lo0_even_0;
1917 red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_0 : red_lo1_even_0;
1918 red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_0 : red_hi0_even_0;
1919 red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_0 : red_hi1_even_0;
1920 redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way0_spare_odd_0 : redrow_way0_spare_even_0;
1921 redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way0_spare_odd_1 : redrow_way0_spare_even_1;
1922 end
1923 else if(waysel_c4[1])
1924 begin
1925 red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_1 : red_lo0_even_1;
1926 red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_1 : red_lo1_even_1;
1927 red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_1 : red_hi0_even_1;
1928 red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_1 : red_hi1_even_1;
1929 redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way1_spare_odd_0 : redrow_way1_spare_even_0;
1930 redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way1_spare_odd_1 : redrow_way1_spare_even_1;
1931 end
1932 else if(waysel_c4[2])
1933 begin
1934 red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_2 : red_lo0_even_2;
1935 red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_2 : red_lo1_even_2;
1936 red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_2 : red_hi0_even_2;
1937 red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_2 : red_hi1_even_2;
1938 redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way2_spare_odd_0 : redrow_way2_spare_even_0;
1939 redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way2_spare_odd_1 : redrow_way2_spare_even_1;
1940 end
1941 else if(waysel_c4[3])
1942 begin
1943 red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_3 : red_lo0_even_3;
1944 red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_3 : red_lo1_even_3;
1945 red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_3 : red_hi0_even_3;
1946 red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_3 : red_hi1_even_3;
1947 redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way3_spare_odd_0 : redrow_way3_spare_even_0;
1948 redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way3_spare_odd_1 : redrow_way3_spare_even_1;
1949 end
1950 else if(waysel_c4[4])
1951 begin
1952 red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_4 : red_lo0_even_4;
1953 red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_4 : red_lo1_even_4;
1954 red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_4 : red_hi0_even_4;
1955 red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_4 : red_hi1_even_4;
1956 redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way4_spare_odd_0 : redrow_way4_spare_even_0;
1957 redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way4_spare_odd_1 : redrow_way4_spare_even_1;
1958 end
1959 else if(waysel_c4[5])
1960 begin
1961 red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_5 : red_lo0_even_5;
1962 red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_5 : red_lo1_even_5;
1963 red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_5 : red_hi0_even_5;
1964 red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_5 : red_hi1_even_5;
1965 redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way5_spare_odd_0 : redrow_way5_spare_even_0;
1966 redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way5_spare_odd_1 : redrow_way5_spare_even_1;
1967 end
1968 else if(waysel_c4[6])
1969 begin
1970 red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_6 : red_lo0_even_6;
1971 red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_6 : red_lo1_even_6;
1972 red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_6 : red_hi0_even_6;
1973 red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_6 : red_hi1_even_6;
1974 redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way6_spare_odd_0 : redrow_way6_spare_even_0;
1975 redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way6_spare_odd_1 : redrow_way6_spare_even_1;
1976 end
1977 else if(waysel_c4[7])
1978 begin
1979 red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_7 : red_lo0_even_7;
1980 red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_7 : red_lo1_even_7;
1981 red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_7 : red_hi0_even_7;
1982 red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_7 : red_hi1_even_7;
1983 redrow_rd_spare_0 <= (set_c4[0]) ? redrow_way7_spare_odd_0 : redrow_way7_spare_even_0;
1984 redrow_rd_spare_1 <= (set_c4[0]) ? redrow_way7_spare_odd_1 : redrow_way7_spare_even_1;
1985 end
1986end
1987end
1988
1989always@(negedge l1clk)
1990begin
1991 red_lo0_out_bc_d_l <= ~red_lo0_out_bc;
1992 red_hi0_out_bc_d_l <= ~red_hi0_out_bc;
1993 red_lo1_out_bc_d_l <= ~red_lo1_out_bc;
1994 red_hi1_out_bc_d_l <= ~red_hi1_out_bc;
1995 redrow_rd_spare_0_d_l <= ~redrow_rd_spare_0;
1996 redrow_rd_spare_1_d_l <= ~redrow_rd_spare_1;
1997end
1998
1999always@(posedge l1clk)
2000begin
2001 red_lo0_bc_c5b_l <= red_lo0_out_bc_d_l;
2002 red_hi0_bc_c5b_l <= red_hi0_out_bc_d_l;
2003 red_lo1_bc_c5b_l <= red_lo1_out_bc_d_l;
2004 red_hi1_bc_c5b_l <= red_hi1_out_bc_d_l;
2005 redrow_rdd_spare_0 <= redrow_rd_spare_0_d_l;
2006 redrow_rdd_spare_1 <= redrow_rd_spare_1_d_l;
2007end
2008
2009assign red_rd_data[19:0] =
2010 {redrow_rdd_spare_0, red_lo1_bc_c5b_l[4], red_hi0_bc_c5b_l[4],red_lo0_bc_c5b_l[4],
2011 red_hi1_bc_c5b_l[3], red_lo1_bc_c5b_l[3], red_hi0_bc_c5b_l[3],red_lo0_bc_c5b_l[3],
2012 red_hi1_bc_c5b_l[2], red_lo1_bc_c5b_l[2], red_hi0_bc_c5b_l[2],red_lo0_bc_c5b_l[2],
2013 red_hi1_bc_c5b_l[1], red_lo1_bc_c5b_l[1], red_hi0_bc_c5b_l[1],red_lo0_bc_c5b_l[1],
2014 red_hi1_bc_c5b_l[0], red_lo1_bc_c5b_l[0], red_hi0_bc_c5b_l[0],red_lo0_bc_c5b_l[0]};
2015
2016 assign red_rd_data[39:20] = {
2017 red_lo1_bc_c5b_l[9], red_hi0_bc_c5b_l[9],red_lo0_bc_c5b_l[9],
2018 red_hi1_bc_c5b_l[8], red_lo1_bc_c5b_l[8], red_hi0_bc_c5b_l[8],red_lo0_bc_c5b_l[8],
2019 red_hi1_bc_c5b_l[7], red_lo1_bc_c5b_l[7], red_hi0_bc_c5b_l[7],red_lo0_bc_c5b_l[7],
2020 red_hi1_bc_c5b_l[6], red_lo1_bc_c5b_l[6], red_hi0_bc_c5b_l[6],red_lo0_bc_c5b_l[6],
2021 red_hi1_bc_c5b_l[5], red_lo1_bc_c5b_l[5], red_hi0_bc_c5b_l[5],red_lo0_bc_c5b_l[5], red_hi1_bc_c5b_l[4]};
2022
2023
2024 assign red_rd_data[59:40] = {
2025 red_lo1_bc_c5b_l[14], red_hi0_bc_c5b_l[14],red_lo0_bc_c5b_l[14],
2026 red_hi1_bc_c5b_l[13], red_lo1_bc_c5b_l[13], red_hi0_bc_c5b_l[13],red_lo0_bc_c5b_l[13],
2027 red_hi1_bc_c5b_l[12], red_lo1_bc_c5b_l[12], red_hi0_bc_c5b_l[12],red_lo0_bc_c5b_l[12],
2028 red_hi1_bc_c5b_l[11], red_lo1_bc_c5b_l[11], red_hi0_bc_c5b_l[11],red_lo0_bc_c5b_l[11],
2029 red_hi1_bc_c5b_l[10], red_lo1_bc_c5b_l[10], red_hi0_bc_c5b_l[10],red_lo0_bc_c5b_l[10], red_hi1_bc_c5b_l[9]};
2030
2031 assign red_rd_data[79:60] = {
2032 red_hi0_bc_c5b_l[19], red_lo0_bc_c5b_l[19],
2033 red_hi1_bc_c5b_l[18], red_lo1_bc_c5b_l[18], red_hi0_bc_c5b_l[18],red_lo0_bc_c5b_l[18],
2034 red_hi1_bc_c5b_l[17], red_lo1_bc_c5b_l[17], red_hi0_bc_c5b_l[17],red_lo0_bc_c5b_l[17],
2035 red_hi1_bc_c5b_l[16], red_lo1_bc_c5b_l[16], red_hi0_bc_c5b_l[16],red_lo0_bc_c5b_l[16],
2036 red_hi1_bc_c5b_l[15], red_lo1_bc_c5b_l[15], red_hi0_bc_c5b_l[15],red_lo0_bc_c5b_l[15], red_hi1_bc_c5b_l[14],redrow_rdd_spare_1};
2037
2038
2039 always@(cred_mod or red_rd_data)
2040 begin
2041
2042 for(i=0;i<19;i=i+1)
2043 begin
2044 red_read_data[i] = cred_mod[i] ? red_rd_data[i+1] : red_rd_data[i];
2045 end
2046
2047 for(i=20;i<40;i=i+1)
2048 begin
2049 red_read_data[i] = cred_mod[i] ? red_rd_data[i-1] : red_rd_data[i];
2050 end
2051
2052
2053 for(i=40;i<60;i=i+1)
2054 begin
2055 red_read_data[i] = cred_mod[i] ? red_rd_data[i+1] : red_rd_data[i];
2056 end
2057
2058 for(i=61;i<80;i=i+1)
2059 begin
2060 red_read_data[i] = cred_mod[i] ? red_rd_data[i-1] : red_rd_data[i];
2061 end
2062
2063 end
2064
2065
2066
2067 assign { red_hi0_b_out_l[19], red_lo0_b_out_l[19],
2068 red_hi1_b_out_l[18], red_lo1_b_out_l[18], red_hi0_b_out_l[18],red_lo0_b_out_l[18],
2069 red_hi1_b_out_l[17], red_lo1_b_out_l[17], red_hi0_b_out_l[17],red_lo0_b_out_l[17],
2070 red_hi1_b_out_l[16], red_lo1_b_out_l[16], red_hi0_b_out_l[16],red_lo0_b_out_l[16],
2071 red_hi1_b_out_l[15], red_lo1_b_out_l[15], red_hi0_b_out_l[15],red_lo0_b_out_l[15],
2072 red_hi1_b_out_l[14]} = red_read_data[79:61];
2073
2074 assign {red_lo1_b_out_l[14], red_hi0_b_out_l[14],red_lo0_b_out_l[14],
2075 red_hi1_b_out_l[13], red_lo1_b_out_l[13], red_hi0_b_out_l[13],red_lo0_b_out_l[13],
2076 red_hi1_b_out_l[12], red_lo1_b_out_l[12], red_hi0_b_out_l[12],red_lo0_b_out_l[12],
2077 red_hi1_b_out_l[11], red_lo1_b_out_l[11], red_hi0_b_out_l[11],red_lo0_b_out_l[11],
2078 red_hi1_b_out_l[10], red_lo1_b_out_l[10], red_hi0_b_out_l[10],red_lo0_b_out_l[10],
2079 red_hi1_b_out_l[9]} = red_read_data[59:40];
2080
2081 assign { red_lo1_b_out_l[9], red_hi0_b_out_l[9],red_lo0_b_out_l[9],
2082 red_hi1_b_out_l[8], red_lo1_b_out_l[8], red_hi0_b_out_l[8],red_lo0_b_out_l[8],
2083 red_hi1_b_out_l[7], red_lo1_b_out_l[7], red_hi0_b_out_l[7],red_lo0_b_out_l[7],
2084 red_hi1_b_out_l[6], red_lo1_b_out_l[6], red_hi0_b_out_l[6],red_lo0_b_out_l[6],
2085 red_hi1_b_out_l[5], red_lo1_b_out_l[5], red_hi0_b_out_l[5],red_lo0_b_out_l[5],
2086 red_hi1_b_out_l[4]} = red_read_data[39:20];
2087
2088 assign {red_lo1_b_out_l[4], red_hi0_b_out_l[4],red_lo0_b_out_l[4],
2089 red_hi1_b_out_l[3], red_lo1_b_out_l[3], red_hi0_b_out_l[3],red_lo0_b_out_l[3],
2090 red_hi1_b_out_l[2], red_lo1_b_out_l[2], red_hi0_b_out_l[2],red_lo0_b_out_l[2],
2091 red_hi1_b_out_l[1], red_lo1_b_out_l[1], red_hi0_b_out_l[1],red_lo0_b_out_l[1],
2092 red_hi1_b_out_l[0], red_lo1_b_out_l[0], red_hi0_b_out_l[0],red_lo0_b_out_l[0]} = red_read_data[18:0];
2093
2094
2095//////////////////////////////////////////////////////////////////////////////
2096// col redudancy
2097// hi1, lo1, hi0, lo0
2098
2099//assign cred_mod_lo0[18:0] = cred_mod[18:0];
2100//assign cred_mod_hi0[38:19] = cred_mod[38:19];
2101//assign cred_mod_lo1[58:39] = cred_mod[58:39];
2102//assign cred_mod_hi1[77:59] = cred_mod[77:59];
2103
2104// mux 0+1
2105// mux 19 spare
2106// mux 18 and spare
2107// mux 38 and 37
2108// mux 77
2109
2110
2111
2112
2113endmodule
2114
2115
2116module n2_l2d_dmux78_cust (
2117 waysel_c3,
2118 set_c3,
2119 coloff_c3,
2120 coloff_c4_l,
2121 rd_wr_c3,
2122 worden_c3,
2123 l2clk,
2124 tcu_pce_ov,
2125 tcu_pce,
2126 se,
2127 tcu_clk_stop,
2128 waysel_top_c4,
2129 waysel_bot_c4,
2130 set_top_c3b,
2131 set_bot_c3b,
2132 coloff_top_c3b_l,
2133 coloff_bot_c3b_l,
2134 writeen_top_c3b,
2135 writeen_bot_c3b,
2136 l1clk,
2137 worden_top_c3b,
2138 worden_bot_c3b,
2139 sat_lo0_bc_l,
2140 sat_hi0_bc_l,
2141 sat_lo1_bc_l,
2142 sat_hi1_bc_l,
2143 sab_lo0_bc_l,
2144 sab_hi0_bc_l,
2145 sab_lo1_bc_l,
2146 sab_hi1_bc_l,
2147 ldin0lo_b,
2148 ldin0hi_b,
2149 ldin1lo_b,
2150 ldin1hi_b,
2151 ldout0lo_b,
2152 ldout0hi_b,
2153 ldout1lo_b,
2154 ldout1hi_b,
2155 red_d_in_00,
2156 red_d_out_00,
2157 fuse_l2d_rid_00,
2158 fuse_l2d_wren_00,
2159 fuse_l2d_reset_00_l,
2160 sel_quad_00,
2161 red_d_in_01,
2162 red_d_out_01,
2163 fuse_l2d_rid_01,
2164 fuse_l2d_wren_01,
2165 fuse_l2d_reset_01_l,
2166 sel_quad_01,
2167 red_addr_top,
2168 red_addr_bot,
2169 red_top_d_00,
2170 red_top_d_01,
2171 cred);
2172
2173input [7:0] waysel_c3;
2174input [8:0] set_c3;
2175input coloff_c3;
2176input coloff_c4_l;
2177//input [1:0] coloff_c5;
2178input rd_wr_c3;
2179//input readen_c5;
2180input [3:0] worden_c3;
2181input l2clk;
2182input tcu_pce_ov;
2183input tcu_pce;
2184input se;
2185input tcu_clk_stop;
2186
2187output [7:0] waysel_top_c4;
2188output [7:0] waysel_bot_c4;
2189output [8:0] set_top_c3b; // Set 8 will be inverted for top/bot
2190output [8:0] set_bot_c3b; // Set 8 will be inverted for top/bot
2191output coloff_top_c3b_l;
2192output coloff_bot_c3b_l;
2193//output coloff_top_c4_l ;
2194//output coloff_bot_c4_l;
2195//output [1:0] coloff_top_c5;
2196//output [1:0] coloff_bot_c5;
2197output writeen_top_c3b;
2198output writeen_bot_c3b;
2199//output readen_top_c5;
2200//output readen_bot_c5;
2201output l1clk;
2202output [3:0] worden_top_c3b;
2203output [3:0] worden_bot_c3b;
2204
2205
2206input [19:0] sat_lo0_bc_l; // Senseamp out from top-16kb
2207input [19:0] sat_hi0_bc_l; // Senseamp out from top-16kb
2208input [18:0] sat_lo1_bc_l; // Senseamp out from top-16kb
2209input [18:0] sat_hi1_bc_l; // Senseamp out from top-16kb
2210input [19:0] sab_lo0_bc_l; // Senseamp out from bot-16kb
2211input [19:0] sab_hi0_bc_l; // Senseamp out from bot-16kb
2212input [18:0] sab_lo1_bc_l; // Senseamp out from bot-16kb
2213input [18:0] sab_hi1_bc_l; // Senseamp out from bot-16kb
2214input [19:0] ldin0lo_b;
2215input [19:0] ldin0hi_b;
2216input [18:0] ldin1lo_b;
2217input [18:0] ldin1hi_b;
2218//input bnken_lat; // Address latch enable (1.5cycle)
2219output [19:0] ldout0lo_b;
2220output [19:0] ldout0hi_b;
2221output [18:0] ldout1lo_b;
2222output [18:0] ldout1hi_b;
2223
2224
2225input [9:0] red_d_in_00;
2226output [9:0] red_d_out_00;
2227input [2:0] fuse_l2d_rid_00;
2228input fuse_l2d_wren_00;
2229input fuse_l2d_reset_00_l;
2230input sel_quad_00;
2231
2232input [9:0] red_d_in_01;
2233output [9:0] red_d_out_01;
2234input [2:0] fuse_l2d_rid_01;
2235input fuse_l2d_wren_01;
2236input fuse_l2d_reset_01_l;
2237input sel_quad_01;
2238
2239output [9:0] red_addr_top;
2240output [9:0] red_addr_bot;
2241// forwarded
2242input [9:0] red_top_d_00;
2243input [9:0] red_top_d_01;
2244
2245output [77:0] cred;
2246//output fuse_l2d_reset_00_l_buf;
2247//output fuse_l2d_reset_01_l_buf;
2248
2249reg [7:0] waysel_top_c4;
2250reg [7:0] waysel_bot_c4;
2251reg [8:0] set_top_c3b;
2252reg [8:0] set_bot_c3b;
2253reg writeen_top_c3b;
2254reg writeen_bot_c3b;
2255reg [3:0] worden_top_c3b;
2256reg [3:0] worden_bot_c3b;
2257reg coloff_top_c3b_l;
2258reg coloff_bot_c3b_l;
2259reg [7:0] waysel_top_c3b;
2260reg [7:0] waysel_bot_c3b;
2261//always@(posedge l2clk)
2262always@(negedge l2clk)
2263begin
2264 coloff_top_c3b_l <= ~coloff_c3;
2265 coloff_bot_c3b_l <= ~coloff_c3;
2266 worden_top_c3b[3:0] <= worden_c3[3:0];
2267 worden_bot_c3b[3:0] <= worden_c3[3:0];
2268 writeen_top_c3b <= ~rd_wr_c3;
2269 writeen_bot_c3b <= ~rd_wr_c3;
2270end
2271
2272//always@(negedge l2clk)
2273//always@(l2clk or bnken_lat)
2274always@(l2clk or coloff_c4_l)
2275begin
2276// if(~bnken_lat)
2277 if(~l2clk & coloff_c4_l)
2278 begin
2279 waysel_top_c3b[7:0] <= waysel_c3[7:0];
2280 waysel_bot_c3b[7:0] <= waysel_c3[7:0];
2281 set_bot_c3b[8:0] <= set_c3[8:0];
2282 set_top_c3b[8:0] <= {~set_c3[8],set_c3[7:0]};
2283
2284 end
2285end
2286
2287always@(posedge l2clk )
2288begin
2289waysel_top_c4[7:0] <= waysel_top_c3b[7:0];
2290waysel_bot_c4[7:0] <= waysel_bot_c3b[7:0];
2291end
2292//assign readen_top_c5 = readen_c5;
2293//assign readen_bot_c5 = readen_c5;
2294//assign coloff_top_c5 = coloff_c5[1:0];
2295//assign coloff_bot_c5 = coloff_c5[1:0];
2296//assign coloff_top_c4_l = coloff_c4_l;
2297//assign coloff_bot_c4_l = coloff_c4_l;
2298
2299
2300wire [19:0] sat_lo0_bc;
2301wire [19:0] sab_lo0_bc;
2302wire [19:0] sat_hi0_bc;
2303wire [19:0] sab_hi0_bc;
2304
2305wire [18:0] sat_lo1_bc;
2306wire [18:0] sab_lo1_bc;
2307wire [18:0] sat_hi1_bc;
2308wire [18:0] sab_hi1_bc;
2309
2310
2311//always@(posedge l1clk)
2312//begin
2313assign sat_lo0_bc[19:0] = ~sat_lo0_bc_l[19:0];
2314assign sab_lo0_bc[19:0] = ~sab_lo0_bc_l[19:0];
2315assign sat_hi0_bc[19:0] = ~sat_hi0_bc_l[19:0];
2316assign sab_hi0_bc[19:0] = ~sab_hi0_bc_l[19:0];
2317
2318assign sat_lo1_bc[18:0] = ~sat_lo1_bc_l[18:0];
2319assign sab_lo1_bc[18:0] = ~sab_lo1_bc_l[18:0];
2320assign sat_hi1_bc[18:0] = ~sat_hi1_bc_l[18:0];
2321assign sab_hi1_bc[18:0] = ~sab_hi1_bc_l[18:0];
2322//end
2323
2324
2325
2326n2_l2d_quad_cust_or_macro__ports_3__width_20 or_ldout0lo_b
2327 (
2328 .dout (ldout0lo_b[19:0]),
2329 .din0 (sat_lo0_bc[19:0]),
2330 .din1 (sab_lo0_bc[19:0]),
2331 .din2 (ldin0lo_b[19:0])
2332 );
2333
2334n2_l2d_quad_cust_or_macro__ports_3__width_20 or_ldout0hi_b
2335 (
2336 .dout (ldout0hi_b[19:0]),
2337 .din0 (sat_hi0_bc[19:0]),
2338 .din1 (sab_hi0_bc[19:0]),
2339 .din2 (ldin0hi_b[19:0])
2340 );
2341
2342n2_l2d_quad_cust_or_macro__ports_3__width_19 or_ldout1lo_b
2343 (
2344 .dout (ldout1lo_b[18:0]),
2345 .din0 (sat_lo1_bc[18:0]),
2346 .din1 (sab_lo1_bc[18:0]),
2347 .din2 (ldin1lo_b[18:0])
2348 );
2349
2350
2351n2_l2d_quad_cust_or_macro__ports_3__width_19 or_ldout1hi_b
2352 (
2353 .dout (ldout1hi_b[18:0]),
2354 .din0 (sat_hi1_bc[18:0]),
2355 .din1 (sab_hi1_bc[18:0]),
2356 .din2 (ldin1hi_b[18:0])
2357 );
2358
2359
2360cl_sc1_l1hdr_12x clk_hdr (
2361 .l2clk (l2clk),
2362 .se (se),
2363 .pce (tcu_pce),
2364 .pce_ov (tcu_pce_ov),
2365 .stop (tcu_clk_stop),
2366 .l1clk (l1clk)
2367 );
2368
2369
2370// Redudant row modelling
2371
2372
2373
2374reg [9:0] red_odd_0;
2375reg [9:0] red_odd_1;
2376reg [9:0] red_even_0;
2377reg [9:0] red_even_1;
2378reg [7:0] red_col_0;
2379reg [7:0] red_col_1;
2380//reg [9:0] red_d_out_00;
2381//reg [9:0] red_d_out_01;
2382
2383wire red_reg_clk_even_0;
2384wire red_reg_clk_even_1;
2385wire red_reg_clk_odd_0;
2386wire red_reg_clk_odd_1;
2387wire red_reg_clk_col_0;
2388wire red_reg_clk_col_1;
2389wire [9:0] red_data_00;
2390wire [9:0] red_data_01;
2391
2392// Initialize the register.
2393initial begin
2394
2395 red_odd_0[9:0] = 10'b0;
2396 red_odd_1[9:0] = 10'b0;
2397 red_even_0[9:0]= 10'b0;
2398 red_even_1[9:0]= 10'b0;
2399 red_col_0[7:0] = 8'b0;
2400 red_col_1[7:0] = 8'b0;
2401end
2402
2403assign red_reg_clk_even_0 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b000) & sel_quad_00) | ~fuse_l2d_reset_00_l);
2404assign red_reg_clk_even_1 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b010) & sel_quad_00) | ~fuse_l2d_reset_00_l);
2405assign red_reg_clk_col_0 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b100) & sel_quad_00) | ~fuse_l2d_reset_00_l);
2406
2407assign red_reg_clk_odd_0 =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b001) & sel_quad_01) | ~fuse_l2d_reset_01_l);
2408assign red_reg_clk_odd_1 =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b011) & sel_quad_01) | ~fuse_l2d_reset_01_l);
2409assign red_reg_clk_col_1 =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b101) & sel_quad_01) | ~fuse_l2d_reset_01_l);
2410
2411assign red_data_00[9:0] = red_d_in_00[9:0] & {10{fuse_l2d_reset_00_l}};
2412assign red_data_01[9:0] = red_d_in_01[9:0] & {10{fuse_l2d_reset_01_l}};
2413
2414always @(red_reg_clk_even_0 or red_reg_clk_even_1 or red_reg_clk_col_0 or red_reg_clk_odd_0 or red_reg_clk_odd_1 or red_reg_clk_col_1 or red_d_in_00 or red_d_in_01) begin
2415 if (~red_reg_clk_even_0) begin
2416 red_even_0[9:0] <= red_data_00[9:0];
2417 end
2418
2419 if (~red_reg_clk_even_1) begin
2420 red_even_1[9:0] <= red_data_00[9:0];
2421 end
2422
2423 if (~red_reg_clk_col_0) begin
2424 red_col_0[7:0] <= {red_data_00[9:8],red_data_00[5:0]};
2425 end
2426
2427 if (~red_reg_clk_odd_0) begin
2428 red_odd_0[9:0] <= red_data_01[9:0];
2429 end
2430
2431 if (~red_reg_clk_odd_1) begin
2432 red_odd_1[9:0] <= red_data_01[9:0];
2433 end
2434
2435 if (~red_reg_clk_col_1) begin
2436 red_col_1[7:0] <= {red_data_01[9:8],red_data_01[5:0]};
2437 end
2438end
2439
2440
2441// 00 = bot and 01 = top
2442
2443//always@(fuse_l2d_wren_00 or fuse_l2d_wren_01 or fuse_l2d_rid_01 or fuse_l2d_rid_00
2444// or red_d_in_00 or red_d_in_01 or sel_quad_00 or sel_quad_01)
2445//begin
2446// if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & set_bot_c3b[8] & (fuse_l2d_rid_00[2:1]==2'b00) & sel_quad_00)
2447// red_even_0 <= red_d_in_00;
2448// else if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & set_top_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b01) & sel_quad_00)
2449// red_even_1 <= red_d_in_00;
2450// else if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & (fuse_l2d_rid_01[2:1]==2'b10) & sel_quad_00)
2451// red_col_0 <= red_d_in_00[7:0];
2452//
2453// if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & set_top_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b00) & sel_quad_01)
2454// red_odd_0 <= red_d_in_01;
2455// else if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & set_bot_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b01) & sel_quad_01)
2456// red_odd_1 <= red_d_in_01;
2457// else if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & (fuse_l2d_rid_01[2:1]==2'b10) & sel_quad_01)
2458// red_col_1 <= red_d_in_01[7:0];
2459//end
2460//
2461
2462//assign red_addr_top = set_top_c3b[0] ? red_odd_0 : red_even_0;
2463//assign red_addr_bot = set_top_c3b[0] ? red_odd_1 : red_even_1;
2464assign red_addr_top = set_top_c3b[0] ? red_odd_1 : red_even_1;
2465assign red_addr_bot = set_top_c3b[0] ? red_odd_0 : red_even_0;
2466
2467assign red_d_out_00[7:0] = (red_even_0[7:0] & {8{fuse_l2d_rid_00[2:0]==3'b000}}) |
2468 (red_even_1[7:0] & {8{fuse_l2d_rid_00[2:0]==3'b010}}) |
2469 ({2'b0,(red_col_0[5:0] & {6{fuse_l2d_rid_00[2:0]==3'b100}})}) |
2470 (red_top_d_00[7:0] & {8{~sel_quad_00}});
2471
2472assign red_d_out_00[9:8] = (red_even_0[9:8] & {2{fuse_l2d_rid_00[2:0]==3'b000}}) |
2473 (red_even_1[9:8] & {2{fuse_l2d_rid_00[2:0]==3'b010}}) |
2474 (red_col_0[7:6] & {2{fuse_l2d_rid_00[2:0]==3'b100}}) |
2475 (red_top_d_00[9:8] & {2{~sel_quad_00}});
2476
2477
2478
2479
2480assign red_d_out_01[7:0] = (red_odd_0[7:0] & {8{fuse_l2d_rid_01[2:0]==3'b001}}) |
2481 (red_odd_1[7:0] & {8{fuse_l2d_rid_01[2:0]==3'b011}}) |
2482 ({2'b0,(red_col_1[5:0] & {6{fuse_l2d_rid_01[2:0]==3'b101}})}) |
2483 (red_top_d_01[7:0] & {8{~sel_quad_01}});
2484
2485assign red_d_out_01[9:8] = (red_odd_0[9:8] & {2{fuse_l2d_rid_01[2:0]==3'b001}}) |
2486 (red_odd_1[9:8] & {2{fuse_l2d_rid_01[2:0]==3'b011}}) |
2487 (red_col_1[7:6] & {2{fuse_l2d_rid_01[2:0]==3'b101}}) |
2488 (red_top_d_01[9:8] & {2{~sel_quad_01}});
2489
2490
2491
2492//always@(fuse_l2d_rid_00)
2493//begin
2494//case(fuse_l2d_rid_00)
2495//3'b000 : begin
2496// red_d_out_00 = red_even_0;
2497// red_d_out_01 = 10'b0;
2498// end
2499//3'b010 : begin
2500// red_d_out_00 = red_even_1;
2501// red_d_out_01 = 10'b0;
2502// end
2503//3'b100 : begin
2504// red_d_out_00 = {2'b0,red_col_0};
2505// red_d_out_01 = 10'b0;
2506// end
2507//
2508//3'b001 : begin
2509// red_d_out_01 = red_odd_0;
2510// red_d_out_00 = 10'b0;
2511// end
2512//3'b011 : begin
2513// red_d_out_01 = red_odd_1;
2514// red_d_out_00 = 10'b0;
2515// end
2516//3'b101 : begin
2517// red_d_out_01 = {2'b0,red_col_1};
2518// red_d_out_00 = 10'b0;
2519// end
2520//
2521//default : begin
2522// red_d_out_00 = red_top_d_00;
2523// red_d_out_01 = red_top_d_01;
2524// end
2525//endcase
2526//end
2527
2528// Col redudancy
2529
2530//reg [7:0] red_col_0;
2531//reg [7:0] red_col_1;
2532
2533reg [38:0] cred0;
2534reg [38:0] cred1;
2535
2536// Initialize cred0, cred1
2537initial begin
2538 cred0[38:0] = 39'b0;
2539 cred1[38:0] = 39'b0;
2540end
2541
2542always@(red_col_0)
2543if(red_col_0[7] & red_col_0[6] & ~red_col_0[5])
2544case(red_col_0)
25458'b11_0_00000 : cred0[18:0] = 19'b111_1111_1111_1111_1111; //0
25468'b11_0_00001 : cred0[18:0] = 19'b111_1111_1111_1111_1110; //1
25478'b11_0_00010 : cred0[18:0] = 19'b111_1111_1111_1111_1100; //2
25488'b11_0_00011 : cred0[18:0] = 19'b111_1111_1111_1111_1000; //3
25498'b11_0_00100 : cred0[18:0] = 19'b111_1111_1111_1111_0000; //4
25508'b11_0_00101 : cred0[18:0] = 19'b111_1111_1111_1110_0000; //5
25518'b11_0_00110 : cred0[18:0] = 19'b111_1111_1111_1100_0000; //6
25528'b11_0_00111 : cred0[18:0] = 19'b111_1111_1111_1000_0000; //7
25538'b11_0_01000 : cred0[18:0] = 19'b111_1111_1111_0000_0000; //8
25548'b11_0_01001 : cred0[18:0] = 19'b111_1111_1110_0000_0000; //9
25558'b11_0_01010 : cred0[18:0] = 19'b111_1111_1100_0000_0000; //10
25568'b11_0_01011 : cred0[18:0] = 19'b111_1111_1000_0000_0000; //11
25578'b11_0_01100 : cred0[18:0] = 19'b111_1111_0000_0000_0000; //12
25588'b11_0_01101 : cred0[18:0] = 19'b111_1110_0000_0000_0000; //13
25598'b11_0_01110 : cred0[18:0] = 19'b111_1100_0000_0000_0000; //14
25608'b11_0_01111 : cred0[18:0] = 19'b111_1000_0000_0000_0000; //15
25618'b11_0_10000 : cred0[18:0] = 19'b111_0000_0000_0000_0000; //16
25628'b11_0_10001 : cred0[18:0] = 19'b110_0000_0000_0000_0000; //17
25638'b11_0_10010 : cred0[18:0] = 19'b100_0000_0000_0000_0000; //18
2564default : cred0[18:0] = 19'b0;
2565endcase
2566else cred0[18:0] = 19'b0;
2567
2568always@(red_col_0)
2569if(red_col_0[7] & red_col_0[6] & red_col_0[5])
2570case(red_col_0)
25718'b11_1_00000 : cred0[38:19] = 20'b1111_1111_1111_1111_1111;//0
25728'b11_1_00001 : cred0[38:19] = 20'b0111_1111_1111_1111_1111;//1
25738'b11_1_00010 : cred0[38:19] = 20'b0011_1111_1111_1111_1111;//2
25748'b11_1_00011 : cred0[38:19] = 20'b0001_1111_1111_1111_1111;//3
25758'b11_1_00100 : cred0[38:19] = 20'b0000_1111_1111_1111_1111;//4
25768'b11_1_00101 : cred0[38:19] = 20'b0000_0111_1111_1111_1111;//5
25778'b11_1_00110 : cred0[38:19] = 20'b0000_0011_1111_1111_1111;//6
25788'b11_1_00111 : cred0[38:19] = 20'b0000_0001_1111_1111_1111;//7
25798'b11_1_01000 : cred0[38:19] = 20'b0000_0000_1111_1111_1111;//8
25808'b11_1_01001 : cred0[38:19] = 20'b0000_0000_0111_1111_1111;//9
25818'b11_1_01010 : cred0[38:19] = 20'b0000_0000_0011_1111_1111;//10
25828'b11_1_01011 : cred0[38:19] = 20'b0000_0000_0001_1111_1111;//11
25838'b11_1_01100 : cred0[38:19] = 20'b0000_0000_0000_1111_1111;//12
25848'b11_1_01101 : cred0[38:19] = 20'b0000_0000_0000_0111_1111;//13
25858'b11_1_01110 : cred0[38:19] = 20'b0000_0000_0000_0011_1111;//14
25868'b11_1_01111 : cred0[38:19] = 20'b0000_0000_0000_0001_1111;//15
25878'b11_1_10000 : cred0[38:19] = 20'b0000_0000_0000_0000_1111;//16
25888'b11_1_10001 : cred0[38:19] = 20'b0000_0000_0000_0000_0111;//17
25898'b11_1_10010 : cred0[38:19] = 20'b0000_0000_0000_0000_0011;//18
25908'b11_1_10011 : cred0[38:19] = 20'b0000_0000_0000_0000_0001;//19
2591default : cred0[38:19] = 20'b0;
2592endcase
2593else cred0[38:19] = 20'b0;
2594
2595always@(red_col_1)
2596if(red_col_1[7] & red_col_1[6] & red_col_1[5])
2597case(red_col_1)
25988'b11_1_00000 : cred1[19:0] = 20'b1111_1111_1111_1111_1111; //0
25998'b11_1_00001 : cred1[19:0] = 20'b1111_1111_1111_1111_1110; //1
26008'b11_1_00010 : cred1[19:0] = 20'b1111_1111_1111_1111_1100; //2
26018'b11_1_00011 : cred1[19:0] = 20'b1111_1111_1111_1111_1000; //3
26028'b11_1_00100 : cred1[19:0] = 20'b1111_1111_1111_1111_0000; //4
26038'b11_1_00101 : cred1[19:0] = 20'b1111_1111_1111_1110_0000; //5
26048'b11_1_00110 : cred1[19:0] = 20'b1111_1111_1111_1100_0000; //6
26058'b11_1_00111 : cred1[19:0] = 20'b1111_1111_1111_1000_0000; //7
26068'b11_1_01000 : cred1[19:0] = 20'b1111_1111_1111_0000_0000; //8
26078'b11_1_01001 : cred1[19:0] = 20'b1111_1111_1110_0000_0000; //9
26088'b11_1_01010 : cred1[19:0] = 20'b1111_1111_1100_0000_0000; //10
26098'b11_1_01011 : cred1[19:0] = 20'b1111_1111_1000_0000_0000; //11
26108'b11_1_01100 : cred1[19:0] = 20'b1111_1111_0000_0000_0000; //12
26118'b11_1_01101 : cred1[19:0] = 20'b1111_1110_0000_0000_0000; //13
26128'b11_1_01110 : cred1[19:0] = 20'b1111_1100_0000_0000_0000; //14
26138'b11_1_01111 : cred1[19:0] = 20'b1111_1000_0000_0000_0000; //15
26148'b11_1_10000 : cred1[19:0] = 20'b1111_0000_0000_0000_0000; //16
26158'b11_1_10001 : cred1[19:0] = 20'b1110_0000_0000_0000_0000; //17
26168'b11_1_10010 : cred1[19:0] = 20'b1100_0000_0000_0000_0000; //18
26178'b11_1_10011 : cred1[19:0] = 20'b1000_0000_0000_0000_0000; //19
2618default : cred1[19:0] = 20'b0;
2619endcase
2620else cred1[19:0] = 20'b0;
2621
2622always@(red_col_1)
2623if(red_col_1[7] & red_col_1[6] & ~red_col_1[5])
2624case(red_col_1)
26258'b11_0_00000 : cred1[38:20] = 19'b111_1111_1111_1111_1111;//0
26268'b11_0_00001 : cred1[38:20] = 19'b011_1111_1111_1111_1111;//1
26278'b11_0_00010 : cred1[38:20] = 19'b001_1111_1111_1111_1111;//2
26288'b11_0_00011 : cred1[38:20] = 19'b000_1111_1111_1111_1111;//3
26298'b11_0_00100 : cred1[38:20] = 19'b000_0111_1111_1111_1111;//4
26308'b11_0_00101 : cred1[38:20] = 19'b000_0011_1111_1111_1111;//5
26318'b11_0_00110 : cred1[38:20] = 19'b000_0001_1111_1111_1111;//6
26328'b11_0_00111 : cred1[38:20] = 19'b000_0000_1111_1111_1111;//7
26338'b11_0_01000 : cred1[38:20] = 19'b000_0000_0111_1111_1111;//8
26348'b11_0_01001 : cred1[38:20] = 19'b000_0000_0011_1111_1111;//9
26358'b11_0_01010 : cred1[38:20] = 19'b000_0000_0001_1111_1111;//10
26368'b11_0_01011 : cred1[38:20] = 19'b000_0000_0000_1111_1111;//11
26378'b11_0_01100 : cred1[38:20] = 19'b000_0000_0000_0111_1111;//12
26388'b11_0_01101 : cred1[38:20] = 19'b000_0000_0000_0011_1111;//13
26398'b11_0_01110 : cred1[38:20] = 19'b000_0000_0000_0001_1111;//14
26408'b11_0_01111 : cred1[38:20] = 19'b000_0000_0000_0000_1111;//15
26418'b11_0_10000 : cred1[38:20] = 19'b000_0000_0000_0000_0111;//16
26428'b11_0_10001 : cred1[38:20] = 19'b000_0000_0000_0000_0011;//17
26438'b11_0_10010 : cred1[38:20] = 19'b000_0000_0000_0000_0001;//18
2644default : cred1[38:20] = 19'b0;
2645endcase
2646else cred1[38:20] = 19'b0;
2647
2648assign cred[77:0] = {cred1[38:0], cred0[38:0]};
2649//assign cred[77:0] = 78'b0;
2650
2651
2652//assign fuse_l2d_reset_00_buf = fuse_l2d_reset_00;
2653//assign fuse_l2d_reset_01_buf = fuse_l2d_reset_01;
2654
2655
2656
2657
2658endmodule
2659
2660
2661//
2662// or macro for ports = 2,3
2663//
2664//
2665
2666
2667
2668
2669
2670module n2_l2d_quad_cust_or_macro__ports_3__width_20 (
2671 din0,
2672 din1,
2673 din2,
2674 dout);
2675 input [19:0] din0;
2676 input [19:0] din1;
2677 input [19:0] din2;
2678 output [19:0] dout;
2679
2680
2681
2682
2683
2684
2685or3 #(20) d0_0 (
2686.in0(din0[19:0]),
2687.in1(din1[19:0]),
2688.in2(din2[19:0]),
2689.out(dout[19:0])
2690);
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700endmodule
2701
2702
2703
2704
2705
2706//
2707// or macro for ports = 2,3
2708//
2709//
2710
2711
2712
2713
2714
2715module n2_l2d_quad_cust_or_macro__ports_3__width_19 (
2716 din0,
2717 din1,
2718 din2,
2719 dout);
2720 input [18:0] din0;
2721 input [18:0] din1;
2722 input [18:0] din2;
2723 output [18:0] dout;
2724
2725
2726
2727
2728
2729
2730or3 #(19) d0_0 (
2731.in0(din0[18:0]),
2732.in1(din1[18:0]),
2733.in2(din2[18:0]),
2734.out(dout[18:0])
2735);
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745endmodule
2746
2747
2748
2749
Full OpenSPARC design & verification tarball including full HDL.