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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_l2d_tstmod_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module n2_l2d_tstmod_cust ( | |
36 | rd_wr_c3, | |
37 | wayerr_c3, | |
38 | wr_inhibit, | |
39 | coloff_c3, | |
40 | l2clk, | |
41 | scanen, | |
42 | si, | |
43 | siclk, | |
44 | soclk, | |
45 | so, | |
46 | delout20_rgt, | |
47 | delout31_lft, | |
48 | delout31_rgt, | |
49 | delout20_lft) ; | |
50 | wire not_wayerr_c3; | |
51 | wire coloff_c3_1_3; | |
52 | wire coloff_c3_2_0; | |
53 | wire [1:0] msff_read_c4_scanin; | |
54 | wire [1:0] msff_read_c4_scanout; | |
55 | wire msff_buf_out_top_scanin; | |
56 | wire msff_buf_out_top_scanout; | |
57 | wire msff_buf_out_bot_scanin; | |
58 | wire msff_buf_out_bot_scanout; | |
59 | wire [2:0] msff_buf_out_corse_scanin; | |
60 | wire [2:0] msff_buf_out_corse_scanout; | |
61 | wire [2:0] msff_buf_out_fine_scanin; | |
62 | wire [2:0] msff_buf_out_fine_scanout; | |
63 | wire wr_inhibit_n; | |
64 | wire [2:0] ff_buf_out_corse_n; | |
65 | wire [2:0] ff_buf_out_fine_n; | |
66 | ||
67 | //----------------------------------------------------------- | |
68 | // I/O declarations | |
69 | //----------------------------------------------------------- | |
70 | input rd_wr_c3; // | |
71 | input wayerr_c3; // added 9/21/2005 | |
72 | input wr_inhibit; // | |
73 | // coloff_c3<3:0>, | |
74 | input [3:0] coloff_c3; // | |
75 | input l2clk; // | |
76 | input scanen; // | |
77 | input si; // | |
78 | input siclk; // | |
79 | input soclk; // | |
80 | ||
81 | output so; // | |
82 | output delout20_rgt; // | |
83 | output delout31_lft; // | |
84 | output delout31_rgt; // | |
85 | output delout20_lft; // | |
86 | ||
87 | ||
88 | //----------------------------------------------------------------------------- | |
89 | // Wire/reg declarations | |
90 | //----------------------------------------------------------------------------- | |
91 | ||
92 | // connecting between n2_l2d_tstmod_logic & n2_l2d_tstmod_delay_cust | |
93 | wire l1clk; | |
94 | wire tst_bnken31_setb; | |
95 | wire tst_bnken02_setb; | |
96 | wire tst_bnken31_rstb; | |
97 | wire tst_bnken02_rstb; | |
98 | wire tst_bnken31_rstb_n; | |
99 | wire tst_bnken02_rstb_n; | |
100 | //wire so_internal; | |
101 | wire tstmod_rst_l; | |
102 | wire [5:0] corse_sel; | |
103 | wire [7:0] fine_sel; | |
104 | ||
105 | ||
106 | wire [1:0] tst_read_c3a; | |
107 | //wire [1:0] tst_read_c3b; | |
108 | //wire [3:0] tst_read_c4; | |
109 | //wire [3:0] tst_so; | |
110 | wire [1:0] tst_so; | |
111 | wire [2:0] tst_so_corse; | |
112 | wire [2:0] tst_so_fine; | |
113 | wire tst_so_en0; | |
114 | ||
115 | wire ff_buf_out_top; | |
116 | wire [2:0] ff_buf_out_corse; | |
117 | wire [2:0] ff_buf_out_fine; | |
118 | wire ff_buf_out_bot; | |
119 | ||
120 | ||
121 | // start n2_l2d_tstmod_logic | |
122 | ||
123 | ||
124 | n2_l2d_tstmod_cust_l1clkhdr_ctl_macro l1_clk_hdr ( | |
125 | .l2clk (l2clk), | |
126 | .se (scanen), | |
127 | .l1en (1'b1), | |
128 | .pce_ov (1'b1), | |
129 | .stop (1'b0), | |
130 | .l1clk (l1clk) | |
131 | ); | |
132 | ||
133 | ||
134 | ||
135 | //assign tst_read_c3a[1] = (~wayerr_c3 & rd_wr_c3 & (coloff_c3[3] | coloff_c3[1])); | |
136 | //assign tst_read_c3a[0] = (~wayerr_c3 & rd_wr_c3 & (coloff_c3[2] | coloff_c3[0])); | |
137 | ||
138 | ||
139 | n2_l2d_tstmod_cust_inv_macro__width_1 inv_wayerr_c3 | |
140 | ( | |
141 | .dout (not_wayerr_c3), | |
142 | .din (wayerr_c3) | |
143 | ); | |
144 | ||
145 | n2_l2d_tstmod_cust_or_macro__width_1 or_coloff_c3_1_3 | |
146 | ( | |
147 | .din0 (coloff_c3[1]), | |
148 | .din1 (coloff_c3[3]), | |
149 | .dout (coloff_c3_1_3) | |
150 | ); | |
151 | ||
152 | ||
153 | n2_l2d_tstmod_cust_or_macro__width_1 or_coloff_c3_2_3 | |
154 | ( | |
155 | .din0 (coloff_c3[2]), | |
156 | .din1 (coloff_c3[0]), | |
157 | .dout (coloff_c3_2_0) | |
158 | ); | |
159 | ||
160 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_tst_read_c3a_1 | |
161 | ( | |
162 | .dout (tst_read_c3a[1]), | |
163 | .din0 (not_wayerr_c3), | |
164 | .din1 (coloff_c3_1_3), | |
165 | .din2 (rd_wr_c3) | |
166 | ); | |
167 | ||
168 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_tst_read_c3a_0 | |
169 | ( | |
170 | .dout (tst_read_c3a[0]), | |
171 | .din0 (not_wayerr_c3), | |
172 | .din1 (coloff_c3_2_0), | |
173 | .din2 (rd_wr_c3) | |
174 | ); | |
175 | ||
176 | n2_l2d_tstmod_cust_tisram_blb_macro__dmsff_4x__width_1 blb_read_c3_1 | |
177 | ( | |
178 | .l1clk (l1clk), | |
179 | .d_a (tst_read_c3a[1]), | |
180 | .q_b (tst_bnken31_setb) | |
181 | ); | |
182 | n2_l2d_tstmod_cust_tisram_blb_macro__dmsff_4x__width_1 blb_read_c3_0 | |
183 | ( | |
184 | .l1clk (l1clk), | |
185 | .d_a (tst_read_c3a[0]), | |
186 | .q_b (tst_bnken02_setb) | |
187 | ); | |
188 | ||
189 | //initialize | |
190 | //assign tst_read_c4[3:0] = 4'b0; | |
191 | ||
192 | n2_l2d_tstmod_cust_msff_ctl_macro__fs_1__width_2 msff_read_c4 | |
193 | ( | |
194 | .scan_in (msff_read_c4_scanin[1:0]), | |
195 | .scan_out (msff_read_c4_scanout[1:0]), | |
196 | .din ( tst_read_c3a[1:0] & {~tst_bnken31_rstb_n,~tst_bnken02_rstb_n} ), | |
197 | .l1clk ( l1clk ), | |
198 | .dout ( {tst_bnken31_rstb_n,tst_bnken02_rstb_n} ), | |
199 | .siclk(siclk), | |
200 | .soclk(soclk) | |
201 | ); | |
202 | ||
203 | ||
204 | //assign tst_bnken31_rstb = ~tst_bnken31_rstb_n; | |
205 | //assign tst_bnken02_rstb = ~tst_bnken02_rstb_n; | |
206 | ||
207 | n2_l2d_tstmod_cust_inv_macro__width_1 inv_tst_bnken31_rstb | |
208 | ( | |
209 | .dout (tst_bnken31_rstb), | |
210 | .din (tst_bnken31_rstb_n) | |
211 | ); | |
212 | ||
213 | n2_l2d_tstmod_cust_inv_macro__width_1 inv_tst_bnken02_rstb | |
214 | ( | |
215 | .dout (tst_bnken02_rstb), | |
216 | .din (tst_bnken02_rstb_n) | |
217 | ); | |
218 | ||
219 | n2_l2d_tstmod_cust_msff_ctl_macro__fs_1__width_1 msff_buf_out_top | |
220 | ( | |
221 | .scan_in (msff_buf_out_top_scanin), | |
222 | .scan_out (msff_buf_out_top_scanout), | |
223 | .din ( ff_buf_out_top ), | |
224 | .l1clk ( l1clk ), | |
225 | .dout ( ff_buf_out_top ), | |
226 | .siclk(siclk), | |
227 | .soclk(soclk) | |
228 | ); | |
229 | ||
230 | n2_l2d_tstmod_cust_msff_ctl_macro__fs_1__width_1 msff_buf_out_bot | |
231 | ( | |
232 | .scan_in (msff_buf_out_bot_scanin), | |
233 | .scan_out (msff_buf_out_bot_scanout), | |
234 | .din ( ff_buf_out_bot ), | |
235 | .l1clk ( l1clk ), | |
236 | .dout ( ff_buf_out_bot ), | |
237 | .siclk(siclk), | |
238 | .soclk(soclk) | |
239 | ); | |
240 | ||
241 | ||
242 | n2_l2d_tstmod_cust_msff_ctl_macro__fs_1__width_3 msff_buf_out_corse | |
243 | ( | |
244 | .scan_in (msff_buf_out_corse_scanin[2:0]), | |
245 | .scan_out (msff_buf_out_corse_scanout[2:0]), | |
246 | .din ( ff_buf_out_corse[2:0] ), | |
247 | .l1clk ( l1clk ), | |
248 | .dout ( ff_buf_out_corse[2:0] ), | |
249 | .siclk(siclk), | |
250 | .soclk(soclk) | |
251 | ); | |
252 | ||
253 | n2_l2d_tstmod_cust_msff_ctl_macro__fs_1__width_3 msff_buf_out_fine | |
254 | ( | |
255 | .scan_in (msff_buf_out_fine_scanin[2:0]), | |
256 | .scan_out (msff_buf_out_fine_scanout[2:0]), | |
257 | .din ( ff_buf_out_fine[2:0] ), | |
258 | .l1clk ( l1clk ), | |
259 | .dout ( ff_buf_out_fine[2:0] ), | |
260 | .siclk(siclk), | |
261 | .soclk(soclk) | |
262 | ); | |
263 | ||
264 | //assign tstmod_rst_l = ff_buf_out_top & ff_buf_out_bot & ~wr_inhibit; | |
265 | ||
266 | ||
267 | n2_l2d_tstmod_cust_inv_macro__width_1 inv_wr_inhibit | |
268 | ( | |
269 | .dout (wr_inhibit_n), | |
270 | .din (wr_inhibit) | |
271 | ); | |
272 | ||
273 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_tstmod_rst_l | |
274 | ( | |
275 | .dout (tstmod_rst_l), | |
276 | .din0 (ff_buf_out_top), | |
277 | .din1 (ff_buf_out_bot), | |
278 | .din2 (wr_inhibit_n) | |
279 | ); | |
280 | ||
281 | ||
282 | n2_l2d_tstmod_cust_inv_macro__width_3 inv_ff_buf_out_corse_012 | |
283 | ( | |
284 | .dout (ff_buf_out_corse_n[2:0]), | |
285 | .din (ff_buf_out_corse[2:0]) | |
286 | ); | |
287 | ||
288 | ||
289 | ||
290 | ||
291 | ||
292 | //decoding: 3-to-8. 2/3, 1/0 swapped | |
293 | //assign corse_sel[5] = ff_buf_out_corse[2] & ~ff_buf_out_corse[1] & ~ff_buf_out_corse[0]; | |
294 | ||
295 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_corse_sel_5 | |
296 | ( | |
297 | .dout (corse_sel[5]), | |
298 | .din0 (ff_buf_out_corse[2]), | |
299 | .din1 (ff_buf_out_corse_n[1]), | |
300 | .din2 (ff_buf_out_corse_n[0]) | |
301 | ); | |
302 | ||
303 | //assign corse_sel[4] = ff_buf_out_corse[2] & ~ff_buf_out_corse[1] & ff_buf_out_corse[0]; | |
304 | ||
305 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_corse_sel_4 | |
306 | ( | |
307 | .dout (corse_sel[4]), | |
308 | .din0 (ff_buf_out_corse[2]), | |
309 | .din1 (ff_buf_out_corse_n[1]), | |
310 | .din2 (ff_buf_out_corse[0]) | |
311 | ); | |
312 | ||
313 | //assign corse_sel[3] = ~ff_buf_out_corse[2] & ff_buf_out_corse[1] & ~ff_buf_out_corse[0]; | |
314 | ||
315 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_corse_sel_3 | |
316 | ( | |
317 | .dout (corse_sel[3]), | |
318 | .din0 (ff_buf_out_corse_n[2]), | |
319 | .din1 (ff_buf_out_corse[1]), | |
320 | .din2 (ff_buf_out_corse_n[0]) | |
321 | ); | |
322 | ||
323 | //assign corse_sel[2] = ~ff_buf_out_corse[2] & ff_buf_out_corse[1] & ff_buf_out_corse[0]; | |
324 | ||
325 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_corse_sel_2 | |
326 | ( | |
327 | .dout (corse_sel[2]), | |
328 | .din0 (ff_buf_out_corse_n[2]), | |
329 | .din1 (ff_buf_out_corse[1]), | |
330 | .din2 (ff_buf_out_corse[0]) | |
331 | ); | |
332 | ||
333 | //assign corse_sel[1] = ~ff_buf_out_corse[2] & ~ff_buf_out_corse[1] & ~ff_buf_out_corse[0]; | |
334 | ||
335 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_corse_sel_1 | |
336 | ( | |
337 | .dout (corse_sel[1]), | |
338 | .din0 (ff_buf_out_corse_n[2]), | |
339 | .din1 (ff_buf_out_corse_n[1]), | |
340 | .din2 (ff_buf_out_corse_n[0]) | |
341 | ); | |
342 | ||
343 | //assign corse_sel[0] = ~ff_buf_out_corse[2] & ~ff_buf_out_corse[1] & ff_buf_out_corse[0]; | |
344 | ||
345 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_corse_sel_0 | |
346 | ( | |
347 | .dout (corse_sel[0]), | |
348 | .din0 (ff_buf_out_corse_n[2]), | |
349 | .din1 (ff_buf_out_corse_n[1]), | |
350 | .din2 (ff_buf_out_corse[0]) | |
351 | ); | |
352 | ||
353 | n2_l2d_tstmod_cust_inv_macro__width_3 inv_ff_buf_out_fine_n | |
354 | ( | |
355 | .dout (ff_buf_out_fine_n[2:0]), | |
356 | .din (ff_buf_out_fine[2:0]) | |
357 | ); | |
358 | ||
359 | ||
360 | //assign fine_sel[7] = ff_buf_out_fine[2] & ff_buf_out_fine[1] & ~ff_buf_out_fine[0]; | |
361 | ||
362 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_fine_sel_7 | |
363 | ( | |
364 | .dout (fine_sel[7]), | |
365 | .din0 (ff_buf_out_fine[2]), | |
366 | .din1 (ff_buf_out_fine[1]), | |
367 | .din2 (ff_buf_out_fine_n[0]) | |
368 | ); | |
369 | ||
370 | //assign fine_sel[6] = ff_buf_out_fine[2] & ff_buf_out_fine[1] & ff_buf_out_fine[0]; | |
371 | ||
372 | ||
373 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_fine_sel_6 | |
374 | ( | |
375 | .dout (fine_sel[6]), | |
376 | .din0 (ff_buf_out_fine[2]), | |
377 | .din1 (ff_buf_out_fine[1]), | |
378 | .din2 (ff_buf_out_fine[0]) | |
379 | ); | |
380 | ||
381 | //assign fine_sel[5] = ff_buf_out_fine[2] & ~ff_buf_out_fine[1] & ~ff_buf_out_fine[0]; | |
382 | ||
383 | ||
384 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_fine_sel_5 | |
385 | ( | |
386 | .dout (fine_sel[5]), | |
387 | .din0 (ff_buf_out_fine[2]), | |
388 | .din1 (ff_buf_out_fine_n[1]), | |
389 | .din2 (ff_buf_out_fine_n[0]) | |
390 | ); | |
391 | ||
392 | //assign fine_sel[4] = ff_buf_out_fine[2] & ~ff_buf_out_fine[1] & ff_buf_out_fine[0]; | |
393 | ||
394 | ||
395 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_fine_sel_4 | |
396 | ( | |
397 | .dout (fine_sel[4]), | |
398 | .din0 (ff_buf_out_fine[2]), | |
399 | .din1 (ff_buf_out_fine_n[1]), | |
400 | .din2 (ff_buf_out_fine[0]) | |
401 | ); | |
402 | ||
403 | //assign fine_sel[3] = ~ff_buf_out_fine[2] & ff_buf_out_fine[1] & ~ff_buf_out_fine[0]; | |
404 | ||
405 | ||
406 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_fine_sel_3 | |
407 | ( | |
408 | .dout (fine_sel[3]), | |
409 | .din0 (ff_buf_out_fine_n[2]), | |
410 | .din1 (ff_buf_out_fine[1]), | |
411 | .din2 (ff_buf_out_fine_n[0]) | |
412 | ); | |
413 | ||
414 | //assign fine_sel[2] = ~ff_buf_out_fine[2] & ff_buf_out_fine[1] & ff_buf_out_fine[0]; | |
415 | ||
416 | ||
417 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_fine_sel_2 | |
418 | ( | |
419 | .dout (fine_sel[2]), | |
420 | .din0 (ff_buf_out_fine_n[2]), | |
421 | .din1 (ff_buf_out_fine[1]), | |
422 | .din2 (ff_buf_out_fine[0]) | |
423 | ); | |
424 | ||
425 | //assign fine_sel[1] = ~ff_buf_out_fine[2] & ~ff_buf_out_fine[1] & ~ff_buf_out_fine[0]; | |
426 | ||
427 | ||
428 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_fine_sel_1 | |
429 | ( | |
430 | .dout (fine_sel[1]), | |
431 | .din0 (ff_buf_out_fine_n[2]), | |
432 | .din1 (ff_buf_out_fine_n[1]), | |
433 | .din2 (ff_buf_out_fine_n[0]) | |
434 | ); | |
435 | ||
436 | //assign fine_sel[0] = ~ff_buf_out_fine[2] & ~ff_buf_out_fine[1] & ff_buf_out_fine[0]; | |
437 | ||
438 | ||
439 | n2_l2d_tstmod_cust_and_macro__ports_3__width_1 and_fine_sel_0 | |
440 | ( | |
441 | .dout (fine_sel[0]), | |
442 | .din0 (ff_buf_out_fine_n[2]), | |
443 | .din1 (ff_buf_out_fine_n[1]), | |
444 | .din2 (ff_buf_out_fine[0]) | |
445 | ); | |
446 | ||
447 | ||
448 | //end of n2_l2d_tstmod_logic | |
449 | ||
450 | n2_l2d_tstmod_delay_cust tstmod_delay // NOT ATPGABLE | |
451 | ( | |
452 | .l1clk (l1clk), | |
453 | .tstmod_rst_l (tstmod_rst_l), | |
454 | .tst_bnken31_setb(tst_bnken31_setb), | |
455 | .tst_bnken02_setb(tst_bnken02_setb), | |
456 | .tst_bnken31_rstb(tst_bnken31_rstb), | |
457 | .tst_bnken02_rstb(tst_bnken02_rstb), | |
458 | .corse_sel (corse_sel[5:0]), | |
459 | .fine_sel (fine_sel[7:0]), | |
460 | .delout31_lft (delout31_lft), | |
461 | .delout31_rgt (delout31_rgt), | |
462 | .delout20_lft (delout20_lft), | |
463 | .delout20_rgt (delout20_rgt) | |
464 | ); | |
465 | ||
466 | ||
467 | ||
468 | // scanorder start | |
469 | //msff_read_c4_scanin[1:0] | |
470 | //msff_buf_out_top_scanin | |
471 | //msff_buf_out_corse_scanin[0] | |
472 | //msff_buf_out_corse_scanin[1] | |
473 | //msff_buf_out_corse_scanin[2] | |
474 | //msff_buf_out_fine_scanin[0] | |
475 | //msff_buf_out_fine_scanin[1] | |
476 | //msff_buf_out_fine_scanin[2] | |
477 | //msff_buf_out_bot_scanin | |
478 | // scanorder end281 // fixscan start | |
479 | assign msff_read_c4_scanin[1]=si; | |
480 | assign msff_read_c4_scanin[0]=msff_read_c4_scanout[1]; | |
481 | assign msff_buf_out_top_scanin=msff_read_c4_scanout[0]; | |
482 | assign msff_buf_out_corse_scanin[0]=msff_buf_out_top_scanout; | |
483 | assign msff_buf_out_corse_scanin[1]=msff_buf_out_corse_scanout[0]; | |
484 | assign msff_buf_out_corse_scanin[2]=msff_buf_out_corse_scanout[1]; | |
485 | assign msff_buf_out_fine_scanin[0]=msff_buf_out_corse_scanout[2]; | |
486 | assign msff_buf_out_fine_scanin[1]=msff_buf_out_fine_scanout[0]; | |
487 | assign msff_buf_out_fine_scanin[2]=msff_buf_out_fine_scanout[1]; | |
488 | assign msff_buf_out_bot_scanin=msff_buf_out_fine_scanout[2]; | |
489 | assign so=msff_buf_out_bot_scanout; | |
490 | // fixscan end | |
491 | endmodule // main program | |
492 | ||
493 | ////////////////////////////////////////////// | |
494 | ////////////////////////////////////////////// | |
495 | ////////////////////////////////////////////// | |
496 | ////////////////////////////////////////////// | |
497 | ////////////////////////////////////////////// | |
498 | ////////////////////////////////////////////// | |
499 | ////////////////////////////////////////////// | |
500 | ////////////////////////////////////////////// | |
501 | ////////////////////////////////////////////// | |
502 | ////////////////////////////////////////////// | |
503 | ////////////////////////////////////////////// | |
504 | // THE FOLLOWING MODULE IS BLACKBOX TO ATPG | |
505 | ////////////////////////////////////////////// | |
506 | ||
507 | module n2_l2d_tstmod_delay_cust ( | |
508 | l1clk, | |
509 | tstmod_rst_l, | |
510 | tst_bnken31_setb, | |
511 | tst_bnken02_setb, | |
512 | tst_bnken31_rstb, | |
513 | tst_bnken02_rstb, | |
514 | corse_sel, | |
515 | fine_sel, | |
516 | delout31_lft, | |
517 | delout31_rgt, | |
518 | delout20_lft, | |
519 | delout20_rgt) ; | |
520 | ||
521 | input l1clk; | |
522 | input tstmod_rst_l; | |
523 | input tst_bnken31_setb; | |
524 | input tst_bnken02_setb; | |
525 | input tst_bnken31_rstb; | |
526 | input tst_bnken02_rstb; | |
527 | input [5:0] corse_sel; | |
528 | input [7:0] fine_sel; | |
529 | ||
530 | output delout31_lft; | |
531 | output delout31_rgt; | |
532 | output delout20_lft; | |
533 | output delout20_rgt; | |
534 | ||
535 | wire [5:0] corse_sel_muxout; | |
536 | wire [7:1] fine_sel_muxout; | |
537 | ||
538 | wire delayline_en_31; | |
539 | wire delayline_en_02; | |
540 | wire fine_dout_31; | |
541 | wire fine_dout_02; | |
542 | ||
543 | assign corse_sel_muxout[5:0] = ( {1'b0,corse_sel_muxout[5:1]} & {~({5{tstmod_rst_l}} & corse_sel[5:1]),(tstmod_rst_l & ~corse_sel[0])}) | | |
544 | ({6{l1clk}} & {{{5{tstmod_rst_l}} & corse_sel[5:1]},(~(tstmod_rst_l & ~corse_sel[0])) & tstmod_rst_l}); | |
545 | ||
546 | // | |
547 | //assign fine_sel_muxout[7:1] = ( ({corse_sel_muxout[0],fine_sel_muxout[7:2]}) & (~fine_sel[7:1]) ) | |
548 | // | ({&{corse_sel_muxout[0]}} & fine_sel[7:1]); | |
549 | ||
550 | ||
551 | assign fine_sel_muxout[7:1] = ( ({corse_sel_muxout[0],fine_sel_muxout[7:2]}) & (~fine_sel[7:1]) ) | | |
552 | ({7{corse_sel_muxout[0]}} & fine_sel[7:1]); | |
553 | ||
554 | ||
555 | srlatch1 latch1_31 | |
556 | ( | |
557 | .setl (~(l1clk & tstmod_rst_l & tst_bnken31_setb)), | |
558 | .rstl1 (tstmod_rst_l), | |
559 | .rstl2 (l1clk|~tst_bnken31_rstb), | |
560 | .out (delayline_en_31) | |
561 | ); | |
562 | ||
563 | srlatch1 latch1_02 | |
564 | ( | |
565 | .setl (~(l1clk & tstmod_rst_l & tst_bnken02_setb)), | |
566 | .rstl1 (tstmod_rst_l), | |
567 | .rstl2 (l1clk|~tst_bnken02_rstb), | |
568 | .out (delayline_en_02) | |
569 | ); | |
570 | ||
571 | srlatch2 latch2_31 | |
572 | ( | |
573 | .setl1 (~(fine_sel_muxout[1] & delayline_en_31 & ~fine_sel[0])), | |
574 | .setl2 (~(corse_sel_muxout[0] & delayline_en_31 & fine_sel[0])), | |
575 | .rstl (delayline_en_31), | |
576 | .out (fine_dout_31) | |
577 | ); | |
578 | ||
579 | srlatch2 latch2_02 | |
580 | ( | |
581 | .setl1 (~(fine_sel_muxout[1] & delayline_en_02 & ~fine_sel[0])), | |
582 | .setl2 (~(corse_sel_muxout[0] & delayline_en_02 & fine_sel[0])), | |
583 | .rstl (delayline_en_02), | |
584 | .out (fine_dout_02) | |
585 | ); | |
586 | ||
587 | assign delout31_lft = ~fine_dout_31; | |
588 | assign delout31_rgt = ~fine_dout_31; | |
589 | assign delout20_lft = ~fine_dout_02; | |
590 | assign delout20_rgt = ~fine_dout_02; | |
591 | endmodule //n2_l2d_tstmod_delay_cust | |
592 | ||
593 | ||
594 | module srlatch1 ( | |
595 | setl, | |
596 | rstl1, | |
597 | rstl2, | |
598 | out) ; | |
599 | ||
600 | input setl; | |
601 | input rstl1; | |
602 | input rstl2; | |
603 | output out; | |
604 | ||
605 | reg out; | |
606 | ||
607 | always @(setl or rstl1 or rstl2) | |
608 | begin | |
609 | if(~setl) out = 1'b1; | |
610 | else if( ~(rstl1 & rstl2) ) out = 1'b0; | |
611 | end | |
612 | endmodule // srlatch1 | |
613 | ||
614 | ||
615 | module srlatch2 ( | |
616 | setl1, | |
617 | setl2, | |
618 | rstl, | |
619 | out) ; | |
620 | ||
621 | input setl1; | |
622 | input setl2; | |
623 | input rstl; | |
624 | output out; | |
625 | ||
626 | reg out; | |
627 | ||
628 | always @(setl1 or setl2 or rstl) begin | |
629 | if( (setl1==0) || (setl2==0)) out = 1'b1; | |
630 | else if(~rstl) out = 1'b0; | |
631 | end | |
632 | endmodule // srlatch2 | |
633 | ||
634 | ||
635 | ||
636 | ||
637 | ||
638 | ||
639 | // any PARAMS parms go into naming of macro | |
640 | ||
641 | module n2_l2d_tstmod_cust_l1clkhdr_ctl_macro ( | |
642 | l2clk, | |
643 | l1en, | |
644 | pce_ov, | |
645 | stop, | |
646 | se, | |
647 | l1clk); | |
648 | ||
649 | ||
650 | input l2clk; | |
651 | input l1en; | |
652 | input pce_ov; | |
653 | input stop; | |
654 | input se; | |
655 | output l1clk; | |
656 | ||
657 | ||
658 | ||
659 | ||
660 | ||
661 | cl_sc1_l1hdr_8x c_0 ( | |
662 | ||
663 | ||
664 | .l2clk(l2clk), | |
665 | .pce(l1en), | |
666 | .l1clk(l1clk), | |
667 | .se(se), | |
668 | .pce_ov(pce_ov), | |
669 | .stop(stop) | |
670 | ); | |
671 | ||
672 | ||
673 | ||
674 | endmodule | |
675 | ||
676 | ||
677 | ||
678 | ||
679 | ||
680 | ||
681 | ||
682 | ||
683 | ||
684 | // | |
685 | // invert macro | |
686 | // | |
687 | // | |
688 | ||
689 | ||
690 | ||
691 | ||
692 | ||
693 | module n2_l2d_tstmod_cust_inv_macro__width_1 ( | |
694 | din, | |
695 | dout); | |
696 | input [0:0] din; | |
697 | output [0:0] dout; | |
698 | ||
699 | ||
700 | ||
701 | ||
702 | ||
703 | ||
704 | inv #(1) d0_0 ( | |
705 | .in(din[0:0]), | |
706 | .out(dout[0:0]) | |
707 | ); | |
708 | ||
709 | ||
710 | ||
711 | ||
712 | ||
713 | ||
714 | ||
715 | ||
716 | ||
717 | endmodule | |
718 | ||
719 | ||
720 | ||
721 | ||
722 | ||
723 | // | |
724 | // or macro for ports = 2,3 | |
725 | // | |
726 | // | |
727 | ||
728 | ||
729 | ||
730 | ||
731 | ||
732 | module n2_l2d_tstmod_cust_or_macro__width_1 ( | |
733 | din0, | |
734 | din1, | |
735 | dout); | |
736 | input [0:0] din0; | |
737 | input [0:0] din1; | |
738 | output [0:0] dout; | |
739 | ||
740 | ||
741 | ||
742 | ||
743 | ||
744 | ||
745 | or2 #(1) d0_0 ( | |
746 | .in0(din0[0:0]), | |
747 | .in1(din1[0:0]), | |
748 | .out(dout[0:0]) | |
749 | ); | |
750 | ||
751 | ||
752 | ||
753 | ||
754 | ||
755 | ||
756 | ||
757 | ||
758 | ||
759 | endmodule | |
760 | ||
761 | ||
762 | ||
763 | ||
764 | ||
765 | // | |
766 | // and macro for ports = 2,3,4 | |
767 | // | |
768 | // | |
769 | ||
770 | ||
771 | ||
772 | ||
773 | ||
774 | module n2_l2d_tstmod_cust_and_macro__ports_3__width_1 ( | |
775 | din0, | |
776 | din1, | |
777 | din2, | |
778 | dout); | |
779 | input [0:0] din0; | |
780 | input [0:0] din1; | |
781 | input [0:0] din2; | |
782 | output [0:0] dout; | |
783 | ||
784 | ||
785 | ||
786 | ||
787 | ||
788 | ||
789 | and3 #(1) d0_0 ( | |
790 | .in0(din0[0:0]), | |
791 | .in1(din1[0:0]), | |
792 | .in2(din2[0:0]), | |
793 | .out(dout[0:0]) | |
794 | ); | |
795 | ||
796 | ||
797 | ||
798 | ||
799 | ||
800 | ||
801 | ||
802 | ||
803 | ||
804 | endmodule | |
805 | ||
806 | ||
807 | ||
808 | ||
809 | ||
810 | // | |
811 | // macro for cl_mc1_tisram_blb_{8,4}x flops | |
812 | // | |
813 | // | |
814 | ||
815 | ||
816 | ||
817 | ||
818 | ||
819 | module n2_l2d_tstmod_cust_tisram_blb_macro__dmsff_4x__width_1 ( | |
820 | d_a, | |
821 | l1clk, | |
822 | q_b); | |
823 | input [0:0] d_a; | |
824 | input l1clk; | |
825 | output [0:0] q_b; | |
826 | ||
827 | ||
828 | ||
829 | ||
830 | ||
831 | ||
832 | tisram_blb #(1) d0_0 ( | |
833 | .d(d_a[0:0]), | |
834 | .l1clk(l1clk), | |
835 | .latout_l(q_b[0:0]) | |
836 | ); | |
837 | ||
838 | ||
839 | ||
840 | ||
841 | ||
842 | ||
843 | ||
844 | ||
845 | ||
846 | ||
847 | //place::generic_place($width,$stack,$left); | |
848 | ||
849 | endmodule | |
850 | ||
851 | ||
852 | ||
853 | ||
854 | ||
855 | ||
856 | ||
857 | ||
858 | ||
859 | // any PARAMS parms go into naming of macro | |
860 | ||
861 | module n2_l2d_tstmod_cust_msff_ctl_macro__fs_1__width_2 ( | |
862 | din, | |
863 | l1clk, | |
864 | scan_in, | |
865 | siclk, | |
866 | soclk, | |
867 | dout, | |
868 | scan_out); | |
869 | wire [1:0] fdin; | |
870 | ||
871 | input [1:0] din; | |
872 | input l1clk; | |
873 | input [1:0] scan_in; | |
874 | ||
875 | ||
876 | input siclk; | |
877 | input soclk; | |
878 | ||
879 | output [1:0] dout; | |
880 | output [1:0] scan_out; | |
881 | assign fdin[1:0] = din[1:0]; | |
882 | ||
883 | ||
884 | ||
885 | ||
886 | ||
887 | ||
888 | dff #(2) d0_0 ( | |
889 | .l1clk(l1clk), | |
890 | .siclk(siclk), | |
891 | .soclk(soclk), | |
892 | .d(fdin[1:0]), | |
893 | .si(scan_in[1:0]), | |
894 | .so(scan_out[1:0]), | |
895 | .q(dout[1:0]) | |
896 | ); | |
897 | ||
898 | ||
899 | ||
900 | ||
901 | ||
902 | ||
903 | ||
904 | ||
905 | ||
906 | ||
907 | ||
908 | ||
909 | endmodule | |
910 | ||
911 | ||
912 | ||
913 | ||
914 | ||
915 | ||
916 | ||
917 | ||
918 | ||
919 | ||
920 | ||
921 | ||
922 | ||
923 | // any PARAMS parms go into naming of macro | |
924 | ||
925 | module n2_l2d_tstmod_cust_msff_ctl_macro__fs_1__width_1 ( | |
926 | din, | |
927 | l1clk, | |
928 | scan_in, | |
929 | siclk, | |
930 | soclk, | |
931 | dout, | |
932 | scan_out); | |
933 | wire [0:0] fdin; | |
934 | ||
935 | input [0:0] din; | |
936 | input l1clk; | |
937 | input [0:0] scan_in; | |
938 | ||
939 | ||
940 | input siclk; | |
941 | input soclk; | |
942 | ||
943 | output [0:0] dout; | |
944 | output [0:0] scan_out; | |
945 | assign fdin[0:0] = din[0:0]; | |
946 | ||
947 | ||
948 | ||
949 | ||
950 | ||
951 | ||
952 | dff #(1) d0_0 ( | |
953 | .l1clk(l1clk), | |
954 | .siclk(siclk), | |
955 | .soclk(soclk), | |
956 | .d(fdin[0:0]), | |
957 | .si(scan_in[0:0]), | |
958 | .so(scan_out[0:0]), | |
959 | .q(dout[0:0]) | |
960 | ); | |
961 | ||
962 | ||
963 | ||
964 | ||
965 | ||
966 | ||
967 | ||
968 | ||
969 | ||
970 | ||
971 | ||
972 | ||
973 | endmodule | |
974 | ||
975 | ||
976 | ||
977 | ||
978 | ||
979 | ||
980 | ||
981 | ||
982 | ||
983 | ||
984 | ||
985 | ||
986 | ||
987 | // any PARAMS parms go into naming of macro | |
988 | ||
989 | module n2_l2d_tstmod_cust_msff_ctl_macro__fs_1__width_3 ( | |
990 | din, | |
991 | l1clk, | |
992 | scan_in, | |
993 | siclk, | |
994 | soclk, | |
995 | dout, | |
996 | scan_out); | |
997 | wire [2:0] fdin; | |
998 | ||
999 | input [2:0] din; | |
1000 | input l1clk; | |
1001 | input [2:0] scan_in; | |
1002 | ||
1003 | ||
1004 | input siclk; | |
1005 | input soclk; | |
1006 | ||
1007 | output [2:0] dout; | |
1008 | output [2:0] scan_out; | |
1009 | assign fdin[2:0] = din[2:0]; | |
1010 | ||
1011 | ||
1012 | ||
1013 | ||
1014 | ||
1015 | ||
1016 | dff #(3) d0_0 ( | |
1017 | .l1clk(l1clk), | |
1018 | .siclk(siclk), | |
1019 | .soclk(soclk), | |
1020 | .d(fdin[2:0]), | |
1021 | .si(scan_in[2:0]), | |
1022 | .so(scan_out[2:0]), | |
1023 | .q(dout[2:0]) | |
1024 | ); | |
1025 | ||
1026 | ||
1027 | ||
1028 | ||
1029 | ||
1030 | ||
1031 | ||
1032 | ||
1033 | ||
1034 | ||
1035 | ||
1036 | ||
1037 | endmodule | |
1038 | ||
1039 | ||
1040 | ||
1041 | ||
1042 | ||
1043 | ||
1044 | ||
1045 | ||
1046 | ||
1047 | // | |
1048 | // invert macro | |
1049 | // | |
1050 | // | |
1051 | ||
1052 | ||
1053 | ||
1054 | ||
1055 | ||
1056 | module n2_l2d_tstmod_cust_inv_macro__width_3 ( | |
1057 | din, | |
1058 | dout); | |
1059 | input [2:0] din; | |
1060 | output [2:0] dout; | |
1061 | ||
1062 | ||
1063 | ||
1064 | ||
1065 | ||
1066 | ||
1067 | inv #(3) d0_0 ( | |
1068 | .in(din[2:0]), | |
1069 | .out(dout[2:0]) | |
1070 | ); | |
1071 | ||
1072 | ||
1073 | ||
1074 | ||
1075 | ||
1076 | ||
1077 | ||
1078 | ||
1079 | ||
1080 | endmodule | |
1081 | ||
1082 | ||
1083 | ||
1084 |