projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: n2_l2t_bank.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | `define L2T_ARR_D_WIDTH 28 | |
| 36 | `define L2T_ARR_DEPTH 512 | |
| 37 | `define WAY_HIT_WIDTH 16 | |
| 38 | `define BADREAD BADBADD | |
| 39 | ||
| 40 | ||
| 41 | ||
| 42 | module n2_l2t_bank ( | |
| 43 | l1clk_in, | |
| 44 | scan_in, | |
| 45 | clk_stop, | |
| 46 | se_outff, | |
| 47 | scan_en, | |
| 48 | vnw_ary, | |
| 49 | scan_out, | |
| 50 | din, | |
| 51 | index_a, | |
| 52 | l2clk, | |
| 53 | lkuptag_d1, | |
| 54 | pce_out, | |
| 55 | pce_ctl, | |
| 56 | pce_ov, | |
| 57 | rd_en_a, | |
| 58 | reg_d_in, | |
| 59 | reg_en_in, | |
| 60 | reg_wen_lft, | |
| 61 | reg_wen_rgt, | |
| 62 | rid_lft, | |
| 63 | rid_rgt, | |
| 64 | tcu_aclk, | |
| 65 | tcu_bclk, | |
| 66 | way_a, | |
| 67 | wr_en_a, | |
| 68 | wr_inhibit_a, | |
| 69 | reg_d, | |
| 70 | reg_en, | |
| 71 | tag_way0, | |
| 72 | tag_way1, | |
| 73 | way_hit_a); | |
| 74 | wire l1clk_int_v1; | |
| 75 | wire l1clk_int_v2; | |
| 76 | wire l1clk_out0; | |
| 77 | wire l1clk_out1; | |
| 78 | wire se_unused; | |
| 79 | wire siclk; | |
| 80 | wire soclk; | |
| 81 | wire w1_cmp27to19; | |
| 82 | wire w1_cmp27to25; | |
| 83 | wire w1_cmp24to22; | |
| 84 | wire w1_cmp21to19; | |
| 85 | wire w0_cmp27to19; | |
| 86 | wire w0_cmp27to25; | |
| 87 | wire w0_cmp24to22; | |
| 88 | wire w0_cmp21to19; | |
| 89 | wire w1_cmp18to10; | |
| 90 | wire w1_cmp18to16; | |
| 91 | wire w1_cmp15to13; | |
| 92 | wire w1_cmp12to10; | |
| 93 | wire w0_cmp18to10; | |
| 94 | wire w0_cmp18to16; | |
| 95 | wire w0_cmp15to13; | |
| 96 | wire w0_cmp12to10; | |
| 97 | wire w1_cmp9to1; | |
| 98 | wire w1_cmp9to7; | |
| 99 | wire w1_cmp6to4; | |
| 100 | wire w1_cmp3to1; | |
| 101 | wire w0_cmp9to1; | |
| 102 | wire w0_cmp9to7; | |
| 103 | wire w0_cmp6to4; | |
| 104 | wire w0_cmp3to1; | |
| 105 | wire w1_cmp27to1; | |
| 106 | wire rd_en_d1_a; | |
| 107 | wire w0_cmp27to1; | |
| 108 | wire [4:0] reg_d_lft; | |
| 109 | wire [4:0] reg_d_rgt; | |
| 110 | wire rid_lft_b; | |
| 111 | wire rid_rgt_b; | |
| 112 | wire [1:0] reg_en_lft; | |
| 113 | wire [1:0] reg_en_rgt; | |
| 114 | wire ln1clk; | |
| 115 | wire ln2clk; | |
| 116 | wire wr_inhibit_a_l; | |
| 117 | wire not_reg_wen_lft; | |
| 118 | wire wen_clk_lft; | |
| 119 | wire not_reg_wen_rgt; | |
| 120 | wire wen_clk_rgt; | |
| 121 | wire en_lft; | |
| 122 | wire en_rgt; | |
| 123 | wire [4:0] not_reg_d_lft; | |
| 124 | wire [1:0] rpda_lft; | |
| 125 | wire [3:0] rpdb_lft; | |
| 126 | wire [3:0] rpdc_lft; | |
| 127 | wire [4:0] not_reg_d_rgt; | |
| 128 | wire [1:0] rpda_rgt; | |
| 129 | wire [3:0] rpdb_rgt; | |
| 130 | wire [3:0] rpdc_rgt; | |
| 131 | wire [27:0] sao_mx0_h; | |
| 132 | wire [27:0] sao_mx0_l; | |
| 133 | wire [27:0] sao_mx1_h; | |
| 134 | wire [27:0] sao_mx1_l; | |
| 135 | wire [8:0] addr_b; | |
| 136 | wire rd_en_b; | |
| 137 | wire wr_en_b; | |
| 138 | wire wr_en_d1_a; | |
| 139 | wire [1:0] wr_way_b; | |
| 140 | wire [1:0] wr_way_b_l; | |
| 141 | wire [27:0] sao_mx1; | |
| 142 | wire [27:0] sao_mx0; | |
| 143 | wire reg_addr_b_8_scanin; | |
| 144 | wire reg_addr_b_8_scanout; | |
| 145 | wire reg_addr_b_8_unused; | |
| 146 | wire reg_addr_b_7_scanin; | |
| 147 | wire reg_addr_b_7_scanout; | |
| 148 | wire reg_addr_b_7_unused; | |
| 149 | wire reg_addr_b_6_scanin; | |
| 150 | wire reg_addr_b_6_scanout; | |
| 151 | wire reg_addr_b_6_unused; | |
| 152 | wire reg_addr_b_5_scanin; | |
| 153 | wire reg_addr_b_5_scanout; | |
| 154 | wire reg_addr_b_5_unused; | |
| 155 | wire reg_addr_b_4_scanin; | |
| 156 | wire reg_addr_b_4_scanout; | |
| 157 | wire reg_addr_b_4_unused; | |
| 158 | wire reg_addr_b_3_scanin; | |
| 159 | wire reg_addr_b_3_scanout; | |
| 160 | wire reg_addr_b_3_unused; | |
| 161 | wire reg_addr_b_2_scanin; | |
| 162 | wire reg_addr_b_2_scanout; | |
| 163 | wire reg_addr_b_2_unused; | |
| 164 | wire reg_addr_b_1_scanin; | |
| 165 | wire reg_addr_b_1_scanout; | |
| 166 | wire reg_addr_b_1_unused; | |
| 167 | wire reg_addr_b_0_scanin; | |
| 168 | wire reg_addr_b_0_scanout; | |
| 169 | wire reg_addr_b_0_unused; | |
| 170 | wire reg_wr_way_b_scanin; | |
| 171 | wire reg_wr_way_b_scanout; | |
| 172 | wire reg_wr_en_b_scanin; | |
| 173 | wire reg_wr_en_b_scanout; | |
| 174 | wire reg_wr_en_b_unused; | |
| 175 | wire reg_rd_en_b_scanin; | |
| 176 | wire reg_rd_en_b_scanout; | |
| 177 | wire reg_rd_en_b_unused; | |
| 178 | wire reg_wr_en_a_scanin; | |
| 179 | wire reg_wr_en_a_scanout; | |
| 180 | wire reg_rd_en_a_scanin; | |
| 181 | wire reg_rd_en_a_scanout; | |
| 182 | wire reg_tag_way1_27_scanin; | |
| 183 | wire reg_tag_way1_27_scanout; | |
| 184 | wire reg_tag_way0_27_scanin; | |
| 185 | wire reg_tag_way0_27_scanout; | |
| 186 | wire reg_tag_way1_26_scanin; | |
| 187 | wire reg_tag_way1_26_scanout; | |
| 188 | wire reg_tag_way0_26_scanin; | |
| 189 | wire reg_tag_way0_26_scanout; | |
| 190 | wire reg_tag_way1_25_scanin; | |
| 191 | wire reg_tag_way1_25_scanout; | |
| 192 | wire reg_tag_way0_25_scanin; | |
| 193 | wire reg_tag_way0_25_scanout; | |
| 194 | wire reg_tag_way1_24_scanin; | |
| 195 | wire reg_tag_way1_24_scanout; | |
| 196 | wire reg_tag_way0_24_scanin; | |
| 197 | wire reg_tag_way0_24_scanout; | |
| 198 | wire reg_tag_way1_23_scanin; | |
| 199 | wire reg_tag_way1_23_scanout; | |
| 200 | wire reg_tag_way0_23_scanin; | |
| 201 | wire reg_tag_way0_23_scanout; | |
| 202 | wire reg_tag_way1_22_scanin; | |
| 203 | wire reg_tag_way1_22_scanout; | |
| 204 | wire reg_tag_way0_22_scanin; | |
| 205 | wire reg_tag_way0_22_scanout; | |
| 206 | wire reg_tag_way1_21_scanin; | |
| 207 | wire reg_tag_way1_21_scanout; | |
| 208 | wire reg_tag_way0_21_scanin; | |
| 209 | wire reg_tag_way0_21_scanout; | |
| 210 | wire reg_tag_way1_20_scanin; | |
| 211 | wire reg_tag_way1_20_scanout; | |
| 212 | wire reg_tag_way0_20_scanin; | |
| 213 | wire reg_tag_way0_20_scanout; | |
| 214 | wire reg_tag_way1_19_scanin; | |
| 215 | wire reg_tag_way1_19_scanout; | |
| 216 | wire reg_tag_way0_19_scanin; | |
| 217 | wire reg_tag_way0_19_scanout; | |
| 218 | wire reg_tag_way1_18_scanin; | |
| 219 | wire reg_tag_way1_18_scanout; | |
| 220 | wire reg_tag_way0_18_scanin; | |
| 221 | wire reg_tag_way0_18_scanout; | |
| 222 | wire reg_tag_way1_17_scanin; | |
| 223 | wire reg_tag_way1_17_scanout; | |
| 224 | wire reg_tag_way0_17_scanin; | |
| 225 | wire reg_tag_way0_17_scanout; | |
| 226 | wire reg_tag_way1_16_scanin; | |
| 227 | wire reg_tag_way1_16_scanout; | |
| 228 | wire reg_tag_way0_16_scanin; | |
| 229 | wire reg_tag_way0_16_scanout; | |
| 230 | wire reg_tag_way1_15_scanin; | |
| 231 | wire reg_tag_way1_15_scanout; | |
| 232 | wire reg_tag_way0_15_scanin; | |
| 233 | wire reg_tag_way0_15_scanout; | |
| 234 | wire reg_tag_way1_14_scanin; | |
| 235 | wire reg_tag_way1_14_scanout; | |
| 236 | wire reg_tag_way0_14_scanin; | |
| 237 | wire reg_tag_way0_14_scanout; | |
| 238 | wire reg_tag_way1_13_scanin; | |
| 239 | wire reg_tag_way1_13_scanout; | |
| 240 | wire reg_tag_way0_13_scanin; | |
| 241 | wire reg_tag_way0_13_scanout; | |
| 242 | wire reg_tag_way1_12_scanin; | |
| 243 | wire reg_tag_way1_12_scanout; | |
| 244 | wire reg_tag_way0_12_scanin; | |
| 245 | wire reg_tag_way0_12_scanout; | |
| 246 | wire reg_tag_way1_11_scanin; | |
| 247 | wire reg_tag_way1_11_scanout; | |
| 248 | wire reg_tag_way0_11_scanin; | |
| 249 | wire reg_tag_way0_11_scanout; | |
| 250 | wire reg_tag_way1_10_scanin; | |
| 251 | wire reg_tag_way1_10_scanout; | |
| 252 | wire reg_tag_way0_10_scanin; | |
| 253 | wire reg_tag_way0_10_scanout; | |
| 254 | wire reg_tag_way1_9_scanin; | |
| 255 | wire reg_tag_way1_9_scanout; | |
| 256 | wire reg_tag_way0_9_scanin; | |
| 257 | wire reg_tag_way0_9_scanout; | |
| 258 | wire reg_tag_way1_8_scanin; | |
| 259 | wire reg_tag_way1_8_scanout; | |
| 260 | wire reg_tag_way0_8_scanin; | |
| 261 | wire reg_tag_way0_8_scanout; | |
| 262 | wire reg_tag_way1_7_scanin; | |
| 263 | wire reg_tag_way1_7_scanout; | |
| 264 | wire reg_tag_way0_7_scanin; | |
| 265 | wire reg_tag_way0_7_scanout; | |
| 266 | wire reg_tag_way1_6_scanin; | |
| 267 | wire reg_tag_way1_6_scanout; | |
| 268 | wire reg_tag_way0_6_scanin; | |
| 269 | wire reg_tag_way0_6_scanout; | |
| 270 | wire reg_tag_way1_5_scanin; | |
| 271 | wire reg_tag_way1_5_scanout; | |
| 272 | wire reg_tag_way0_5_scanin; | |
| 273 | wire reg_tag_way0_5_scanout; | |
| 274 | wire reg_tag_way1_4_scanin; | |
| 275 | wire reg_tag_way1_4_scanout; | |
| 276 | wire reg_tag_way0_4_scanin; | |
| 277 | wire reg_tag_way0_4_scanout; | |
| 278 | wire reg_tag_way1_3_scanin; | |
| 279 | wire reg_tag_way1_3_scanout; | |
| 280 | wire reg_tag_way0_3_scanin; | |
| 281 | wire reg_tag_way0_3_scanout; | |
| 282 | wire reg_tag_way1_2_scanin; | |
| 283 | wire reg_tag_way1_2_scanout; | |
| 284 | wire reg_tag_way0_2_scanin; | |
| 285 | wire reg_tag_way0_2_scanout; | |
| 286 | wire reg_tag_way1_1_scanin; | |
| 287 | wire reg_tag_way1_1_scanout; | |
| 288 | wire reg_tag_way0_1_scanin; | |
| 289 | wire reg_tag_way0_1_scanout; | |
| 290 | wire reg_tag_way1_0_scanin; | |
| 291 | wire reg_tag_way1_0_scanout; | |
| 292 | wire reg_tag_way0_0_scanin; | |
| 293 | wire reg_tag_way0_0_scanout; | |
| 294 | wire reg_way_hit_a0_scanin; | |
| 295 | wire reg_way_hit_a0_scanout; | |
| 296 | wire reg_way_hit_a1_scanin; | |
| 297 | wire reg_way_hit_a1_scanout; | |
| 298 | ||
| 299 | ||
| 300 | // input l2clk; // cmp clock | |
| 301 | input l1clk_in; // io clock | |
| 302 | input scan_in; | |
| 303 | input clk_stop; | |
| 304 | input se_outff; | |
| 305 | input scan_en; | |
| 306 | input vnw_ary; | |
| 307 | ||
| 308 | // input tcu_aclk; | |
| 309 | // input tcu_bclk; | |
| 310 | // input tcu_scan_en; | |
| 311 | // input tcu_muxtest; | |
| 312 | // input tcu_dectest; | |
| 313 | output scan_out; | |
| 314 | ||
| 315 | input [`L2T_ARR_D_WIDTH - 1:0] din; | |
| 316 | input [8:0] index_a; | |
| 317 | input l2clk; | |
| 318 | input [`L2T_ARR_D_WIDTH - 1:1] lkuptag_d1; | |
| 319 | input pce_out; | |
| 320 | input pce_ctl; | |
| 321 | input pce_ov; | |
| 322 | input rd_en_a; | |
| 323 | input [4:0] reg_d_in; | |
| 324 | input [1:0] reg_en_in; | |
| 325 | input reg_wen_lft; | |
| 326 | input reg_wen_rgt; | |
| 327 | input rid_lft; | |
| 328 | input rid_rgt; | |
| 329 | input tcu_aclk; | |
| 330 | input tcu_bclk; | |
| 331 | input [1:0] way_a; | |
| 332 | input wr_en_a; | |
| 333 | input wr_inhibit_a; | |
| 334 | ||
| 335 | output [4:0] reg_d; | |
| 336 | output [1:0] reg_en; | |
| 337 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way0; | |
| 338 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way1; | |
| 339 | output [1:0] way_hit_a; | |
| 340 | ||
| 341 | ||
| 342 | ||
| 343 | ///////////////////////////////////////// | |
| 344 | // Clock Header // | |
| 345 | ///////////////////////////////////////// | |
| 346 | ||
| 347 | //INTERNAL HEADER | |
| 348 | // | |
| 349 | n2_l2t_bank_l1clkhdr_ctl_macro clk_hdr_int_v1 ( | |
| 350 | .l2clk (l2clk), | |
| 351 | .l1en (pce_ctl), | |
| 352 | .pce_ov (pce_ov), | |
| 353 | .stop (clk_stop), | |
| 354 | .se (scan_en), | |
| 355 | .l1clk (l1clk_int_v1)); | |
| 356 | ||
| 357 | n2_l2t_bank_l1clkhdr_ctl_macro clk_hdr_int_v2 ( | |
| 358 | .l2clk (l2clk), | |
| 359 | .l1en (pce_ctl), | |
| 360 | .pce_ov (pce_ov), | |
| 361 | .stop (clk_stop), | |
| 362 | .se (scan_en), | |
| 363 | .l1clk (l1clk_int_v2)); | |
| 364 | ||
| 365 | ||
| 366 | //OUTPUT HEADER | |
| 367 | // | |
| 368 | n2_l2t_bank_l1clkhdr_ctl_macro clk_hdr_out0 ( | |
| 369 | .l2clk (l2clk), | |
| 370 | .l1en (pce_out), | |
| 371 | .pce_ov (pce_ov), | |
| 372 | .stop (clk_stop), | |
| 373 | .se (se_outff), | |
| 374 | .l1clk (l1clk_out0)); | |
| 375 | ||
| 376 | n2_l2t_bank_l1clkhdr_ctl_macro clk_hdr_out1 ( | |
| 377 | .l2clk (l2clk), | |
| 378 | .l1en (pce_out), | |
| 379 | .pce_ov (pce_ov), | |
| 380 | .stop (clk_stop), | |
| 381 | .se (se_outff), | |
| 382 | .l1clk (l1clk_out1)); | |
| 383 | ||
| 384 | assign se_unused = se_outff; | |
| 385 | assign siclk = tcu_aclk; | |
| 386 | assign soclk = tcu_bclk; | |
| 387 | ||
| 388 | //--------------------------------------- | |
| 389 | // output signals | |
| 390 | //--------------------------------------- | |
| 391 | ||
| 392 | // Behaviourial coding for compare: | |
| 393 | //assign way_hit_a_l[1] = (lkuptag_d1[`L2T_ARR_D_WIDTH - 1 :1] == sao_mx1_h[`L2T_ARR_D_WIDTH - 1 :1] ) ? | |
| 394 | // 1'b0 : 1'b1; | |
| 395 | //assign way_hit_a_l[0] = (lkuptag_d1[`L2T_ARR_D_WIDTH - 1 :1] == sao_mx0_h[`L2T_ARR_D_WIDTH - 1 :1] ) ? | |
| 396 | // 1'b0 : 1'b1; | |
| 397 | ||
| 398 | // Structural coding for 27bit compare (for two ways): | |
| 399 | n2_l2t_bank_nor_macro__ports_3__width_1 w1_nor_cmp27to19 ( | |
| 400 | .dout (w1_cmp27to19), | |
| 401 | .din0 (w1_cmp27to25), | |
| 402 | .din1 (w1_cmp24to22), | |
| 403 | .din2 (w1_cmp21to19)); | |
| 404 | ||
| 405 | n2_l2t_bank_nor_macro__ports_3__width_1 w0_nor_cmp27to19 | |
| 406 | ( | |
| 407 | .dout (w0_cmp27to19), | |
| 408 | .din0 (w0_cmp27to25), | |
| 409 | .din1 (w0_cmp24to22), | |
| 410 | .din2 (w0_cmp21to19)); | |
| 411 | ||
| 412 | n2_l2t_bank_nor_macro__ports_3__width_1 w1_nor_cmp18to10 | |
| 413 | ( | |
| 414 | .dout (w1_cmp18to10), | |
| 415 | .din0 (w1_cmp18to16), | |
| 416 | .din1 (w1_cmp15to13), | |
| 417 | .din2 (w1_cmp12to10)); | |
| 418 | ||
| 419 | n2_l2t_bank_nor_macro__ports_3__width_1 w0_nor_cmp18to10 | |
| 420 | ( | |
| 421 | .dout (w0_cmp18to10), | |
| 422 | .din0 (w0_cmp18to16), | |
| 423 | .din1 (w0_cmp15to13), | |
| 424 | .din2 (w0_cmp12to10)); | |
| 425 | ||
| 426 | ||
| 427 | n2_l2t_bank_nor_macro__ports_3__width_1 w1_nor_cmp9to1 | |
| 428 | ( | |
| 429 | .dout (w1_cmp9to1), | |
| 430 | .din0 (w1_cmp9to7), | |
| 431 | .din1 (w1_cmp6to4), | |
| 432 | .din2 (w1_cmp3to1)); | |
| 433 | ||
| 434 | ||
| 435 | n2_l2t_bank_nor_macro__ports_3__width_1 w0_nor_cmp9to1 | |
| 436 | ( | |
| 437 | .dout (w0_cmp9to1), | |
| 438 | .din0 (w0_cmp9to7), | |
| 439 | .din1 (w0_cmp6to4), | |
| 440 | .din2 (w0_cmp3to1)); | |
| 441 | ||
| 442 | ||
| 443 | // Third stage nand | |
| 444 | //assign w1_cmp27to1 = ~(rd_en_d1_a & w1_cmp27to19 & w1_cmp18to10 & w1_cmp9to1); | |
| 445 | //assign w0_cmp27to1 = ~(rd_en_d1_a & w0_cmp27to19 & w0_cmp18to10 & w0_cmp9to1); | |
| 446 | ||
| 447 | n2_l2t_bank_nand_macro__ports_4__width_1 w1_nand_cmp27to1 | |
| 448 | ( | |
| 449 | .dout (w1_cmp27to1), | |
| 450 | .din0 (rd_en_d1_a), | |
| 451 | .din1 (w1_cmp27to19), | |
| 452 | .din2 (w1_cmp18to10), | |
| 453 | .din3 (w1_cmp9to1)); | |
| 454 | ||
| 455 | n2_l2t_bank_nand_macro__ports_4__width_1 w0_nand_cmp27to1 | |
| 456 | ( | |
| 457 | .dout (w0_cmp27to1), | |
| 458 | .din0 (rd_en_d1_a), | |
| 459 | .din1 (w0_cmp27to19), | |
| 460 | .din2 (w0_cmp18to10), | |
| 461 | .din3 (w0_cmp9to1)); | |
| 462 | ||
| 463 | // The mux is not explicit (check with Connie) | |
| 464 | //assign reg_sel[1:0] = {rid_lft_b, rid_rgt_b}; | |
| 465 | //assign reg_d[4:0] = (reg_sel == 2'b10) ? reg_d_lft[4:0] : (reg_sel == 2'b01) ? reg_d_rgt[4:0] : 5'b00000; | |
| 466 | //assign reg_en[1:0] = (reg_sel == 2'b10) ? reg_en_lft[1:0] : (reg_sel == 2'b01) ? reg_en_rgt[1:0] : 2'b00; | |
| 467 | ||
| 468 | n2_l2t_bank_mux_macro__mux_aonpe__ports_2__stack_156c__width_5 mux_reg_d_lft_reg_d_rgt | |
| 469 | ( | |
| 470 | .dout (reg_d[4:0]), | |
| 471 | .din0 (reg_d_lft[4:0]), | |
| 472 | .din1 (reg_d_rgt[4:0]), | |
| 473 | .sel0 (rid_lft_b), | |
| 474 | .sel1 (rid_rgt_b) | |
| 475 | ); | |
| 476 | ||
| 477 | n2_l2t_bank_mux_macro__mux_aonpe__ports_2__stack_156c__width_2 mux_reg_en_lft_reg_en_rgt | |
| 478 | ( | |
| 479 | .dout (reg_en[1:0]), | |
| 480 | .din0 (reg_en_lft[1:0]), | |
| 481 | .din1 (reg_en_rgt[1:0]), | |
| 482 | .sel0 (rid_lft_b), | |
| 483 | .sel1 (rid_rgt_b) | |
| 484 | ); | |
| 485 | ||
| 486 | ||
| 487 | ||
| 488 | //--------------------------------------- | |
| 489 | // internal signals | |
| 490 | //--------------------------------------- | |
| 491 | assign ln1clk = l1clk_int_v2; | |
| 492 | assign ln2clk = l1clk_int_v2; | |
| 493 | //Change to structural CC | |
| 494 | // assign wr_inhibit_a_l = ~wr_inhibit_a; | |
| 495 | ||
| 496 | n2_l2t_bank_inv_macro__width_1 inv_wr_inhibit_a | |
| 497 | ( | |
| 498 | .din (wr_inhibit_a), | |
| 499 | .dout (wr_inhibit_a_l) | |
| 500 | ); | |
| 501 | ||
| 502 | //--------------------------------------- | |
| 503 | // Redundancy section | |
| 504 | //--------------------------------------- | |
| 505 | ||
| 506 | //Change to structural CC | |
| 507 | //assign wen_clk_lft = ~((~l1clk_int_v1) && reg_wen_lft); | |
| 508 | //assign wen_clk_rgt = ~((~l1clk_int_v2) && reg_wen_rgt); | |
| 509 | ||
| 510 | n2_l2t_bank_inv_macro__width_1 inv_reg_wen_lft | |
| 511 | ( | |
| 512 | .din (reg_wen_lft), | |
| 513 | .dout (not_reg_wen_lft) | |
| 514 | ); | |
| 515 | ||
| 516 | n2_l2t_bank_or_macro__ports_2__width_1 or_wen_clk_lft | |
| 517 | ( | |
| 518 | .din0 (l1clk_int_v1), | |
| 519 | .din1 (not_reg_wen_lft), | |
| 520 | .dout (wen_clk_lft) | |
| 521 | ); | |
| 522 | ||
| 523 | n2_l2t_bank_inv_macro__width_1 inv_reg_wen_rgt | |
| 524 | ( | |
| 525 | .din (reg_wen_rgt), | |
| 526 | .dout (not_reg_wen_rgt) | |
| 527 | ); | |
| 528 | ||
| 529 | n2_l2t_bank_or_macro__ports_2__width_1 or_wen_clk_rgt | |
| 530 | ( | |
| 531 | .din0 (l1clk_int_v2), | |
| 532 | .din1 (not_reg_wen_rgt), | |
| 533 | .dout (wen_clk_rgt) | |
| 534 | ); | |
| 535 | ||
| 536 | ||
| 537 | //assign en_lft = ®_en_lft[1:0]; | |
| 538 | //assign en_rgt = ®_en_rgt[1:0]; | |
| 539 | ||
| 540 | n2_l2t_bank_and_macro__ports_2__width_1 and_en_lft | |
| 541 | ( | |
| 542 | .din0 (reg_en_lft[0]), | |
| 543 | .din1 (reg_en_lft[1]), | |
| 544 | .dout (en_lft) | |
| 545 | ); | |
| 546 | ||
| 547 | n2_l2t_bank_and_macro__ports_2__width_1 and_en_rgt | |
| 548 | ( | |
| 549 | .din0 (reg_en_rgt[0]), | |
| 550 | .din1 (reg_en_rgt[1]), | |
| 551 | .dout (en_rgt) | |
| 552 | ); | |
| 553 | ||
| 554 | // Redundancy decoding : | |
| 555 | //Change to structural CC | |
| 556 | ||
| 557 | // LEFT SIDE | |
| 558 | n2_l2t_bank_inv_macro__width_5 inv_reg_d_lft | |
| 559 | ( | |
| 560 | .din (reg_d_lft[4:0]), | |
| 561 | .dout (not_reg_d_lft[4:0]) | |
| 562 | ); | |
| 563 | ||
| 564 | //assign rpdb_lft[3] = en_lft && ( reg_d_lft[3]) && ( reg_d_lft[2]); | |
| 565 | //assign rpda_lft[1] = en_lft && ( reg_d_lft[4]); | |
| 566 | n2_l2t_bank_and_macro__ports_2__width_1 and_rpda_lft_1 | |
| 567 | ( | |
| 568 | .din0 (reg_d_lft[4]), | |
| 569 | .din1 (en_lft), | |
| 570 | .dout (rpda_lft[1]) | |
| 571 | ); | |
| 572 | ||
| 573 | //assign rpda_lft[0] = en_lft && (~reg_d_lft[4]); | |
| 574 | n2_l2t_bank_and_macro__ports_2__width_1 and_rpda_lft_0 | |
| 575 | ( | |
| 576 | .din0 (not_reg_d_lft[4]), | |
| 577 | .din1 (en_lft), | |
| 578 | .dout (rpda_lft[0]) | |
| 579 | ); | |
| 580 | ||
| 581 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdb_lft_3 | |
| 582 | ( | |
| 583 | .din0 (reg_d_lft[3]), | |
| 584 | .din1 (en_lft), | |
| 585 | .din2 (reg_d_lft[2]), | |
| 586 | .dout (rpdb_lft[3]) | |
| 587 | ); | |
| 588 | ||
| 589 | //assign rpdb_lft[2] = en_lft && ( reg_d_lft[3]) && (~reg_d_lft[2]); | |
| 590 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdb_lft_2 | |
| 591 | ( | |
| 592 | .din0 (reg_d_lft[3]), | |
| 593 | .din1 (en_lft), | |
| 594 | .din2 (not_reg_d_lft[2]), | |
| 595 | .dout (rpdb_lft[2]) | |
| 596 | ); | |
| 597 | ||
| 598 | //assign rpdb_lft[1] = en_lft && (~reg_d_lft[3]) && ( reg_d_lft[2]); | |
| 599 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdb_lft_1 | |
| 600 | ( | |
| 601 | .din0 (not_reg_d_lft[3]), | |
| 602 | .din1 (en_lft), | |
| 603 | .din2 (reg_d_lft[2]), | |
| 604 | .dout (rpdb_lft[1]) | |
| 605 | ); | |
| 606 | ||
| 607 | //assign rpdb_lft[0] = en_lft && (~reg_d_lft[3]) && (~reg_d_lft[2]); | |
| 608 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdb_lft_0 | |
| 609 | ( | |
| 610 | .din0 (not_reg_d_lft[3]), | |
| 611 | .din1 (en_lft), | |
| 612 | .din2 (not_reg_d_lft[2]), | |
| 613 | .dout (rpdb_lft[0]) | |
| 614 | ); | |
| 615 | ||
| 616 | //assign rpdc_lft[3] = en_lft && ( reg_d_lft[1]) && ( reg_d_lft[0]); | |
| 617 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdc_lft_3 | |
| 618 | ( | |
| 619 | .din0 (reg_d_lft[1]), | |
| 620 | .din1 (en_lft), | |
| 621 | .din2 (reg_d_lft[0]), | |
| 622 | .dout (rpdc_lft[3]) | |
| 623 | ); | |
| 624 | ||
| 625 | //assign rpdc_lft[2] = en_lft && ( reg_d_lft[1]) && (~reg_d_lft[0]); | |
| 626 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdc_lft_2 | |
| 627 | ( | |
| 628 | .din0 (reg_d_lft[1]), | |
| 629 | .din1 (en_lft), | |
| 630 | .din2 (not_reg_d_lft[0]), | |
| 631 | .dout (rpdc_lft[2]) | |
| 632 | ); | |
| 633 | ||
| 634 | //assign rpdc_lft[1] = en_lft && (~reg_d_lft[1]) && ( reg_d_lft[0]); | |
| 635 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdc_lft_1 | |
| 636 | ( | |
| 637 | .din0 (reg_d_lft[0]), | |
| 638 | .din1 (en_lft), | |
| 639 | .din2 (not_reg_d_lft[1]), | |
| 640 | .dout (rpdc_lft[1]) | |
| 641 | ); | |
| 642 | ||
| 643 | //assign rpdc_lft[0] = en_lft && (~reg_d_lft[1]) && (~reg_d_lft[0]); | |
| 644 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdc_lft_0 | |
| 645 | ( | |
| 646 | .din0 (not_reg_d_lft[0]), | |
| 647 | .din1 (en_lft), | |
| 648 | .din2 (not_reg_d_lft[1]), | |
| 649 | .dout (rpdc_lft[0]) | |
| 650 | ); | |
| 651 | // RIGHT SIDE | |
| 652 | n2_l2t_bank_inv_macro__width_5 inv_reg_d_rgt | |
| 653 | ( | |
| 654 | .din (reg_d_rgt[4:0]), | |
| 655 | .dout (not_reg_d_rgt[4:0]) | |
| 656 | ); | |
| 657 | ||
| 658 | //assign rpda_rgt[1] = en_rgt && ( reg_d_rgt[4]); | |
| 659 | n2_l2t_bank_and_macro__ports_2__width_1 and_rpda_rgt_1 | |
| 660 | ( | |
| 661 | .din0 (reg_d_rgt[4]), | |
| 662 | .din1 (en_rgt), | |
| 663 | .dout (rpda_rgt[1]) | |
| 664 | ); | |
| 665 | ||
| 666 | //assign rpda_rgt[0] = en_rgt && (~reg_d_rgt[4]); | |
| 667 | n2_l2t_bank_and_macro__ports_2__width_1 and_rpda_rgt_0 | |
| 668 | ( | |
| 669 | .din0 (not_reg_d_rgt[4]), | |
| 670 | .din1 (en_rgt), | |
| 671 | .dout (rpda_rgt[0]) | |
| 672 | ); | |
| 673 | ||
| 674 | //assign rpdb_rgt[3] = en_rgt && ( reg_d_rgt[3]) && ( reg_d_rgt[2]); | |
| 675 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdb_rgt_3 | |
| 676 | ( | |
| 677 | .din0 (reg_d_rgt[2]), | |
| 678 | .din1 (en_rgt), | |
| 679 | .din2 (reg_d_rgt[3]), | |
| 680 | .dout (rpdb_rgt[3]) | |
| 681 | ); | |
| 682 | ||
| 683 | //assign rpdb_rgt[2] = en_rgt && ( reg_d_rgt[3]) && (~reg_d_rgt[2]); | |
| 684 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdb_rgt_2 | |
| 685 | ( | |
| 686 | .din0 (not_reg_d_rgt[2]), | |
| 687 | .din1 (en_rgt), | |
| 688 | .din2 (reg_d_rgt[3]), | |
| 689 | .dout (rpdb_rgt[2]) | |
| 690 | ); | |
| 691 | ||
| 692 | //assign rpdb_rgt[1] = en_rgt && (~reg_d_rgt[3]) && ( reg_d_rgt[2]); | |
| 693 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdb_rgt_1 | |
| 694 | ( | |
| 695 | .din0 (reg_d_rgt[2]), | |
| 696 | .din1 (en_rgt), | |
| 697 | .din2 (not_reg_d_rgt[3]), | |
| 698 | .dout (rpdb_rgt[1]) | |
| 699 | ); | |
| 700 | ||
| 701 | //assign rpdb_rgt[0] = en_rgt && (~reg_d_rgt[3]) && (~reg_d_rgt[2]); | |
| 702 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdb_rgt_0 | |
| 703 | ( | |
| 704 | .din0 (not_reg_d_rgt[2]), | |
| 705 | .din1 (en_rgt), | |
| 706 | .din2 (not_reg_d_rgt[3]), | |
| 707 | .dout (rpdb_rgt[0]) | |
| 708 | ); | |
| 709 | ||
| 710 | //assign rpdc_rgt[3] = en_rgt && ( reg_d_rgt[1]) && ( reg_d_rgt[0]); | |
| 711 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdc_rgt_3 | |
| 712 | ( | |
| 713 | .din0 (reg_d_rgt[1]), | |
| 714 | .din1 (en_rgt), | |
| 715 | .din2 (reg_d_rgt[0]), | |
| 716 | .dout (rpdc_rgt[3]) | |
| 717 | ); | |
| 718 | ||
| 719 | //assign rpdc_rgt[2] = en_rgt && ( reg_d_rgt[1]) && (~reg_d_rgt[0]); | |
| 720 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdc_rgt_2 | |
| 721 | ( | |
| 722 | .din0 (reg_d_rgt[1]), | |
| 723 | .din1 (en_rgt), | |
| 724 | .din2 (not_reg_d_rgt[0]), | |
| 725 | .dout (rpdc_rgt[2]) | |
| 726 | ); | |
| 727 | ||
| 728 | //assign rpdc_rgt[1] = en_rgt && (~reg_d_rgt[1]) && ( reg_d_rgt[0]); | |
| 729 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdc_rgt_1 | |
| 730 | ( | |
| 731 | .din0 (not_reg_d_rgt[1]), | |
| 732 | .din1 (en_rgt), | |
| 733 | .din2 (reg_d_rgt[0]), | |
| 734 | .dout (rpdc_rgt[1]) | |
| 735 | ); | |
| 736 | ||
| 737 | //assign rpdc_rgt[0] = en_rgt && (~reg_d_rgt[1]) && (~reg_d_rgt[0]); | |
| 738 | n2_l2t_bank_and_macro__ports_3__width_1 and_rpdc_rgt_0 | |
| 739 | ( | |
| 740 | .din0 (not_reg_d_rgt[1]), | |
| 741 | .din1 (en_rgt), | |
| 742 | .din2 (not_reg_d_rgt[0]), | |
| 743 | .dout (rpdc_rgt[0]) | |
| 744 | ); | |
| 745 | ||
| 746 | // --- | |
| 747 | ||
| 748 | ||
| 749 | //assign rpda_lft[1:0] = en_lft ? (reg_d_lft[4] ? 2'b10 : 2'b01 ): 2'b00; | |
| 750 | //assign rpdb_lft[3:0] = en_lft ? ((reg_d_lft[3:2] == 2'b11) ? 4'b1000 : | |
| 751 | // (reg_d_lft[3:2] == 2'b10) ? 4'b0100 : | |
| 752 | // (reg_d_lft[3:2] == 2'b01) ? 4'b0010 : | |
| 753 | // 4'b0001 ) : 4'b0000; | |
| 754 | //assign rpdc_lft[3:0] = en_lft ? ((reg_d_lft[1:0] == 2'b11) ? 4'b1000 : | |
| 755 | // (reg_d_lft[1:0] == 2'b10) ? 4'b0100 : | |
| 756 | // (reg_d_lft[1:0] == 2'b01) ? 4'b0010 : | |
| 757 | // 4'b0001 ) : 4'b0000; | |
| 758 | //assign rpda_rgt[1:0] = en_rgt ? (reg_d_rgt[4] ? 2'b10 : 2'b01 ): 2'b00; | |
| 759 | //assign rpdb_rgt[3:0] = en_rgt ? ((reg_d_rgt[3:2] == 2'b11) ? 4'b1000 : | |
| 760 | // (reg_d_rgt[3:2] == 2'b10) ? 4'b0100 : | |
| 761 | // (reg_d_rgt[3:2] == 2'b01) ? 4'b0010 : | |
| 762 | // 4'b0001 ) : 4'b0000; | |
| 763 | //assign rpdc_rgt[3:0] = en_rgt ? ((reg_d_rgt[1:0] == 2'b11) ? 4'b1000 : | |
| 764 | // (reg_d_rgt[1:0] == 2'b10) ? 4'b0100 : | |
| 765 | // (reg_d_rgt[1:0] == 2'b01) ? 4'b0010 : | |
| 766 | // 4'b0001 ) : 4'b0000; | |
| 767 | ||
| 768 | ||
| 769 | //--------------------------------------- | |
| 770 | // L2T ARRAY INSTANTIATION | |
| 771 | //--------------------------------------- | |
| 772 | n2_l2t_array l2t_array (/*AUTOINST*/ | |
| 773 | // Outputs | |
| 774 | .sao_mx0_h (sao_mx0_h[`L2T_ARR_D_WIDTH-1:0]), | |
| 775 | .sao_mx0_l (sao_mx0_l[`L2T_ARR_D_WIDTH-1:0]), | |
| 776 | .sao_mx1_h (sao_mx1_h[`L2T_ARR_D_WIDTH-1:0]), | |
| 777 | .sao_mx1_l (sao_mx1_l[`L2T_ARR_D_WIDTH-1:0]), | |
| 778 | // Inputs | |
| 779 | .vnw_ary (vnw_ary), | |
| 780 | .din (din[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
| 781 | .addr_b (addr_b[8:0]), | |
| 782 | .l1clk_internal_v1(l1clk_int_v1), // Templated | |
| 783 | .l1clk_internal_v2(l1clk_int_v2), // Templated | |
| 784 | .ln1clk (ln1clk), | |
| 785 | .ln2clk (ln2clk), | |
| 786 | .rd_en_b (rd_en_b), | |
| 787 | .rd_en_d1_a (rd_en_d1_a), | |
| 788 | .rpda_lft (rpda_lft[1:0]), | |
| 789 | .rpda_rgt (rpda_rgt[1:0]), | |
| 790 | .rpdb_lft (rpdb_lft[3:0]), | |
| 791 | .rpdb_rgt (rpdb_rgt[3:0]), | |
| 792 | .rpdc_lft (rpdc_lft[3:0]), | |
| 793 | .rpdc_rgt (rpdc_rgt[3:0]), | |
| 794 | .w_inhibit_l (wr_inhibit_a_l), | |
| 795 | .wr_en_b (wr_en_b), | |
| 796 | .wr_en_d1_a (wr_en_d1_a), | |
| 797 | .wr_way_b (wr_way_b[1:0]), | |
| 798 | .wr_way_b_l (wr_way_b_l[1:0])); | |
| 799 | ||
| 800 | //--------------------------------------- | |
| 801 | // SET RESET LATCH FOR SENSE AMP OUT | |
| 802 | //--------------------------------------- | |
| 803 | ||
| 804 | n2_l2t_sr_latch srlatch_sao_mx1_27 (.set (sao_mx1_h[27]), .reset (sao_mx1_l[27]), .out (sao_mx1[27])); | |
| 805 | n2_l2t_sr_latch srlatch_sao_mx1_26 (.set (sao_mx1_h[26]), .reset (sao_mx1_l[26]), .out (sao_mx1[26])); | |
| 806 | n2_l2t_sr_latch srlatch_sao_mx1_25 (.set (sao_mx1_h[25]), .reset (sao_mx1_l[25]), .out (sao_mx1[25])); | |
| 807 | n2_l2t_sr_latch srlatch_sao_mx1_24 (.set (sao_mx1_h[24]), .reset (sao_mx1_l[24]), .out (sao_mx1[24])); | |
| 808 | n2_l2t_sr_latch srlatch_sao_mx1_23 (.set (sao_mx1_h[23]), .reset (sao_mx1_l[23]), .out (sao_mx1[23])); | |
| 809 | n2_l2t_sr_latch srlatch_sao_mx1_22 (.set (sao_mx1_h[22]), .reset (sao_mx1_l[22]), .out (sao_mx1[22])); | |
| 810 | n2_l2t_sr_latch srlatch_sao_mx1_21 (.set (sao_mx1_h[21]), .reset (sao_mx1_l[21]), .out (sao_mx1[21])); | |
| 811 | n2_l2t_sr_latch srlatch_sao_mx1_20 (.set (sao_mx1_h[20]), .reset (sao_mx1_l[20]), .out (sao_mx1[20])); | |
| 812 | n2_l2t_sr_latch srlatch_sao_mx1_19 (.set (sao_mx1_h[19]), .reset (sao_mx1_l[19]), .out (sao_mx1[19])); | |
| 813 | n2_l2t_sr_latch srlatch_sao_mx1_18 (.set (sao_mx1_h[18]), .reset (sao_mx1_l[18]), .out (sao_mx1[18])); | |
| 814 | n2_l2t_sr_latch srlatch_sao_mx1_17 (.set (sao_mx1_h[17]), .reset (sao_mx1_l[17]), .out (sao_mx1[17])); | |
| 815 | n2_l2t_sr_latch srlatch_sao_mx1_16 (.set (sao_mx1_h[16]), .reset (sao_mx1_l[16]), .out (sao_mx1[16])); | |
| 816 | n2_l2t_sr_latch srlatch_sao_mx1_15 (.set (sao_mx1_h[15]), .reset (sao_mx1_l[15]), .out (sao_mx1[15])); | |
| 817 | n2_l2t_sr_latch srlatch_sao_mx1_14 (.set (sao_mx1_h[14]), .reset (sao_mx1_l[14]), .out (sao_mx1[14])); | |
| 818 | n2_l2t_sr_latch srlatch_sao_mx1_13 (.set (sao_mx1_h[13]), .reset (sao_mx1_l[13]), .out (sao_mx1[13])); | |
| 819 | n2_l2t_sr_latch srlatch_sao_mx1_12 (.set (sao_mx1_h[12]), .reset (sao_mx1_l[12]), .out (sao_mx1[12])); | |
| 820 | n2_l2t_sr_latch srlatch_sao_mx1_11 (.set (sao_mx1_h[11]), .reset (sao_mx1_l[11]), .out (sao_mx1[11])); | |
| 821 | n2_l2t_sr_latch srlatch_sao_mx1_10 (.set (sao_mx1_h[10]), .reset (sao_mx1_l[10]), .out (sao_mx1[10])); | |
| 822 | n2_l2t_sr_latch srlatch_sao_mx1_9 (.set (sao_mx1_h[9]), .reset (sao_mx1_l[9]), .out (sao_mx1[9])); | |
| 823 | n2_l2t_sr_latch srlatch_sao_mx1_8 (.set (sao_mx1_h[8]), .reset (sao_mx1_l[8]), .out (sao_mx1[8])); | |
| 824 | n2_l2t_sr_latch srlatch_sao_mx1_7 (.set (sao_mx1_h[7]), .reset (sao_mx1_l[7]), .out (sao_mx1[7])); | |
| 825 | n2_l2t_sr_latch srlatch_sao_mx1_6 (.set (sao_mx1_h[6]), .reset (sao_mx1_l[6]), .out (sao_mx1[6])); | |
| 826 | n2_l2t_sr_latch srlatch_sao_mx1_5 (.set (sao_mx1_h[5]), .reset (sao_mx1_l[5]), .out (sao_mx1[5])); | |
| 827 | n2_l2t_sr_latch srlatch_sao_mx1_4 (.set (sao_mx1_h[4]), .reset (sao_mx1_l[4]), .out (sao_mx1[4])); | |
| 828 | n2_l2t_sr_latch srlatch_sao_mx1_3 (.set (sao_mx1_h[3]), .reset (sao_mx1_l[3]), .out (sao_mx1[3])); | |
| 829 | n2_l2t_sr_latch srlatch_sao_mx1_2 (.set (sao_mx1_h[2]), .reset (sao_mx1_l[2]), .out (sao_mx1[2])); | |
| 830 | n2_l2t_sr_latch srlatch_sao_mx1_1 (.set (sao_mx1_h[1]), .reset (sao_mx1_l[1]), .out (sao_mx1[1])); | |
| 831 | n2_l2t_sr_latch srlatch_sao_mx1_0 (.set (sao_mx1_h[0]), .reset (sao_mx1_l[0 ]), .out (sao_mx1[0])); | |
| 832 | ||
| 833 | n2_l2t_sr_latch srlatch_sao_mx0_27 (.set (sao_mx0_h[27]), .reset (sao_mx0_l[27]), .out (sao_mx0[27])); | |
| 834 | n2_l2t_sr_latch srlatch_sao_mx0_26 (.set (sao_mx0_h[26]), .reset (sao_mx0_l[26]), .out (sao_mx0[26])); | |
| 835 | n2_l2t_sr_latch srlatch_sao_mx0_25 (.set (sao_mx0_h[25]), .reset (sao_mx0_l[25]), .out (sao_mx0[25])); | |
| 836 | n2_l2t_sr_latch srlatch_sao_mx0_24 (.set (sao_mx0_h[24]), .reset (sao_mx0_l[24]), .out (sao_mx0[24])); | |
| 837 | n2_l2t_sr_latch srlatch_sao_mx0_23 (.set (sao_mx0_h[23]), .reset (sao_mx0_l[23]), .out (sao_mx0[23])); | |
| 838 | n2_l2t_sr_latch srlatch_sao_mx0_22 (.set (sao_mx0_h[22]), .reset (sao_mx0_l[22]), .out (sao_mx0[22])); | |
| 839 | n2_l2t_sr_latch srlatch_sao_mx0_21 (.set (sao_mx0_h[21]), .reset (sao_mx0_l[21]), .out (sao_mx0[21])); | |
| 840 | n2_l2t_sr_latch srlatch_sao_mx0_20 (.set (sao_mx0_h[20]), .reset (sao_mx0_l[20]), .out (sao_mx0[20])); | |
| 841 | n2_l2t_sr_latch srlatch_sao_mx0_19 (.set (sao_mx0_h[19]), .reset (sao_mx0_l[19]), .out (sao_mx0[19])); | |
| 842 | n2_l2t_sr_latch srlatch_sao_mx0_18 (.set (sao_mx0_h[18]), .reset (sao_mx0_l[18]), .out (sao_mx0[18])); | |
| 843 | n2_l2t_sr_latch srlatch_sao_mx0_17 (.set (sao_mx0_h[17]), .reset (sao_mx0_l[17]), .out (sao_mx0[17])); | |
| 844 | n2_l2t_sr_latch srlatch_sao_mx0_16 (.set (sao_mx0_h[16]), .reset (sao_mx0_l[16]), .out (sao_mx0[16])); | |
| 845 | n2_l2t_sr_latch srlatch_sao_mx0_15 (.set (sao_mx0_h[15]), .reset (sao_mx0_l[15]), .out (sao_mx0[15])); | |
| 846 | n2_l2t_sr_latch srlatch_sao_mx0_14 (.set (sao_mx0_h[14]), .reset (sao_mx0_l[14]), .out (sao_mx0[14])); | |
| 847 | n2_l2t_sr_latch srlatch_sao_mx0_13 (.set (sao_mx0_h[13]), .reset (sao_mx0_l[13]), .out (sao_mx0[13])); | |
| 848 | n2_l2t_sr_latch srlatch_sao_mx0_12 (.set (sao_mx0_h[12]), .reset (sao_mx0_l[12]), .out (sao_mx0[12])); | |
| 849 | n2_l2t_sr_latch srlatch_sao_mx0_11 (.set (sao_mx0_h[11]), .reset (sao_mx0_l[11]), .out (sao_mx0[11])); | |
| 850 | n2_l2t_sr_latch srlatch_sao_mx0_10 (.set (sao_mx0_h[10]), .reset (sao_mx0_l[10]), .out (sao_mx0[10])); | |
| 851 | n2_l2t_sr_latch srlatch_sao_mx0_9 (.set (sao_mx0_h[9]), .reset (sao_mx0_l[9]), .out (sao_mx0[9])); | |
| 852 | n2_l2t_sr_latch srlatch_sao_mx0_8 (.set (sao_mx0_h[8]), .reset (sao_mx0_l[8]), .out (sao_mx0[8])); | |
| 853 | n2_l2t_sr_latch srlatch_sao_mx0_7 (.set (sao_mx0_h[7]), .reset (sao_mx0_l[7]), .out (sao_mx0[7])); | |
| 854 | n2_l2t_sr_latch srlatch_sao_mx0_6 (.set (sao_mx0_h[6]), .reset (sao_mx0_l[6]), .out (sao_mx0[6])); | |
| 855 | n2_l2t_sr_latch srlatch_sao_mx0_5 (.set (sao_mx0_h[5]), .reset (sao_mx0_l[5]), .out (sao_mx0[5])); | |
| 856 | n2_l2t_sr_latch srlatch_sao_mx0_4 (.set (sao_mx0_h[4]), .reset (sao_mx0_l[4]), .out (sao_mx0[4])); | |
| 857 | n2_l2t_sr_latch srlatch_sao_mx0_3 (.set (sao_mx0_h[3]), .reset (sao_mx0_l[3]), .out (sao_mx0[3])); | |
| 858 | n2_l2t_sr_latch srlatch_sao_mx0_2 (.set (sao_mx0_h[2]), .reset (sao_mx0_l[2]), .out (sao_mx0[2])); | |
| 859 | n2_l2t_sr_latch srlatch_sao_mx0_1 (.set (sao_mx0_h[1]), .reset (sao_mx0_l[1]), .out (sao_mx0[1])); | |
| 860 | n2_l2t_sr_latch srlatch_sao_mx0_0 (.set (sao_mx0_h[0]), .reset (sao_mx0_l[0]), .out (sao_mx0[0])); | |
| 861 | ||
| 862 | ||
| 863 | ||
| 864 | //--------------------------------------- | |
| 865 | // L2T 3BIT COMPARE (FIRST STAGE) | |
| 866 | //--------------------------------------- | |
| 867 | n2_l2t_cmp_3bx2 cmp27to25 ( | |
| 868 | .sao_mx1_h (sao_mx1_h[27:25]), | |
| 869 | .sao_mx1_l (sao_mx1_l[27:25]), | |
| 870 | .sao_mx0_h (sao_mx0_h[27:25]), | |
| 871 | .sao_mx0_l (sao_mx0_l[27:25]), | |
| 872 | .lkuptag_d1 (lkuptag_d1[27:25]), | |
| 873 | .l1clk_d (l1clk_int_v2), | |
| 874 | .w1_cmp3b (w1_cmp27to25), | |
| 875 | .w0_cmp3b (w0_cmp27to25)); | |
| 876 | ||
| 877 | n2_l2t_cmp_3bx2 cmp24to22 ( | |
| 878 | .sao_mx1_h (sao_mx1_h[24:22]), | |
| 879 | .sao_mx1_l (sao_mx1_l[24:22]), | |
| 880 | .sao_mx0_h (sao_mx0_h[24:22]), | |
| 881 | .sao_mx0_l (sao_mx0_l[24:22]), | |
| 882 | .lkuptag_d1 (lkuptag_d1[24:22]), | |
| 883 | .l1clk_d (l1clk_int_v2), | |
| 884 | .w1_cmp3b (w1_cmp24to22), | |
| 885 | .w0_cmp3b (w0_cmp24to22)); | |
| 886 | ||
| 887 | n2_l2t_cmp_3bx2 cmp21to19 ( | |
| 888 | .sao_mx1_h (sao_mx1_h[21:19]), | |
| 889 | .sao_mx1_l (sao_mx1_l[21:19]), | |
| 890 | .sao_mx0_h (sao_mx0_h[21:19]), | |
| 891 | .sao_mx0_l (sao_mx0_l[21:19]), | |
| 892 | .lkuptag_d1 (lkuptag_d1[21:19]), | |
| 893 | .l1clk_d (l1clk_int_v2), | |
| 894 | .w1_cmp3b (w1_cmp21to19), | |
| 895 | .w0_cmp3b (w0_cmp21to19)); | |
| 896 | ||
| 897 | n2_l2t_cmp_3bx2 cmp18to16 ( | |
| 898 | .sao_mx1_h (sao_mx1_h[18:16]), | |
| 899 | .sao_mx1_l (sao_mx1_l[18:16]), | |
| 900 | .sao_mx0_h (sao_mx0_h[18:16]), | |
| 901 | .sao_mx0_l (sao_mx0_l[18:16]), | |
| 902 | .lkuptag_d1 (lkuptag_d1[18:16]), | |
| 903 | .l1clk_d (l1clk_int_v2), | |
| 904 | .w1_cmp3b (w1_cmp18to16), | |
| 905 | .w0_cmp3b (w0_cmp18to16)); | |
| 906 | ||
| 907 | n2_l2t_cmp_3bx2 cmp15to13 ( | |
| 908 | .sao_mx1_h (sao_mx1_h[15:13]), | |
| 909 | .sao_mx1_l (sao_mx1_l[15:13]), | |
| 910 | .sao_mx0_h (sao_mx0_h[15:13]), | |
| 911 | .sao_mx0_l (sao_mx0_l[15:13]), | |
| 912 | .lkuptag_d1 (lkuptag_d1[15:13]), | |
| 913 | .l1clk_d (l1clk_int_v2), | |
| 914 | .w1_cmp3b (w1_cmp15to13), | |
| 915 | .w0_cmp3b (w0_cmp15to13)); | |
| 916 | ||
| 917 | n2_l2t_cmp_3bx2 cmp12to10 ( | |
| 918 | .sao_mx1_h (sao_mx1_h[12:10]), | |
| 919 | .sao_mx1_l (sao_mx1_l[12:10]), | |
| 920 | .sao_mx0_h (sao_mx0_h[12:10]), | |
| 921 | .sao_mx0_l (sao_mx0_l[12:10]), | |
| 922 | .lkuptag_d1 (lkuptag_d1[12:10]), | |
| 923 | .l1clk_d (l1clk_int_v2), | |
| 924 | .w1_cmp3b (w1_cmp12to10), | |
| 925 | .w0_cmp3b (w0_cmp12to10)); | |
| 926 | ||
| 927 | n2_l2t_cmp_3bx2 cmp9to7 ( | |
| 928 | .sao_mx1_h (sao_mx1_h[9:7]), | |
| 929 | .sao_mx1_l (sao_mx1_l[9:7]), | |
| 930 | .sao_mx0_h (sao_mx0_h[9:7]), | |
| 931 | .sao_mx0_l (sao_mx0_l[9:7]), | |
| 932 | .lkuptag_d1 (lkuptag_d1[9:7]), | |
| 933 | .l1clk_d (l1clk_int_v2), | |
| 934 | .w1_cmp3b (w1_cmp9to7), | |
| 935 | .w0_cmp3b (w0_cmp9to7)); | |
| 936 | ||
| 937 | ||
| 938 | n2_l2t_cmp_3bx2 cmp6to4 ( | |
| 939 | .sao_mx1_h (sao_mx1_h[6:4]), | |
| 940 | .sao_mx1_l (sao_mx1_l[6:4]), | |
| 941 | .sao_mx0_h (sao_mx0_h[6:4]), | |
| 942 | .sao_mx0_l (sao_mx0_l[6:4]), | |
| 943 | .lkuptag_d1 (lkuptag_d1[6:4]), | |
| 944 | .l1clk_d (l1clk_int_v2), | |
| 945 | .w1_cmp3b (w1_cmp6to4), | |
| 946 | .w0_cmp3b (w0_cmp6to4)); | |
| 947 | ||
| 948 | ||
| 949 | n2_l2t_cmp_3bx2 cmp3to1 ( | |
| 950 | .sao_mx1_h (sao_mx1_h[3:1]), | |
| 951 | .sao_mx1_l (sao_mx1_l[3:1]), | |
| 952 | .sao_mx0_h (sao_mx0_h[3:1]), | |
| 953 | .sao_mx0_l (sao_mx0_l[3:1]), | |
| 954 | .lkuptag_d1 (lkuptag_d1[3:1]), | |
| 955 | .l1clk_d (l1clk_int_v2), | |
| 956 | .w1_cmp3b (w1_cmp3to1), | |
| 957 | .w0_cmp3b (w0_cmp3to1)); | |
| 958 | ||
| 959 | ||
| 960 | ||
| 961 | //************************************************************************ | |
| 962 | // REGISTERS SECTION | |
| 963 | //************************************************************************ | |
| 964 | ||
| 965 | // INPUT FLOPS | |
| 966 | n2_l2t_bank_tisram_blb_macro__dmsff_4x__width_2 lat_reg_en_lft | |
| 967 | ( | |
| 968 | .d_a(reg_en_in[1:0]), | |
| 969 | .q_b(reg_en_lft[1:0]), | |
| 970 | .l1clk(wen_clk_lft) | |
| 971 | ); | |
| 972 | ||
| 973 | n2_l2t_bank_tisram_blb_macro__dmsff_4x__width_5 lat_reg_d_lft | |
| 974 | ( | |
| 975 | .d_a(reg_d_in[4:0]), | |
| 976 | .q_b(reg_d_lft[4:0]), | |
| 977 | .l1clk(wen_clk_lft) | |
| 978 | ); | |
| 979 | ||
| 980 | n2_l2t_bank_tisram_blb_macro__dmsff_4x__width_2 lat_reg_en_rgt | |
| 981 | ( | |
| 982 | .d_a(reg_en_in[1:0]), | |
| 983 | .q_b(reg_en_rgt[1:0]), | |
| 984 | .l1clk(wen_clk_rgt) | |
| 985 | ); | |
| 986 | ||
| 987 | n2_l2t_bank_tisram_blb_macro__dmsff_4x__width_5 lat_reg_d_rgt | |
| 988 | ( | |
| 989 | .d_a(reg_d_in[4:0]), | |
| 990 | .q_b(reg_d_rgt[4:0]), | |
| 991 | .l1clk(wen_clk_rgt) | |
| 992 | ); | |
| 993 | ||
| 994 | // BLB for rid_lft and rid_rgt: | |
| 995 | ||
| 996 | n2_l2t_bank_tisram_blb_macro__dmsff_4x__width_1 lat_rid_lft | |
| 997 | ( | |
| 998 | .d_a(rid_lft), | |
| 999 | .q_b(rid_lft_b), | |
| 1000 | .l1clk(l1clk_int_v1) | |
| 1001 | ); | |
| 1002 | ||
| 1003 | n2_l2t_bank_tisram_blb_macro__dmsff_4x__width_1 lat_rid_rgt | |
| 1004 | ( | |
| 1005 | .d_a(rid_rgt), | |
| 1006 | .q_b(rid_rgt_b), | |
| 1007 | .l1clk(l1clk_int_v1) | |
| 1008 | ); | |
| 1009 | ||
| 1010 | ||
| 1011 | n2_l2t_bank_tisram_msff_macro__width_1 reg_addr_b_8 (.scan_in (reg_addr_b_8_scanin), .scan_out(reg_addr_b_8_scanout), | |
| 1012 | .latout(addr_b[8]), .latout_l(reg_addr_b_8_unused), .l1clk(l1clk_in), .d(index_a[8]), | |
| 1013 | .siclk(siclk), | |
| 1014 | .soclk(soclk)); | |
| 1015 | n2_l2t_bank_tisram_msff_macro__width_1 reg_addr_b_7 (.scan_in (reg_addr_b_7_scanin), .scan_out(reg_addr_b_7_scanout), | |
| 1016 | .latout(addr_b[7]), .latout_l(reg_addr_b_7_unused), .l1clk(l1clk_in), .d(index_a[7]), | |
| 1017 | .siclk(siclk), | |
| 1018 | .soclk(soclk)); | |
| 1019 | n2_l2t_bank_tisram_msff_macro__width_1 reg_addr_b_6 (.scan_in (reg_addr_b_6_scanin), .scan_out(reg_addr_b_6_scanout), | |
| 1020 | .latout(addr_b[6]), .latout_l(reg_addr_b_6_unused), .l1clk(l1clk_in), .d(index_a[6]), | |
| 1021 | .siclk(siclk), | |
| 1022 | .soclk(soclk)); | |
| 1023 | n2_l2t_bank_tisram_msff_macro__width_1 reg_addr_b_5 (.scan_in (reg_addr_b_5_scanin), .scan_out(reg_addr_b_5_scanout), | |
| 1024 | .latout(addr_b[5]), .latout_l(reg_addr_b_5_unused), .l1clk(l1clk_in), .d(index_a[5]), | |
| 1025 | .siclk(siclk), | |
| 1026 | .soclk(soclk)); | |
| 1027 | n2_l2t_bank_tisram_msff_macro__width_1 reg_addr_b_4 (.scan_in (reg_addr_b_4_scanin), .scan_out(reg_addr_b_4_scanout), | |
| 1028 | .latout(addr_b[4]), .latout_l(reg_addr_b_4_unused), .l1clk(l1clk_in), .d(index_a[4]), | |
| 1029 | .siclk(siclk), | |
| 1030 | .soclk(soclk)); | |
| 1031 | n2_l2t_bank_tisram_msff_macro__width_1 reg_addr_b_3 (.scan_in (reg_addr_b_3_scanin), .scan_out(reg_addr_b_3_scanout), | |
| 1032 | .latout(addr_b[3]), .latout_l(reg_addr_b_3_unused), .l1clk(l1clk_in), .d(index_a[3]), | |
| 1033 | .siclk(siclk), | |
| 1034 | .soclk(soclk)); | |
| 1035 | n2_l2t_bank_tisram_msff_macro__width_1 reg_addr_b_2 (.scan_in (reg_addr_b_2_scanin), .scan_out(reg_addr_b_2_scanout), | |
| 1036 | .latout(addr_b[2]), .latout_l(reg_addr_b_2_unused), .l1clk(l1clk_in), .d(index_a[2]), | |
| 1037 | .siclk(siclk), | |
| 1038 | .soclk(soclk)); | |
| 1039 | n2_l2t_bank_tisram_msff_macro__width_1 reg_addr_b_1 (.scan_in (reg_addr_b_1_scanin), .scan_out(reg_addr_b_1_scanout), | |
| 1040 | .latout(addr_b[1]), .latout_l(reg_addr_b_1_unused), .l1clk(l1clk_in), .d(index_a[1]), | |
| 1041 | .siclk(siclk), | |
| 1042 | .soclk(soclk)); | |
| 1043 | ||
| 1044 | n2_l2t_bank_tisram_msff_macro__width_1 reg_addr_b_0 (.scan_in (reg_addr_b_0_scanin), .scan_out(reg_addr_b_0_scanout), | |
| 1045 | .latout(addr_b[0]), .latout_l(reg_addr_b_0_unused), .l1clk(l1clk_in), .d(index_a[0]), | |
| 1046 | .siclk(siclk), | |
| 1047 | .soclk(soclk)); | |
| 1048 | ||
| 1049 | n2_l2t_bank_tisram_msff_macro__width_2 reg_wr_way_b ( | |
| 1050 | .scan_in (reg_wr_way_b_scanin), | |
| 1051 | .scan_out(reg_wr_way_b_scanout), | |
| 1052 | .latout (wr_way_b[1:0]), | |
| 1053 | .latout_l(wr_way_b_l[1:0]), | |
| 1054 | .l1clk(l1clk_in), | |
| 1055 | .d(way_a[1:0]), | |
| 1056 | .siclk(siclk), | |
| 1057 | .soclk(soclk)); | |
| 1058 | ||
| 1059 | n2_l2t_bank_tisram_msff_macro__width_1 reg_wr_en_b ( | |
| 1060 | .scan_in (reg_wr_en_b_scanin), | |
| 1061 | .scan_out(reg_wr_en_b_scanout), | |
| 1062 | .latout(wr_en_b), | |
| 1063 | .latout_l(reg_wr_en_b_unused), | |
| 1064 | .l1clk(l1clk_in), | |
| 1065 | .d(wr_en_a), | |
| 1066 | .siclk(siclk), | |
| 1067 | .soclk(soclk)); | |
| 1068 | ||
| 1069 | n2_l2t_bank_tisram_msff_macro__width_1 reg_rd_en_b ( | |
| 1070 | .scan_in (reg_rd_en_b_scanin), | |
| 1071 | .scan_out(reg_rd_en_b_scanout), | |
| 1072 | .latout(rd_en_b), | |
| 1073 | .latout_l(reg_rd_en_b_unused), | |
| 1074 | .l1clk(l1clk_in), | |
| 1075 | .d(rd_en_a), | |
| 1076 | .siclk(siclk), | |
| 1077 | .soclk(soclk)); | |
| 1078 | ||
| 1079 | n2_l2t_bank_msff_ctl_macro__width_1 reg_wr_en_a ( | |
| 1080 | .scan_in(reg_wr_en_a_scanin), | |
| 1081 | .scan_out(reg_wr_en_a_scanout), | |
| 1082 | .dout(wr_en_d1_a), | |
| 1083 | .l1clk(l1clk_in), | |
| 1084 | .din(wr_en_a), | |
| 1085 | .siclk(siclk), | |
| 1086 | .soclk(soclk)); | |
| 1087 | ||
| 1088 | n2_l2t_bank_msff_ctl_macro__width_1 reg_rd_en_a ( | |
| 1089 | .scan_in(reg_rd_en_a_scanin), | |
| 1090 | .scan_out(reg_rd_en_a_scanout), | |
| 1091 | .dout(rd_en_d1_a), | |
| 1092 | .l1clk(l1clk_in), | |
| 1093 | .din(rd_en_a), | |
| 1094 | .siclk(siclk), | |
| 1095 | .soclk(soclk)); | |
| 1096 | ||
| 1097 | //----------------------------------------------------------- | |
| 1098 | // output | |
| 1099 | //----------------------------------------------------------- | |
| 1100 | ||
| 1101 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_27 (.scan_in(reg_tag_way1_27_scanin), .scan_out(reg_tag_way1_27_scanout), | |
| 1102 | .din(sao_mx1[27]), .dout(tag_way1[27]), .l1clk(l1clk_out0), | |
| 1103 | .siclk(siclk), | |
| 1104 | .soclk(soclk)); | |
| 1105 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_27 (.scan_in(reg_tag_way0_27_scanin), .scan_out(reg_tag_way0_27_scanout), | |
| 1106 | .din(sao_mx0[27]), .dout(tag_way0[27]), .l1clk(l1clk_out0), | |
| 1107 | .siclk(siclk), | |
| 1108 | .soclk(soclk)); | |
| 1109 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_26 (.scan_in(reg_tag_way1_26_scanin), .scan_out(reg_tag_way1_26_scanout), | |
| 1110 | .din(sao_mx1[26]), .dout(tag_way1[26]), .l1clk(l1clk_out0), | |
| 1111 | .siclk(siclk), | |
| 1112 | .soclk(soclk)); | |
| 1113 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_26 (.scan_in(reg_tag_way0_26_scanin), .scan_out(reg_tag_way0_26_scanout), | |
| 1114 | .din(sao_mx0[26]), .dout(tag_way0[26]), .l1clk(l1clk_out0), | |
| 1115 | .siclk(siclk), | |
| 1116 | .soclk(soclk)); | |
| 1117 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_25 (.scan_in(reg_tag_way1_25_scanin), .scan_out(reg_tag_way1_25_scanout), | |
| 1118 | .din(sao_mx1[25]), .dout(tag_way1[25]), .l1clk(l1clk_out0), | |
| 1119 | .siclk(siclk), | |
| 1120 | .soclk(soclk)); | |
| 1121 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_25 (.scan_in(reg_tag_way0_25_scanin), .scan_out(reg_tag_way0_25_scanout), | |
| 1122 | .din(sao_mx0[25]), .dout(tag_way0[25]), .l1clk(l1clk_out0), | |
| 1123 | .siclk(siclk), | |
| 1124 | .soclk(soclk)); | |
| 1125 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_24 (.scan_in(reg_tag_way1_24_scanin), .scan_out(reg_tag_way1_24_scanout), | |
| 1126 | .din(sao_mx1[24]), .dout(tag_way1[24]), .l1clk(l1clk_out0), | |
| 1127 | .siclk(siclk), | |
| 1128 | .soclk(soclk)); | |
| 1129 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_24 (.scan_in(reg_tag_way0_24_scanin), .scan_out(reg_tag_way0_24_scanout), | |
| 1130 | .din(sao_mx0[24]), .dout(tag_way0[24]), .l1clk(l1clk_out0), | |
| 1131 | .siclk(siclk), | |
| 1132 | .soclk(soclk)); | |
| 1133 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_23 (.scan_in(reg_tag_way1_23_scanin), .scan_out(reg_tag_way1_23_scanout), | |
| 1134 | .din(sao_mx1[23]), .dout(tag_way1[23]), .l1clk(l1clk_out0), | |
| 1135 | .siclk(siclk), | |
| 1136 | .soclk(soclk)); | |
| 1137 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_23 (.scan_in(reg_tag_way0_23_scanin), .scan_out(reg_tag_way0_23_scanout), | |
| 1138 | .din(sao_mx0[23]), .dout(tag_way0[23]), .l1clk(l1clk_out0), | |
| 1139 | .siclk(siclk), | |
| 1140 | .soclk(soclk)); | |
| 1141 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_22 (.scan_in(reg_tag_way1_22_scanin), .scan_out(reg_tag_way1_22_scanout), | |
| 1142 | .din(sao_mx1[22]), .dout(tag_way1[22]), .l1clk(l1clk_out0), | |
| 1143 | .siclk(siclk), | |
| 1144 | .soclk(soclk)); | |
| 1145 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_22 (.scan_in(reg_tag_way0_22_scanin), .scan_out(reg_tag_way0_22_scanout), | |
| 1146 | .din(sao_mx0[22]), .dout(tag_way0[22]), .l1clk(l1clk_out0), | |
| 1147 | .siclk(siclk), | |
| 1148 | .soclk(soclk)); | |
| 1149 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_21 (.scan_in(reg_tag_way1_21_scanin), .scan_out(reg_tag_way1_21_scanout), | |
| 1150 | .din(sao_mx1[21]), .dout(tag_way1[21]), .l1clk(l1clk_out0), | |
| 1151 | .siclk(siclk), | |
| 1152 | .soclk(soclk)); | |
| 1153 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_21 (.scan_in(reg_tag_way0_21_scanin), .scan_out(reg_tag_way0_21_scanout), | |
| 1154 | .din(sao_mx0[21]), .dout(tag_way0[21]), .l1clk(l1clk_out0), | |
| 1155 | .siclk(siclk), | |
| 1156 | .soclk(soclk)); | |
| 1157 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_20 (.scan_in(reg_tag_way1_20_scanin), .scan_out(reg_tag_way1_20_scanout), | |
| 1158 | .din(sao_mx1[20]), .dout(tag_way1[20]), .l1clk(l1clk_out0), | |
| 1159 | .siclk(siclk), | |
| 1160 | .soclk(soclk)); | |
| 1161 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_20 (.scan_in(reg_tag_way0_20_scanin), .scan_out(reg_tag_way0_20_scanout), | |
| 1162 | .din(sao_mx0[20]), .dout(tag_way0[20]), .l1clk(l1clk_out0), | |
| 1163 | .siclk(siclk), | |
| 1164 | .soclk(soclk)); | |
| 1165 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_19 (.scan_in(reg_tag_way1_19_scanin), .scan_out(reg_tag_way1_19_scanout), | |
| 1166 | .din(sao_mx1[19]), .dout(tag_way1[19]), .l1clk(l1clk_out0), | |
| 1167 | .siclk(siclk), | |
| 1168 | .soclk(soclk)); | |
| 1169 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_19 (.scan_in(reg_tag_way0_19_scanin), .scan_out(reg_tag_way0_19_scanout), | |
| 1170 | .din(sao_mx0[19]), .dout(tag_way0[19]), .l1clk(l1clk_out0), | |
| 1171 | .siclk(siclk), | |
| 1172 | .soclk(soclk)); | |
| 1173 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_18 (.scan_in(reg_tag_way1_18_scanin), .scan_out(reg_tag_way1_18_scanout), | |
| 1174 | .din(sao_mx1[18]), .dout(tag_way1[18]), .l1clk(l1clk_out0), | |
| 1175 | .siclk(siclk), | |
| 1176 | .soclk(soclk)); | |
| 1177 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_18 (.scan_in(reg_tag_way0_18_scanin), .scan_out(reg_tag_way0_18_scanout), | |
| 1178 | .din(sao_mx0[18]), .dout(tag_way0[18]), .l1clk(l1clk_out0), | |
| 1179 | .siclk(siclk), | |
| 1180 | .soclk(soclk)); | |
| 1181 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_17 (.scan_in(reg_tag_way1_17_scanin), .scan_out(reg_tag_way1_17_scanout), | |
| 1182 | .din(sao_mx1[17]), .dout(tag_way1[17]), .l1clk(l1clk_out0), | |
| 1183 | .siclk(siclk), | |
| 1184 | .soclk(soclk)); | |
| 1185 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_17 (.scan_in(reg_tag_way0_17_scanin), .scan_out(reg_tag_way0_17_scanout), | |
| 1186 | .din(sao_mx0[17]), .dout(tag_way0[17]), .l1clk(l1clk_out0), | |
| 1187 | .siclk(siclk), | |
| 1188 | .soclk(soclk)); | |
| 1189 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_16 (.scan_in(reg_tag_way1_16_scanin), .scan_out(reg_tag_way1_16_scanout), | |
| 1190 | .din(sao_mx1[16]), .dout(tag_way1[16]), .l1clk(l1clk_out0), | |
| 1191 | .siclk(siclk), | |
| 1192 | .soclk(soclk)); | |
| 1193 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_16 (.scan_in(reg_tag_way0_16_scanin), .scan_out(reg_tag_way0_16_scanout), | |
| 1194 | .din(sao_mx0[16]), .dout(tag_way0[16]), .l1clk(l1clk_out0), | |
| 1195 | .siclk(siclk), | |
| 1196 | .soclk(soclk)); | |
| 1197 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_15 (.scan_in(reg_tag_way1_15_scanin), .scan_out(reg_tag_way1_15_scanout), | |
| 1198 | .din(sao_mx1[15]), .dout(tag_way1[15]), .l1clk(l1clk_out0), | |
| 1199 | .siclk(siclk), | |
| 1200 | .soclk(soclk)); | |
| 1201 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_15 (.scan_in(reg_tag_way0_15_scanin), .scan_out(reg_tag_way0_15_scanout), | |
| 1202 | .din(sao_mx0[15]), .dout(tag_way0[15]), .l1clk(l1clk_out0), | |
| 1203 | .siclk(siclk), | |
| 1204 | .soclk(soclk)); | |
| 1205 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_14 (.scan_in(reg_tag_way1_14_scanin), .scan_out(reg_tag_way1_14_scanout), | |
| 1206 | .din(sao_mx1[14]), .dout(tag_way1[14]), .l1clk(l1clk_out0), | |
| 1207 | .siclk(siclk), | |
| 1208 | .soclk(soclk)); | |
| 1209 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_14 (.scan_in(reg_tag_way0_14_scanin), .scan_out(reg_tag_way0_14_scanout), | |
| 1210 | .din(sao_mx0[14]), .dout(tag_way0[14]), .l1clk(l1clk_out0), | |
| 1211 | .siclk(siclk), | |
| 1212 | .soclk(soclk)); | |
| 1213 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_13 (.scan_in(reg_tag_way1_13_scanin), .scan_out(reg_tag_way1_13_scanout), | |
| 1214 | .din(sao_mx1[13]), .dout(tag_way1[13]), .l1clk(l1clk_out0), | |
| 1215 | .siclk(siclk), | |
| 1216 | .soclk(soclk)); | |
| 1217 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_13 (.scan_in(reg_tag_way0_13_scanin), .scan_out(reg_tag_way0_13_scanout), | |
| 1218 | .din(sao_mx0[13]), .dout(tag_way0[13]), .l1clk(l1clk_out0), | |
| 1219 | .siclk(siclk), | |
| 1220 | .soclk(soclk)); | |
| 1221 | ||
| 1222 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_12 (.scan_in(reg_tag_way1_12_scanin), .scan_out(reg_tag_way1_12_scanout), | |
| 1223 | .din(sao_mx1[12]), .dout(tag_way1[12]), .l1clk(l1clk_out1), | |
| 1224 | .siclk(siclk), | |
| 1225 | .soclk(soclk)); | |
| 1226 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_12 (.scan_in(reg_tag_way0_12_scanin), .scan_out(reg_tag_way0_12_scanout), | |
| 1227 | .din(sao_mx0[12]), .dout(tag_way0[12]), .l1clk(l1clk_out1), | |
| 1228 | .siclk(siclk), | |
| 1229 | .soclk(soclk)); | |
| 1230 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_11 (.scan_in(reg_tag_way1_11_scanin), .scan_out(reg_tag_way1_11_scanout), | |
| 1231 | .din(sao_mx1[11]), .dout(tag_way1[11]), .l1clk(l1clk_out1), | |
| 1232 | .siclk(siclk), | |
| 1233 | .soclk(soclk)); | |
| 1234 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_11 (.scan_in(reg_tag_way0_11_scanin), .scan_out(reg_tag_way0_11_scanout), | |
| 1235 | .din(sao_mx0[11]), .dout(tag_way0[11]), .l1clk(l1clk_out1), | |
| 1236 | .siclk(siclk), | |
| 1237 | .soclk(soclk)); | |
| 1238 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_10 (.scan_in(reg_tag_way1_10_scanin), .scan_out(reg_tag_way1_10_scanout), | |
| 1239 | .din(sao_mx1[10]), .dout(tag_way1[10]), .l1clk(l1clk_out1), | |
| 1240 | .siclk(siclk), | |
| 1241 | .soclk(soclk)); | |
| 1242 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_10 (.scan_in(reg_tag_way0_10_scanin), .scan_out(reg_tag_way0_10_scanout), | |
| 1243 | .din(sao_mx0[10]), .dout(tag_way0[10]), .l1clk(l1clk_out1), | |
| 1244 | .siclk(siclk), | |
| 1245 | .soclk(soclk)); | |
| 1246 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_9 (.scan_in(reg_tag_way1_9_scanin), .scan_out(reg_tag_way1_9_scanout), | |
| 1247 | .din(sao_mx1[9]), .dout(tag_way1[9]), .l1clk(l1clk_out1), | |
| 1248 | .siclk(siclk), | |
| 1249 | .soclk(soclk)); | |
| 1250 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_9 (.scan_in(reg_tag_way0_9_scanin), .scan_out(reg_tag_way0_9_scanout), | |
| 1251 | .din(sao_mx0[9]), .dout(tag_way0[9]), .l1clk(l1clk_out1), | |
| 1252 | .siclk(siclk), | |
| 1253 | .soclk(soclk)); | |
| 1254 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_8 (.scan_in(reg_tag_way1_8_scanin), .scan_out(reg_tag_way1_8_scanout), | |
| 1255 | .din(sao_mx1[8]), .dout(tag_way1[8]), .l1clk(l1clk_out1), | |
| 1256 | .siclk(siclk), | |
| 1257 | .soclk(soclk)); | |
| 1258 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_8 (.scan_in(reg_tag_way0_8_scanin), .scan_out(reg_tag_way0_8_scanout), | |
| 1259 | .din(sao_mx0[8]), .dout(tag_way0[8]), .l1clk(l1clk_out1), | |
| 1260 | .siclk(siclk), | |
| 1261 | .soclk(soclk)); | |
| 1262 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_7 (.scan_in(reg_tag_way1_7_scanin), .scan_out(reg_tag_way1_7_scanout), | |
| 1263 | .din(sao_mx1[7]), .dout(tag_way1[7]), .l1clk(l1clk_out1), | |
| 1264 | .siclk(siclk), | |
| 1265 | .soclk(soclk)); | |
| 1266 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_7 (.scan_in(reg_tag_way0_7_scanin), .scan_out(reg_tag_way0_7_scanout), | |
| 1267 | .din(sao_mx0[7]), .dout(tag_way0[7]), .l1clk(l1clk_out1), | |
| 1268 | .siclk(siclk), | |
| 1269 | .soclk(soclk)); | |
| 1270 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_6 (.scan_in(reg_tag_way1_6_scanin), .scan_out(reg_tag_way1_6_scanout), | |
| 1271 | .din(sao_mx1[6]), .dout(tag_way1[6]), .l1clk(l1clk_out1), | |
| 1272 | .siclk(siclk), | |
| 1273 | .soclk(soclk)); | |
| 1274 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_6 (.scan_in(reg_tag_way0_6_scanin), .scan_out(reg_tag_way0_6_scanout), | |
| 1275 | .din(sao_mx0[6]), .dout(tag_way0[6]), .l1clk(l1clk_out1), | |
| 1276 | .siclk(siclk), | |
| 1277 | .soclk(soclk)); | |
| 1278 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_5 (.scan_in(reg_tag_way1_5_scanin), .scan_out(reg_tag_way1_5_scanout), | |
| 1279 | .din(sao_mx1[5]), .dout(tag_way1[5]), .l1clk(l1clk_out1), | |
| 1280 | .siclk(siclk), | |
| 1281 | .soclk(soclk)); | |
| 1282 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_5 (.scan_in(reg_tag_way0_5_scanin), .scan_out(reg_tag_way0_5_scanout), | |
| 1283 | .din(sao_mx0[5]), .dout(tag_way0[5]), .l1clk(l1clk_out1), | |
| 1284 | .siclk(siclk), | |
| 1285 | .soclk(soclk)); | |
| 1286 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_4 (.scan_in(reg_tag_way1_4_scanin), .scan_out(reg_tag_way1_4_scanout), | |
| 1287 | .din(sao_mx1[4]), .dout(tag_way1[4]), .l1clk(l1clk_out1), | |
| 1288 | .siclk(siclk), | |
| 1289 | .soclk(soclk)); | |
| 1290 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_4 (.scan_in(reg_tag_way0_4_scanin), .scan_out(reg_tag_way0_4_scanout), | |
| 1291 | .din(sao_mx0[4]), .dout(tag_way0[4]), .l1clk(l1clk_out1), | |
| 1292 | .siclk(siclk), | |
| 1293 | .soclk(soclk)); | |
| 1294 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_3 (.scan_in(reg_tag_way1_3_scanin), .scan_out(reg_tag_way1_3_scanout), | |
| 1295 | .din(sao_mx1[3]), .dout(tag_way1[3]), .l1clk(l1clk_out1), | |
| 1296 | .siclk(siclk), | |
| 1297 | .soclk(soclk)); | |
| 1298 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_3 (.scan_in(reg_tag_way0_3_scanin), .scan_out(reg_tag_way0_3_scanout), | |
| 1299 | .din(sao_mx0[3]), .dout(tag_way0[3]), .l1clk(l1clk_out1), | |
| 1300 | .siclk(siclk), | |
| 1301 | .soclk(soclk)); | |
| 1302 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_2 (.scan_in(reg_tag_way1_2_scanin), .scan_out(reg_tag_way1_2_scanout), | |
| 1303 | .din(sao_mx1[2]), .dout(tag_way1[2]), .l1clk(l1clk_out1), | |
| 1304 | .siclk(siclk), | |
| 1305 | .soclk(soclk)); | |
| 1306 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_2 (.scan_in(reg_tag_way0_2_scanin), .scan_out(reg_tag_way0_2_scanout), | |
| 1307 | .din(sao_mx0[2]), .dout(tag_way0[2]), .l1clk(l1clk_out1), | |
| 1308 | .siclk(siclk), | |
| 1309 | .soclk(soclk)); | |
| 1310 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_1 (.scan_in(reg_tag_way1_1_scanin), .scan_out(reg_tag_way1_1_scanout), | |
| 1311 | .din(sao_mx1[1]), .dout(tag_way1[1]), .l1clk(l1clk_out1), | |
| 1312 | .siclk(siclk), | |
| 1313 | .soclk(soclk)); | |
| 1314 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_1 (.scan_in(reg_tag_way0_1_scanin), .scan_out(reg_tag_way0_1_scanout), | |
| 1315 | .din(sao_mx0[1]), .dout(tag_way0[1]), .l1clk(l1clk_out1), | |
| 1316 | .siclk(siclk), | |
| 1317 | .soclk(soclk)); | |
| 1318 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way1_0 (.scan_in(reg_tag_way1_0_scanin), .scan_out(reg_tag_way1_0_scanout), | |
| 1319 | .din(sao_mx1[0]), .dout(tag_way1[0]), .l1clk(l1clk_out1), | |
| 1320 | .siclk(siclk), | |
| 1321 | .soclk(soclk)); | |
| 1322 | n2_l2t_bank_msff_ctl_macro__width_1 reg_tag_way0_0 (.scan_in(reg_tag_way0_0_scanin), .scan_out(reg_tag_way0_0_scanout), | |
| 1323 | .din(sao_mx0[0]), .dout(tag_way0[0]), .l1clk(l1clk_out1), | |
| 1324 | .siclk(siclk), | |
| 1325 | .soclk(soclk)); | |
| 1326 | ||
| 1327 | n2_l2t_bank_msffi_ctl_macro__clockwidth_0__width_1 reg_way_hit_a0 (.scan_in(reg_way_hit_a0_scanin), .scan_out(reg_way_hit_a0_scanout), | |
| 1328 | .din(w0_cmp27to1), .q_l(way_hit_a[0]), .l1clk(l1clk_out1), | |
| 1329 | .siclk(siclk), | |
| 1330 | .soclk(soclk)); | |
| 1331 | n2_l2t_bank_msffi_ctl_macro__clockwidth_0__width_1 reg_way_hit_a1 (.scan_in(reg_way_hit_a1_scanin), .scan_out(reg_way_hit_a1_scanout), | |
| 1332 | .din(w1_cmp27to1), .q_l(way_hit_a[1]), .l1clk(l1clk_out1), | |
| 1333 | .siclk(siclk), | |
| 1334 | .soclk(soclk)); | |
| 1335 | ||
| 1336 | ||
| 1337 | // =============== VERILOG-MODE AUTO TEMPLATES | |
| 1338 | ||
| 1339 | /* | |
| 1340 | ||
| 1341 | n2_l2t_array AUTO_TEMPLATE ( | |
| 1342 | .din(din[`L2T_ARR_D_WIDTH - 1 : 0]), | |
| 1343 | .l1clk_internal_v1 (l1clk_int), | |
| 1344 | .l1clk_internal_v2 (l1clk_int), | |
| 1345 | ||
| 1346 | ); | |
| 1347 | ||
| 1348 | */ | |
| 1349 | // Manual scan hookup : | |
| 1350 | ||
| 1351 | assign reg_tag_way1_27_scanin = scan_in ; | |
| 1352 | assign reg_tag_way0_27_scanin = reg_tag_way1_27_scanout ; | |
| 1353 | assign reg_tag_way1_26_scanin = reg_tag_way0_27_scanout ; | |
| 1354 | assign reg_tag_way0_26_scanin = reg_tag_way1_26_scanout ; | |
| 1355 | assign reg_tag_way1_25_scanin = reg_tag_way0_26_scanout ; | |
| 1356 | assign reg_tag_way0_25_scanin = reg_tag_way1_25_scanout ; | |
| 1357 | assign reg_tag_way1_24_scanin = reg_tag_way0_25_scanout ; | |
| 1358 | assign reg_tag_way0_24_scanin = reg_tag_way1_24_scanout ; | |
| 1359 | assign reg_tag_way1_23_scanin = reg_tag_way0_24_scanout ; | |
| 1360 | assign reg_tag_way0_23_scanin = reg_tag_way1_23_scanout ; | |
| 1361 | assign reg_tag_way1_22_scanin = reg_tag_way0_23_scanout ; | |
| 1362 | assign reg_tag_way0_22_scanin = reg_tag_way1_22_scanout ; | |
| 1363 | assign reg_tag_way1_21_scanin = reg_tag_way0_22_scanout ; | |
| 1364 | assign reg_tag_way0_21_scanin = reg_tag_way1_21_scanout ; | |
| 1365 | assign reg_tag_way1_20_scanin = reg_tag_way0_21_scanout ; | |
| 1366 | assign reg_tag_way0_20_scanin = reg_tag_way1_20_scanout ; | |
| 1367 | assign reg_tag_way1_19_scanin = reg_tag_way0_20_scanout ; | |
| 1368 | assign reg_tag_way0_19_scanin = reg_tag_way1_19_scanout ; | |
| 1369 | assign reg_tag_way1_18_scanin = reg_tag_way0_19_scanout ; | |
| 1370 | assign reg_tag_way0_18_scanin = reg_tag_way1_18_scanout ; | |
| 1371 | assign reg_tag_way1_17_scanin = reg_tag_way0_18_scanout ; | |
| 1372 | assign reg_tag_way0_17_scanin = reg_tag_way1_17_scanout ; | |
| 1373 | assign reg_tag_way1_16_scanin = reg_tag_way0_17_scanout ; | |
| 1374 | assign reg_tag_way0_16_scanin = reg_tag_way1_16_scanout ; | |
| 1375 | assign reg_tag_way1_15_scanin = reg_tag_way0_16_scanout ; | |
| 1376 | assign reg_tag_way0_15_scanin = reg_tag_way1_15_scanout ; | |
| 1377 | assign reg_tag_way1_14_scanin = reg_tag_way0_15_scanout ; | |
| 1378 | assign reg_tag_way0_14_scanin = reg_tag_way1_14_scanout ; | |
| 1379 | assign reg_tag_way1_13_scanin = reg_tag_way0_14_scanout ; | |
| 1380 | assign reg_tag_way0_13_scanin = reg_tag_way1_13_scanout ; | |
| 1381 | ||
| 1382 | ||
| 1383 | assign reg_way_hit_a0_scanin = reg_tag_way0_13_scanout ; | |
| 1384 | assign reg_way_hit_a1_scanin = reg_way_hit_a0_scanout ; | |
| 1385 | ||
| 1386 | assign reg_addr_b_8_scanin = reg_way_hit_a1_scanout ; | |
| 1387 | assign reg_addr_b_7_scanin = reg_addr_b_8_scanout ; | |
| 1388 | assign reg_addr_b_6_scanin = reg_addr_b_7_scanout ; | |
| 1389 | assign reg_addr_b_5_scanin = reg_addr_b_6_scanout ; | |
| 1390 | assign reg_addr_b_4_scanin = reg_addr_b_5_scanout ; | |
| 1391 | assign reg_addr_b_3_scanin = reg_addr_b_4_scanout ; | |
| 1392 | assign reg_addr_b_2_scanin = reg_addr_b_3_scanout ; | |
| 1393 | assign reg_addr_b_1_scanin = reg_addr_b_2_scanout ; | |
| 1394 | ||
| 1395 | assign reg_wr_way_b_scanin = reg_addr_b_1_scanout ; | |
| 1396 | assign reg_addr_b_0_scanin = reg_wr_way_b_scanout ; | |
| 1397 | assign reg_wr_en_b_scanin = reg_addr_b_0_scanout ; | |
| 1398 | assign reg_rd_en_b_scanin = reg_wr_en_b_scanout ; | |
| 1399 | assign reg_wr_en_a_scanin = reg_rd_en_b_scanout ; | |
| 1400 | assign reg_rd_en_a_scanin = reg_wr_en_a_scanout ; | |
| 1401 | ||
| 1402 | assign reg_tag_way1_12_scanin = reg_rd_en_a_scanout ; | |
| 1403 | assign reg_tag_way0_12_scanin = reg_tag_way1_12_scanout ; | |
| 1404 | assign reg_tag_way1_11_scanin = reg_tag_way0_12_scanout ; | |
| 1405 | assign reg_tag_way0_11_scanin = reg_tag_way1_11_scanout ; | |
| 1406 | assign reg_tag_way1_10_scanin = reg_tag_way0_11_scanout ; | |
| 1407 | assign reg_tag_way0_10_scanin = reg_tag_way1_10_scanout ; | |
| 1408 | assign reg_tag_way1_9_scanin = reg_tag_way0_10_scanout ; | |
| 1409 | assign reg_tag_way0_9_scanin = reg_tag_way1_9_scanout ; | |
| 1410 | assign reg_tag_way1_8_scanin = reg_tag_way0_9_scanout ; | |
| 1411 | assign reg_tag_way0_8_scanin = reg_tag_way1_8_scanout ; | |
| 1412 | assign reg_tag_way1_7_scanin = reg_tag_way0_8_scanout ; | |
| 1413 | assign reg_tag_way0_7_scanin = reg_tag_way1_7_scanout ; | |
| 1414 | assign reg_tag_way1_6_scanin = reg_tag_way0_7_scanout ; | |
| 1415 | assign reg_tag_way0_6_scanin = reg_tag_way1_6_scanout ; | |
| 1416 | assign reg_tag_way1_5_scanin = reg_tag_way0_6_scanout ; | |
| 1417 | assign reg_tag_way0_5_scanin = reg_tag_way1_5_scanout ; | |
| 1418 | assign reg_tag_way1_4_scanin = reg_tag_way0_5_scanout ; | |
| 1419 | assign reg_tag_way0_4_scanin = reg_tag_way1_4_scanout ; | |
| 1420 | assign reg_tag_way1_3_scanin = reg_tag_way0_4_scanout ; | |
| 1421 | assign reg_tag_way0_3_scanin = reg_tag_way1_3_scanout ; | |
| 1422 | assign reg_tag_way1_2_scanin = reg_tag_way0_3_scanout ; | |
| 1423 | assign reg_tag_way0_2_scanin = reg_tag_way1_2_scanout ; | |
| 1424 | assign reg_tag_way1_1_scanin = reg_tag_way0_2_scanout ; | |
| 1425 | assign reg_tag_way0_1_scanin = reg_tag_way1_1_scanout ; | |
| 1426 | assign reg_tag_way1_0_scanin = reg_tag_way0_1_scanout ; | |
| 1427 | assign reg_tag_way0_0_scanin = reg_tag_way1_0_scanout ; | |
| 1428 | ||
| 1429 | assign scan_out = reg_tag_way0_0_scanout ; | |
| 1430 | endmodule | |
| 1431 | ||
| 1432 | ||
| 1433 | ||
| 1434 | ||
| 1435 | ||
| 1436 | ||
| 1437 | ||
| 1438 | ||
| 1439 | // any PARAMS parms go into naming of macro | |
| 1440 | ||
| 1441 | module n2_l2t_bank_l1clkhdr_ctl_macro ( | |
| 1442 | l2clk, | |
| 1443 | l1en, | |
| 1444 | pce_ov, | |
| 1445 | stop, | |
| 1446 | se, | |
| 1447 | l1clk); | |
| 1448 | ||
| 1449 | ||
| 1450 | input l2clk; | |
| 1451 | input l1en; | |
| 1452 | input pce_ov; | |
| 1453 | input stop; | |
| 1454 | input se; | |
| 1455 | output l1clk; | |
| 1456 | ||
| 1457 | ||
| 1458 | ||
| 1459 | ||
| 1460 | ||
| 1461 | cl_sc1_l1hdr_8x c_0 ( | |
| 1462 | ||
| 1463 | ||
| 1464 | .l2clk(l2clk), | |
| 1465 | .pce(l1en), | |
| 1466 | .l1clk(l1clk), | |
| 1467 | .se(se), | |
| 1468 | .pce_ov(pce_ov), | |
| 1469 | .stop(stop) | |
| 1470 | ); | |
| 1471 | ||
| 1472 | ||
| 1473 | ||
| 1474 | endmodule | |
| 1475 | ||
| 1476 | ||
| 1477 | ||
| 1478 | ||
| 1479 | ||
| 1480 | ||
| 1481 | ||
| 1482 | ||
| 1483 | ||
| 1484 | // | |
| 1485 | // nor macro for ports = 2,3 | |
| 1486 | // | |
| 1487 | // | |
| 1488 | ||
| 1489 | ||
| 1490 | ||
| 1491 | ||
| 1492 | ||
| 1493 | module n2_l2t_bank_nor_macro__ports_3__width_1 ( | |
| 1494 | din0, | |
| 1495 | din1, | |
| 1496 | din2, | |
| 1497 | dout); | |
| 1498 | input [0:0] din0; | |
| 1499 | input [0:0] din1; | |
| 1500 | input [0:0] din2; | |
| 1501 | output [0:0] dout; | |
| 1502 | ||
| 1503 | ||
| 1504 | ||
| 1505 | ||
| 1506 | ||
| 1507 | ||
| 1508 | nor3 #(1) d0_0 ( | |
| 1509 | .in0(din0[0:0]), | |
| 1510 | .in1(din1[0:0]), | |
| 1511 | .in2(din2[0:0]), | |
| 1512 | .out(dout[0:0]) | |
| 1513 | ); | |
| 1514 | ||
| 1515 | ||
| 1516 | ||
| 1517 | ||
| 1518 | ||
| 1519 | ||
| 1520 | ||
| 1521 | endmodule | |
| 1522 | ||
| 1523 | ||
| 1524 | ||
| 1525 | ||
| 1526 | ||
| 1527 | // | |
| 1528 | // nand macro for ports = 2,3,4 | |
| 1529 | // | |
| 1530 | // | |
| 1531 | ||
| 1532 | ||
| 1533 | ||
| 1534 | ||
| 1535 | ||
| 1536 | module n2_l2t_bank_nand_macro__ports_4__width_1 ( | |
| 1537 | din0, | |
| 1538 | din1, | |
| 1539 | din2, | |
| 1540 | din3, | |
| 1541 | dout); | |
| 1542 | input [0:0] din0; | |
| 1543 | input [0:0] din1; | |
| 1544 | input [0:0] din2; | |
| 1545 | input [0:0] din3; | |
| 1546 | output [0:0] dout; | |
| 1547 | ||
| 1548 | ||
| 1549 | ||
| 1550 | ||
| 1551 | ||
| 1552 | ||
| 1553 | nand4 #(1) d0_0 ( | |
| 1554 | .in0(din0[0:0]), | |
| 1555 | .in1(din1[0:0]), | |
| 1556 | .in2(din2[0:0]), | |
| 1557 | .in3(din3[0:0]), | |
| 1558 | .out(dout[0:0]) | |
| 1559 | ); | |
| 1560 | ||
| 1561 | ||
| 1562 | ||
| 1563 | ||
| 1564 | ||
| 1565 | ||
| 1566 | ||
| 1567 | ||
| 1568 | ||
| 1569 | endmodule | |
| 1570 | ||
| 1571 | ||
| 1572 | ||
| 1573 | ||
| 1574 | ||
| 1575 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 1576 | // also for pass-gate with decoder | |
| 1577 | ||
| 1578 | ||
| 1579 | ||
| 1580 | ||
| 1581 | ||
| 1582 | // any PARAMS parms go into naming of macro | |
| 1583 | ||
| 1584 | module n2_l2t_bank_mux_macro__mux_aonpe__ports_2__stack_156c__width_5 ( | |
| 1585 | din0, | |
| 1586 | sel0, | |
| 1587 | din1, | |
| 1588 | sel1, | |
| 1589 | dout); | |
| 1590 | wire buffout0; | |
| 1591 | wire buffout1; | |
| 1592 | ||
| 1593 | input [4:0] din0; | |
| 1594 | input sel0; | |
| 1595 | input [4:0] din1; | |
| 1596 | input sel1; | |
| 1597 | output [4:0] dout; | |
| 1598 | ||
| 1599 | ||
| 1600 | ||
| 1601 | ||
| 1602 | ||
| 1603 | cl_dp1_muxbuff2_8x c0_0 ( | |
| 1604 | .in0(sel0), | |
| 1605 | .in1(sel1), | |
| 1606 | .out0(buffout0), | |
| 1607 | .out1(buffout1) | |
| 1608 | ); | |
| 1609 | mux2s #(5) d0_0 ( | |
| 1610 | .sel0(buffout0), | |
| 1611 | .sel1(buffout1), | |
| 1612 | .in0(din0[4:0]), | |
| 1613 | .in1(din1[4:0]), | |
| 1614 | .dout(dout[4:0]) | |
| 1615 | ); | |
| 1616 | ||
| 1617 | ||
| 1618 | ||
| 1619 | ||
| 1620 | ||
| 1621 | ||
| 1622 | ||
| 1623 | ||
| 1624 | ||
| 1625 | ||
| 1626 | ||
| 1627 | ||
| 1628 | ||
| 1629 | endmodule | |
| 1630 | ||
| 1631 | ||
| 1632 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
| 1633 | // also for pass-gate with decoder | |
| 1634 | ||
| 1635 | ||
| 1636 | ||
| 1637 | ||
| 1638 | ||
| 1639 | // any PARAMS parms go into naming of macro | |
| 1640 | ||
| 1641 | module n2_l2t_bank_mux_macro__mux_aonpe__ports_2__stack_156c__width_2 ( | |
| 1642 | din0, | |
| 1643 | sel0, | |
| 1644 | din1, | |
| 1645 | sel1, | |
| 1646 | dout); | |
| 1647 | wire buffout0; | |
| 1648 | wire buffout1; | |
| 1649 | ||
| 1650 | input [1:0] din0; | |
| 1651 | input sel0; | |
| 1652 | input [1:0] din1; | |
| 1653 | input sel1; | |
| 1654 | output [1:0] dout; | |
| 1655 | ||
| 1656 | ||
| 1657 | ||
| 1658 | ||
| 1659 | ||
| 1660 | cl_dp1_muxbuff2_8x c0_0 ( | |
| 1661 | .in0(sel0), | |
| 1662 | .in1(sel1), | |
| 1663 | .out0(buffout0), | |
| 1664 | .out1(buffout1) | |
| 1665 | ); | |
| 1666 | mux2s #(2) d0_0 ( | |
| 1667 | .sel0(buffout0), | |
| 1668 | .sel1(buffout1), | |
| 1669 | .in0(din0[1:0]), | |
| 1670 | .in1(din1[1:0]), | |
| 1671 | .dout(dout[1:0]) | |
| 1672 | ); | |
| 1673 | ||
| 1674 | ||
| 1675 | ||
| 1676 | ||
| 1677 | ||
| 1678 | ||
| 1679 | ||
| 1680 | ||
| 1681 | ||
| 1682 | ||
| 1683 | ||
| 1684 | ||
| 1685 | ||
| 1686 | endmodule | |
| 1687 | ||
| 1688 | ||
| 1689 | // | |
| 1690 | // invert macro | |
| 1691 | // | |
| 1692 | // | |
| 1693 | ||
| 1694 | ||
| 1695 | ||
| 1696 | ||
| 1697 | ||
| 1698 | module n2_l2t_bank_inv_macro__width_1 ( | |
| 1699 | din, | |
| 1700 | dout); | |
| 1701 | input [0:0] din; | |
| 1702 | output [0:0] dout; | |
| 1703 | ||
| 1704 | ||
| 1705 | ||
| 1706 | ||
| 1707 | ||
| 1708 | ||
| 1709 | inv #(1) d0_0 ( | |
| 1710 | .in(din[0:0]), | |
| 1711 | .out(dout[0:0]) | |
| 1712 | ); | |
| 1713 | ||
| 1714 | ||
| 1715 | ||
| 1716 | ||
| 1717 | ||
| 1718 | ||
| 1719 | ||
| 1720 | ||
| 1721 | ||
| 1722 | endmodule | |
| 1723 | ||
| 1724 | ||
| 1725 | ||
| 1726 | ||
| 1727 | ||
| 1728 | // | |
| 1729 | // or macro for ports = 2,3 | |
| 1730 | // | |
| 1731 | // | |
| 1732 | ||
| 1733 | ||
| 1734 | ||
| 1735 | ||
| 1736 | ||
| 1737 | module n2_l2t_bank_or_macro__ports_2__width_1 ( | |
| 1738 | din0, | |
| 1739 | din1, | |
| 1740 | dout); | |
| 1741 | input [0:0] din0; | |
| 1742 | input [0:0] din1; | |
| 1743 | output [0:0] dout; | |
| 1744 | ||
| 1745 | ||
| 1746 | ||
| 1747 | ||
| 1748 | ||
| 1749 | ||
| 1750 | or2 #(1) d0_0 ( | |
| 1751 | .in0(din0[0:0]), | |
| 1752 | .in1(din1[0:0]), | |
| 1753 | .out(dout[0:0]) | |
| 1754 | ); | |
| 1755 | ||
| 1756 | ||
| 1757 | ||
| 1758 | ||
| 1759 | ||
| 1760 | ||
| 1761 | ||
| 1762 | ||
| 1763 | ||
| 1764 | endmodule | |
| 1765 | ||
| 1766 | ||
| 1767 | ||
| 1768 | ||
| 1769 | ||
| 1770 | // | |
| 1771 | // and macro for ports = 2,3,4 | |
| 1772 | // | |
| 1773 | // | |
| 1774 | ||
| 1775 | ||
| 1776 | ||
| 1777 | ||
| 1778 | ||
| 1779 | module n2_l2t_bank_and_macro__ports_2__width_1 ( | |
| 1780 | din0, | |
| 1781 | din1, | |
| 1782 | dout); | |
| 1783 | input [0:0] din0; | |
| 1784 | input [0:0] din1; | |
| 1785 | output [0:0] dout; | |
| 1786 | ||
| 1787 | ||
| 1788 | ||
| 1789 | ||
| 1790 | ||
| 1791 | ||
| 1792 | and2 #(1) d0_0 ( | |
| 1793 | .in0(din0[0:0]), | |
| 1794 | .in1(din1[0:0]), | |
| 1795 | .out(dout[0:0]) | |
| 1796 | ); | |
| 1797 | ||
| 1798 | ||
| 1799 | ||
| 1800 | ||
| 1801 | ||
| 1802 | ||
| 1803 | ||
| 1804 | ||
| 1805 | ||
| 1806 | endmodule | |
| 1807 | ||
| 1808 | ||
| 1809 | ||
| 1810 | ||
| 1811 | ||
| 1812 | // | |
| 1813 | // invert macro | |
| 1814 | // | |
| 1815 | // | |
| 1816 | ||
| 1817 | ||
| 1818 | ||
| 1819 | ||
| 1820 | ||
| 1821 | module n2_l2t_bank_inv_macro__width_5 ( | |
| 1822 | din, | |
| 1823 | dout); | |
| 1824 | input [4:0] din; | |
| 1825 | output [4:0] dout; | |
| 1826 | ||
| 1827 | ||
| 1828 | ||
| 1829 | ||
| 1830 | ||
| 1831 | ||
| 1832 | inv #(5) d0_0 ( | |
| 1833 | .in(din[4:0]), | |
| 1834 | .out(dout[4:0]) | |
| 1835 | ); | |
| 1836 | ||
| 1837 | ||
| 1838 | ||
| 1839 | ||
| 1840 | ||
| 1841 | ||
| 1842 | ||
| 1843 | ||
| 1844 | ||
| 1845 | endmodule | |
| 1846 | ||
| 1847 | ||
| 1848 | ||
| 1849 | ||
| 1850 | ||
| 1851 | // | |
| 1852 | // and macro for ports = 2,3,4 | |
| 1853 | // | |
| 1854 | // | |
| 1855 | ||
| 1856 | ||
| 1857 | ||
| 1858 | ||
| 1859 | ||
| 1860 | module n2_l2t_bank_and_macro__ports_3__width_1 ( | |
| 1861 | din0, | |
| 1862 | din1, | |
| 1863 | din2, | |
| 1864 | dout); | |
| 1865 | input [0:0] din0; | |
| 1866 | input [0:0] din1; | |
| 1867 | input [0:0] din2; | |
| 1868 | output [0:0] dout; | |
| 1869 | ||
| 1870 | ||
| 1871 | ||
| 1872 | ||
| 1873 | ||
| 1874 | ||
| 1875 | and3 #(1) d0_0 ( | |
| 1876 | .in0(din0[0:0]), | |
| 1877 | .in1(din1[0:0]), | |
| 1878 | .in2(din2[0:0]), | |
| 1879 | .out(dout[0:0]) | |
| 1880 | ); | |
| 1881 | ||
| 1882 | ||
| 1883 | ||
| 1884 | ||
| 1885 | ||
| 1886 | ||
| 1887 | ||
| 1888 | ||
| 1889 | ||
| 1890 | endmodule | |
| 1891 | ||
| 1892 | ||
| 1893 | ||
| 1894 | ||
| 1895 | ||
| 1896 | ||
| 1897 | ||
| 1898 | ||
| 1899 | `define L2T_ARR_D_WIDTH 28 | |
| 1900 | `define L2T_ARR_DEPTH 512 | |
| 1901 | `define WAY_HIT_WIDTH 16 | |
| 1902 | `define BADREAD BADBADD | |
| 1903 | ||
| 1904 | ||
| 1905 | `define sh_index_lft 5'b00000 | |
| 1906 | `define sh_index_rgt 5'b00000 | |
| 1907 | ||
| 1908 | module n2_l2t_array ( | |
| 1909 | din, | |
| 1910 | addr_b, | |
| 1911 | l1clk_internal_v1, | |
| 1912 | l1clk_internal_v2, | |
| 1913 | ln1clk, | |
| 1914 | ln2clk, | |
| 1915 | rd_en_b, | |
| 1916 | rd_en_d1_a, | |
| 1917 | rpda_lft, | |
| 1918 | rpda_rgt, | |
| 1919 | rpdb_lft, | |
| 1920 | rpdb_rgt, | |
| 1921 | rpdc_lft, | |
| 1922 | rpdc_rgt, | |
| 1923 | w_inhibit_l, | |
| 1924 | wr_en_b, | |
| 1925 | wr_en_d1_a, | |
| 1926 | wr_way_b, | |
| 1927 | wr_way_b_l, | |
| 1928 | vnw_ary, | |
| 1929 | sao_mx0_h, | |
| 1930 | sao_mx0_l, | |
| 1931 | sao_mx1_h, | |
| 1932 | sao_mx1_l); | |
| 1933 | wire ln1clk_unused; | |
| 1934 | wire ln2clk_unused; | |
| 1935 | wire l1clk_int_v2_unused; | |
| 1936 | wire rd_en_b_unused; | |
| 1937 | wire wr_en_b_unused; | |
| 1938 | wire [1:0] wr_way_b_unused; | |
| 1939 | wire l1clk_int; | |
| 1940 | wire rd_en; | |
| 1941 | wire [4:0] sf_l; | |
| 1942 | wire [4:0] sf_r; | |
| 1943 | wire shift_en_lft; | |
| 1944 | wire shift_en_rgt; | |
| 1945 | wire redundancy_en; | |
| 1946 | wire [4:0] sh_index_lft; | |
| 1947 | wire [4:0] sh_index_rgt; | |
| 1948 | wire mem_wr_en0; | |
| 1949 | wire mem_wr_en1; | |
| 1950 | ||
| 1951 | ||
| 1952 | // input l2clk; // cmp clock | |
| 1953 | // input iol2clk; // io clock | |
| 1954 | // input scan_in; | |
| 1955 | // input tcu_pce_ov; // scan signals | |
| 1956 | // input tcu_clk_stop; | |
| 1957 | // input tcu_aclk; | |
| 1958 | // input tcu_bclk; | |
| 1959 | // input tcu_scan_en; | |
| 1960 | // input tcu_muxtest; | |
| 1961 | // input tcu_dectest; | |
| 1962 | // output scan_out; | |
| 1963 | ||
| 1964 | ||
| 1965 | input [`L2T_ARR_D_WIDTH - 1:0] din; | |
| 1966 | input [8:0] addr_b; | |
| 1967 | input l1clk_internal_v1; | |
| 1968 | input l1clk_internal_v2; | |
| 1969 | input ln1clk; | |
| 1970 | input ln2clk; | |
| 1971 | input rd_en_b; | |
| 1972 | input rd_en_d1_a; | |
| 1973 | input [1:0] rpda_lft; | |
| 1974 | input [1:0] rpda_rgt; | |
| 1975 | input [3:0] rpdb_lft; | |
| 1976 | input [3:0] rpdb_rgt; | |
| 1977 | input [3:0] rpdc_lft; | |
| 1978 | input [3:0] rpdc_rgt; | |
| 1979 | input w_inhibit_l; | |
| 1980 | input wr_en_b; | |
| 1981 | input wr_en_d1_a; | |
| 1982 | input [1:0] wr_way_b; | |
| 1983 | input [1:0] wr_way_b_l; | |
| 1984 | ||
| 1985 | // Added vnw_ary pin for n2 for 2.0 | |
| 1986 | ||
| 1987 | input vnw_ary; | |
| 1988 | ||
| 1989 | output [`L2T_ARR_D_WIDTH - 1:0] sao_mx0_h; | |
| 1990 | output [`L2T_ARR_D_WIDTH - 1:0] sao_mx0_l; | |
| 1991 | output [`L2T_ARR_D_WIDTH - 1:0] sao_mx1_h; | |
| 1992 | output [`L2T_ARR_D_WIDTH - 1:0] sao_mx1_l; | |
| 1993 | ||
| 1994 | ||
| 1995 | reg [`L2T_ARR_D_WIDTH + 2:0] mem_lft[`L2T_ARR_DEPTH - 1 :0]; //one extra bit for redundancy | |
| 1996 | reg [0:`L2T_ARR_D_WIDTH - 2] mem_rgt[`L2T_ARR_DEPTH - 1 :0]; | |
| 1997 | reg [`L2T_ARR_D_WIDTH + 2:0] mem_lft_reg ; | |
| 1998 | reg [0:`L2T_ARR_D_WIDTH - 2] mem_rgt_reg ; // one entry of the memonry | |
| 1999 | ||
| 2000 | ||
| 2001 | reg [`L2T_ARR_D_WIDTH + 2:0] mem_data_lft; | |
| 2002 | reg [0:`L2T_ARR_D_WIDTH - 2] mem_data_rgt; | |
| 2003 | ||
| 2004 | reg [14:0] rdata0_lft; | |
| 2005 | reg [14:0] rdata1_lft; | |
| 2006 | reg [0:12] rdata0_rgt; | |
| 2007 | reg [0:12] rdata1_rgt; | |
| 2008 | reg [30:0] wdata_lft; | |
| 2009 | reg [30:0] wdata_rgt; | |
| 2010 | reg [29:0] tmp_lft; | |
| 2011 | reg [25:0] tmp_rgt; | |
| 2012 | ||
| 2013 | wire [14:0] mem0_lft; | |
| 2014 | wire [14:0] mem1_lft; | |
| 2015 | wire [12:0] mem0_rgt; | |
| 2016 | wire [12:0] mem1_rgt; | |
| 2017 | wire [30:0] mem_all_lft; | |
| 2018 | wire [26:0] mem_all_rgt; | |
| 2019 | wire [30:0] rdata_out_lft; | |
| 2020 | wire [26:0] rdata_out_rgt; | |
| 2021 | integer i; | |
| 2022 | integer j; | |
| 2023 | integer l; | |
| 2024 | integer k; | |
| 2025 | ||
| 2026 | reg [`L2T_ARR_D_WIDTH - 1:0] sao_mx0_h ; | |
| 2027 | reg [`L2T_ARR_D_WIDTH - 1:0] sao_mx0_l ; | |
| 2028 | reg [`L2T_ARR_D_WIDTH - 1:0] sao_mx1_h ; | |
| 2029 | reg [`L2T_ARR_D_WIDTH - 1:0] sao_mx1_l ; | |
| 2030 | ||
| 2031 | wire [`L2T_ARR_D_WIDTH - 1:0] rdata0_out ; | |
| 2032 | wire [`L2T_ARR_D_WIDTH - 1:0] rdata1_out ; | |
| 2033 | //----------------------------------------------------------------- | |
| 2034 | // INITIALIZE MEMORY | |
| 2035 | //----------------------------------------------------------------- | |
| 2036 | `ifndef NOINITMEM | |
| 2037 | initial begin | |
| 2038 | for (i = 0; i < `L2T_ARR_DEPTH - 1; i = i + 1) | |
| 2039 | begin | |
| 2040 | mem_rgt[i]=27'h0; | |
| 2041 | mem_lft[i]=31'h0; | |
| 2042 | end | |
| 2043 | end | |
| 2044 | `endif | |
| 2045 | ||
| 2046 | ||
| 2047 | //----------------------------------------------------------------- | |
| 2048 | // UNUSED SIGNALS | |
| 2049 | //----------------------------------------------------------------- | |
| 2050 | assign ln1clk_unused = ln1clk; | |
| 2051 | assign ln2clk_unused = ln2clk; | |
| 2052 | assign l1clk_int_v2_unused = l1clk_internal_v2; | |
| 2053 | assign rd_en_b_unused = rd_en_b; | |
| 2054 | assign wr_en_b_unused = wr_en_b; | |
| 2055 | assign wr_way_b_unused[1:0] = wr_way_b_l[1:0]; | |
| 2056 | ||
| 2057 | ||
| 2058 | assign l1clk_int = l1clk_internal_v1; | |
| 2059 | ||
| 2060 | //----------------------------------------------------------------- | |
| 2061 | // OUTPUTS | |
| 2062 | //----------------------------------------------------------------- | |
| 2063 | // | |
| 2064 | //always @ (l1clk_int or rd_en) | |
| 2065 | // if (l1clk_int || ~rd_en) | |
| 2066 | // begin | |
| 2067 | // sao_mx0_h [`L2T_ARR_D_WIDTH - 1:0] <= 28'h0; | |
| 2068 | // sao_mx0_l [`L2T_ARR_D_WIDTH - 1:0] <= 28'h0; | |
| 2069 | // sao_mx1_h [`L2T_ARR_D_WIDTH - 1:0] <= 28'h0; | |
| 2070 | // sao_mx1_l [`L2T_ARR_D_WIDTH - 1:0] <= 28'h0; | |
| 2071 | // end | |
| 2072 | // | |
| 2073 | //----------------------------------------------------------------- | |
| 2074 | // INTERNAL LOGIC | |
| 2075 | //----------------------------------------------------------------- | |
| 2076 | // Add vnw_ary high check for read operation for n2_to_2.0 | |
| 2077 | // assign rd_en = rd_en_d1_a && ~wr_en_d1_a && w_inhibit_l; | |
| 2078 | assign rd_en = rd_en_d1_a && ~wr_en_d1_a && w_inhibit_l && vnw_ary; | |
| 2079 | ||
| 2080 | //----------------------------------------------------------------- | |
| 2081 | // REDUNDANCY | |
| 2082 | //----------------------------------------------------------------- | |
| 2083 | // Use [511:0] way0[29] as the redundancy bit, there are total 512 redundancy | |
| 2084 | // bits. | |
| 2085 | // Left side : way0_tmp[29:15] = mem0_lft[14:0] | |
| 2086 | // way1_tmp[27:13] = mem1_lft[14:0] | |
| 2087 | // way0_tmp[14] = red_bit_lft (redundancy bit) | |
| 2088 | // Shift mem1_lft[n] -> mem0_lft[n] , shift mem0_lft[n]->men1_rgt[n-1] | |
| 2089 | // mem0_lft[0]->redundancy bit = red_bit_lft. | |
| 2090 | // | |
| 2091 | // Right side : way0_tmp[12:0] = mem0_rgt[12:0] | |
| 2092 | // way1_tmp[12:0] = mem1_rgt[12:0] | |
| 2093 | // way0_tmp[13] = red_bit_rgt (redundancy bit) | |
| 2094 | // Shift mem1_rgt[n] -> mem0_rgt[n] , shift mem0_rgt[n]->men1_rgt[n+1] | |
| 2095 | // mem0_rgt[0]->redundancy bit = red_bit_rgt. | |
| 2096 | // | |
| 2097 | //----------------------------------------------------------------- | |
| 2098 | ||
| 2099 | //----------------------------------------------------------------- | |
| 2100 | // recover the shift index from rpda, rpdb, rpdc | |
| 2101 | //----------------------------------------------------------------- | |
| 2102 | assign sf_l[4] = rpda_lft[1] ; | |
| 2103 | assign sf_l[3:2] = rpdb_lft[3] ? 2'b11 : | |
| 2104 | rpdb_lft[2] ? 2'b10 : | |
| 2105 | rpdb_lft[1] ? 2'b01 : | |
| 2106 | 2'b00; | |
| 2107 | assign sf_l[1:0] = rpdc_lft[3] ? 2'b11 : | |
| 2108 | rpdc_lft[2] ? 2'b10 : | |
| 2109 | rpdc_lft[1] ? 2'b01 : | |
| 2110 | 2'b00; | |
| 2111 | ||
| 2112 | assign sf_r[4] = rpda_rgt[1] ; | |
| 2113 | assign sf_r[3:2] = rpdb_rgt[3] ? 2'b11 : | |
| 2114 | rpdb_rgt[2] ? 2'b10 : | |
| 2115 | rpdb_rgt[1] ? 2'b01 : | |
| 2116 | 2'b00; | |
| 2117 | assign sf_r[1:0] = rpdc_rgt[3] ? 2'b11 : | |
| 2118 | rpdc_rgt[2] ? 2'b10 : | |
| 2119 | rpdc_rgt[1] ? 2'b01 : | |
| 2120 | 2'b00; | |
| 2121 | ||
| 2122 | assign shift_en_lft = (sf_l[4:0] < 5'd30) ? (|rpda_lft[1:0]) && (|rpdb_lft[3:0]) && (|rpdc_lft[3:0]) : 1'b0; | |
| 2123 | assign shift_en_rgt = (sf_r[4:0] < 5'd26) ? (|rpda_rgt[1:0]) && (|rpdb_rgt[3:0]) && (|rpdc_rgt[3:0]) : 1'b0; | |
| 2124 | ||
| 2125 | assign redundancy_en = shift_en_lft || shift_en_rgt; | |
| 2126 | ||
| 2127 | assign sh_index_lft[4:0] = shift_en_lft && (sf_l[4:0] < 5'd30) ? sf_l[4:0] : 5'b00000; | |
| 2128 | assign sh_index_rgt[4:0] = shift_en_rgt && (sf_r[4:0] < 5'd26) ? sf_r[4:0] : 5'b00000; | |
| 2129 | ||
| 2130 | ||
| 2131 | ||
| 2132 | //----------------------------------------------------------------- | |
| 2133 | // Write Arrays | |
| 2134 | //----------------------------------------------------------------- | |
| 2135 | ||
| 2136 | ||
| 2137 | //-------------------------------------- | |
| 2138 | // Write Redundancy Mapping | |
| 2139 | //-------------------------------------- | |
| 2140 | // Shifting of redundancy base on the sh_index_lft and sh_index_rgt | |
| 2141 | ||
| 2142 | wire [14:0] din_lft ; | |
| 2143 | wire [0:12] din_rgt ; | |
| 2144 | assign din_lft[14:0] = din[27:13]; | |
| 2145 | assign din_rgt[0:12] = din[12:0]; | |
| 2146 | ||
| 2147 | // Add vnw_high check for write operation (implemented for n2_to_2.0) | |
| 2148 | ||
| 2149 | assign mem_wr_en0 = wr_way_b[0] && wr_en_b && ~rd_en_b && w_inhibit_l && wr_en_d1_a && vnw_ary; | |
| 2150 | assign mem_wr_en1 = wr_way_b[1] && wr_en_b && ~rd_en_b && w_inhibit_l && wr_en_d1_a && vnw_ary; | |
| 2151 | ||
| 2152 | ||
| 2153 | ||
| 2154 | ||
| 2155 | //-------left------- | |
| 2156 | always @ (sh_index_lft or din_lft[14:0] or shift_en_lft or mem_wr_en0 or mem_wr_en1 | |
| 2157 | or l1clk_int or addr_b[8:0] ) | |
| 2158 | ||
| 2159 | ||
| 2160 | #0 | |
| 2161 | ||
| 2162 | begin | |
| 2163 | ||
| 2164 | ||
| 2165 | mem_lft_reg[`L2T_ARR_D_WIDTH + 2:0] = mem_lft[addr_b] ; | |
| 2166 | ||
| 2167 | ||
| 2168 | ||
| 2169 | // Write to redundant bit in write cycle for way0 with no redundancy | |
| 2170 | if (l1clk_int && (~shift_en_lft) && mem_wr_en0) | |
| 2171 | begin | |
| 2172 | mem_lft_reg[0] = din_lft[0]; | |
| 2173 | end | |
| 2174 | ||
| 2175 | for (i=14; i >= 0; i=i-1) | |
| 2176 | begin | |
| 2177 | if (mem_wr_en0 && l1clk_int) //way0 | |
| 2178 | begin | |
| 2179 | if (( sh_index_lft < (2*i)) || ~shift_en_lft) | |
| 2180 | mem_lft_reg[2*i+1] = din_lft[i]; //no shift | |
| 2181 | else | |
| 2182 | begin | |
| 2183 | mem_lft_reg[2*i] = din_lft[i]; // shift | |
| 2184 | end | |
| 2185 | end | |
| 2186 | if(shift_en_lft) | |
| 2187 | mem_lft_reg[sh_index_lft+1] = 1'bx; // write "x" to bad bit | |
| 2188 | end //for | |
| 2189 | ||
| 2190 | for (i=14; i >= 0; i=i-1) | |
| 2191 | begin | |
| 2192 | if (mem_wr_en1 && l1clk_int ) //way1 | |
| 2193 | begin | |
| 2194 | if (( sh_index_lft < (2*i + 1)) || ~shift_en_lft) | |
| 2195 | mem_lft_reg[2*i+2] = din_lft[i]; //no shift | |
| 2196 | else | |
| 2197 | begin | |
| 2198 | mem_lft_reg[2*i+1] = din_lft[i]; //shift | |
| 2199 | end | |
| 2200 | end | |
| 2201 | if(shift_en_lft) | |
| 2202 | mem_lft_reg[sh_index_lft+1] = 1'bx; //write "x" to bad bit | |
| 2203 | end | |
| 2204 | ||
| 2205 | if (l1clk_int) mem_lft[addr_b] = mem_lft_reg[`L2T_ARR_D_WIDTH + 2:0] ; | |
| 2206 | ||
| 2207 | ||
| 2208 | end | |
| 2209 | ||
| 2210 | //-------right------- | |
| 2211 | ||
| 2212 | always @ (sh_index_rgt or din_rgt[0:12] or shift_en_rgt or mem_wr_en0 or mem_wr_en1 | |
| 2213 | or l1clk_int or addr_b[8:0] ) | |
| 2214 | ||
| 2215 | ||
| 2216 | #0 | |
| 2217 | ||
| 2218 | begin | |
| 2219 | ||
| 2220 | mem_rgt_reg[0 : `L2T_ARR_D_WIDTH - 2] = mem_rgt[addr_b]; | |
| 2221 | ||
| 2222 | ||
| 2223 | ||
| 2224 | // Write to redundant bit in write cycle for way0 with no redundancy | |
| 2225 | if (l1clk_int && (~shift_en_rgt) && mem_wr_en0) | |
| 2226 | begin | |
| 2227 | mem_rgt_reg[0] = din_rgt[0]; | |
| 2228 | end | |
| 2229 | ||
| 2230 | for (k=12; k >= 0; k=k-1) | |
| 2231 | begin | |
| 2232 | if (mem_wr_en0 && l1clk_int) //WAY0 | |
| 2233 | begin | |
| 2234 | if (( sh_index_rgt < (2*k )) || ~shift_en_rgt) | |
| 2235 | mem_rgt_reg[2*k+1] = din_rgt[k]; //no shift | |
| 2236 | else | |
| 2237 | begin | |
| 2238 | mem_rgt_reg[2*k] = din_rgt[k]; // shift | |
| 2239 | end | |
| 2240 | end | |
| 2241 | if(shift_en_rgt) | |
| 2242 | mem_rgt_reg[sh_index_rgt+1] = 1'bx; // Write "X" to the bad bit | |
| 2243 | end //for | |
| 2244 | ||
| 2245 | for (k=12; k >= 0; k=k-1) | |
| 2246 | begin | |
| 2247 | if (mem_wr_en1 && l1clk_int ) //WAY1 | |
| 2248 | begin | |
| 2249 | if (( sh_index_rgt < (2*k + 1)) || ~shift_en_rgt) | |
| 2250 | mem_rgt_reg[2*k+2] = din_rgt[k]; //no shift | |
| 2251 | else | |
| 2252 | begin | |
| 2253 | mem_rgt_reg[2*k+1] = din_rgt[k]; // shift | |
| 2254 | end | |
| 2255 | end | |
| 2256 | if(shift_en_rgt) | |
| 2257 | mem_rgt_reg[sh_index_rgt+1] = 1'bx; // Write "X" to the bad bit | |
| 2258 | end //for | |
| 2259 | ||
| 2260 | if (l1clk_int) mem_rgt[addr_b] = mem_rgt_reg[0 : `L2T_ARR_D_WIDTH - 2] ; | |
| 2261 | ||
| 2262 | ||
| 2263 | ||
| 2264 | end | |
| 2265 | ||
| 2266 | //----------------------------------------------------------------- | |
| 2267 | // Read Arrays | |
| 2268 | //----------------------------------------------------------------- | |
| 2269 | ||
| 2270 | //-------------------------------------- | |
| 2271 | // Read Redundancy Mapping | |
| 2272 | //-------------------------------------- | |
| 2273 | ||
| 2274 | ||
| 2275 | //---------Left-------------- | |
| 2276 | always @ (sh_index_lft or shift_en_lft or rd_en or l1clk_int or addr_b[8:0] ) | |
| 2277 | begin | |
| 2278 | if (l1clk_int) | |
| 2279 | begin | |
| 2280 | ||
| 2281 | mem_data_lft[`L2T_ARR_D_WIDTH + 2:0] = ~rd_en ? 31'hx : mem_lft[addr_b] ; | |
| 2282 | ||
| 2283 | end | |
| 2284 | ||
| 2285 | ||
| 2286 | if (rd_en && ~l1clk_int) | |
| 2287 | ||
| 2288 | ||
| 2289 | begin | |
| 2290 | ||
| 2291 | for (j=14; j >= 0; j=j-1) //WAY0 | |
| 2292 | begin | |
| 2293 | if (( sh_index_lft < (2*j )) || ~shift_en_lft) | |
| 2294 | rdata0_lft[j] = mem_data_lft[2*j+1]; // no shift | |
| 2295 | else | |
| 2296 | rdata0_lft[j] = mem_data_lft[2*j]; // shift | |
| 2297 | end //for | |
| 2298 | ||
| 2299 | for (j=14; j >= 0; j=j-1) //WAY1 | |
| 2300 | begin | |
| 2301 | if (( sh_index_lft < (2*j + 1)) || ~shift_en_lft) | |
| 2302 | rdata1_lft[j] = mem_data_lft[2*j+2]; //no shift | |
| 2303 | else | |
| 2304 | rdata1_lft[j] = mem_data_lft[2*j+1]; // shift | |
| 2305 | end | |
| 2306 | sao_mx0_h[27:13] = rdata0_lft[14:0] & {15{rd_en}}; | |
| 2307 | sao_mx0_l[27:13] = ~rdata0_lft[14:0] & {15{rd_en}}; | |
| 2308 | sao_mx1_h[27:13] = rdata1_lft[14:0] & {15{rd_en}}; | |
| 2309 | sao_mx1_l[27:13] = ~rdata1_lft[14:0] & {15{rd_en}}; | |
| 2310 | end | |
| 2311 | else if(l1clk_int || ~rd_en) | |
| 2312 | begin | |
| 2313 | sao_mx0_h[27:13] = 15'h0; | |
| 2314 | sao_mx0_l[27:13] = 15'h0; | |
| 2315 | sao_mx1_h[27:13] = 15'h0; | |
| 2316 | sao_mx1_l[27:13] = 15'h0; | |
| 2317 | end | |
| 2318 | end | |
| 2319 | ||
| 2320 | //---------Right-------------- | |
| 2321 | ||
| 2322 | always @ (sh_index_rgt or shift_en_rgt or rd_en or l1clk_int or addr_b[8:0] ) | |
| 2323 | ||
| 2324 | begin | |
| 2325 | if (l1clk_int) | |
| 2326 | begin | |
| 2327 | ||
| 2328 | mem_data_rgt[0: `L2T_ARR_D_WIDTH - 2] = ~rd_en ? 27'hx : mem_rgt[addr_b] ; | |
| 2329 | ||
| 2330 | end | |
| 2331 | ||
| 2332 | ||
| 2333 | if (rd_en && ~l1clk_int) | |
| 2334 | ||
| 2335 | ||
| 2336 | begin | |
| 2337 | ||
| 2338 | for (l=12; l >= 0; l=l-1) //WAY0 | |
| 2339 | begin | |
| 2340 | if (( sh_index_rgt < (2*l)) || ~shift_en_rgt) | |
| 2341 | rdata0_rgt[l] = mem_data_rgt[2*l+1]; // no shift | |
| 2342 | else | |
| 2343 | rdata0_rgt[l] = mem_data_rgt[2*l]; // shift | |
| 2344 | end //for | |
| 2345 | ||
| 2346 | for (l=12; l >= 0; l=l-1) //WAY1 | |
| 2347 | begin | |
| 2348 | if (( sh_index_rgt < (2*l + 1)) || ~shift_en_rgt) | |
| 2349 | rdata1_rgt[l] = mem_data_rgt[2*l+2]; //no shift | |
| 2350 | else | |
| 2351 | rdata1_rgt[l] = mem_data_rgt[2*l+1]; // shift | |
| 2352 | end | |
| 2353 | sao_mx0_h[12:0] = rdata0_rgt[0:12] & {13{rd_en}}; | |
| 2354 | sao_mx0_l[12:0] = ~rdata0_rgt[0:12] & {13{rd_en}}; | |
| 2355 | sao_mx1_h[12:0] = rdata1_rgt[0:12] & {13{rd_en}}; | |
| 2356 | sao_mx1_l[12:0] = ~rdata1_rgt[0:12] & {13{rd_en}}; | |
| 2357 | end | |
| 2358 | else if (l1clk_int || ~rd_en) | |
| 2359 | begin | |
| 2360 | sao_mx0_h[12:0] = 13'h0; | |
| 2361 | sao_mx0_l[12:0] = 13'h0; | |
| 2362 | sao_mx1_h[12:0] = 13'h0; | |
| 2363 | sao_mx1_l[12:0] = 13'h0; | |
| 2364 | end | |
| 2365 | end | |
| 2366 | ||
| 2367 | ||
| 2368 | endmodule | |
| 2369 | ||
| 2370 | ||
| 2371 | ||
| 2372 | module n2_l2t_sr_latch ( | |
| 2373 | set, | |
| 2374 | reset, | |
| 2375 | out) ; | |
| 2376 | ||
| 2377 | ||
| 2378 | input set; | |
| 2379 | input reset; | |
| 2380 | output out; | |
| 2381 | ||
| 2382 | reg out; | |
| 2383 | ||
| 2384 | always @(set or reset) | |
| 2385 | begin | |
| 2386 | if (reset) out=1'b0; | |
| 2387 | else if (set) out=1'b1; | |
| 2388 | end | |
| 2389 | endmodule // n2_l2t_sr_latch | |
| 2390 | ||
| 2391 | ||
| 2392 | ||
| 2393 | // Compare sao_mx_h with lkuptag_d1, and sao_mx_l with ~lkuptag_d1. | |
| 2394 | // Output is "0" for hit and "1" for miss | |
| 2395 | ||
| 2396 | module n2_l2t_cmp_3bx2 ( | |
| 2397 | sao_mx1_h, | |
| 2398 | sao_mx1_l, | |
| 2399 | sao_mx0_h, | |
| 2400 | sao_mx0_l, | |
| 2401 | lkuptag_d1, | |
| 2402 | l1clk_d, | |
| 2403 | w1_cmp3b, | |
| 2404 | w0_cmp3b) ; | |
| 2405 | ||
| 2406 | ||
| 2407 | input [2:0] sao_mx1_h; | |
| 2408 | input [2:0] sao_mx1_l; | |
| 2409 | input [2:0] sao_mx0_h; | |
| 2410 | input [2:0] sao_mx0_l; | |
| 2411 | input [2:0] lkuptag_d1; | |
| 2412 | input l1clk_d; | |
| 2413 | output w1_cmp3b; | |
| 2414 | output w0_cmp3b; | |
| 2415 | ||
| 2416 | reg w1_cmp3b; | |
| 2417 | reg w0_cmp3b; | |
| 2418 | ||
| 2419 | //Compare ouput is 0 for match and 1 for mismatch | |
| 2420 | ||
| 2421 | always @(l1clk_d or sao_mx1_h or sao_mx1_l or sao_mx0_h or sao_mx0_l or lkuptag_d1) | |
| 2422 | ||
| 2423 | if (l1clk_d) // Precharge mode | |
| 2424 | begin | |
| 2425 | w1_cmp3b = 1'b0; | |
| 2426 | w0_cmp3b = 1'b0; | |
| 2427 | end | |
| 2428 | else | |
| 2429 | if (~l1clk_d ) // Evaluation mode | |
| 2430 | begin | |
| 2431 | w1_cmp3b = (lkuptag_d1[2] && sao_mx1_l[2]) || (~lkuptag_d1[2] && sao_mx1_h[2]) || | |
| 2432 | (lkuptag_d1[1] && sao_mx1_l[1]) || (~lkuptag_d1[1] && sao_mx1_h[1]) || | |
| 2433 | (lkuptag_d1[0] && sao_mx1_l[0]) || (~lkuptag_d1[0] && sao_mx1_h[0]); | |
| 2434 | ||
| 2435 | w0_cmp3b = (lkuptag_d1[2] && sao_mx0_l[2]) || (~lkuptag_d1[2] && sao_mx0_h[2]) || | |
| 2436 | (lkuptag_d1[1] && sao_mx0_l[1]) || (~lkuptag_d1[1] && sao_mx0_h[1]) || | |
| 2437 | (lkuptag_d1[0] && sao_mx0_l[0]) || (~lkuptag_d1[0] && sao_mx0_h[0]); | |
| 2438 | end | |
| 2439 | ||
| 2440 | endmodule // n2_l2t_cmp_3bx2 | |
| 2441 | ||
| 2442 | ||
| 2443 | // | |
| 2444 | // macro for cl_mc1_tisram_blb_{8,4}x flops | |
| 2445 | // | |
| 2446 | // | |
| 2447 | ||
| 2448 | ||
| 2449 | ||
| 2450 | ||
| 2451 | ||
| 2452 | module n2_l2t_bank_tisram_blb_macro__dmsff_4x__width_2 ( | |
| 2453 | d_a, | |
| 2454 | l1clk, | |
| 2455 | q_b); | |
| 2456 | input [1:0] d_a; | |
| 2457 | input l1clk; | |
| 2458 | output [1:0] q_b; | |
| 2459 | ||
| 2460 | ||
| 2461 | ||
| 2462 | ||
| 2463 | ||
| 2464 | ||
| 2465 | tisram_blb #(2) d0_0 ( | |
| 2466 | .d(d_a[1:0]), | |
| 2467 | .l1clk(l1clk), | |
| 2468 | .latout_l(q_b[1:0]) | |
| 2469 | ); | |
| 2470 | ||
| 2471 | ||
| 2472 | ||
| 2473 | ||
| 2474 | ||
| 2475 | ||
| 2476 | ||
| 2477 | ||
| 2478 | ||
| 2479 | ||
| 2480 | //place::generic_place($width,$stack,$left); | |
| 2481 | ||
| 2482 | endmodule | |
| 2483 | ||
| 2484 | ||
| 2485 | ||
| 2486 | ||
| 2487 | ||
| 2488 | // | |
| 2489 | // macro for cl_mc1_tisram_blb_{8,4}x flops | |
| 2490 | // | |
| 2491 | // | |
| 2492 | ||
| 2493 | ||
| 2494 | ||
| 2495 | ||
| 2496 | ||
| 2497 | module n2_l2t_bank_tisram_blb_macro__dmsff_4x__width_5 ( | |
| 2498 | d_a, | |
| 2499 | l1clk, | |
| 2500 | q_b); | |
| 2501 | input [4:0] d_a; | |
| 2502 | input l1clk; | |
| 2503 | output [4:0] q_b; | |
| 2504 | ||
| 2505 | ||
| 2506 | ||
| 2507 | ||
| 2508 | ||
| 2509 | ||
| 2510 | tisram_blb #(5) d0_0 ( | |
| 2511 | .d(d_a[4:0]), | |
| 2512 | .l1clk(l1clk), | |
| 2513 | .latout_l(q_b[4:0]) | |
| 2514 | ); | |
| 2515 | ||
| 2516 | ||
| 2517 | ||
| 2518 | ||
| 2519 | ||
| 2520 | ||
| 2521 | ||
| 2522 | ||
| 2523 | ||
| 2524 | ||
| 2525 | //place::generic_place($width,$stack,$left); | |
| 2526 | ||
| 2527 | endmodule | |
| 2528 | ||
| 2529 | ||
| 2530 | ||
| 2531 | ||
| 2532 | ||
| 2533 | // | |
| 2534 | // macro for cl_mc1_tisram_blb_{8,4}x flops | |
| 2535 | // | |
| 2536 | // | |
| 2537 | ||
| 2538 | ||
| 2539 | ||
| 2540 | ||
| 2541 | ||
| 2542 | module n2_l2t_bank_tisram_blb_macro__dmsff_4x__width_1 ( | |
| 2543 | d_a, | |
| 2544 | l1clk, | |
| 2545 | q_b); | |
| 2546 | input [0:0] d_a; | |
| 2547 | input l1clk; | |
| 2548 | output [0:0] q_b; | |
| 2549 | ||
| 2550 | ||
| 2551 | ||
| 2552 | ||
| 2553 | ||
| 2554 | ||
| 2555 | tisram_blb #(1) d0_0 ( | |
| 2556 | .d(d_a[0:0]), | |
| 2557 | .l1clk(l1clk), | |
| 2558 | .latout_l(q_b[0:0]) | |
| 2559 | ); | |
| 2560 | ||
| 2561 | ||
| 2562 | ||
| 2563 | ||
| 2564 | ||
| 2565 | ||
| 2566 | ||
| 2567 | ||
| 2568 | ||
| 2569 | ||
| 2570 | //place::generic_place($width,$stack,$left); | |
| 2571 | ||
| 2572 | endmodule | |
| 2573 | ||
| 2574 | ||
| 2575 | ||
| 2576 | ||
| 2577 | ||
| 2578 | // | |
| 2579 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
| 2580 | // | |
| 2581 | // | |
| 2582 | ||
| 2583 | ||
| 2584 | ||
| 2585 | ||
| 2586 | ||
| 2587 | module n2_l2t_bank_tisram_msff_macro__width_1 ( | |
| 2588 | d, | |
| 2589 | scan_in, | |
| 2590 | l1clk, | |
| 2591 | siclk, | |
| 2592 | soclk, | |
| 2593 | scan_out, | |
| 2594 | latout, | |
| 2595 | latout_l); | |
| 2596 | input [0:0] d; | |
| 2597 | input scan_in; | |
| 2598 | input l1clk; | |
| 2599 | input siclk; | |
| 2600 | input soclk; | |
| 2601 | output scan_out; | |
| 2602 | output [0:0] latout; | |
| 2603 | output [0:0] latout_l; | |
| 2604 | ||
| 2605 | ||
| 2606 | ||
| 2607 | ||
| 2608 | ||
| 2609 | ||
| 2610 | tisram_msff #(1) d0_0 ( | |
| 2611 | .d(d[0:0]), | |
| 2612 | .si(scan_in), | |
| 2613 | .so(scan_out), | |
| 2614 | .l1clk(l1clk), | |
| 2615 | .siclk(siclk), | |
| 2616 | .soclk(soclk), | |
| 2617 | .latout(latout[0:0]), | |
| 2618 | .latout_l(latout_l[0:0]) | |
| 2619 | ); | |
| 2620 | ||
| 2621 | ||
| 2622 | ||
| 2623 | ||
| 2624 | ||
| 2625 | ||
| 2626 | ||
| 2627 | ||
| 2628 | ||
| 2629 | ||
| 2630 | ||
| 2631 | ||
| 2632 | //place::generic_place($width,$stack,$left); | |
| 2633 | ||
| 2634 | endmodule | |
| 2635 | ||
| 2636 | ||
| 2637 | ||
| 2638 | ||
| 2639 | ||
| 2640 | // | |
| 2641 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
| 2642 | // | |
| 2643 | // | |
| 2644 | ||
| 2645 | ||
| 2646 | ||
| 2647 | ||
| 2648 | ||
| 2649 | module n2_l2t_bank_tisram_msff_macro__width_2 ( | |
| 2650 | d, | |
| 2651 | scan_in, | |
| 2652 | l1clk, | |
| 2653 | siclk, | |
| 2654 | soclk, | |
| 2655 | scan_out, | |
| 2656 | latout, | |
| 2657 | latout_l); | |
| 2658 | wire [0:0] so; | |
| 2659 | ||
| 2660 | input [1:0] d; | |
| 2661 | input scan_in; | |
| 2662 | input l1clk; | |
| 2663 | input siclk; | |
| 2664 | input soclk; | |
| 2665 | output scan_out; | |
| 2666 | output [1:0] latout; | |
| 2667 | output [1:0] latout_l; | |
| 2668 | ||
| 2669 | ||
| 2670 | ||
| 2671 | ||
| 2672 | ||
| 2673 | ||
| 2674 | tisram_msff #(2) d0_0 ( | |
| 2675 | .d(d[1:0]), | |
| 2676 | .si({scan_in,so[0:0]}), | |
| 2677 | .so({so[0:0],scan_out}), | |
| 2678 | .l1clk(l1clk), | |
| 2679 | .siclk(siclk), | |
| 2680 | .soclk(soclk), | |
| 2681 | .latout(latout[1:0]), | |
| 2682 | .latout_l(latout_l[1:0]) | |
| 2683 | ); | |
| 2684 | ||
| 2685 | ||
| 2686 | ||
| 2687 | ||
| 2688 | ||
| 2689 | ||
| 2690 | ||
| 2691 | ||
| 2692 | ||
| 2693 | ||
| 2694 | ||
| 2695 | ||
| 2696 | //place::generic_place($width,$stack,$left); | |
| 2697 | ||
| 2698 | endmodule | |
| 2699 | ||
| 2700 | ||
| 2701 | ||
| 2702 | ||
| 2703 | ||
| 2704 | ||
| 2705 | ||
| 2706 | ||
| 2707 | ||
| 2708 | // any PARAMS parms go into naming of macro | |
| 2709 | ||
| 2710 | module n2_l2t_bank_msff_ctl_macro__width_1 ( | |
| 2711 | din, | |
| 2712 | l1clk, | |
| 2713 | scan_in, | |
| 2714 | siclk, | |
| 2715 | soclk, | |
| 2716 | dout, | |
| 2717 | scan_out); | |
| 2718 | wire [0:0] fdin; | |
| 2719 | ||
| 2720 | input [0:0] din; | |
| 2721 | input l1clk; | |
| 2722 | input scan_in; | |
| 2723 | ||
| 2724 | ||
| 2725 | input siclk; | |
| 2726 | input soclk; | |
| 2727 | ||
| 2728 | output [0:0] dout; | |
| 2729 | output scan_out; | |
| 2730 | assign fdin[0:0] = din[0:0]; | |
| 2731 | ||
| 2732 | ||
| 2733 | ||
| 2734 | ||
| 2735 | ||
| 2736 | ||
| 2737 | dff #(1) d0_0 ( | |
| 2738 | .l1clk(l1clk), | |
| 2739 | .siclk(siclk), | |
| 2740 | .soclk(soclk), | |
| 2741 | .d(fdin[0:0]), | |
| 2742 | .si(scan_in), | |
| 2743 | .so(scan_out), | |
| 2744 | .q(dout[0:0]) | |
| 2745 | ); | |
| 2746 | ||
| 2747 | ||
| 2748 | ||
| 2749 | ||
| 2750 | ||
| 2751 | ||
| 2752 | ||
| 2753 | ||
| 2754 | ||
| 2755 | ||
| 2756 | ||
| 2757 | ||
| 2758 | endmodule | |
| 2759 | ||
| 2760 | ||
| 2761 | ||
| 2762 | ||
| 2763 | ||
| 2764 | ||
| 2765 | ||
| 2766 | ||
| 2767 | ||
| 2768 | ||
| 2769 | ||
| 2770 | ||
| 2771 | ||
| 2772 | // any PARAMS parms go into naming of macro | |
| 2773 | ||
| 2774 | module n2_l2t_bank_msffi_ctl_macro__clockwidth_0__width_1 ( | |
| 2775 | din, | |
| 2776 | l1clk, | |
| 2777 | scan_in, | |
| 2778 | siclk, | |
| 2779 | soclk, | |
| 2780 | q_l, | |
| 2781 | scan_out); | |
| 2782 | input [0:0] din; | |
| 2783 | input l1clk; | |
| 2784 | input scan_in; | |
| 2785 | ||
| 2786 | ||
| 2787 | input siclk; | |
| 2788 | input soclk; | |
| 2789 | ||
| 2790 | output [0:0] q_l; | |
| 2791 | output scan_out; | |
| 2792 | ||
| 2793 | ||
| 2794 | ||
| 2795 | ||
| 2796 | ||
| 2797 | ||
| 2798 | msffi #(1) d0_0 ( | |
| 2799 | .l1clk(l1clk), | |
| 2800 | .siclk(siclk), | |
| 2801 | .soclk(soclk), | |
| 2802 | .d(din[0:0]), | |
| 2803 | .si(scan_in), | |
| 2804 | .so(scan_out), | |
| 2805 | .q_l(q_l[0:0]) | |
| 2806 | ); | |
| 2807 | ||
| 2808 | ||
| 2809 | ||
| 2810 | ||
| 2811 | ||
| 2812 | ||
| 2813 | ||
| 2814 | ||
| 2815 | ||
| 2816 | ||
| 2817 | ||
| 2818 | ||
| 2819 | endmodule | |
| 2820 | ||
| 2821 | ||
| 2822 | ||
| 2823 | ||
| 2824 | ||
| 2825 | ||
| 2826 | ||
| 2827 |