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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_l2t_sp_28kb_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define L2T_ARR_D_WIDTH 28 | |
36 | `define L2T_ARR_DEPTH 512 | |
37 | `define WAY_HIT_WIDTH 16 | |
38 | `define BADREAD BADBADD | |
39 | ||
40 | ||
41 | ||
42 | module n2_l2t_sp_28kb_cust ( | |
43 | scan_in, | |
44 | scan_out, | |
45 | tcu_scan_en0, | |
46 | tcu_scan_en1, | |
47 | l2t_bist_en0, | |
48 | l2t_bist_en1, | |
49 | bist_index0, | |
50 | bist_index1, | |
51 | bist_rd_en0, | |
52 | bist_rd_en1, | |
53 | bist_way, | |
54 | bist_wr_en0, | |
55 | bist_wr_en1, | |
56 | bist_wrdata0, | |
57 | bist_wrdata1, | |
58 | tcu_clk_stop, | |
59 | index0, | |
60 | index1, | |
61 | l2clk, | |
62 | lkup_tag0, | |
63 | lkup_tag1, | |
64 | pce, | |
65 | tcu_pce_ov, | |
66 | rd_en0, | |
67 | rd_en1, | |
68 | hdr_l2t_rvalue, | |
69 | hdr_l2t_rid, | |
70 | hdr_l2t_wr_en, | |
71 | hdr_l2t_red_clr, | |
72 | tcu_se_scancollar_in0, | |
73 | tcu_se_scancollar_in1, | |
74 | tcu_se_scancollar_out0, | |
75 | tcu_se_scancollar_out1, | |
76 | tcu_aclk0, | |
77 | tcu_aclk1, | |
78 | tcu_bclk0, | |
79 | tcu_bclk1, | |
80 | w_inhibit0, | |
81 | w_inhibit1, | |
82 | way, | |
83 | wr_en0, | |
84 | wr_en1, | |
85 | wrdata0, | |
86 | wrdata1, | |
87 | vnw_ary, | |
88 | l2t_hdr_read_data, | |
89 | tag_way0, | |
90 | tag_way1, | |
91 | tag_way2, | |
92 | tag_way3, | |
93 | tag_way4, | |
94 | tag_way5, | |
95 | tag_way6, | |
96 | tag_way7, | |
97 | tag_way8, | |
98 | tag_way9, | |
99 | tag_way10, | |
100 | tag_way11, | |
101 | tag_way12, | |
102 | tag_way13, | |
103 | tag_way14, | |
104 | tag_way15, | |
105 | way_hit, | |
106 | wr_en_ov, | |
107 | clk_en0, | |
108 | clk_en1, | |
109 | clk_en_ov); | |
110 | wire l1clk_in; | |
111 | wire l1clk_out; | |
112 | wire pce_unused; | |
113 | wire stop_unused; | |
114 | wire siclk; | |
115 | wire soclk; | |
116 | wire scan_en2; | |
117 | wire scan_en0; | |
118 | wire scan_en3; | |
119 | wire scan_en1; | |
120 | wire [3:0] way_hit3; | |
121 | wire [3:0] way_hit2; | |
122 | wire [3:0] way_hit1; | |
123 | wire [3:0] way_hit0; | |
124 | wire [27:0] tag_way0_0; | |
125 | wire [27:0] tag_way1_0; | |
126 | wire [27:0] tag_way2_0; | |
127 | wire [27:0] tag_way3_0; | |
128 | wire [27:0] tag_way0_1; | |
129 | wire [27:0] tag_way1_1; | |
130 | wire [27:0] tag_way2_1; | |
131 | wire [27:0] tag_way3_1; | |
132 | wire [27:0] tag_way0_2; | |
133 | wire [27:0] tag_way1_2; | |
134 | wire [27:0] tag_way2_2; | |
135 | wire [27:0] tag_way3_2; | |
136 | wire [27:0] tag_way0_3; | |
137 | wire [27:0] tag_way1_3; | |
138 | wire [27:0] tag_way2_3; | |
139 | wire [27:0] tag_way3_3; | |
140 | wire [4:0] red_d_quad_2_0; | |
141 | wire [4:0] req_d_quad0; | |
142 | wire [4:0] req_d_quad1; | |
143 | wire [4:0] req_d_quad2; | |
144 | wire [5:0] red_data; | |
145 | wire [4:0] req_d_quad3; | |
146 | wire red_data_tmp0; | |
147 | wire red_data_tmp1; | |
148 | wire [1:0] req_en_quad2_0; | |
149 | wire [1:0] req_en_quad3; | |
150 | wire [1:0] req_en_quad0; | |
151 | wire [1:0] req_en_quad1; | |
152 | wire [1:0] req_en_quad2; | |
153 | wire [8:0] tag_index1; | |
154 | wire [8:0] tag_index0; | |
155 | wire [8:0] index_3; | |
156 | wire [8:0] index_1; | |
157 | wire [8:0] index_2; | |
158 | wire [8:0] index_0; | |
159 | wire [15:0] wrway; | |
160 | wire [3:0] way3; | |
161 | wire [3:0] way2; | |
162 | wire [3:0] way1; | |
163 | wire [3:0] way0; | |
164 | wire [27:0] din1_v1; | |
165 | wire [27:0] din0_v1; | |
166 | wire [27:0] din3; | |
167 | wire [27:0] din2; | |
168 | wire [27:0] din1; | |
169 | wire [27:0] din0; | |
170 | wire rd_en_a3_tmp; | |
171 | wire not_l2t_bist_en1; | |
172 | wire not_bist_wr_en1; | |
173 | wire rd_en_a3; | |
174 | wire rd_en_a1_tmp; | |
175 | wire rd_en_a1; | |
176 | wire rd_en_a2_tmp; | |
177 | wire not_l2t_bist_en0; | |
178 | wire not_bist_wr_en0; | |
179 | wire rd_en_a2; | |
180 | wire rd_en_a0_tmp; | |
181 | wire rd_en_a0; | |
182 | wire wr_en_a2_tmp; | |
183 | wire not_bist_rd_en0; | |
184 | wire wr_en_a2; | |
185 | wire wr_en_a0_tmp; | |
186 | wire wr_en_a0; | |
187 | wire wr_en_a3_tmp; | |
188 | wire not_bist_rd_en1; | |
189 | wire wr_en_a3; | |
190 | wire wr_en_a1_tmp; | |
191 | wire wr_en_a1; | |
192 | wire [27:1] lkup_tag_3; | |
193 | wire [27:1] lkup_tag_1; | |
194 | wire [27:1] lkup_tag_2; | |
195 | wire [27:1] lkup_tag_0; | |
196 | wire rd_en; | |
197 | wire pce_out_a3; | |
198 | wire rd_en_r; | |
199 | wire clk_en_ov_r; | |
200 | wire pce_out_a1; | |
201 | wire pce_out_a2; | |
202 | wire pce_out_a0; | |
203 | wire pce_ctl_a3; | |
204 | wire pce_ctl_a1; | |
205 | wire pce_ctl_a2; | |
206 | wire pce_ctl_a0; | |
207 | wire pce_din_a3; | |
208 | wire wr_en_ov_r; | |
209 | wire pce_din_a1; | |
210 | wire pce_din_a2; | |
211 | wire pce_din_a0; | |
212 | wire pce_ov_a3; | |
213 | wire pce_ov_a1; | |
214 | wire pce_ov_a2; | |
215 | wire pce_ov_a0; | |
216 | wire [4:0] red_d_in_3; | |
217 | wire [5:0] hdr_l2t_rvalue_r; | |
218 | wire [4:0] red_d_in_1; | |
219 | wire [4:0] red_d_in_2; | |
220 | wire [4:0] red_d_in_0; | |
221 | wire [1:0] red_en_in_3; | |
222 | wire [1:0] red_en_in_1; | |
223 | wire [1:0] red_en_in_2; | |
224 | wire [1:0] red_en_in_0; | |
225 | wire not_w_inhibit0; | |
226 | wire red_wen_3; | |
227 | wire hdr_l2t_wr_en_r; | |
228 | wire red_wen_2; | |
229 | wire red_wen_1; | |
230 | wire red_wen_0; | |
231 | wire and_red_clr_r_w_inhibit0; | |
232 | wire hdr_l2t_red_clr_r; | |
233 | wire hdr_l2t_red_clr_r1; | |
234 | wire [3:0] rid_in_quad3; | |
235 | wire [3:0] hdr_l2t_rid_r; | |
236 | wire [3:0] rid_in_quad1; | |
237 | wire [3:0] rid_in_quad2; | |
238 | wire [3:0] rid_in_quad0; | |
239 | wire se_inff3; | |
240 | wire se_inff1; | |
241 | wire se_inff2; | |
242 | wire se_inff0; | |
243 | wire se_outff3; | |
244 | wire se_outff1; | |
245 | wire se_outff2; | |
246 | wire se_outff0; | |
247 | wire tcu_aclk_3; | |
248 | wire tcu_aclk_1; | |
249 | wire tcu_aclk_2; | |
250 | wire tcu_aclk_0; | |
251 | wire tcu_bclk_3; | |
252 | wire tcu_bclk_1; | |
253 | wire tcu_bclk_2; | |
254 | wire tcu_bclk_0; | |
255 | wire wr_inhibit_a3; | |
256 | wire wr_inhibit_a1; | |
257 | wire wr_inhibit_a2; | |
258 | wire wr_inhibit_a0; | |
259 | wire quad0_scanout; | |
260 | wire quad0_scanin; | |
261 | wire quad1_scanout; | |
262 | wire quad1_scanin; | |
263 | wire quad2_scanout; | |
264 | wire quad2_scanin; | |
265 | wire quad3_scanout; | |
266 | wire quad3_scanin; | |
267 | wire hdr_l2t_rvalue_scanin; | |
268 | wire hdr_l2t_rvalue_scanout; | |
269 | wire hdr_l2t_rid_scanin; | |
270 | wire hdr_l2t_rid_scanout; | |
271 | wire hdr_l2t_red_clr_scanin; | |
272 | wire hdr_l2t_red_clr_scanout; | |
273 | wire hdr_l2t_wr_en_scanin; | |
274 | wire hdr_l2t_wr_en_scanout; | |
275 | wire rd_en_scanin; | |
276 | wire rd_en_scanout; | |
277 | wire clk_en_ov_scanin; | |
278 | wire clk_en_ov_scanout; | |
279 | wire wr_en_ov_scanin; | |
280 | wire wr_en_ov_scanout; | |
281 | wire l2t_hdr_read_data_scanin; | |
282 | wire l2t_hdr_read_data_scanout; | |
283 | ||
284 | ||
285 | input scan_in; | |
286 | output scan_out; | |
287 | input tcu_scan_en0; | |
288 | input tcu_scan_en1; | |
289 | input l2t_bist_en0; | |
290 | input l2t_bist_en1; | |
291 | ||
292 | //XXinput arst_l; | |
293 | input [8:0] bist_index0; | |
294 | input [8:0] bist_index1; | |
295 | input bist_rd_en0; | |
296 | input bist_rd_en1; | |
297 | input [15:0] bist_way; | |
298 | input bist_wr_en0; | |
299 | input bist_wr_en1; | |
300 | input [7:0] bist_wrdata0; | |
301 | input [7:0] bist_wrdata1; | |
302 | input tcu_clk_stop; | |
303 | input [8:0] index0; | |
304 | input [8:0] index1; | |
305 | input l2clk; | |
306 | input [27:1] lkup_tag0; | |
307 | input [27:1] lkup_tag1; | |
308 | input pce; | |
309 | input tcu_pce_ov; | |
310 | input rd_en0; | |
311 | input rd_en1; | |
312 | //XXinput [4:0] red_d_in0; | |
313 | //XXinput [4:0] red_d_in1; | |
314 | //XXinput [1:0] red_en_in0; | |
315 | //XXinput [1:0] red_en_in1; | |
316 | //XXinput red_wen0; | |
317 | //XXinput red_wen1; | |
318 | //XXinput [3:0] rid_in; | |
319 | ||
320 | input [5:0] hdr_l2t_rvalue; | |
321 | input [3:0] hdr_l2t_rid; | |
322 | input hdr_l2t_wr_en; | |
323 | input hdr_l2t_red_clr; | |
324 | ||
325 | input tcu_se_scancollar_in0; | |
326 | input tcu_se_scancollar_in1; | |
327 | input tcu_se_scancollar_out0; | |
328 | input tcu_se_scancollar_out1; | |
329 | input tcu_aclk0; | |
330 | input tcu_aclk1; | |
331 | input tcu_bclk0; | |
332 | input tcu_bclk1; | |
333 | input w_inhibit0; | |
334 | input w_inhibit1; | |
335 | input [15:0] way; | |
336 | input wr_en0; | |
337 | input wr_en1; | |
338 | input [27:0] wrdata0; | |
339 | input [27:0] wrdata1; | |
340 | ||
341 | input vnw_ary; | |
342 | ||
343 | //XXoutput [4:0] reg_d_out; | |
344 | ||
345 | output [5:0] l2t_hdr_read_data; | |
346 | ||
347 | //output [1:0] reg_en_out; | |
348 | output [27:0] tag_way0; | |
349 | output [27:0] tag_way1; | |
350 | output [27:0] tag_way2; | |
351 | output [27:0] tag_way3; | |
352 | output [27:0] tag_way4; | |
353 | output [27:0] tag_way5; | |
354 | output [27:0] tag_way6; | |
355 | output [27:0] tag_way7; | |
356 | output [27:0] tag_way8; | |
357 | output [27:0] tag_way9; | |
358 | output [27:0] tag_way10; | |
359 | output [27:0] tag_way11; | |
360 | output [27:0] tag_way12; | |
361 | output [27:0] tag_way13; | |
362 | output [27:0] tag_way14; | |
363 | output [27:0] tag_way15; | |
364 | output [15:0] way_hit; | |
365 | ||
366 | // Power save pins | |
367 | ||
368 | input wr_en_ov; | |
369 | input clk_en0; | |
370 | input clk_en1; | |
371 | input clk_en_ov; | |
372 | ||
373 | ||
374 | // JDL 05/17/07 | |
375 | // synopsys translate_off | |
376 | ||
377 | ///////////////////////////////////////// | |
378 | // Clock Header // | |
379 | ///////////////////////////////////////// | |
380 | ||
381 | //INPUT HEADER | |
382 | ||
383 | n2_l2t_sp_28kb_cust_l1clkhdr_ctl_macro clkgen_in ( | |
384 | .l2clk (l2clk), | |
385 | .l1en (1'b1), | |
386 | .pce_ov (1'b1), | |
387 | .stop (1'b0), | |
388 | .se (tcu_se_scancollar_in0), | |
389 | .l1clk (l1clk_in) | |
390 | ); | |
391 | ||
392 | ||
393 | //OUTPUT HEADER | |
394 | n2_l2t_sp_28kb_cust_l1clkhdr_ctl_macro clkgen_out ( | |
395 | .l2clk (l2clk), | |
396 | .l1en (1'b1), | |
397 | .pce_ov (1'b1), | |
398 | .stop (1'b0), | |
399 | .se (tcu_se_scancollar_out1), | |
400 | .l1clk (l1clk_out) | |
401 | ); | |
402 | ||
403 | //assign pce_ov = tcu_pce_ov; | |
404 | assign pce_unused = pce; | |
405 | assign stop_unused = tcu_clk_stop; | |
406 | //assign se = tcu_scan_en0; | |
407 | ||
408 | assign siclk = tcu_aclk0; | |
409 | assign soclk = tcu_bclk0; | |
410 | ||
411 | assign scan_en2 = tcu_scan_en0; | |
412 | assign scan_en0 = tcu_scan_en0; | |
413 | assign scan_en3 = tcu_scan_en1; | |
414 | assign scan_en1 = tcu_scan_en1; | |
415 | ||
416 | ||
417 | //--------------------------------------- | |
418 | // output signals | |
419 | //--------------------------------------- | |
420 | ||
421 | assign {way_hit[15:14], way_hit[11:10]} = way_hit3[3:0]; | |
422 | assign {way_hit[7:6] , way_hit[3:2] } = way_hit2[3:0]; | |
423 | assign {way_hit[13:12], way_hit[9:8] } = way_hit1[3:0]; | |
424 | assign {way_hit[5:4] , way_hit[1:0] } = way_hit0[3:0]; | |
425 | ||
426 | //quad_00 | |
427 | assign tag_way0[`L2T_ARR_D_WIDTH - 1:0] = tag_way0_0[`L2T_ARR_D_WIDTH - 1:0]; | |
428 | assign tag_way1[`L2T_ARR_D_WIDTH - 1:0] = tag_way1_0[`L2T_ARR_D_WIDTH - 1:0]; | |
429 | assign tag_way4[`L2T_ARR_D_WIDTH - 1:0] = tag_way2_0[`L2T_ARR_D_WIDTH - 1:0]; | |
430 | assign tag_way5[`L2T_ARR_D_WIDTH - 1:0] = tag_way3_0[`L2T_ARR_D_WIDTH - 1:0]; | |
431 | ||
432 | //quad_01 | |
433 | assign tag_way8[`L2T_ARR_D_WIDTH - 1:0] = tag_way0_1[`L2T_ARR_D_WIDTH - 1:0]; | |
434 | assign tag_way9[`L2T_ARR_D_WIDTH - 1:0] = tag_way1_1[`L2T_ARR_D_WIDTH - 1:0]; | |
435 | assign tag_way12[`L2T_ARR_D_WIDTH - 1:0] = tag_way2_1[`L2T_ARR_D_WIDTH - 1:0]; | |
436 | assign tag_way13[`L2T_ARR_D_WIDTH - 1:0] = tag_way3_1[`L2T_ARR_D_WIDTH - 1:0]; | |
437 | ||
438 | //quad_10 | |
439 | assign tag_way2[`L2T_ARR_D_WIDTH - 1:0] = tag_way0_2[`L2T_ARR_D_WIDTH - 1:0]; | |
440 | assign tag_way3[`L2T_ARR_D_WIDTH - 1:0] = tag_way1_2[`L2T_ARR_D_WIDTH - 1:0]; | |
441 | assign tag_way6[`L2T_ARR_D_WIDTH - 1:0] = tag_way2_2[`L2T_ARR_D_WIDTH - 1:0]; | |
442 | assign tag_way7[`L2T_ARR_D_WIDTH - 1:0] = tag_way3_2[`L2T_ARR_D_WIDTH - 1:0]; | |
443 | ||
444 | //quad_11 | |
445 | assign tag_way10[`L2T_ARR_D_WIDTH - 1:0] = tag_way0_3[`L2T_ARR_D_WIDTH - 1:0]; | |
446 | assign tag_way11[`L2T_ARR_D_WIDTH - 1:0] = tag_way1_3[`L2T_ARR_D_WIDTH - 1:0]; | |
447 | assign tag_way14[`L2T_ARR_D_WIDTH - 1:0] = tag_way2_3[`L2T_ARR_D_WIDTH - 1:0]; | |
448 | assign tag_way15[`L2T_ARR_D_WIDTH - 1:0] = tag_way3_3[`L2T_ARR_D_WIDTH - 1:0]; | |
449 | ||
450 | // redundancy data signals from four quads are "ored". redundancy enable | |
451 | // signals are ored and anded together to generate 1 bit enable out signal. | |
452 | // Change to structural coding CC | |
453 | ||
454 | //assign red_data[5:1] = (req_d_quad0[4:0] | req_d_quad2[4:0]) | (req_d_quad1[4:0] | req_d_quad3[4:0]); | |
455 | n2_l2t_sp_28kb_cust_or_macro__ports_3__width_5 or_req_d_quad2_0 ( | |
456 | .dout (red_d_quad_2_0[4:0]), | |
457 | .din0 (req_d_quad0[4:0]), | |
458 | .din1 (req_d_quad1[4:0]), | |
459 | .din2 (req_d_quad2[4:0])); | |
460 | ||
461 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_5 or_req_d_quad3_0 ( | |
462 | .dout (red_data[5:1]), | |
463 | .din0 (red_d_quad_2_0[4:0]), | |
464 | .din1 (req_d_quad3[4:0])); | |
465 | ||
466 | //assign red_data[0] = ((req_en_quad0[1] || req_en_quad2[1]) || (req_en_quad1[1] || req_en_quad3[1])) && | |
467 | // ((req_en_quad0[0] || req_en_quad1[0]) || (req_en_quad2[0] || req_en_quad3[0])); | |
468 | ||
469 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_red_0 | |
470 | ( | |
471 | .dout (red_data[0]), | |
472 | .din0 (red_data_tmp0), | |
473 | .din1 (red_data_tmp1) | |
474 | ); | |
475 | ||
476 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_red_data_0 | |
477 | ( | |
478 | .dout (red_data_tmp0), | |
479 | .din0 (req_en_quad2_0[0]), | |
480 | .din1 (req_en_quad3[0])); | |
481 | ||
482 | n2_l2t_sp_28kb_cust_or_macro__ports_3__width_1 or_red_data_2_0 | |
483 | ( | |
484 | .dout (req_en_quad2_0[0]), | |
485 | .din0 (req_en_quad0[0]), | |
486 | .din1 (req_en_quad1[0]), | |
487 | .din2 (req_en_quad2[0])); | |
488 | ||
489 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_red_data_1 | |
490 | ( | |
491 | .dout (red_data_tmp1), | |
492 | .din0 (req_en_quad2_0[1]), | |
493 | .din1 (req_en_quad3[1])); | |
494 | ||
495 | n2_l2t_sp_28kb_cust_or_macro__ports_3__width_1 or_red_data_2_0_1 | |
496 | ( | |
497 | .dout (req_en_quad2_0[1]), | |
498 | .din0 (req_en_quad0[1]), | |
499 | .din1 (req_en_quad1[1]), | |
500 | .din2 (req_en_quad2[1])); | |
501 | ||
502 | ||
503 | //--------------------------------------- | |
504 | // internal signals | |
505 | //--------------------------------------- | |
506 | ||
507 | // Index and bist_index mux. Muxed output is tag_index. | |
508 | n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_9 mux_index_bist_index1 ( | |
509 | .dout (tag_index1[8:0]), | |
510 | .din0 (index1[8:0]), | |
511 | .din1 (bist_index1[8:0]), | |
512 | .sel0 (~l2t_bist_en1), | |
513 | .sel1 (l2t_bist_en1)); | |
514 | ||
515 | n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_9 mux_index_bist_index0 ( | |
516 | .dout (tag_index0[8:0]), | |
517 | .din0 (index0[8:0]), | |
518 | .din1 (bist_index0[8:0]), | |
519 | .sel0 (~l2t_bist_en0), | |
520 | .sel1 (l2t_bist_en0)); | |
521 | ||
522 | assign index_3[8:0] = tag_index1[8:0]; | |
523 | assign index_1[8:0] = tag_index1[8:0]; | |
524 | assign index_2[8:0] = tag_index0[8:0]; | |
525 | assign index_0[8:0] = tag_index0[8:0]; | |
526 | ||
527 | // Way and bist_way mux. Mux output is wrway. | |
528 | ||
529 | n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_8 mux_way_bistway1 ( | |
530 | .dout (wrway[15:8]), | |
531 | .din0 (way[15:8]), | |
532 | .din1 (bist_way[15:8]), | |
533 | .sel0 (~l2t_bist_en1), | |
534 | .sel1 (l2t_bist_en1)); | |
535 | ||
536 | n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_8 mux_way_bistway0 ( | |
537 | .dout (wrway[7:0]), | |
538 | .din0 (way[7:0]), | |
539 | .din1 (bist_way[7:0]), | |
540 | .sel0 (~l2t_bist_en0), | |
541 | .sel1 (l2t_bist_en0)); | |
542 | ||
543 | assign way3[3:0] = {wrway[15:14],wrway[11:10]}; | |
544 | assign way2[3:0] = {wrway[7:6],wrway[3:2]}; | |
545 | assign way1[3:0] = {wrway[13:12],wrway[9:8]}; | |
546 | assign way0[3:0] = {wrway[5:4],wrway[1:0]}; | |
547 | ||
548 | // wrdata and bist_wrdata mux. Mux output is din0_v1 and din1_v1: | |
549 | ||
550 | n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_28 mux_wrdata_bist_wrdata1 ( | |
551 | .dout (din1_v1[`L2T_ARR_D_WIDTH - 1:0]), | |
552 | .din0 (wrdata1[`L2T_ARR_D_WIDTH - 1:0]), | |
553 | .din1 ({bist_wrdata1[3:0], bist_wrdata1[7:0], bist_wrdata1[7:0], bist_wrdata1[7:0]}), | |
554 | .sel0 (~l2t_bist_en1), | |
555 | .sel1 (l2t_bist_en1)); | |
556 | ||
557 | n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_28 mux_wrdata_bist_wrdata0 ( | |
558 | .dout (din0_v1[`L2T_ARR_D_WIDTH - 1:0]), | |
559 | .din0 (wrdata0[`L2T_ARR_D_WIDTH - 1:0]), | |
560 | .din1 ({bist_wrdata0[3:0], bist_wrdata0[7:0], bist_wrdata0[7:0], bist_wrdata0[7:0]}), | |
561 | .sel0 (~l2t_bist_en0), | |
562 | .sel1 (l2t_bist_en0)); | |
563 | ||
564 | assign din3[`L2T_ARR_D_WIDTH - 1:0] = din1_v1[`L2T_ARR_D_WIDTH - 1:0]; | |
565 | assign din2[`L2T_ARR_D_WIDTH - 1:0] = din0_v1[`L2T_ARR_D_WIDTH - 1:0]; | |
566 | assign din1[`L2T_ARR_D_WIDTH - 1:0] = din1_v1[`L2T_ARR_D_WIDTH - 1:0]; | |
567 | assign din0[`L2T_ARR_D_WIDTH - 1:0] = din0_v1[`L2T_ARR_D_WIDTH - 1:0]; | |
568 | ||
569 | // rd_en and wr_en mux. | |
570 | // Change to structural coding CC | |
571 | //assign rd_en_a3 = ((~l2t_bist_en1) && (~bist_wr_en1) && rd_en1) || bist_rd_en1; | |
572 | //assign rd_en_a1 = ((~l2t_bist_en1) && (~bist_wr_en1) && rd_en1) || bist_rd_en1; | |
573 | //assign rd_en_a2 = ((~l2t_bist_en0) && (~bist_wr_en0) && rd_en0) || bist_rd_en0; | |
574 | //assign rd_en_a0 = ((~l2t_bist_en0) && (~bist_wr_en0) && rd_en0) || bist_rd_en0; | |
575 | ||
576 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rd_en_a3 | |
577 | ( | |
578 | .dout (rd_en_a3_tmp), | |
579 | .din0 (not_l2t_bist_en1), | |
580 | .din1 (not_bist_wr_en1), | |
581 | .din2 (rd_en1) | |
582 | ); | |
583 | ||
584 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_rd_en_a3 | |
585 | ( | |
586 | .dout (rd_en_a3), | |
587 | .din0 (rd_en_a3_tmp), | |
588 | .din1 (bist_rd_en1) | |
589 | ); | |
590 | ||
591 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rd_en_a1 | |
592 | ( | |
593 | .dout (rd_en_a1_tmp), | |
594 | .din0 (not_l2t_bist_en1), | |
595 | .din1 (not_bist_wr_en1), | |
596 | .din2 (rd_en1) | |
597 | ); | |
598 | ||
599 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_rd_en_a1 | |
600 | ( | |
601 | .dout (rd_en_a1), | |
602 | .din0 (rd_en_a1_tmp), | |
603 | .din1 (bist_rd_en1) | |
604 | ); | |
605 | //-- | |
606 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rd_en_a2 | |
607 | ( | |
608 | .dout (rd_en_a2_tmp), | |
609 | .din0 (not_l2t_bist_en0), | |
610 | .din1 (not_bist_wr_en0), | |
611 | .din2 (rd_en0) | |
612 | ); | |
613 | ||
614 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_rd_en_a2 | |
615 | ( | |
616 | .dout (rd_en_a2), | |
617 | .din0 (rd_en_a2_tmp), | |
618 | .din1 (bist_rd_en0) | |
619 | ); | |
620 | ||
621 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rd_en_a0 | |
622 | ( | |
623 | .dout (rd_en_a0_tmp), | |
624 | .din0 (not_l2t_bist_en0), | |
625 | .din1 (not_bist_wr_en0), | |
626 | .din2 (rd_en0) | |
627 | ); | |
628 | ||
629 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_rd_en_a0 | |
630 | ( | |
631 | .dout (rd_en_a0), | |
632 | .din0 (rd_en_a0_tmp), | |
633 | .din1 (bist_rd_en0) | |
634 | ); | |
635 | ||
636 | //-- | |
637 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_l2t_bist_en1 | |
638 | ( | |
639 | .din (l2t_bist_en1), | |
640 | .dout(not_l2t_bist_en1) | |
641 | ); | |
642 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_l2t_bist_en0 | |
643 | ( | |
644 | .din (l2t_bist_en0), | |
645 | .dout(not_l2t_bist_en0) | |
646 | ); | |
647 | ||
648 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_bist_wr_en1 | |
649 | ( | |
650 | .din (bist_wr_en1), | |
651 | .dout(not_bist_wr_en1) | |
652 | ); | |
653 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_bist_wr_en0 | |
654 | ( | |
655 | .din (bist_wr_en0), | |
656 | .dout(not_bist_wr_en0) | |
657 | ); | |
658 | ||
659 | //assign wr_en_a3 = ((~l2t_bist_en1) &&(~bist_rd_en1) && wr_en1) || bist_wr_en1; | |
660 | //assign wr_en_a1 = ((~l2t_bist_en1) &&(~bist_rd_en1) && wr_en1) || bist_wr_en1; | |
661 | //assign wr_en_a2 = ((~l2t_bist_en0) &&(~bist_rd_en0) && wr_en0) || bist_wr_en0; | |
662 | //assign wr_en_a0 = ((~l2t_bist_en0) &&(~bist_rd_en0) && wr_en0) || bist_wr_en0; | |
663 | ||
664 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_wr_en_a2 | |
665 | ( | |
666 | .dout (wr_en_a2_tmp), | |
667 | .din0 (not_l2t_bist_en0), | |
668 | .din1 (not_bist_rd_en0), | |
669 | .din2 (wr_en0) | |
670 | ); | |
671 | ||
672 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_wr_en_a2 | |
673 | ( | |
674 | .dout (wr_en_a2), | |
675 | .din0 (wr_en_a2_tmp), | |
676 | .din1 (bist_wr_en0) | |
677 | ); | |
678 | ||
679 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_wr_en_a0 | |
680 | ( | |
681 | .dout (wr_en_a0_tmp), | |
682 | .din0 (not_l2t_bist_en0), | |
683 | .din1 (not_bist_rd_en0), | |
684 | .din2 (wr_en0) | |
685 | ); | |
686 | ||
687 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_wr_en_a0 | |
688 | ( | |
689 | .dout (wr_en_a0), | |
690 | .din0 (wr_en_a0_tmp), | |
691 | .din1 (bist_wr_en0) | |
692 | ); | |
693 | //-- | |
694 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_wr_en_a3 | |
695 | ( | |
696 | .dout (wr_en_a3_tmp), | |
697 | .din0 (not_l2t_bist_en1), | |
698 | .din1 (not_bist_rd_en1), | |
699 | .din2 (wr_en1) | |
700 | ); | |
701 | ||
702 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_wr_en_a3 | |
703 | ( | |
704 | .dout (wr_en_a3), | |
705 | .din0 (wr_en_a3_tmp), | |
706 | .din1 (bist_wr_en1) | |
707 | ); | |
708 | ||
709 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_wr_en_a1 | |
710 | ( | |
711 | .dout (wr_en_a1_tmp), | |
712 | .din0 (not_l2t_bist_en1), | |
713 | .din1 (not_bist_rd_en1), | |
714 | .din2 (wr_en1) | |
715 | ); | |
716 | ||
717 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_wr_en_a1 | |
718 | ( | |
719 | .dout (wr_en_a1), | |
720 | .din0 (wr_en_a1_tmp), | |
721 | .din1 (bist_wr_en1) | |
722 | ); | |
723 | //-- | |
724 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_bist_rd_en1 | |
725 | ( | |
726 | .din (bist_rd_en1), | |
727 | .dout(not_bist_rd_en1) | |
728 | ); | |
729 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_bist_rd_en0 | |
730 | ( | |
731 | .din (bist_rd_en0), | |
732 | .dout(not_bist_rd_en0) | |
733 | ); | |
734 | ||
735 | // lkup_tag distribution to different quads | |
736 | ||
737 | assign lkup_tag_3[`L2T_ARR_D_WIDTH - 1:1] = lkup_tag1[`L2T_ARR_D_WIDTH - 1:1]; | |
738 | assign lkup_tag_1[`L2T_ARR_D_WIDTH - 1:1] = lkup_tag1[`L2T_ARR_D_WIDTH - 1:1]; | |
739 | assign lkup_tag_2[`L2T_ARR_D_WIDTH - 1:1] = lkup_tag0[`L2T_ARR_D_WIDTH - 1:1]; | |
740 | assign lkup_tag_0[`L2T_ARR_D_WIDTH - 1:1] = lkup_tag0[`L2T_ARR_D_WIDTH - 1:1]; | |
741 | ||
742 | //--------------------------------------- | |
743 | // Generation of pce signal | |
744 | //--------------------------------------- | |
745 | // Change to structural coding CC | |
746 | ||
747 | //assign rd_en = rd_en_a0 || rd_en_a1; | |
748 | ||
749 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_rd_en | |
750 | ( | |
751 | .dout (rd_en), | |
752 | .din0 (rd_en_a0), | |
753 | .din1 (rd_en_a1) | |
754 | ); | |
755 | ||
756 | ||
757 | //assign pce_out_a3 = rd_en_r || clk_en_ov_r; | |
758 | //assign pce_out_a1 = rd_en_r || clk_en_ov_r; | |
759 | //assign pce_out_a2 = rd_en_r || clk_en_ov_r; | |
760 | //assign pce_out_a0 = rd_en_r || clk_en_ov_r; | |
761 | ||
762 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_pce_out_a3 | |
763 | ( | |
764 | .dout (pce_out_a3), | |
765 | .din0 (rd_en_r), | |
766 | .din1 (clk_en_ov_r) | |
767 | ); | |
768 | ||
769 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_pce_out_a1 | |
770 | ( | |
771 | .dout (pce_out_a1), | |
772 | .din0 (rd_en_r), | |
773 | .din1 (clk_en_ov_r) | |
774 | ); | |
775 | ||
776 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_pce_out_a2 | |
777 | ( | |
778 | .dout (pce_out_a2), | |
779 | .din0 (rd_en_r), | |
780 | .din1 (clk_en_ov_r) | |
781 | ); | |
782 | ||
783 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_pce_out_a0 | |
784 | ( | |
785 | .dout (pce_out_a0), | |
786 | .din0 (rd_en_r), | |
787 | .din1 (clk_en_ov_r) | |
788 | ); | |
789 | ||
790 | ||
791 | //assign pce_ctl_a3 = clk_en1 || clk_en_ov_r; | |
792 | //assign pce_ctl_a1 = clk_en1 || clk_en_ov_r; | |
793 | //assign pce_ctl_a2 = clk_en0 || clk_en_ov_r; | |
794 | //assign pce_ctl_a0 = clk_en0 || clk_en_ov_r; | |
795 | ||
796 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_pce_ctl_a3 | |
797 | ( | |
798 | .dout (pce_ctl_a3), | |
799 | .din0 (clk_en1), | |
800 | .din1 (clk_en_ov_r) | |
801 | ); | |
802 | ||
803 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_pce_ctl_a1 | |
804 | ( | |
805 | .dout (pce_ctl_a1), | |
806 | .din0 (clk_en1), | |
807 | .din1 (clk_en_ov_r) | |
808 | ); | |
809 | ||
810 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_pce_ctl_a2 | |
811 | ( | |
812 | .dout (pce_ctl_a2), | |
813 | .din0 (clk_en0), | |
814 | .din1 (clk_en_ov_r) | |
815 | ); | |
816 | ||
817 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_pce_ctl_a0 | |
818 | ( | |
819 | .dout (pce_ctl_a0), | |
820 | .din0 (clk_en0), | |
821 | .din1 (clk_en_ov_r) | |
822 | ); | |
823 | ||
824 | //assign pce_din_a3 = wr_en_ov_r || bist_wr_en1 || wr_en1; | |
825 | //assign pce_din_a1 = wr_en_ov_r || bist_wr_en1 || wr_en1; | |
826 | //assign pce_din_a2 = wr_en_ov_r || bist_wr_en0 || wr_en0; | |
827 | //assign pce_din_a0 = wr_en_ov_r || bist_wr_en0 || wr_en0; | |
828 | ||
829 | n2_l2t_sp_28kb_cust_or_macro__ports_3__width_1 or_pce_din_a3 | |
830 | ( | |
831 | .dout (pce_din_a3), | |
832 | .din0 (wr_en_ov_r), | |
833 | .din1 (bist_wr_en1), | |
834 | .din2 (wr_en1) | |
835 | ); | |
836 | ||
837 | n2_l2t_sp_28kb_cust_or_macro__ports_3__width_1 or_pce_din_a1 | |
838 | ( | |
839 | .dout (pce_din_a1), | |
840 | .din0 (wr_en_ov_r), | |
841 | .din1 (bist_wr_en1), | |
842 | .din2 (wr_en1) | |
843 | ); | |
844 | ||
845 | n2_l2t_sp_28kb_cust_or_macro__ports_3__width_1 or_pce_din_a2 | |
846 | ( | |
847 | .dout (pce_din_a2), | |
848 | .din0 (wr_en_ov_r), | |
849 | .din1 (bist_wr_en0), | |
850 | .din2 (wr_en0) | |
851 | ); | |
852 | ||
853 | n2_l2t_sp_28kb_cust_or_macro__ports_3__width_1 or_pce_din_a0 | |
854 | ( | |
855 | .dout (pce_din_a0), | |
856 | .din0 (wr_en_ov_r), | |
857 | .din1 (bist_wr_en0), | |
858 | .din2 (wr_en0) | |
859 | ); | |
860 | ||
861 | assign pce_ov_a3 = tcu_pce_ov; | |
862 | assign pce_ov_a1 = tcu_pce_ov; | |
863 | assign pce_ov_a2 = tcu_pce_ov; | |
864 | assign pce_ov_a0 = tcu_pce_ov; | |
865 | ||
866 | //--------------------------------------- | |
867 | // Redundancy section | |
868 | //--------------------------------------- | |
869 | ||
870 | assign red_d_in_3[4:0] = hdr_l2t_rvalue_r[5:1]; | |
871 | assign red_d_in_1[4:0] = hdr_l2t_rvalue_r[5:1]; | |
872 | assign red_d_in_2[4:0] = hdr_l2t_rvalue_r[5:1]; | |
873 | assign red_d_in_0[4:0] = hdr_l2t_rvalue_r[5:1]; | |
874 | ||
875 | assign red_en_in_3[1:0] = {hdr_l2t_rvalue_r[0],hdr_l2t_rvalue_r[0]}; | |
876 | assign red_en_in_1[1:0] = {hdr_l2t_rvalue_r[0],hdr_l2t_rvalue_r[0]}; | |
877 | assign red_en_in_2[1:0] = {hdr_l2t_rvalue_r[0],hdr_l2t_rvalue_r[0]}; | |
878 | assign red_en_in_0[1:0] = {hdr_l2t_rvalue_r[0],hdr_l2t_rvalue_r[0]}; | |
879 | ||
880 | // Input is hdr_l2t_wr_en. Flopped version is hdr_l2t_wr_en_r | |
881 | // Chane to structural coding CC | |
882 | // assign red_wen_3 = hdr_l2t_wr_en_r && (~w_inhibit0); | |
883 | // assign red_wen_1 = hdr_l2t_wr_en_r && (~w_inhibit0); | |
884 | // assign red_wen_2 = hdr_l2t_wr_en_r && (~w_inhibit0); | |
885 | // assign red_wen_0 = hdr_l2t_wr_en_r && (~w_inhibit0); | |
886 | ||
887 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_w_inhibit0 | |
888 | ( | |
889 | .din (w_inhibit0), | |
890 | .dout(not_w_inhibit0) | |
891 | ); | |
892 | ||
893 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_red_wen_3 | |
894 | ( | |
895 | .dout (red_wen_3), | |
896 | .din0 (hdr_l2t_wr_en_r), | |
897 | .din1 (not_w_inhibit0) | |
898 | ); | |
899 | ||
900 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_red_wen_2 | |
901 | ( | |
902 | .dout (red_wen_2), | |
903 | .din0 (hdr_l2t_wr_en_r), | |
904 | .din1 (not_w_inhibit0) | |
905 | ); | |
906 | ||
907 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_red_wen_1 | |
908 | ( | |
909 | .dout (red_wen_1), | |
910 | .din0 (hdr_l2t_wr_en_r), | |
911 | .din1 (not_w_inhibit0) | |
912 | ); | |
913 | ||
914 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_red_wen_0 | |
915 | ( | |
916 | .dout (red_wen_0), | |
917 | .din0 (hdr_l2t_wr_en_r), | |
918 | .din1 (not_w_inhibit0) | |
919 | ); | |
920 | ||
921 | // Input is hdr_l2t_red_clr, flopped output is hdr_l2t_red_clr_r. | |
922 | // assign hdr_l2t_red_clr_r1 = ~(hdr_l2t_red_clr_r && (~w_inhibit0)) ; | |
923 | ||
924 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_hdr_l2t_red_clr_r_w_inhibit0 | |
925 | ( | |
926 | .dout (and_red_clr_r_w_inhibit0), | |
927 | .din0 (hdr_l2t_red_clr_r), | |
928 | .din1 (not_w_inhibit0) | |
929 | ); | |
930 | ||
931 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_hdr_l2t_red_clr_r1 | |
932 | ( | |
933 | .din (and_red_clr_r_w_inhibit0), | |
934 | .dout(hdr_l2t_red_clr_r1) | |
935 | ); | |
936 | ||
937 | //Input is hdr_l2t_rid and flopped output is hdr_l2t_rid_r | |
938 | assign rid_in_quad3[3:0] = { ( hdr_l2t_rid_r[3]), ( hdr_l2t_rid_r[2]), hdr_l2t_rid_r[1:0]}; | |
939 | assign rid_in_quad1[3:0] = { (~hdr_l2t_rid_r[3]), ( hdr_l2t_rid_r[2]), hdr_l2t_rid_r[1:0]}; | |
940 | assign rid_in_quad2[3:0] = { ( hdr_l2t_rid_r[3]), (~hdr_l2t_rid_r[2]), hdr_l2t_rid_r[1:0]}; | |
941 | assign rid_in_quad0[3:0] = { (~hdr_l2t_rid_r[3]), (~hdr_l2t_rid_r[2]), hdr_l2t_rid_r[1:0]}; | |
942 | ||
943 | ||
944 | //----------- | |
945 | //dft signals | |
946 | //----------- | |
947 | ||
948 | assign se_inff3 = tcu_se_scancollar_in1; | |
949 | assign se_inff1 = tcu_se_scancollar_in1; | |
950 | assign se_inff2 = tcu_se_scancollar_in0; | |
951 | assign se_inff0 = tcu_se_scancollar_in0; | |
952 | ||
953 | assign se_outff3 = tcu_se_scancollar_out1; | |
954 | assign se_outff1 = tcu_se_scancollar_out1; | |
955 | assign se_outff2 = tcu_se_scancollar_out0; | |
956 | assign se_outff0 = tcu_se_scancollar_out0; | |
957 | ||
958 | assign tcu_aclk_3 = tcu_aclk1; | |
959 | assign tcu_aclk_1 = tcu_aclk1; | |
960 | assign tcu_aclk_2 = tcu_aclk0; | |
961 | assign tcu_aclk_0 = tcu_aclk0; | |
962 | ||
963 | assign tcu_bclk_3 = tcu_bclk1; | |
964 | assign tcu_bclk_1 = tcu_bclk1; | |
965 | assign tcu_bclk_2 = tcu_bclk0; | |
966 | assign tcu_bclk_0 = tcu_bclk0; | |
967 | ||
968 | assign wr_inhibit_a3 = w_inhibit1; | |
969 | assign wr_inhibit_a1 = w_inhibit1; | |
970 | assign wr_inhibit_a2 = w_inhibit0; | |
971 | assign wr_inhibit_a0 = w_inhibit0; | |
972 | ||
973 | ||
974 | ||
975 | ||
976 | //--------------------------------------- | |
977 | // L2T ARRAY INSTANTIATION | |
978 | //--------------------------------------- | |
979 | n2_l2t_quad quad0 (/*AUTOINST*/ | |
980 | // Outputs | |
981 | .scan_out (quad0_scanout), // Templated | |
982 | .req_d_quad (req_d_quad0[4 : 0]), // Templated | |
983 | .req_en_quad (req_en_quad0[1 : 0]), // Templated | |
984 | .tag_way0 (tag_way0_0[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
985 | .tag_way1 (tag_way1_0[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
986 | .tag_way2 (tag_way2_0[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
987 | .tag_way3 (tag_way3_0[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
988 | .way_hit (way_hit0[3 : 0]), // Templated | |
989 | // Inputs | |
990 | .vnw_ary (vnw_ary), | |
991 | .scan_in (quad0_scanin), // Templated | |
992 | .arst_l (hdr_l2t_red_clr_r1), | |
993 | .din (din0[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
994 | .index (index_0[8 : 0]), // Templated | |
995 | .lkup_tag (lkup_tag_0[`L2T_ARR_D_WIDTH - 1 : 1]), // Templated | |
996 | .l2clk (l2clk), | |
997 | .pce_ov (pce_ov_a0), // Templated | |
998 | .pce_out (pce_out_a0), // Templated | |
999 | .pce_din (pce_din_a0), // Templated | |
1000 | .pce_ctl (pce_ctl_a0), // Templated | |
1001 | .rd_en_a (rd_en_a0), // Templated | |
1002 | .red_d_in (red_d_in_0[4 : 0]), // Templated | |
1003 | .red_en_in (red_en_in_0[1 : 0]), // Templated | |
1004 | .red_wen (red_wen_0), // Templated | |
1005 | .rid_in (rid_in_quad0[3:0]), | |
1006 | .tcu_aclk (tcu_aclk_0), // Templated | |
1007 | .tcu_bclk (tcu_bclk_0), // Templated | |
1008 | .se_inff (se_inff0), // Templated | |
1009 | .se_outff (se_outff0), // Templated | |
1010 | .scan_en (scan_en0), // Templated | |
1011 | .way (way0[3:0]), | |
1012 | .wr_en_a (wr_en_a0), // Templated | |
1013 | .wr_inhibit_a (wr_inhibit_a0)); // Templated | |
1014 | ||
1015 | n2_l2t_quad quad1 (/*AUTOINST*/ | |
1016 | // Outputs | |
1017 | .scan_out (quad1_scanout), // Templated | |
1018 | .req_d_quad (req_d_quad1[4 : 0]), // Templated | |
1019 | .req_en_quad (req_en_quad1[1 : 0]), // Templated | |
1020 | .tag_way0 (tag_way0_1[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1021 | .tag_way1 (tag_way1_1[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1022 | .tag_way2 (tag_way2_1[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1023 | .tag_way3 (tag_way3_1[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1024 | .way_hit (way_hit1[3 : 0]), // Templated | |
1025 | // Inputs | |
1026 | .vnw_ary (vnw_ary), | |
1027 | .scan_in (quad1_scanin), // Templated | |
1028 | .arst_l (hdr_l2t_red_clr_r1), | |
1029 | .din (din1[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1030 | .index (index_1[8 : 0]), // Templated | |
1031 | .lkup_tag (lkup_tag_1[`L2T_ARR_D_WIDTH - 1 : 1]), // Templated | |
1032 | .l2clk (l2clk), | |
1033 | .pce_ov (pce_ov_a1), // Templated | |
1034 | .pce_out (pce_out_a1), // Templated | |
1035 | .pce_din (pce_din_a1), // Templated | |
1036 | .pce_ctl (pce_ctl_a1), // Templated | |
1037 | .rd_en_a (rd_en_a1), // Templated | |
1038 | .red_d_in (red_d_in_1[4 : 0]), // Templated | |
1039 | .red_en_in (red_en_in_1[1 : 0]), // Templated | |
1040 | .red_wen (red_wen_1), // Templated | |
1041 | .rid_in (rid_in_quad1[3:0]), | |
1042 | .tcu_aclk (tcu_aclk_1), // Templated | |
1043 | .tcu_bclk (tcu_bclk_1), // Templated | |
1044 | .se_inff (se_inff1), // Templated | |
1045 | .se_outff (se_outff1), // Templated | |
1046 | .scan_en (scan_en1), // Templated | |
1047 | .way (way1[3 : 0]), // Templated | |
1048 | .wr_en_a (wr_en_a1), // Templated | |
1049 | .wr_inhibit_a (wr_inhibit_a1)); // Templated | |
1050 | ||
1051 | n2_l2t_quad quad2 (/*AUTOINST*/ | |
1052 | // Outputs | |
1053 | .scan_out (quad2_scanout), // Templated | |
1054 | .req_d_quad (req_d_quad2[4 : 0]), // Templated | |
1055 | .req_en_quad (req_en_quad2[1 : 0]), // Templated | |
1056 | .tag_way0 (tag_way0_2[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1057 | .tag_way1 (tag_way1_2[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1058 | .tag_way2 (tag_way2_2[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1059 | .tag_way3 (tag_way3_2[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1060 | .way_hit (way_hit2[3 : 0]), // Templated | |
1061 | // Inputs | |
1062 | .vnw_ary (vnw_ary), | |
1063 | .scan_in (quad2_scanin), // Templated | |
1064 | .arst_l (hdr_l2t_red_clr_r1), | |
1065 | .din (din2[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1066 | .index (index_2[8 : 0]), // Templated | |
1067 | .lkup_tag (lkup_tag_2[`L2T_ARR_D_WIDTH - 1 : 1]), // Templated | |
1068 | .l2clk (l2clk), | |
1069 | .pce_ov (pce_ov_a2), // Templated | |
1070 | .pce_out (pce_out_a2), // Templated | |
1071 | .pce_din (pce_din_a2), // Templated | |
1072 | .pce_ctl (pce_ctl_a2), // Templated | |
1073 | .rd_en_a (rd_en_a2), // Templated | |
1074 | .red_d_in (red_d_in_2[4 : 0]), // Templated | |
1075 | .red_en_in (red_en_in_2[1 : 0]), // Templated | |
1076 | .red_wen (red_wen_2), // Templated | |
1077 | .rid_in (rid_in_quad2[3:0]), | |
1078 | .tcu_aclk (tcu_aclk_2), // Templated | |
1079 | .tcu_bclk (tcu_bclk_2), // Templated | |
1080 | .se_inff (se_inff2), // Templated | |
1081 | .se_outff (se_outff2), // Templated | |
1082 | .scan_en (scan_en2), // Templated | |
1083 | .way (way2[3 : 0]), // Templated | |
1084 | .wr_en_a (wr_en_a2), // Templated | |
1085 | .wr_inhibit_a (wr_inhibit_a2)); // Templated | |
1086 | ||
1087 | n2_l2t_quad quad3 (/*AUTOINST*/ | |
1088 | // Outputs | |
1089 | .scan_out (quad3_scanout), // Templated | |
1090 | .req_d_quad (req_d_quad3[4 : 0]), // Templated | |
1091 | .req_en_quad (req_en_quad3[1 : 0]), // Templated | |
1092 | .tag_way0 (tag_way0_3[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1093 | .tag_way1 (tag_way1_3[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1094 | .tag_way2 (tag_way2_3[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1095 | .tag_way3 (tag_way3_3[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1096 | .way_hit (way_hit3[3 : 0]), // Templated | |
1097 | // Inputs | |
1098 | .vnw_ary (vnw_ary), | |
1099 | .scan_in (quad3_scanin), // Templated | |
1100 | .arst_l (hdr_l2t_red_clr_r1), | |
1101 | .din (din3[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
1102 | .index (index_3[8 : 0]), // Templated | |
1103 | .lkup_tag (lkup_tag_3[`L2T_ARR_D_WIDTH - 1 : 1]), // Templated | |
1104 | .l2clk (l2clk), | |
1105 | .pce_ov (pce_ov_a3), // Templated | |
1106 | .pce_out (pce_out_a3), // Templated | |
1107 | .pce_din (pce_din_a3), // Templated | |
1108 | .pce_ctl (pce_ctl_a3), // Templated | |
1109 | .rd_en_a (rd_en_a3), // Templated | |
1110 | .red_d_in (red_d_in_3[4 : 0]), // Templated | |
1111 | .red_en_in (red_en_in_3[1 : 0]), // Templated | |
1112 | .red_wen (red_wen_3), // Templated | |
1113 | .rid_in (rid_in_quad3[3:0]), | |
1114 | .tcu_aclk (tcu_aclk_3), // Templated | |
1115 | .tcu_bclk (tcu_bclk_3), // Templated | |
1116 | .se_inff (se_inff3), // Templated | |
1117 | .se_outff (se_outff3), // Templated | |
1118 | .scan_en (scan_en3), // Templated | |
1119 | .way (way3[3 : 0]), // Templated | |
1120 | .wr_en_a (wr_en_a3), // Templated | |
1121 | .wr_inhibit_a (wr_inhibit_a3)); // Templated | |
1122 | ||
1123 | //************************************************************************ | |
1124 | // REGISTERS SECTION | |
1125 | //************************************************************************ | |
1126 | ||
1127 | //REDUNDANCY INPUTS FLOPS | |
1128 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_6 ff_hdr_l2t_rvalue | |
1129 | ( | |
1130 | .scan_in(hdr_l2t_rvalue_scanin), | |
1131 | .scan_out(hdr_l2t_rvalue_scanout), | |
1132 | .l1clk (l1clk_in), | |
1133 | .dout (hdr_l2t_rvalue_r[5:0]), | |
1134 | .din (hdr_l2t_rvalue[5:0]), | |
1135 | .siclk(siclk), | |
1136 | .soclk(soclk) | |
1137 | ); | |
1138 | ||
1139 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_4 ff_hdr_l2t_rid | |
1140 | ( | |
1141 | .scan_in(hdr_l2t_rid_scanin), | |
1142 | .scan_out(hdr_l2t_rid_scanout), | |
1143 | .l1clk (l1clk_in), | |
1144 | .dout (hdr_l2t_rid_r[3:0]), | |
1145 | .din (hdr_l2t_rid[3:0]), | |
1146 | .siclk(siclk), | |
1147 | .soclk(soclk) | |
1148 | ); | |
1149 | ||
1150 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 ff_hdr_l2t_red_clr | |
1151 | ( | |
1152 | .scan_in(hdr_l2t_red_clr_scanin), | |
1153 | .scan_out(hdr_l2t_red_clr_scanout), | |
1154 | .l1clk (l1clk_in), | |
1155 | .dout (hdr_l2t_red_clr_r), | |
1156 | .din (hdr_l2t_red_clr), | |
1157 | .siclk(siclk), | |
1158 | .soclk(soclk) | |
1159 | ); | |
1160 | ||
1161 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 ff_write_enable | |
1162 | ( | |
1163 | .scan_in(hdr_l2t_wr_en_scanin), | |
1164 | .scan_out(hdr_l2t_wr_en_scanout), | |
1165 | .dout (hdr_l2t_wr_en_r), | |
1166 | .din (hdr_l2t_wr_en), | |
1167 | .l1clk (l1clk_in), | |
1168 | .siclk(siclk), | |
1169 | .soclk(soclk) | |
1170 | ); | |
1171 | ||
1172 | // POWER SAVING INPUT FLOPS | |
1173 | ||
1174 | // Remove flop for tcu_pce_ov | |
1175 | //msff_ctl_macro ff_pce_ov (width=1) | |
1176 | // ( | |
1177 | // .scan_in(1'b1), | |
1178 | // .scan_out(tcu_pce_ov_scanout), | |
1179 | // .dout (pce_ov_r), | |
1180 | // .din (tcu_pce_ov), | |
1181 | // .l1clk (l1clk_in)); | |
1182 | ||
1183 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 ff_rd_en | |
1184 | ( | |
1185 | .scan_in(rd_en_scanin), | |
1186 | .scan_out(rd_en_scanout), | |
1187 | .dout (rd_en_r), | |
1188 | .din (rd_en), | |
1189 | .l1clk (l1clk_in), | |
1190 | .siclk(siclk), | |
1191 | .soclk(soclk) | |
1192 | ); | |
1193 | ||
1194 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 ff_clk_en_ov | |
1195 | ( | |
1196 | .scan_in(clk_en_ov_scanin), | |
1197 | .scan_out(clk_en_ov_scanout), | |
1198 | .dout (clk_en_ov_r), | |
1199 | .din (clk_en_ov), | |
1200 | .l1clk (l1clk_in), | |
1201 | .siclk(siclk), | |
1202 | .soclk(soclk) | |
1203 | ); | |
1204 | ||
1205 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 ff_ff_wr_en_ov | |
1206 | ( | |
1207 | .scan_in(wr_en_ov_scanin), | |
1208 | .scan_out(wr_en_ov_scanout), | |
1209 | .dout (wr_en_ov_r), | |
1210 | .din (wr_en_ov), | |
1211 | .l1clk (l1clk_in), | |
1212 | .siclk(siclk), | |
1213 | .soclk(soclk) | |
1214 | ); | |
1215 | ||
1216 | //OUTPUT FLOPS | |
1217 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_6 ff_l2t_hdr_read_data | |
1218 | ( | |
1219 | .scan_in (l2t_hdr_read_data_scanin), | |
1220 | .scan_out(l2t_hdr_read_data_scanout), | |
1221 | .dout (l2t_hdr_read_data[5:0]), | |
1222 | .din (red_data[5:0]), | |
1223 | .l1clk (l1clk_out), | |
1224 | .siclk(siclk), | |
1225 | .soclk(soclk) | |
1226 | ); | |
1227 | ||
1228 | ||
1229 | // =============== VERILOG-MODE AUTO TEMPLATES | |
1230 | ||
1231 | /* | |
1232 | ||
1233 | n2_l2t_quad AUTO_TEMPLATE ( | |
1234 | .scan_in (quad@_scanin), | |
1235 | .se_inff(se_inff@), | |
1236 | .se_outff(se_outff@), | |
1237 | .scan_en(scan_en@), | |
1238 | .din(din@[`L2T_ARR_D_WIDTH - 1 : 0]), | |
1239 | .arst_l (hdr_l2t_red_clr_r1), | |
1240 | .index(index_@[8 : 0]), | |
1241 | .lkup_tag(lkup_tag@[`L2T_ARR_D_WIDTH - 1 : 1]), | |
1242 | .rd_en_a(rd_en_a@), | |
1243 | .wr_en_a(wr_en_a@), | |
1244 | .way(way@[3 : 0]), | |
1245 | .red_d_in(red_d_in_@[4 : 0]), | |
1246 | .red_en_in(red_en_in_@[1 : 0]), | |
1247 | .red_wen(red_wen_@), | |
1248 | .tcu_aclk(tcu_aclk_@), | |
1249 | .tcu_bclk(tcu_bclk_@), | |
1250 | .pce_ov(pce_ov_a@), | |
1251 | .pce_out(pce_out_a@), | |
1252 | .pce_din(pce_din_a@), | |
1253 | .pce_ctl(pce_ctl_a@), | |
1254 | .wr_inhibit_a(wr_inhibit_a@), | |
1255 | .way_hit(way_hit@[3 : 0]), | |
1256 | .tag_way0(tag_way0_@[`L2T_ARR_D_WIDTH - 1 : 0]), | |
1257 | .tag_way1(tag_way1_@[`L2T_ARR_D_WIDTH - 1 : 0]), | |
1258 | .tag_way2(tag_way2_@[`L2T_ARR_D_WIDTH - 1 : 0]), | |
1259 | .tag_way3(tag_way3_@[`L2T_ARR_D_WIDTH - 1 : 0]), | |
1260 | .req_d_quad(req_d_quad@[4 : 0]), | |
1261 | .req_en_quad(req_en_quad@[1 : 0]), | |
1262 | .scan_out (quad@_scanout), | |
1263 | ); | |
1264 | ||
1265 | */ | |
1266 | // fixscan start: | |
1267 | assign quad2_scanin = scan_in ; | |
1268 | assign quad0_scanin = quad2_scanout ; | |
1269 | assign quad1_scanin = quad0_scanout ; | |
1270 | assign quad3_scanin = quad1_scanout ; | |
1271 | assign hdr_l2t_rvalue_scanin = quad3_scanout ; | |
1272 | assign hdr_l2t_rid_scanin = hdr_l2t_rvalue_scanout ; | |
1273 | assign hdr_l2t_wr_en_scanin = hdr_l2t_rid_scanout ; | |
1274 | assign hdr_l2t_red_clr_scanin = hdr_l2t_wr_en_scanout ; | |
1275 | assign l2t_hdr_read_data_scanin = hdr_l2t_red_clr_scanout ; | |
1276 | assign wr_en_ov_scanin = l2t_hdr_read_data_scanout; | |
1277 | assign clk_en_ov_scanin = wr_en_ov_scanout ; | |
1278 | assign rd_en_scanin = clk_en_ov_scanout ; | |
1279 | assign scan_out = rd_en_scanout ; | |
1280 | // fixscan end: | |
1281 | ||
1282 | // JDL 05/17/07 | |
1283 | // synopsys translate_on | |
1284 | ||
1285 | endmodule | |
1286 | ||
1287 | ||
1288 | ||
1289 | ||
1290 | ||
1291 | ||
1292 | // any PARAMS parms go into naming of macro | |
1293 | ||
1294 | module n2_l2t_sp_28kb_cust_l1clkhdr_ctl_macro ( | |
1295 | l2clk, | |
1296 | l1en, | |
1297 | pce_ov, | |
1298 | stop, | |
1299 | se, | |
1300 | l1clk); | |
1301 | ||
1302 | ||
1303 | input l2clk; | |
1304 | input l1en; | |
1305 | input pce_ov; | |
1306 | input stop; | |
1307 | input se; | |
1308 | output l1clk; | |
1309 | ||
1310 | ||
1311 | ||
1312 | ||
1313 | ||
1314 | cl_sc1_l1hdr_8x c_0 ( | |
1315 | ||
1316 | ||
1317 | .l2clk(l2clk), | |
1318 | .pce(l1en), | |
1319 | .l1clk(l1clk), | |
1320 | .se(se), | |
1321 | .pce_ov(pce_ov), | |
1322 | .stop(stop) | |
1323 | ); | |
1324 | ||
1325 | ||
1326 | ||
1327 | endmodule | |
1328 | ||
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | // | |
1338 | // or macro for ports = 2,3 | |
1339 | // | |
1340 | // | |
1341 | ||
1342 | ||
1343 | ||
1344 | ||
1345 | ||
1346 | module n2_l2t_sp_28kb_cust_or_macro__ports_3__width_5 ( | |
1347 | din0, | |
1348 | din1, | |
1349 | din2, | |
1350 | dout); | |
1351 | input [4:0] din0; | |
1352 | input [4:0] din1; | |
1353 | input [4:0] din2; | |
1354 | output [4:0] dout; | |
1355 | ||
1356 | ||
1357 | ||
1358 | ||
1359 | ||
1360 | ||
1361 | or3 #(5) d0_0 ( | |
1362 | .in0(din0[4:0]), | |
1363 | .in1(din1[4:0]), | |
1364 | .in2(din2[4:0]), | |
1365 | .out(dout[4:0]) | |
1366 | ); | |
1367 | ||
1368 | ||
1369 | ||
1370 | ||
1371 | ||
1372 | ||
1373 | ||
1374 | ||
1375 | ||
1376 | endmodule | |
1377 | ||
1378 | ||
1379 | ||
1380 | ||
1381 | ||
1382 | // | |
1383 | // or macro for ports = 2,3 | |
1384 | // | |
1385 | // | |
1386 | ||
1387 | ||
1388 | ||
1389 | ||
1390 | ||
1391 | module n2_l2t_sp_28kb_cust_or_macro__ports_2__width_5 ( | |
1392 | din0, | |
1393 | din1, | |
1394 | dout); | |
1395 | input [4:0] din0; | |
1396 | input [4:0] din1; | |
1397 | output [4:0] dout; | |
1398 | ||
1399 | ||
1400 | ||
1401 | ||
1402 | ||
1403 | ||
1404 | or2 #(5) d0_0 ( | |
1405 | .in0(din0[4:0]), | |
1406 | .in1(din1[4:0]), | |
1407 | .out(dout[4:0]) | |
1408 | ); | |
1409 | ||
1410 | ||
1411 | ||
1412 | ||
1413 | ||
1414 | ||
1415 | ||
1416 | ||
1417 | ||
1418 | endmodule | |
1419 | ||
1420 | ||
1421 | ||
1422 | ||
1423 | ||
1424 | // | |
1425 | // and macro for ports = 2,3,4 | |
1426 | // | |
1427 | // | |
1428 | ||
1429 | ||
1430 | ||
1431 | ||
1432 | ||
1433 | module n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 ( | |
1434 | din0, | |
1435 | din1, | |
1436 | dout); | |
1437 | input [0:0] din0; | |
1438 | input [0:0] din1; | |
1439 | output [0:0] dout; | |
1440 | ||
1441 | ||
1442 | ||
1443 | ||
1444 | ||
1445 | ||
1446 | and2 #(1) d0_0 ( | |
1447 | .in0(din0[0:0]), | |
1448 | .in1(din1[0:0]), | |
1449 | .out(dout[0:0]) | |
1450 | ); | |
1451 | ||
1452 | ||
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | ||
1459 | ||
1460 | endmodule | |
1461 | ||
1462 | ||
1463 | ||
1464 | ||
1465 | ||
1466 | // | |
1467 | // or macro for ports = 2,3 | |
1468 | // | |
1469 | // | |
1470 | ||
1471 | ||
1472 | ||
1473 | ||
1474 | ||
1475 | module n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 ( | |
1476 | din0, | |
1477 | din1, | |
1478 | dout); | |
1479 | input [0:0] din0; | |
1480 | input [0:0] din1; | |
1481 | output [0:0] dout; | |
1482 | ||
1483 | ||
1484 | ||
1485 | ||
1486 | ||
1487 | ||
1488 | or2 #(1) d0_0 ( | |
1489 | .in0(din0[0:0]), | |
1490 | .in1(din1[0:0]), | |
1491 | .out(dout[0:0]) | |
1492 | ); | |
1493 | ||
1494 | ||
1495 | ||
1496 | ||
1497 | ||
1498 | ||
1499 | ||
1500 | ||
1501 | ||
1502 | endmodule | |
1503 | ||
1504 | ||
1505 | ||
1506 | ||
1507 | ||
1508 | // | |
1509 | // or macro for ports = 2,3 | |
1510 | // | |
1511 | // | |
1512 | ||
1513 | ||
1514 | ||
1515 | ||
1516 | ||
1517 | module n2_l2t_sp_28kb_cust_or_macro__ports_3__width_1 ( | |
1518 | din0, | |
1519 | din1, | |
1520 | din2, | |
1521 | dout); | |
1522 | input [0:0] din0; | |
1523 | input [0:0] din1; | |
1524 | input [0:0] din2; | |
1525 | output [0:0] dout; | |
1526 | ||
1527 | ||
1528 | ||
1529 | ||
1530 | ||
1531 | ||
1532 | or3 #(1) d0_0 ( | |
1533 | .in0(din0[0:0]), | |
1534 | .in1(din1[0:0]), | |
1535 | .in2(din2[0:0]), | |
1536 | .out(dout[0:0]) | |
1537 | ); | |
1538 | ||
1539 | ||
1540 | ||
1541 | ||
1542 | ||
1543 | ||
1544 | ||
1545 | ||
1546 | ||
1547 | endmodule | |
1548 | ||
1549 | ||
1550 | ||
1551 | ||
1552 | ||
1553 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1554 | // also for pass-gate with decoder | |
1555 | ||
1556 | ||
1557 | ||
1558 | ||
1559 | ||
1560 | // any PARAMS parms go into naming of macro | |
1561 | ||
1562 | module n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_9 ( | |
1563 | din0, | |
1564 | sel0, | |
1565 | din1, | |
1566 | sel1, | |
1567 | dout); | |
1568 | wire buffout0; | |
1569 | wire buffout1; | |
1570 | ||
1571 | input [8:0] din0; | |
1572 | input sel0; | |
1573 | input [8:0] din1; | |
1574 | input sel1; | |
1575 | output [8:0] dout; | |
1576 | ||
1577 | ||
1578 | ||
1579 | ||
1580 | ||
1581 | cl_dp1_muxbuff2_8x c0_0 ( | |
1582 | .in0(sel0), | |
1583 | .in1(sel1), | |
1584 | .out0(buffout0), | |
1585 | .out1(buffout1) | |
1586 | ); | |
1587 | mux2s #(9) d0_0 ( | |
1588 | .sel0(buffout0), | |
1589 | .sel1(buffout1), | |
1590 | .in0(din0[8:0]), | |
1591 | .in1(din1[8:0]), | |
1592 | .dout(dout[8:0]) | |
1593 | ); | |
1594 | ||
1595 | ||
1596 | ||
1597 | ||
1598 | ||
1599 | ||
1600 | ||
1601 | ||
1602 | ||
1603 | ||
1604 | ||
1605 | ||
1606 | ||
1607 | endmodule | |
1608 | ||
1609 | ||
1610 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1611 | // also for pass-gate with decoder | |
1612 | ||
1613 | ||
1614 | ||
1615 | ||
1616 | ||
1617 | // any PARAMS parms go into naming of macro | |
1618 | ||
1619 | module n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_8 ( | |
1620 | din0, | |
1621 | sel0, | |
1622 | din1, | |
1623 | sel1, | |
1624 | dout); | |
1625 | wire buffout0; | |
1626 | wire buffout1; | |
1627 | ||
1628 | input [7:0] din0; | |
1629 | input sel0; | |
1630 | input [7:0] din1; | |
1631 | input sel1; | |
1632 | output [7:0] dout; | |
1633 | ||
1634 | ||
1635 | ||
1636 | ||
1637 | ||
1638 | cl_dp1_muxbuff2_8x c0_0 ( | |
1639 | .in0(sel0), | |
1640 | .in1(sel1), | |
1641 | .out0(buffout0), | |
1642 | .out1(buffout1) | |
1643 | ); | |
1644 | mux2s #(8) d0_0 ( | |
1645 | .sel0(buffout0), | |
1646 | .sel1(buffout1), | |
1647 | .in0(din0[7:0]), | |
1648 | .in1(din1[7:0]), | |
1649 | .dout(dout[7:0]) | |
1650 | ); | |
1651 | ||
1652 | ||
1653 | ||
1654 | ||
1655 | ||
1656 | ||
1657 | ||
1658 | ||
1659 | ||
1660 | ||
1661 | ||
1662 | ||
1663 | ||
1664 | endmodule | |
1665 | ||
1666 | ||
1667 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1668 | // also for pass-gate with decoder | |
1669 | ||
1670 | ||
1671 | ||
1672 | ||
1673 | ||
1674 | // any PARAMS parms go into naming of macro | |
1675 | ||
1676 | module n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_28 ( | |
1677 | din0, | |
1678 | sel0, | |
1679 | din1, | |
1680 | sel1, | |
1681 | dout); | |
1682 | wire buffout0; | |
1683 | wire buffout1; | |
1684 | ||
1685 | input [27:0] din0; | |
1686 | input sel0; | |
1687 | input [27:0] din1; | |
1688 | input sel1; | |
1689 | output [27:0] dout; | |
1690 | ||
1691 | ||
1692 | ||
1693 | ||
1694 | ||
1695 | cl_dp1_muxbuff2_8x c0_0 ( | |
1696 | .in0(sel0), | |
1697 | .in1(sel1), | |
1698 | .out0(buffout0), | |
1699 | .out1(buffout1) | |
1700 | ); | |
1701 | mux2s #(28) d0_0 ( | |
1702 | .sel0(buffout0), | |
1703 | .sel1(buffout1), | |
1704 | .in0(din0[27:0]), | |
1705 | .in1(din1[27:0]), | |
1706 | .dout(dout[27:0]) | |
1707 | ); | |
1708 | ||
1709 | ||
1710 | ||
1711 | ||
1712 | ||
1713 | ||
1714 | ||
1715 | ||
1716 | ||
1717 | ||
1718 | ||
1719 | ||
1720 | ||
1721 | endmodule | |
1722 | ||
1723 | ||
1724 | // | |
1725 | // and macro for ports = 2,3,4 | |
1726 | // | |
1727 | // | |
1728 | ||
1729 | ||
1730 | ||
1731 | ||
1732 | ||
1733 | module n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 ( | |
1734 | din0, | |
1735 | din1, | |
1736 | din2, | |
1737 | dout); | |
1738 | input [0:0] din0; | |
1739 | input [0:0] din1; | |
1740 | input [0:0] din2; | |
1741 | output [0:0] dout; | |
1742 | ||
1743 | ||
1744 | ||
1745 | ||
1746 | ||
1747 | ||
1748 | and3 #(1) d0_0 ( | |
1749 | .in0(din0[0:0]), | |
1750 | .in1(din1[0:0]), | |
1751 | .in2(din2[0:0]), | |
1752 | .out(dout[0:0]) | |
1753 | ); | |
1754 | ||
1755 | ||
1756 | ||
1757 | ||
1758 | ||
1759 | ||
1760 | ||
1761 | ||
1762 | ||
1763 | endmodule | |
1764 | ||
1765 | ||
1766 | ||
1767 | ||
1768 | ||
1769 | // | |
1770 | // invert macro | |
1771 | // | |
1772 | // | |
1773 | ||
1774 | ||
1775 | ||
1776 | ||
1777 | ||
1778 | module n2_l2t_sp_28kb_cust_inv_macro__width_1 ( | |
1779 | din, | |
1780 | dout); | |
1781 | input [0:0] din; | |
1782 | output [0:0] dout; | |
1783 | ||
1784 | ||
1785 | ||
1786 | ||
1787 | ||
1788 | ||
1789 | inv #(1) d0_0 ( | |
1790 | .in(din[0:0]), | |
1791 | .out(dout[0:0]) | |
1792 | ); | |
1793 | ||
1794 | ||
1795 | ||
1796 | ||
1797 | ||
1798 | ||
1799 | ||
1800 | ||
1801 | ||
1802 | endmodule | |
1803 | ||
1804 | ||
1805 | ||
1806 | ||
1807 | ||
1808 | ||
1809 | ||
1810 | `define L2T_ARR_D_WIDTH 28 | |
1811 | `define L2T_ARR_DEPTH 512 | |
1812 | `define WAY_HIT_WIDTH 16 | |
1813 | `define BADREAD BADBADD | |
1814 | ||
1815 | ||
1816 | ||
1817 | module n2_l2t_quad ( | |
1818 | vnw_ary, | |
1819 | scan_in, | |
1820 | scan_out, | |
1821 | arst_l, | |
1822 | din, | |
1823 | index, | |
1824 | lkup_tag, | |
1825 | l2clk, | |
1826 | pce_ov, | |
1827 | pce_out, | |
1828 | pce_din, | |
1829 | pce_ctl, | |
1830 | rd_en_a, | |
1831 | red_d_in, | |
1832 | red_en_in, | |
1833 | red_wen, | |
1834 | rid_in, | |
1835 | tcu_aclk, | |
1836 | tcu_bclk, | |
1837 | se_inff, | |
1838 | se_outff, | |
1839 | scan_en, | |
1840 | way, | |
1841 | wr_en_a, | |
1842 | wr_inhibit_a, | |
1843 | req_d_quad, | |
1844 | req_en_quad, | |
1845 | tag_way0, | |
1846 | tag_way1, | |
1847 | tag_way2, | |
1848 | tag_way3, | |
1849 | way_hit); | |
1850 | wire l1clk_din0; | |
1851 | wire l1clk_din1; | |
1852 | wire l1clk_in; | |
1853 | wire se_unused; | |
1854 | wire siclk; | |
1855 | wire soclk; | |
1856 | wire clk_stop; | |
1857 | wire [4:0] reg_d1; | |
1858 | wire [4:0] reg_d0; | |
1859 | wire [1:0] reg_en1; | |
1860 | wire [1:0] reg_en0; | |
1861 | wire [27:0] tag_way0_0; | |
1862 | wire [27:0] tag_way1_0; | |
1863 | wire [27:0] tag_way0_1; | |
1864 | wire [27:0] tag_way1_1; | |
1865 | wire [1:0] way_hit_a1; | |
1866 | wire [1:0] way_hit_a0; | |
1867 | wire [8:0] index_a; | |
1868 | wire [1:0] way_a0; | |
1869 | wire [1:0] way_a1; | |
1870 | wire [4:0] reg_d_in; | |
1871 | wire [1:0] reg_en_in; | |
1872 | wire not_quad_active; | |
1873 | wire quad_active_unused; | |
1874 | wire not_arst_l; | |
1875 | wire [1:0] not_rid_in; | |
1876 | wire rid_rgt1; | |
1877 | wire rid_rgt0; | |
1878 | wire rid_lft1; | |
1879 | wire rid_lft0; | |
1880 | wire rid_rgt1_wen; | |
1881 | wire reg_wen_rgt1; | |
1882 | wire rid_rgt0_wen; | |
1883 | wire reg_wen_rgt0; | |
1884 | wire rid_lft1_wen; | |
1885 | wire reg_wen_lft1; | |
1886 | wire rid_lft0_wen; | |
1887 | wire reg_wen_lft0; | |
1888 | wire bank0_scanout; | |
1889 | wire bank0_scanin; | |
1890 | wire [27:0] din_r; | |
1891 | wire bank1_scanout; | |
1892 | wire bank1_scanin; | |
1893 | wire reg_din_27_scanin; | |
1894 | wire reg_din_27_scanout; | |
1895 | wire reg_din_26_scanin; | |
1896 | wire reg_din_26_scanout; | |
1897 | wire reg_din_25_scanin; | |
1898 | wire reg_din_25_scanout; | |
1899 | wire reg_din_24_scanin; | |
1900 | wire reg_din_24_scanout; | |
1901 | wire reg_din_23_scanin; | |
1902 | wire reg_din_23_scanout; | |
1903 | wire reg_din_22_scanin; | |
1904 | wire reg_din_22_scanout; | |
1905 | wire reg_din_21_scanin; | |
1906 | wire reg_din_21_scanout; | |
1907 | wire reg_din_20_scanin; | |
1908 | wire reg_din_20_scanout; | |
1909 | wire reg_din_19_scanin; | |
1910 | wire reg_din_19_scanout; | |
1911 | wire reg_din_18_scanin; | |
1912 | wire reg_din_18_scanout; | |
1913 | wire reg_din_17_scanin; | |
1914 | wire reg_din_17_scanout; | |
1915 | wire reg_din_16_scanin; | |
1916 | wire reg_din_16_scanout; | |
1917 | wire reg_din_15_scanin; | |
1918 | wire reg_din_15_scanout; | |
1919 | wire reg_din_14_scanin; | |
1920 | wire reg_din_14_scanout; | |
1921 | wire reg_din_13_scanin; | |
1922 | wire reg_din_13_scanout; | |
1923 | wire reg_din_12_scanin; | |
1924 | wire reg_din_12_scanout; | |
1925 | wire reg_din_11_scanin; | |
1926 | wire reg_din_11_scanout; | |
1927 | wire reg_din_10_scanin; | |
1928 | wire reg_din_10_scanout; | |
1929 | wire reg_din_9_scanin; | |
1930 | wire reg_din_9_scanout; | |
1931 | wire reg_din_8_scanin; | |
1932 | wire reg_din_8_scanout; | |
1933 | wire reg_din_7_scanin; | |
1934 | wire reg_din_7_scanout; | |
1935 | wire reg_din_6_scanin; | |
1936 | wire reg_din_6_scanout; | |
1937 | wire reg_din_5_scanin; | |
1938 | wire reg_din_5_scanout; | |
1939 | wire reg_din_4_scanin; | |
1940 | wire reg_din_4_scanout; | |
1941 | wire reg_din_3_scanin; | |
1942 | wire reg_din_3_scanout; | |
1943 | wire reg_din_2_scanin; | |
1944 | wire reg_din_2_scanout; | |
1945 | wire reg_din_1_scanin; | |
1946 | wire reg_din_1_scanout; | |
1947 | wire reg_din_0_scanin; | |
1948 | wire reg_din_0_scanout; | |
1949 | ||
1950 | ||
1951 | input vnw_ary; | |
1952 | input scan_in; | |
1953 | output scan_out; | |
1954 | ||
1955 | input arst_l; | |
1956 | input [`L2T_ARR_D_WIDTH - 1:0] din; | |
1957 | input [8:0] index; | |
1958 | input [`L2T_ARR_D_WIDTH - 1:1] lkup_tag; | |
1959 | input l2clk; | |
1960 | input pce_ov; | |
1961 | input pce_out; | |
1962 | input pce_din; | |
1963 | input pce_ctl; | |
1964 | input rd_en_a; | |
1965 | input [4:0] red_d_in; | |
1966 | input [1:0] red_en_in; | |
1967 | input red_wen; | |
1968 | input [3:0] rid_in; | |
1969 | input tcu_aclk; | |
1970 | input tcu_bclk; | |
1971 | input se_inff; | |
1972 | input se_outff; | |
1973 | input scan_en; | |
1974 | input [3:0] way; | |
1975 | input wr_en_a; | |
1976 | input wr_inhibit_a; | |
1977 | ||
1978 | output [4:0] req_d_quad; | |
1979 | output [1:0] req_en_quad; | |
1980 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way0; | |
1981 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way1; | |
1982 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way2; | |
1983 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way3; | |
1984 | output [3:0] way_hit; | |
1985 | ||
1986 | ///////////////////////////////////////// | |
1987 | // Clock Header // | |
1988 | ///////////////////////////////////////// | |
1989 | ||
1990 | // Clk. header for data input flops | |
1991 | //cl_sc1_l1hdr_48x clk_hdr_din ( | |
1992 | // .l2clk (l2clk), | |
1993 | // .pce (pce_din), | |
1994 | // .pce_ov (pce_ov), | |
1995 | // .stop (1'b0), | |
1996 | // .l1clk (l1clk_din), | |
1997 | // .se (se_inff) | |
1998 | // ); | |
1999 | ||
2000 | n2_l2t_sp_28kb_cust_l1clkhdr_ctl_macro clk_hdr_din0 ( | |
2001 | .l2clk (l2clk), | |
2002 | .l1en (pce_din), | |
2003 | .pce_ov (pce_ov), | |
2004 | .stop (1'b0), | |
2005 | .l1clk (l1clk_din0), | |
2006 | .se (se_inff) | |
2007 | ); | |
2008 | ||
2009 | n2_l2t_sp_28kb_cust_l1clkhdr_ctl_macro clk_hdr_din1 ( | |
2010 | .l2clk (l2clk), | |
2011 | .l1en (pce_din), | |
2012 | .pce_ov (pce_ov), | |
2013 | .stop (1'b0), | |
2014 | .l1clk (l1clk_din1), | |
2015 | .se (se_inff) | |
2016 | ); | |
2017 | ||
2018 | ||
2019 | ||
2020 | // Clk. header for control input flops | |
2021 | //cl_sc1_l1hdr_32x clk_hdr_ctl ( | |
2022 | // .l2clk (l2clk), | |
2023 | // .pce (pce_ctl), | |
2024 | // .pce_ov (pce_ov), | |
2025 | // .stop (1'b0), | |
2026 | // .l1clk (l1clk_in), | |
2027 | // .se (se_inff) | |
2028 | // ); | |
2029 | ||
2030 | n2_l2t_sp_28kb_cust_l1clkhdr_ctl_macro clk_hdr_ctl ( | |
2031 | .l2clk (l2clk), | |
2032 | .l1en (pce_ctl), | |
2033 | .pce_ov (pce_ov), | |
2034 | .stop (1'b0), | |
2035 | .l1clk (l1clk_in), | |
2036 | .se (se_inff) | |
2037 | ); | |
2038 | ||
2039 | assign se_unused = se_inff; | |
2040 | assign siclk = tcu_aclk; | |
2041 | assign soclk = tcu_bclk; | |
2042 | assign clk_stop = 1'b0; | |
2043 | ||
2044 | ||
2045 | //--------------------------------------- | |
2046 | // output signals | |
2047 | //--------------------------------------- | |
2048 | // reg_d1/reg_en0 are from top quad. reg_d0/reg_en0 are from bottom quad. | |
2049 | ||
2050 | //assign req_d_quad[4:0] = (reg_d1[4:0] | reg_d0[4:0]); | |
2051 | //assign req_en_quad[1:0] = (reg_en1[1:0] | reg_en0[1:0]); | |
2052 | ||
2053 | //Change to structural coding CC | |
2054 | //assign req_d_quad[4] = (reg_d1[4] | reg_d0[4]); | |
2055 | //assign req_d_quad[3] = (reg_d1[3] | reg_d0[3]); | |
2056 | //assign req_d_quad[2] = (reg_d1[2] | reg_d0[2]); | |
2057 | //assign req_d_quad[1] = (reg_d1[1] | reg_d0[1]); | |
2058 | //assign req_d_quad[0] = (reg_d1[0] | reg_d0[0]); | |
2059 | ||
2060 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_5 or_req_d_quad | |
2061 | ( | |
2062 | .din0 (reg_d1[4:0]), | |
2063 | .din1 (reg_d0[4:0]), | |
2064 | .dout (req_d_quad[4:0]) | |
2065 | ); | |
2066 | ||
2067 | //assign req_en_quad[1] = (reg_en1[1] | reg_en0[1]); | |
2068 | //assign req_en_quad[0] = (reg_en1[0] | reg_en0[0]); | |
2069 | ||
2070 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_2 or_req_en_quad | |
2071 | ( | |
2072 | .din0 (reg_en1[1:0]), | |
2073 | .din1 (reg_en0[1:0]), | |
2074 | .dout (req_en_quad[1:0]) | |
2075 | ); | |
2076 | ||
2077 | assign tag_way0[`L2T_ARR_D_WIDTH - 1:0] = tag_way0_0[`L2T_ARR_D_WIDTH - 1:0]; | |
2078 | assign tag_way2[`L2T_ARR_D_WIDTH - 1:0] = tag_way1_0[`L2T_ARR_D_WIDTH - 1:0]; | |
2079 | assign tag_way1[`L2T_ARR_D_WIDTH - 1:0] = tag_way0_1[`L2T_ARR_D_WIDTH - 1:0]; | |
2080 | assign tag_way3[`L2T_ARR_D_WIDTH - 1:0] = tag_way1_1[`L2T_ARR_D_WIDTH - 1:0]; | |
2081 | ||
2082 | assign way_hit[3] = way_hit_a1[1]; | |
2083 | assign way_hit[2] = way_hit_a0[1]; | |
2084 | assign way_hit[1] = way_hit_a1[0]; | |
2085 | assign way_hit[0] = way_hit_a0[0]; | |
2086 | //--------------------------------------- | |
2087 | // internal signals | |
2088 | //--------------------------------------- | |
2089 | ||
2090 | assign index_a[8:0] = index[8:0]; | |
2091 | ||
2092 | assign way_a0[1:0] = {way[2], way[0]}; | |
2093 | assign way_a1[1:0] = {way[3], way[1]}; | |
2094 | ||
2095 | //assign reg_d_in[4:0] = {arst_l, arst_l, arst_l, arst_l, arst_l} & red_d_in[4:0]; | |
2096 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_5 and_reg_d_in | |
2097 | ( | |
2098 | .din0 ({arst_l,arst_l, arst_l, arst_l, arst_l}), | |
2099 | .din1 (red_d_in[4:0]), | |
2100 | .dout (reg_d_in[4:0]) | |
2101 | ); | |
2102 | ||
2103 | //assign reg_en_in[1:0] = {arst_l, arst_l} & red_en_in[1:0]; | |
2104 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_2 and_reg_en_in | |
2105 | ( | |
2106 | .din0 ({arst_l,arst_l}), | |
2107 | .din1 (red_en_in[1:0]), | |
2108 | .dout (reg_en_in[1:0]) | |
2109 | ); | |
2110 | ||
2111 | // rid_in<3:2> selects one of four quads, and rid_in<1:0> selects one of | |
2112 | // four arrays in a quad. | |
2113 | ||
2114 | //assign quad_active = ~(rid_in[3] && rid_in[2]) ; | |
2115 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_quad_active | |
2116 | ( | |
2117 | .din0 (rid_in[3]), | |
2118 | .din1 (rid_in[2]), | |
2119 | .dout (not_quad_active) | |
2120 | ); | |
2121 | ||
2122 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_quad_active | |
2123 | ( | |
2124 | .din(not_quad_active), | |
2125 | .dout(quad_active_unused) | |
2126 | ); | |
2127 | ||
2128 | // Bank0 (bottom bank) | |
2129 | //assign reg_wen_lft0 = quad_active && (rid_in[1:0] == 2'b00) ? red_wen : 1'b0 ; | |
2130 | //assign reg_wen_rgt0 = quad_active && (rid_in[1:0] == 2'b01) ? red_wen : 1'b0 ; | |
2131 | //assign rid_rgt0 = quad_active && (rid_in[1:0] == 2'b01) ? 1'b1 : 1'b0; | |
2132 | //assign rid_lft0 = quad_active && (rid_in[1:0] == 2'b00) ? 1'b1 : 1'b0; | |
2133 | // Bank1 (top bank) | |
2134 | //assign reg_wen_lft1 = quad_active && (rid_in[1:0] == 2'b10) ? red_wen : 1'b0 ; | |
2135 | //assign reg_wen_rgt1 = quad_active && (rid_in[1:0] == 2'b11) ? red_wen : 1'b0 ; | |
2136 | //assign rid_rgt1 = quad_active && (rid_in[1:0] == 2'b11) ? 1'b1 : 1'b0; | |
2137 | //assign rid_lft1 = quad_active && (rid_in[1:0] == 2'b10) ? 1'b1 : 1'b0; | |
2138 | ||
2139 | // rid_in<1:0> selects one of four arrays : | |
2140 | // rid_in<1:0> = 11 => top, right array | |
2141 | // rid_in<1:0> = 10 => top, left array | |
2142 | // rid_in<1:0> = 01 => bot, right array | |
2143 | // rid_in<1:0> = 00 => bot, left array | |
2144 | ||
2145 | // Change to structural CC | |
2146 | //assign rid_rgt1 = !quad_active && ( (rid_in[1]) && ( rid_in[0])); | |
2147 | //assign rid_lft1 = !quad_active && ( (rid_in[1]) && (!rid_in[0])); | |
2148 | //assign rid_rgt0 = !quad_active && (!(rid_in[1]) && ( rid_in[0])); | |
2149 | //assign rid_lft0 = !quad_active && (!(rid_in[1]) && (!rid_in[0])); | |
2150 | ||
2151 | ||
2152 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_arst_l | |
2153 | ( | |
2154 | .din (arst_l), | |
2155 | .dout (not_arst_l) | |
2156 | ); | |
2157 | ||
2158 | n2_l2t_sp_28kb_cust_inv_macro__width_2 inv_rid_in | |
2159 | ( | |
2160 | .din (rid_in[1:0]), | |
2161 | .dout (not_rid_in[1:0]) | |
2162 | ); | |
2163 | ||
2164 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rid_rgt1 | |
2165 | ( | |
2166 | .din0 (not_quad_active), | |
2167 | .din1 (rid_in[0]), | |
2168 | .din2 (rid_in[1]), | |
2169 | .dout (rid_rgt1) | |
2170 | ); | |
2171 | ||
2172 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rid_rgt0 | |
2173 | ( | |
2174 | .din0 (not_quad_active), | |
2175 | .din1 (rid_in[0]), | |
2176 | .din2 (not_rid_in[1]), | |
2177 | .dout (rid_rgt0) | |
2178 | ); | |
2179 | ||
2180 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rid_lft1 | |
2181 | ( | |
2182 | .din0 (not_quad_active), | |
2183 | .din1 (not_rid_in[0]), | |
2184 | .din2 (rid_in[1]), | |
2185 | .dout (rid_lft1) | |
2186 | ); | |
2187 | ||
2188 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rid_lft0 | |
2189 | ( | |
2190 | .din0 (not_quad_active), | |
2191 | .din1 (not_rid_in[0]), | |
2192 | .din2 (not_rid_in[1]), | |
2193 | .dout (rid_lft0) | |
2194 | ); | |
2195 | ||
2196 | //assign reg_wen_rgt1 = !arst_l || (rid_rgt1 && red_wen); | |
2197 | //assign reg_wen_lft1 = !arst_l || (rid_lft1 && red_wen); | |
2198 | //assign reg_wen_rgt0 = !arst_l || (rid_rgt0 && red_wen); | |
2199 | //assign reg_wen_lft0 = !arst_l || (rid_lft0 && red_wen); | |
2200 | ||
2201 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_reg_wen_rgt1 | |
2202 | ( | |
2203 | .din0 (rid_rgt1_wen), | |
2204 | .din1 (not_arst_l), | |
2205 | .dout (reg_wen_rgt1) | |
2206 | ); | |
2207 | ||
2208 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_reg_wen_rgt0 | |
2209 | ( | |
2210 | .din0 (rid_rgt0_wen), | |
2211 | .din1 (not_arst_l), | |
2212 | .dout (reg_wen_rgt0) | |
2213 | ); | |
2214 | ||
2215 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_reg_wen_lft1 | |
2216 | ( | |
2217 | .din0 (rid_lft1_wen), | |
2218 | .din1 (not_arst_l), | |
2219 | .dout (reg_wen_lft1) | |
2220 | ); | |
2221 | ||
2222 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_reg_wen_lft0 | |
2223 | ( | |
2224 | .din0 (rid_lft0_wen), | |
2225 | .din1 (not_arst_l), | |
2226 | .dout (reg_wen_lft0) | |
2227 | ); | |
2228 | ||
2229 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_rid_rgt1_wen | |
2230 | ( | |
2231 | .din0 (rid_rgt1), | |
2232 | .din1 (red_wen), | |
2233 | .dout (rid_rgt1_wen) | |
2234 | ); | |
2235 | ||
2236 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_rid_rgt0_wen | |
2237 | ( | |
2238 | .din0 (rid_rgt0), | |
2239 | .din1 (red_wen), | |
2240 | .dout (rid_rgt0_wen) | |
2241 | ); | |
2242 | ||
2243 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_rid_lft1_wen | |
2244 | ( | |
2245 | .din0 (rid_lft1), | |
2246 | .din1 (red_wen), | |
2247 | .dout (rid_lft1_wen) | |
2248 | ); | |
2249 | ||
2250 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_rid_lft0_wen | |
2251 | ( | |
2252 | .din0 (rid_lft0), | |
2253 | .din1 (red_wen), | |
2254 | .dout (rid_lft0_wen) | |
2255 | ); | |
2256 | ||
2257 | ||
2258 | //--------------------------------------- | |
2259 | // L2T BANKS INSTANTIATION | |
2260 | //--------------------------------------- | |
2261 | ||
2262 | n2_l2t_bank bank0( /*AUTOINST*/ | |
2263 | // Outputs | |
2264 | .scan_out (bank0_scanout), // Templated | |
2265 | .reg_d (reg_d0[4:0]), // Templated | |
2266 | .reg_en (reg_en0[1:0]), // Templated | |
2267 | .tag_way0 (tag_way0_0[`L2T_ARR_D_WIDTH - 1:0]), // Templated | |
2268 | .tag_way1 (tag_way1_0[`L2T_ARR_D_WIDTH - 1:0]), // Templated | |
2269 | .way_hit_a (way_hit_a0[1:0]), // Templated | |
2270 | // Inputs | |
2271 | .vnw_ary (vnw_ary), | |
2272 | .l1clk_in (l1clk_in), | |
2273 | .scan_in (bank0_scanin), // Templated | |
2274 | .clk_stop (clk_stop), | |
2275 | .se_outff (se_outff), | |
2276 | .scan_en (scan_en), | |
2277 | .din (din_r[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
2278 | .index_a (index_a[8:0]), | |
2279 | .l2clk (l2clk), | |
2280 | .lkuptag_d1 (lkup_tag[`L2T_ARR_D_WIDTH-1:1]), // Templated | |
2281 | .pce_out (pce_out), | |
2282 | .pce_ctl (pce_ctl), | |
2283 | .pce_ov (pce_ov), | |
2284 | .rd_en_a (rd_en_a), | |
2285 | .reg_d_in (reg_d_in[4:0]), | |
2286 | .reg_en_in (reg_en_in[1:0]), | |
2287 | .reg_wen_lft (reg_wen_lft0), // Templated | |
2288 | .reg_wen_rgt (reg_wen_rgt0), // Templated | |
2289 | .rid_lft (rid_lft0), // Templated | |
2290 | .rid_rgt (rid_rgt0), // Templated | |
2291 | .tcu_aclk (tcu_aclk), | |
2292 | .tcu_bclk (tcu_bclk), | |
2293 | .way_a (way_a0[1:0]), // Templated | |
2294 | .wr_en_a (wr_en_a), | |
2295 | .wr_inhibit_a (wr_inhibit_a)); | |
2296 | ||
2297 | n2_l2t_bank bank1( /*AUTOINST*/ | |
2298 | // Outputs | |
2299 | .scan_out (bank1_scanout), // Templated | |
2300 | .reg_d (reg_d1[4:0]), // Templated | |
2301 | .reg_en (reg_en1[1:0]), // Templated | |
2302 | .tag_way0 (tag_way0_1[`L2T_ARR_D_WIDTH - 1:0]), // Templated | |
2303 | .tag_way1 (tag_way1_1[`L2T_ARR_D_WIDTH - 1:0]), // Templated | |
2304 | .way_hit_a (way_hit_a1[1:0]), // Templated | |
2305 | // Inputs | |
2306 | .vnw_ary (vnw_ary), | |
2307 | .l1clk_in (l1clk_in), | |
2308 | .scan_in (bank1_scanin), // Templated | |
2309 | .clk_stop (clk_stop), | |
2310 | .se_outff (se_outff), | |
2311 | .scan_en (scan_en), | |
2312 | .din (din_r[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
2313 | .index_a (index_a[8:0]), | |
2314 | .l2clk (l2clk), | |
2315 | .lkuptag_d1 (lkup_tag[`L2T_ARR_D_WIDTH-1:1]), // Templated | |
2316 | .pce_out (pce_out), | |
2317 | .pce_ctl (pce_ctl), | |
2318 | .pce_ov (pce_ov), | |
2319 | .rd_en_a (rd_en_a), | |
2320 | .reg_d_in (reg_d_in[4:0]), | |
2321 | .reg_en_in (reg_en_in[1:0]), | |
2322 | .reg_wen_lft (reg_wen_lft1), // Templated | |
2323 | .reg_wen_rgt (reg_wen_rgt1), // Templated | |
2324 | .rid_lft (rid_lft1), // Templated | |
2325 | .rid_rgt (rid_rgt1), // Templated | |
2326 | .tcu_aclk (tcu_aclk), | |
2327 | .tcu_bclk (tcu_bclk), | |
2328 | .way_a (way_a1[1:0]), // Templated | |
2329 | .wr_en_a (wr_en_a), | |
2330 | .wr_inhibit_a (wr_inhibit_a)); | |
2331 | //************************************************************************ | |
2332 | // REGISTERS SECTION | |
2333 | //************************************************************************ | |
2334 | ||
2335 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_27 (.scan_in(reg_din_27_scanin), .scan_out(reg_din_27_scanout), | |
2336 | .dout(din_r[27]), .l1clk(l1clk_din0), .din(din[27]), | |
2337 | .siclk(siclk), | |
2338 | .soclk(soclk)); | |
2339 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_26 (.scan_in(reg_din_26_scanin), .scan_out(reg_din_26_scanout), | |
2340 | .dout(din_r[26]), .l1clk(l1clk_din0), .din(din[26]), | |
2341 | .siclk(siclk), | |
2342 | .soclk(soclk)); | |
2343 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_25 (.scan_in(reg_din_25_scanin), .scan_out(reg_din_25_scanout), | |
2344 | .dout(din_r[25]), .l1clk(l1clk_din0), .din(din[25]), | |
2345 | .siclk(siclk), | |
2346 | .soclk(soclk)); | |
2347 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_24 (.scan_in(reg_din_24_scanin), .scan_out(reg_din_24_scanout), | |
2348 | .dout(din_r[24]), .l1clk(l1clk_din0), .din(din[24]), | |
2349 | .siclk(siclk), | |
2350 | .soclk(soclk)); | |
2351 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_23 (.scan_in(reg_din_23_scanin), .scan_out(reg_din_23_scanout), | |
2352 | .dout(din_r[23]), .l1clk(l1clk_din0), .din(din[23]), | |
2353 | .siclk(siclk), | |
2354 | .soclk(soclk)); | |
2355 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_22 (.scan_in(reg_din_22_scanin), .scan_out(reg_din_22_scanout), | |
2356 | .dout(din_r[22]), .l1clk(l1clk_din0), .din(din[22]), | |
2357 | .siclk(siclk), | |
2358 | .soclk(soclk)); | |
2359 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_21 (.scan_in(reg_din_21_scanin), .scan_out(reg_din_21_scanout), | |
2360 | .dout(din_r[21]), .l1clk(l1clk_din0), .din(din[21]), | |
2361 | .siclk(siclk), | |
2362 | .soclk(soclk)); | |
2363 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_20 (.scan_in(reg_din_20_scanin), .scan_out(reg_din_20_scanout), | |
2364 | .dout(din_r[20]), .l1clk(l1clk_din0), .din(din[20]), | |
2365 | .siclk(siclk), | |
2366 | .soclk(soclk)); | |
2367 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_19 (.scan_in(reg_din_19_scanin), .scan_out(reg_din_19_scanout), | |
2368 | .dout(din_r[19]), .l1clk(l1clk_din0), .din(din[19]), | |
2369 | .siclk(siclk), | |
2370 | .soclk(soclk)); | |
2371 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_18 (.scan_in(reg_din_18_scanin), .scan_out(reg_din_18_scanout), | |
2372 | .dout(din_r[18]), .l1clk(l1clk_din0), .din(din[18]), | |
2373 | .siclk(siclk), | |
2374 | .soclk(soclk)); | |
2375 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_17 (.scan_in(reg_din_17_scanin), .scan_out(reg_din_17_scanout), | |
2376 | .dout(din_r[17]), .l1clk(l1clk_din0), .din(din[17]), | |
2377 | .siclk(siclk), | |
2378 | .soclk(soclk)); | |
2379 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_16 (.scan_in(reg_din_16_scanin), .scan_out(reg_din_16_scanout), | |
2380 | .dout(din_r[16]), .l1clk(l1clk_din0), .din(din[16]), | |
2381 | .siclk(siclk), | |
2382 | .soclk(soclk)); | |
2383 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_15 (.scan_in(reg_din_15_scanin), .scan_out(reg_din_15_scanout), | |
2384 | .dout(din_r[15]), .l1clk(l1clk_din0), .din(din[15]), | |
2385 | .siclk(siclk), | |
2386 | .soclk(soclk)); | |
2387 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_14 (.scan_in(reg_din_14_scanin), .scan_out(reg_din_14_scanout), | |
2388 | .dout(din_r[14]), .l1clk(l1clk_din0), .din(din[14]), | |
2389 | .siclk(siclk), | |
2390 | .soclk(soclk)); | |
2391 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_13 (.scan_in(reg_din_13_scanin), .scan_out(reg_din_13_scanout), | |
2392 | .dout(din_r[13]), .l1clk(l1clk_din0), .din(din[13]), | |
2393 | .siclk(siclk), | |
2394 | .soclk(soclk)); | |
2395 | ||
2396 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_12 (.scan_in(reg_din_12_scanin), .scan_out(reg_din_12_scanout), | |
2397 | .dout(din_r[12]), .l1clk(l1clk_din1), .din(din[12]), | |
2398 | .siclk(siclk), | |
2399 | .soclk(soclk)); | |
2400 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_11 (.scan_in(reg_din_11_scanin), .scan_out(reg_din_11_scanout), | |
2401 | .dout(din_r[11]), .l1clk(l1clk_din1), .din(din[11]), | |
2402 | .siclk(siclk), | |
2403 | .soclk(soclk)); | |
2404 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_10 (.scan_in(reg_din_10_scanin), .scan_out(reg_din_10_scanout), | |
2405 | .dout(din_r[10]), .l1clk(l1clk_din1), .din(din[10]), | |
2406 | .siclk(siclk), | |
2407 | .soclk(soclk)); | |
2408 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_9 (.scan_in(reg_din_9_scanin), .scan_out(reg_din_9_scanout), | |
2409 | .dout(din_r[9]), .l1clk(l1clk_din1), .din(din[9]), | |
2410 | .siclk(siclk), | |
2411 | .soclk(soclk)); | |
2412 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_8 (.scan_in(reg_din_8_scanin), .scan_out(reg_din_8_scanout), | |
2413 | .dout(din_r[8]), .l1clk(l1clk_din1), .din(din[8]), | |
2414 | .siclk(siclk), | |
2415 | .soclk(soclk)); | |
2416 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_7 (.scan_in(reg_din_7_scanin), .scan_out(reg_din_7_scanout), | |
2417 | .dout(din_r[7]), .l1clk(l1clk_din1), .din(din[7]), | |
2418 | .siclk(siclk), | |
2419 | .soclk(soclk)); | |
2420 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_6 (.scan_in(reg_din_6_scanin), .scan_out(reg_din_6_scanout), | |
2421 | .dout(din_r[6]), .l1clk(l1clk_din1), .din(din[6]), | |
2422 | .siclk(siclk), | |
2423 | .soclk(soclk)); | |
2424 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_5 (.scan_in(reg_din_5_scanin), .scan_out(reg_din_5_scanout), | |
2425 | .dout(din_r[5]), .l1clk(l1clk_din1), .din(din[5]), | |
2426 | .siclk(siclk), | |
2427 | .soclk(soclk)); | |
2428 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_4 (.scan_in(reg_din_4_scanin), .scan_out(reg_din_4_scanout), | |
2429 | .dout(din_r[4]), .l1clk(l1clk_din1), .din(din[4]), | |
2430 | .siclk(siclk), | |
2431 | .soclk(soclk)); | |
2432 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_3 (.scan_in(reg_din_3_scanin), .scan_out(reg_din_3_scanout), | |
2433 | .dout(din_r[3]), .l1clk(l1clk_din1), .din(din[3]), | |
2434 | .siclk(siclk), | |
2435 | .soclk(soclk)); | |
2436 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_2 (.scan_in(reg_din_2_scanin), .scan_out(reg_din_2_scanout), | |
2437 | .dout(din_r[2]), .l1clk(l1clk_din1), .din(din[2]), | |
2438 | .siclk(siclk), | |
2439 | .soclk(soclk)); | |
2440 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_1 (.scan_in(reg_din_1_scanin), .scan_out(reg_din_1_scanout), | |
2441 | .dout(din_r[1]), .l1clk(l1clk_din1), .din(din[1]), | |
2442 | .siclk(siclk), | |
2443 | .soclk(soclk)); | |
2444 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_din_0 (.scan_in(reg_din_0_scanin), .scan_out(reg_din_0_scanout), | |
2445 | .dout(din_r[0]), .l1clk(l1clk_din1), .din(din[0]), | |
2446 | .siclk(siclk), | |
2447 | .soclk(soclk)); | |
2448 | ||
2449 | // =============== VERILOG-MODE AUTO TEMPLATES | |
2450 | ||
2451 | /* | |
2452 | ||
2453 | n2_l2t_bank AUTO_TEMPLATE ( | |
2454 | .din(din_r[`L2T_ARR_D_WIDTH - 1 : 0]), | |
2455 | .reg_wen_lft (reg_wen_lft@), | |
2456 | .reg_wen_rgt (reg_wen_rgt@), | |
2457 | .rid_lft (rid_lft@), | |
2458 | .rid_rgt (rid_rgt@), | |
2459 | .way_a (way_a@[1:0]), | |
2460 | .tcu_pce_ov(pce_ov), | |
2461 | .lkuptag_d1(lkup_tag[`L2T_ARR_D_WIDTH-1:1]), | |
2462 | .reg_d(reg_d@[4:0]), | |
2463 | .reg_en(reg_en@[1:0]), | |
2464 | .tag_way0(tag_way0_@[`L2T_ARR_D_WIDTH - 1:0]), | |
2465 | .tag_way1(tag_way1_@[`L2T_ARR_D_WIDTH - 1:0]), | |
2466 | .way_hit_a (way_hit_a@[1:0]), | |
2467 | .scan_out (bank@_scanout), | |
2468 | .scan_in (bank@_scanin), | |
2469 | ); | |
2470 | ||
2471 | */ | |
2472 | ||
2473 | // Manual scan section | |
2474 | assign bank1_scanin = scan_in ; | |
2475 | ||
2476 | assign reg_din_0_scanin = bank1_scanout ; | |
2477 | assign reg_din_1_scanin = reg_din_0_scanout ; | |
2478 | assign reg_din_2_scanin = reg_din_1_scanout ; | |
2479 | assign reg_din_3_scanin = reg_din_2_scanout ; | |
2480 | assign reg_din_4_scanin = reg_din_3_scanout ; | |
2481 | assign reg_din_5_scanin = reg_din_4_scanout ; | |
2482 | assign reg_din_6_scanin = reg_din_5_scanout ; | |
2483 | assign reg_din_7_scanin = reg_din_6_scanout ; | |
2484 | assign reg_din_8_scanin = reg_din_7_scanout ; | |
2485 | assign reg_din_9_scanin = reg_din_8_scanout ; | |
2486 | assign reg_din_10_scanin = reg_din_9_scanout ; | |
2487 | assign reg_din_11_scanin = reg_din_10_scanout ; | |
2488 | assign reg_din_12_scanin = reg_din_11_scanout ; | |
2489 | assign reg_din_13_scanin = reg_din_12_scanout ; | |
2490 | assign reg_din_14_scanin = reg_din_13_scanout ; | |
2491 | assign reg_din_15_scanin = reg_din_14_scanout ; | |
2492 | assign reg_din_16_scanin = reg_din_15_scanout ; | |
2493 | assign reg_din_17_scanin = reg_din_16_scanout ; | |
2494 | assign reg_din_18_scanin = reg_din_17_scanout ; | |
2495 | assign reg_din_19_scanin = reg_din_18_scanout ; | |
2496 | assign reg_din_20_scanin = reg_din_19_scanout ; | |
2497 | assign reg_din_21_scanin = reg_din_20_scanout ; | |
2498 | assign reg_din_22_scanin = reg_din_21_scanout ; | |
2499 | assign reg_din_23_scanin = reg_din_22_scanout ; | |
2500 | assign reg_din_24_scanin = reg_din_23_scanout ; | |
2501 | assign reg_din_25_scanin = reg_din_24_scanout ; | |
2502 | assign reg_din_26_scanin = reg_din_25_scanout ; | |
2503 | assign reg_din_27_scanin = reg_din_26_scanout ; | |
2504 | assign bank0_scanin = reg_din_27_scanout ; | |
2505 | assign scan_out = bank0_scanout ; | |
2506 | endmodule | |
2507 | ||
2508 | ||
2509 | // | |
2510 | // or macro for ports = 2,3 | |
2511 | // | |
2512 | // | |
2513 | ||
2514 | ||
2515 | ||
2516 | ||
2517 | ||
2518 | module n2_l2t_sp_28kb_cust_or_macro__ports_2__width_2 ( | |
2519 | din0, | |
2520 | din1, | |
2521 | dout); | |
2522 | input [1:0] din0; | |
2523 | input [1:0] din1; | |
2524 | output [1:0] dout; | |
2525 | ||
2526 | ||
2527 | ||
2528 | ||
2529 | ||
2530 | ||
2531 | or2 #(2) d0_0 ( | |
2532 | .in0(din0[1:0]), | |
2533 | .in1(din1[1:0]), | |
2534 | .out(dout[1:0]) | |
2535 | ); | |
2536 | ||
2537 | ||
2538 | ||
2539 | ||
2540 | ||
2541 | ||
2542 | ||
2543 | ||
2544 | ||
2545 | endmodule | |
2546 | ||
2547 | ||
2548 | ||
2549 | ||
2550 | ||
2551 | // | |
2552 | // and macro for ports = 2,3,4 | |
2553 | // | |
2554 | // | |
2555 | ||
2556 | ||
2557 | ||
2558 | ||
2559 | ||
2560 | module n2_l2t_sp_28kb_cust_and_macro__ports_2__width_5 ( | |
2561 | din0, | |
2562 | din1, | |
2563 | dout); | |
2564 | input [4:0] din0; | |
2565 | input [4:0] din1; | |
2566 | output [4:0] dout; | |
2567 | ||
2568 | ||
2569 | ||
2570 | ||
2571 | ||
2572 | ||
2573 | and2 #(5) d0_0 ( | |
2574 | .in0(din0[4:0]), | |
2575 | .in1(din1[4:0]), | |
2576 | .out(dout[4:0]) | |
2577 | ); | |
2578 | ||
2579 | ||
2580 | ||
2581 | ||
2582 | ||
2583 | ||
2584 | ||
2585 | ||
2586 | ||
2587 | endmodule | |
2588 | ||
2589 | ||
2590 | ||
2591 | ||
2592 | ||
2593 | // | |
2594 | // and macro for ports = 2,3,4 | |
2595 | // | |
2596 | // | |
2597 | ||
2598 | ||
2599 | ||
2600 | ||
2601 | ||
2602 | module n2_l2t_sp_28kb_cust_and_macro__ports_2__width_2 ( | |
2603 | din0, | |
2604 | din1, | |
2605 | dout); | |
2606 | input [1:0] din0; | |
2607 | input [1:0] din1; | |
2608 | output [1:0] dout; | |
2609 | ||
2610 | ||
2611 | ||
2612 | ||
2613 | ||
2614 | ||
2615 | and2 #(2) d0_0 ( | |
2616 | .in0(din0[1:0]), | |
2617 | .in1(din1[1:0]), | |
2618 | .out(dout[1:0]) | |
2619 | ); | |
2620 | ||
2621 | ||
2622 | ||
2623 | ||
2624 | ||
2625 | ||
2626 | ||
2627 | ||
2628 | ||
2629 | endmodule | |
2630 | ||
2631 | ||
2632 | ||
2633 | ||
2634 | ||
2635 | // | |
2636 | // invert macro | |
2637 | // | |
2638 | // | |
2639 | ||
2640 | ||
2641 | ||
2642 | ||
2643 | ||
2644 | module n2_l2t_sp_28kb_cust_inv_macro__width_2 ( | |
2645 | din, | |
2646 | dout); | |
2647 | input [1:0] din; | |
2648 | output [1:0] dout; | |
2649 | ||
2650 | ||
2651 | ||
2652 | ||
2653 | ||
2654 | ||
2655 | inv #(2) d0_0 ( | |
2656 | .in(din[1:0]), | |
2657 | .out(dout[1:0]) | |
2658 | ); | |
2659 | ||
2660 | ||
2661 | ||
2662 | ||
2663 | ||
2664 | ||
2665 | ||
2666 | ||
2667 | ||
2668 | endmodule | |
2669 | ||
2670 | ||
2671 | ||
2672 | ||
2673 | ||
2674 | ||
2675 | `define L2T_ARR_D_WIDTH 28 | |
2676 | `define L2T_ARR_DEPTH 512 | |
2677 | `define WAY_HIT_WIDTH 16 | |
2678 | `define BADREAD BADBADD | |
2679 | ||
2680 | ||
2681 | ||
2682 | module n2_l2t_bank ( | |
2683 | l1clk_in, | |
2684 | scan_in, | |
2685 | clk_stop, | |
2686 | se_outff, | |
2687 | scan_en, | |
2688 | vnw_ary, | |
2689 | scan_out, | |
2690 | din, | |
2691 | index_a, | |
2692 | l2clk, | |
2693 | lkuptag_d1, | |
2694 | pce_out, | |
2695 | pce_ctl, | |
2696 | pce_ov, | |
2697 | rd_en_a, | |
2698 | reg_d_in, | |
2699 | reg_en_in, | |
2700 | reg_wen_lft, | |
2701 | reg_wen_rgt, | |
2702 | rid_lft, | |
2703 | rid_rgt, | |
2704 | tcu_aclk, | |
2705 | tcu_bclk, | |
2706 | way_a, | |
2707 | wr_en_a, | |
2708 | wr_inhibit_a, | |
2709 | reg_d, | |
2710 | reg_en, | |
2711 | tag_way0, | |
2712 | tag_way1, | |
2713 | way_hit_a); | |
2714 | wire l1clk_int_v1; | |
2715 | wire l1clk_int_v2; | |
2716 | wire l1clk_out0; | |
2717 | wire l1clk_out1; | |
2718 | wire se_unused; | |
2719 | wire siclk; | |
2720 | wire soclk; | |
2721 | wire w1_cmp27to19; | |
2722 | wire w1_cmp27to25; | |
2723 | wire w1_cmp24to22; | |
2724 | wire w1_cmp21to19; | |
2725 | wire w0_cmp27to19; | |
2726 | wire w0_cmp27to25; | |
2727 | wire w0_cmp24to22; | |
2728 | wire w0_cmp21to19; | |
2729 | wire w1_cmp18to10; | |
2730 | wire w1_cmp18to16; | |
2731 | wire w1_cmp15to13; | |
2732 | wire w1_cmp12to10; | |
2733 | wire w0_cmp18to10; | |
2734 | wire w0_cmp18to16; | |
2735 | wire w0_cmp15to13; | |
2736 | wire w0_cmp12to10; | |
2737 | wire w1_cmp9to1; | |
2738 | wire w1_cmp9to7; | |
2739 | wire w1_cmp6to4; | |
2740 | wire w1_cmp3to1; | |
2741 | wire w0_cmp9to1; | |
2742 | wire w0_cmp9to7; | |
2743 | wire w0_cmp6to4; | |
2744 | wire w0_cmp3to1; | |
2745 | wire w1_cmp27to1; | |
2746 | wire rd_en_d1_a; | |
2747 | wire w0_cmp27to1; | |
2748 | wire [4:0] reg_d_lft; | |
2749 | wire [4:0] reg_d_rgt; | |
2750 | wire rid_lft_b; | |
2751 | wire rid_rgt_b; | |
2752 | wire [1:0] reg_en_lft; | |
2753 | wire [1:0] reg_en_rgt; | |
2754 | wire ln1clk; | |
2755 | wire ln2clk; | |
2756 | wire wr_inhibit_a_l; | |
2757 | wire not_reg_wen_lft; | |
2758 | wire wen_clk_lft; | |
2759 | wire not_reg_wen_rgt; | |
2760 | wire wen_clk_rgt; | |
2761 | wire en_lft; | |
2762 | wire en_rgt; | |
2763 | wire [4:0] not_reg_d_lft; | |
2764 | wire [1:0] rpda_lft; | |
2765 | wire [3:0] rpdb_lft; | |
2766 | wire [3:0] rpdc_lft; | |
2767 | wire [4:0] not_reg_d_rgt; | |
2768 | wire [1:0] rpda_rgt; | |
2769 | wire [3:0] rpdb_rgt; | |
2770 | wire [3:0] rpdc_rgt; | |
2771 | wire [27:0] sao_mx0_h; | |
2772 | wire [27:0] sao_mx0_l; | |
2773 | wire [27:0] sao_mx1_h; | |
2774 | wire [27:0] sao_mx1_l; | |
2775 | wire [8:0] addr_b; | |
2776 | wire rd_en_b; | |
2777 | wire wr_en_b; | |
2778 | wire wr_en_d1_a; | |
2779 | wire [1:0] wr_way_b; | |
2780 | wire [1:0] wr_way_b_l; | |
2781 | wire [27:0] sao_mx1; | |
2782 | wire [27:0] sao_mx0; | |
2783 | wire reg_addr_b_8_scanin; | |
2784 | wire reg_addr_b_8_scanout; | |
2785 | wire reg_addr_b_8_unused; | |
2786 | wire reg_addr_b_7_scanin; | |
2787 | wire reg_addr_b_7_scanout; | |
2788 | wire reg_addr_b_7_unused; | |
2789 | wire reg_addr_b_6_scanin; | |
2790 | wire reg_addr_b_6_scanout; | |
2791 | wire reg_addr_b_6_unused; | |
2792 | wire reg_addr_b_5_scanin; | |
2793 | wire reg_addr_b_5_scanout; | |
2794 | wire reg_addr_b_5_unused; | |
2795 | wire reg_addr_b_4_scanin; | |
2796 | wire reg_addr_b_4_scanout; | |
2797 | wire reg_addr_b_4_unused; | |
2798 | wire reg_addr_b_3_scanin; | |
2799 | wire reg_addr_b_3_scanout; | |
2800 | wire reg_addr_b_3_unused; | |
2801 | wire reg_addr_b_2_scanin; | |
2802 | wire reg_addr_b_2_scanout; | |
2803 | wire reg_addr_b_2_unused; | |
2804 | wire reg_addr_b_1_scanin; | |
2805 | wire reg_addr_b_1_scanout; | |
2806 | wire reg_addr_b_1_unused; | |
2807 | wire reg_addr_b_0_scanin; | |
2808 | wire reg_addr_b_0_scanout; | |
2809 | wire reg_addr_b_0_unused; | |
2810 | wire reg_wr_way_b_scanin; | |
2811 | wire reg_wr_way_b_scanout; | |
2812 | wire reg_wr_en_b_scanin; | |
2813 | wire reg_wr_en_b_scanout; | |
2814 | wire reg_wr_en_b_unused; | |
2815 | wire reg_rd_en_b_scanin; | |
2816 | wire reg_rd_en_b_scanout; | |
2817 | wire reg_rd_en_b_unused; | |
2818 | wire reg_wr_en_a_scanin; | |
2819 | wire reg_wr_en_a_scanout; | |
2820 | wire reg_rd_en_a_scanin; | |
2821 | wire reg_rd_en_a_scanout; | |
2822 | wire reg_tag_way1_27_scanin; | |
2823 | wire reg_tag_way1_27_scanout; | |
2824 | wire reg_tag_way0_27_scanin; | |
2825 | wire reg_tag_way0_27_scanout; | |
2826 | wire reg_tag_way1_26_scanin; | |
2827 | wire reg_tag_way1_26_scanout; | |
2828 | wire reg_tag_way0_26_scanin; | |
2829 | wire reg_tag_way0_26_scanout; | |
2830 | wire reg_tag_way1_25_scanin; | |
2831 | wire reg_tag_way1_25_scanout; | |
2832 | wire reg_tag_way0_25_scanin; | |
2833 | wire reg_tag_way0_25_scanout; | |
2834 | wire reg_tag_way1_24_scanin; | |
2835 | wire reg_tag_way1_24_scanout; | |
2836 | wire reg_tag_way0_24_scanin; | |
2837 | wire reg_tag_way0_24_scanout; | |
2838 | wire reg_tag_way1_23_scanin; | |
2839 | wire reg_tag_way1_23_scanout; | |
2840 | wire reg_tag_way0_23_scanin; | |
2841 | wire reg_tag_way0_23_scanout; | |
2842 | wire reg_tag_way1_22_scanin; | |
2843 | wire reg_tag_way1_22_scanout; | |
2844 | wire reg_tag_way0_22_scanin; | |
2845 | wire reg_tag_way0_22_scanout; | |
2846 | wire reg_tag_way1_21_scanin; | |
2847 | wire reg_tag_way1_21_scanout; | |
2848 | wire reg_tag_way0_21_scanin; | |
2849 | wire reg_tag_way0_21_scanout; | |
2850 | wire reg_tag_way1_20_scanin; | |
2851 | wire reg_tag_way1_20_scanout; | |
2852 | wire reg_tag_way0_20_scanin; | |
2853 | wire reg_tag_way0_20_scanout; | |
2854 | wire reg_tag_way1_19_scanin; | |
2855 | wire reg_tag_way1_19_scanout; | |
2856 | wire reg_tag_way0_19_scanin; | |
2857 | wire reg_tag_way0_19_scanout; | |
2858 | wire reg_tag_way1_18_scanin; | |
2859 | wire reg_tag_way1_18_scanout; | |
2860 | wire reg_tag_way0_18_scanin; | |
2861 | wire reg_tag_way0_18_scanout; | |
2862 | wire reg_tag_way1_17_scanin; | |
2863 | wire reg_tag_way1_17_scanout; | |
2864 | wire reg_tag_way0_17_scanin; | |
2865 | wire reg_tag_way0_17_scanout; | |
2866 | wire reg_tag_way1_16_scanin; | |
2867 | wire reg_tag_way1_16_scanout; | |
2868 | wire reg_tag_way0_16_scanin; | |
2869 | wire reg_tag_way0_16_scanout; | |
2870 | wire reg_tag_way1_15_scanin; | |
2871 | wire reg_tag_way1_15_scanout; | |
2872 | wire reg_tag_way0_15_scanin; | |
2873 | wire reg_tag_way0_15_scanout; | |
2874 | wire reg_tag_way1_14_scanin; | |
2875 | wire reg_tag_way1_14_scanout; | |
2876 | wire reg_tag_way0_14_scanin; | |
2877 | wire reg_tag_way0_14_scanout; | |
2878 | wire reg_tag_way1_13_scanin; | |
2879 | wire reg_tag_way1_13_scanout; | |
2880 | wire reg_tag_way0_13_scanin; | |
2881 | wire reg_tag_way0_13_scanout; | |
2882 | wire reg_tag_way1_12_scanin; | |
2883 | wire reg_tag_way1_12_scanout; | |
2884 | wire reg_tag_way0_12_scanin; | |
2885 | wire reg_tag_way0_12_scanout; | |
2886 | wire reg_tag_way1_11_scanin; | |
2887 | wire reg_tag_way1_11_scanout; | |
2888 | wire reg_tag_way0_11_scanin; | |
2889 | wire reg_tag_way0_11_scanout; | |
2890 | wire reg_tag_way1_10_scanin; | |
2891 | wire reg_tag_way1_10_scanout; | |
2892 | wire reg_tag_way0_10_scanin; | |
2893 | wire reg_tag_way0_10_scanout; | |
2894 | wire reg_tag_way1_9_scanin; | |
2895 | wire reg_tag_way1_9_scanout; | |
2896 | wire reg_tag_way0_9_scanin; | |
2897 | wire reg_tag_way0_9_scanout; | |
2898 | wire reg_tag_way1_8_scanin; | |
2899 | wire reg_tag_way1_8_scanout; | |
2900 | wire reg_tag_way0_8_scanin; | |
2901 | wire reg_tag_way0_8_scanout; | |
2902 | wire reg_tag_way1_7_scanin; | |
2903 | wire reg_tag_way1_7_scanout; | |
2904 | wire reg_tag_way0_7_scanin; | |
2905 | wire reg_tag_way0_7_scanout; | |
2906 | wire reg_tag_way1_6_scanin; | |
2907 | wire reg_tag_way1_6_scanout; | |
2908 | wire reg_tag_way0_6_scanin; | |
2909 | wire reg_tag_way0_6_scanout; | |
2910 | wire reg_tag_way1_5_scanin; | |
2911 | wire reg_tag_way1_5_scanout; | |
2912 | wire reg_tag_way0_5_scanin; | |
2913 | wire reg_tag_way0_5_scanout; | |
2914 | wire reg_tag_way1_4_scanin; | |
2915 | wire reg_tag_way1_4_scanout; | |
2916 | wire reg_tag_way0_4_scanin; | |
2917 | wire reg_tag_way0_4_scanout; | |
2918 | wire reg_tag_way1_3_scanin; | |
2919 | wire reg_tag_way1_3_scanout; | |
2920 | wire reg_tag_way0_3_scanin; | |
2921 | wire reg_tag_way0_3_scanout; | |
2922 | wire reg_tag_way1_2_scanin; | |
2923 | wire reg_tag_way1_2_scanout; | |
2924 | wire reg_tag_way0_2_scanin; | |
2925 | wire reg_tag_way0_2_scanout; | |
2926 | wire reg_tag_way1_1_scanin; | |
2927 | wire reg_tag_way1_1_scanout; | |
2928 | wire reg_tag_way0_1_scanin; | |
2929 | wire reg_tag_way0_1_scanout; | |
2930 | wire reg_tag_way1_0_scanin; | |
2931 | wire reg_tag_way1_0_scanout; | |
2932 | wire reg_tag_way0_0_scanin; | |
2933 | wire reg_tag_way0_0_scanout; | |
2934 | wire reg_way_hit_a0_scanin; | |
2935 | wire reg_way_hit_a0_scanout; | |
2936 | wire reg_way_hit_a1_scanin; | |
2937 | wire reg_way_hit_a1_scanout; | |
2938 | ||
2939 | ||
2940 | // input l2clk; // cmp clock | |
2941 | input l1clk_in; // io clock | |
2942 | input scan_in; | |
2943 | input clk_stop; | |
2944 | input se_outff; | |
2945 | input scan_en; | |
2946 | input vnw_ary; | |
2947 | ||
2948 | // input tcu_aclk; | |
2949 | // input tcu_bclk; | |
2950 | // input tcu_scan_en; | |
2951 | // input tcu_muxtest; | |
2952 | // input tcu_dectest; | |
2953 | output scan_out; | |
2954 | ||
2955 | input [`L2T_ARR_D_WIDTH - 1:0] din; | |
2956 | input [8:0] index_a; | |
2957 | input l2clk; | |
2958 | input [`L2T_ARR_D_WIDTH - 1:1] lkuptag_d1; | |
2959 | input pce_out; | |
2960 | input pce_ctl; | |
2961 | input pce_ov; | |
2962 | input rd_en_a; | |
2963 | input [4:0] reg_d_in; | |
2964 | input [1:0] reg_en_in; | |
2965 | input reg_wen_lft; | |
2966 | input reg_wen_rgt; | |
2967 | input rid_lft; | |
2968 | input rid_rgt; | |
2969 | input tcu_aclk; | |
2970 | input tcu_bclk; | |
2971 | input [1:0] way_a; | |
2972 | input wr_en_a; | |
2973 | input wr_inhibit_a; | |
2974 | ||
2975 | output [4:0] reg_d; | |
2976 | output [1:0] reg_en; | |
2977 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way0; | |
2978 | output [`L2T_ARR_D_WIDTH - 1:0] tag_way1; | |
2979 | output [1:0] way_hit_a; | |
2980 | ||
2981 | ||
2982 | ||
2983 | ///////////////////////////////////////// | |
2984 | // Clock Header // | |
2985 | ///////////////////////////////////////// | |
2986 | ||
2987 | //INTERNAL HEADER | |
2988 | // | |
2989 | n2_l2t_sp_28kb_cust_l1clkhdr_ctl_macro clk_hdr_int_v1 ( | |
2990 | .l2clk (l2clk), | |
2991 | .l1en (pce_ctl), | |
2992 | .pce_ov (pce_ov), | |
2993 | .stop (clk_stop), | |
2994 | .se (scan_en), | |
2995 | .l1clk (l1clk_int_v1)); | |
2996 | ||
2997 | n2_l2t_sp_28kb_cust_l1clkhdr_ctl_macro clk_hdr_int_v2 ( | |
2998 | .l2clk (l2clk), | |
2999 | .l1en (pce_ctl), | |
3000 | .pce_ov (pce_ov), | |
3001 | .stop (clk_stop), | |
3002 | .se (scan_en), | |
3003 | .l1clk (l1clk_int_v2)); | |
3004 | ||
3005 | ||
3006 | //OUTPUT HEADER | |
3007 | // | |
3008 | n2_l2t_sp_28kb_cust_l1clkhdr_ctl_macro clk_hdr_out0 ( | |
3009 | .l2clk (l2clk), | |
3010 | .l1en (pce_out), | |
3011 | .pce_ov (pce_ov), | |
3012 | .stop (clk_stop), | |
3013 | .se (se_outff), | |
3014 | .l1clk (l1clk_out0)); | |
3015 | ||
3016 | n2_l2t_sp_28kb_cust_l1clkhdr_ctl_macro clk_hdr_out1 ( | |
3017 | .l2clk (l2clk), | |
3018 | .l1en (pce_out), | |
3019 | .pce_ov (pce_ov), | |
3020 | .stop (clk_stop), | |
3021 | .se (se_outff), | |
3022 | .l1clk (l1clk_out1)); | |
3023 | ||
3024 | assign se_unused = se_outff; | |
3025 | assign siclk = tcu_aclk; | |
3026 | assign soclk = tcu_bclk; | |
3027 | ||
3028 | //--------------------------------------- | |
3029 | // output signals | |
3030 | //--------------------------------------- | |
3031 | ||
3032 | // Behaviourial coding for compare: | |
3033 | //assign way_hit_a_l[1] = (lkuptag_d1[`L2T_ARR_D_WIDTH - 1 :1] == sao_mx1_h[`L2T_ARR_D_WIDTH - 1 :1] ) ? | |
3034 | // 1'b0 : 1'b1; | |
3035 | //assign way_hit_a_l[0] = (lkuptag_d1[`L2T_ARR_D_WIDTH - 1 :1] == sao_mx0_h[`L2T_ARR_D_WIDTH - 1 :1] ) ? | |
3036 | // 1'b0 : 1'b1; | |
3037 | ||
3038 | // Structural coding for 27bit compare (for two ways): | |
3039 | n2_l2t_sp_28kb_cust_nor_macro__ports_3__width_1 w1_nor_cmp27to19 ( | |
3040 | .dout (w1_cmp27to19), | |
3041 | .din0 (w1_cmp27to25), | |
3042 | .din1 (w1_cmp24to22), | |
3043 | .din2 (w1_cmp21to19)); | |
3044 | ||
3045 | n2_l2t_sp_28kb_cust_nor_macro__ports_3__width_1 w0_nor_cmp27to19 | |
3046 | ( | |
3047 | .dout (w0_cmp27to19), | |
3048 | .din0 (w0_cmp27to25), | |
3049 | .din1 (w0_cmp24to22), | |
3050 | .din2 (w0_cmp21to19)); | |
3051 | ||
3052 | n2_l2t_sp_28kb_cust_nor_macro__ports_3__width_1 w1_nor_cmp18to10 | |
3053 | ( | |
3054 | .dout (w1_cmp18to10), | |
3055 | .din0 (w1_cmp18to16), | |
3056 | .din1 (w1_cmp15to13), | |
3057 | .din2 (w1_cmp12to10)); | |
3058 | ||
3059 | n2_l2t_sp_28kb_cust_nor_macro__ports_3__width_1 w0_nor_cmp18to10 | |
3060 | ( | |
3061 | .dout (w0_cmp18to10), | |
3062 | .din0 (w0_cmp18to16), | |
3063 | .din1 (w0_cmp15to13), | |
3064 | .din2 (w0_cmp12to10)); | |
3065 | ||
3066 | ||
3067 | n2_l2t_sp_28kb_cust_nor_macro__ports_3__width_1 w1_nor_cmp9to1 | |
3068 | ( | |
3069 | .dout (w1_cmp9to1), | |
3070 | .din0 (w1_cmp9to7), | |
3071 | .din1 (w1_cmp6to4), | |
3072 | .din2 (w1_cmp3to1)); | |
3073 | ||
3074 | ||
3075 | n2_l2t_sp_28kb_cust_nor_macro__ports_3__width_1 w0_nor_cmp9to1 | |
3076 | ( | |
3077 | .dout (w0_cmp9to1), | |
3078 | .din0 (w0_cmp9to7), | |
3079 | .din1 (w0_cmp6to4), | |
3080 | .din2 (w0_cmp3to1)); | |
3081 | ||
3082 | ||
3083 | // Third stage nand | |
3084 | //assign w1_cmp27to1 = ~(rd_en_d1_a & w1_cmp27to19 & w1_cmp18to10 & w1_cmp9to1); | |
3085 | //assign w0_cmp27to1 = ~(rd_en_d1_a & w0_cmp27to19 & w0_cmp18to10 & w0_cmp9to1); | |
3086 | ||
3087 | n2_l2t_sp_28kb_cust_nand_macro__ports_4__width_1 w1_nand_cmp27to1 | |
3088 | ( | |
3089 | .dout (w1_cmp27to1), | |
3090 | .din0 (rd_en_d1_a), | |
3091 | .din1 (w1_cmp27to19), | |
3092 | .din2 (w1_cmp18to10), | |
3093 | .din3 (w1_cmp9to1)); | |
3094 | ||
3095 | n2_l2t_sp_28kb_cust_nand_macro__ports_4__width_1 w0_nand_cmp27to1 | |
3096 | ( | |
3097 | .dout (w0_cmp27to1), | |
3098 | .din0 (rd_en_d1_a), | |
3099 | .din1 (w0_cmp27to19), | |
3100 | .din2 (w0_cmp18to10), | |
3101 | .din3 (w0_cmp9to1)); | |
3102 | ||
3103 | // The mux is not explicit (check with Connie) | |
3104 | //assign reg_sel[1:0] = {rid_lft_b, rid_rgt_b}; | |
3105 | //assign reg_d[4:0] = (reg_sel == 2'b10) ? reg_d_lft[4:0] : (reg_sel == 2'b01) ? reg_d_rgt[4:0] : 5'b00000; | |
3106 | //assign reg_en[1:0] = (reg_sel == 2'b10) ? reg_en_lft[1:0] : (reg_sel == 2'b01) ? reg_en_rgt[1:0] : 2'b00; | |
3107 | ||
3108 | n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_5 mux_reg_d_lft_reg_d_rgt | |
3109 | ( | |
3110 | .dout (reg_d[4:0]), | |
3111 | .din0 (reg_d_lft[4:0]), | |
3112 | .din1 (reg_d_rgt[4:0]), | |
3113 | .sel0 (rid_lft_b), | |
3114 | .sel1 (rid_rgt_b) | |
3115 | ); | |
3116 | ||
3117 | n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_2 mux_reg_en_lft_reg_en_rgt | |
3118 | ( | |
3119 | .dout (reg_en[1:0]), | |
3120 | .din0 (reg_en_lft[1:0]), | |
3121 | .din1 (reg_en_rgt[1:0]), | |
3122 | .sel0 (rid_lft_b), | |
3123 | .sel1 (rid_rgt_b) | |
3124 | ); | |
3125 | ||
3126 | ||
3127 | ||
3128 | //--------------------------------------- | |
3129 | // internal signals | |
3130 | //--------------------------------------- | |
3131 | assign ln1clk = l1clk_int_v2; | |
3132 | assign ln2clk = l1clk_int_v2; | |
3133 | //Change to structural CC | |
3134 | // assign wr_inhibit_a_l = ~wr_inhibit_a; | |
3135 | ||
3136 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_wr_inhibit_a | |
3137 | ( | |
3138 | .din (wr_inhibit_a), | |
3139 | .dout (wr_inhibit_a_l) | |
3140 | ); | |
3141 | ||
3142 | //--------------------------------------- | |
3143 | // Redundancy section | |
3144 | //--------------------------------------- | |
3145 | ||
3146 | //Change to structural CC | |
3147 | //assign wen_clk_lft = ~((~l1clk_int_v1) && reg_wen_lft); | |
3148 | //assign wen_clk_rgt = ~((~l1clk_int_v2) && reg_wen_rgt); | |
3149 | ||
3150 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_reg_wen_lft | |
3151 | ( | |
3152 | .din (reg_wen_lft), | |
3153 | .dout (not_reg_wen_lft) | |
3154 | ); | |
3155 | ||
3156 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_wen_clk_lft | |
3157 | ( | |
3158 | .din0 (l1clk_int_v1), | |
3159 | .din1 (not_reg_wen_lft), | |
3160 | .dout (wen_clk_lft) | |
3161 | ); | |
3162 | ||
3163 | n2_l2t_sp_28kb_cust_inv_macro__width_1 inv_reg_wen_rgt | |
3164 | ( | |
3165 | .din (reg_wen_rgt), | |
3166 | .dout (not_reg_wen_rgt) | |
3167 | ); | |
3168 | ||
3169 | n2_l2t_sp_28kb_cust_or_macro__ports_2__width_1 or_wen_clk_rgt | |
3170 | ( | |
3171 | .din0 (l1clk_int_v2), | |
3172 | .din1 (not_reg_wen_rgt), | |
3173 | .dout (wen_clk_rgt) | |
3174 | ); | |
3175 | ||
3176 | ||
3177 | //assign en_lft = ®_en_lft[1:0]; | |
3178 | //assign en_rgt = ®_en_rgt[1:0]; | |
3179 | ||
3180 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_en_lft | |
3181 | ( | |
3182 | .din0 (reg_en_lft[0]), | |
3183 | .din1 (reg_en_lft[1]), | |
3184 | .dout (en_lft) | |
3185 | ); | |
3186 | ||
3187 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_en_rgt | |
3188 | ( | |
3189 | .din0 (reg_en_rgt[0]), | |
3190 | .din1 (reg_en_rgt[1]), | |
3191 | .dout (en_rgt) | |
3192 | ); | |
3193 | ||
3194 | // Redundancy decoding : | |
3195 | //Change to structural CC | |
3196 | ||
3197 | // LEFT SIDE | |
3198 | n2_l2t_sp_28kb_cust_inv_macro__width_5 inv_reg_d_lft | |
3199 | ( | |
3200 | .din (reg_d_lft[4:0]), | |
3201 | .dout (not_reg_d_lft[4:0]) | |
3202 | ); | |
3203 | ||
3204 | //assign rpdb_lft[3] = en_lft && ( reg_d_lft[3]) && ( reg_d_lft[2]); | |
3205 | //assign rpda_lft[1] = en_lft && ( reg_d_lft[4]); | |
3206 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_rpda_lft_1 | |
3207 | ( | |
3208 | .din0 (reg_d_lft[4]), | |
3209 | .din1 (en_lft), | |
3210 | .dout (rpda_lft[1]) | |
3211 | ); | |
3212 | ||
3213 | //assign rpda_lft[0] = en_lft && (~reg_d_lft[4]); | |
3214 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_rpda_lft_0 | |
3215 | ( | |
3216 | .din0 (not_reg_d_lft[4]), | |
3217 | .din1 (en_lft), | |
3218 | .dout (rpda_lft[0]) | |
3219 | ); | |
3220 | ||
3221 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdb_lft_3 | |
3222 | ( | |
3223 | .din0 (reg_d_lft[3]), | |
3224 | .din1 (en_lft), | |
3225 | .din2 (reg_d_lft[2]), | |
3226 | .dout (rpdb_lft[3]) | |
3227 | ); | |
3228 | ||
3229 | //assign rpdb_lft[2] = en_lft && ( reg_d_lft[3]) && (~reg_d_lft[2]); | |
3230 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdb_lft_2 | |
3231 | ( | |
3232 | .din0 (reg_d_lft[3]), | |
3233 | .din1 (en_lft), | |
3234 | .din2 (not_reg_d_lft[2]), | |
3235 | .dout (rpdb_lft[2]) | |
3236 | ); | |
3237 | ||
3238 | //assign rpdb_lft[1] = en_lft && (~reg_d_lft[3]) && ( reg_d_lft[2]); | |
3239 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdb_lft_1 | |
3240 | ( | |
3241 | .din0 (not_reg_d_lft[3]), | |
3242 | .din1 (en_lft), | |
3243 | .din2 (reg_d_lft[2]), | |
3244 | .dout (rpdb_lft[1]) | |
3245 | ); | |
3246 | ||
3247 | //assign rpdb_lft[0] = en_lft && (~reg_d_lft[3]) && (~reg_d_lft[2]); | |
3248 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdb_lft_0 | |
3249 | ( | |
3250 | .din0 (not_reg_d_lft[3]), | |
3251 | .din1 (en_lft), | |
3252 | .din2 (not_reg_d_lft[2]), | |
3253 | .dout (rpdb_lft[0]) | |
3254 | ); | |
3255 | ||
3256 | //assign rpdc_lft[3] = en_lft && ( reg_d_lft[1]) && ( reg_d_lft[0]); | |
3257 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdc_lft_3 | |
3258 | ( | |
3259 | .din0 (reg_d_lft[1]), | |
3260 | .din1 (en_lft), | |
3261 | .din2 (reg_d_lft[0]), | |
3262 | .dout (rpdc_lft[3]) | |
3263 | ); | |
3264 | ||
3265 | //assign rpdc_lft[2] = en_lft && ( reg_d_lft[1]) && (~reg_d_lft[0]); | |
3266 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdc_lft_2 | |
3267 | ( | |
3268 | .din0 (reg_d_lft[1]), | |
3269 | .din1 (en_lft), | |
3270 | .din2 (not_reg_d_lft[0]), | |
3271 | .dout (rpdc_lft[2]) | |
3272 | ); | |
3273 | ||
3274 | //assign rpdc_lft[1] = en_lft && (~reg_d_lft[1]) && ( reg_d_lft[0]); | |
3275 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdc_lft_1 | |
3276 | ( | |
3277 | .din0 (reg_d_lft[0]), | |
3278 | .din1 (en_lft), | |
3279 | .din2 (not_reg_d_lft[1]), | |
3280 | .dout (rpdc_lft[1]) | |
3281 | ); | |
3282 | ||
3283 | //assign rpdc_lft[0] = en_lft && (~reg_d_lft[1]) && (~reg_d_lft[0]); | |
3284 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdc_lft_0 | |
3285 | ( | |
3286 | .din0 (not_reg_d_lft[0]), | |
3287 | .din1 (en_lft), | |
3288 | .din2 (not_reg_d_lft[1]), | |
3289 | .dout (rpdc_lft[0]) | |
3290 | ); | |
3291 | // RIGHT SIDE | |
3292 | n2_l2t_sp_28kb_cust_inv_macro__width_5 inv_reg_d_rgt | |
3293 | ( | |
3294 | .din (reg_d_rgt[4:0]), | |
3295 | .dout (not_reg_d_rgt[4:0]) | |
3296 | ); | |
3297 | ||
3298 | //assign rpda_rgt[1] = en_rgt && ( reg_d_rgt[4]); | |
3299 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_rpda_rgt_1 | |
3300 | ( | |
3301 | .din0 (reg_d_rgt[4]), | |
3302 | .din1 (en_rgt), | |
3303 | .dout (rpda_rgt[1]) | |
3304 | ); | |
3305 | ||
3306 | //assign rpda_rgt[0] = en_rgt && (~reg_d_rgt[4]); | |
3307 | n2_l2t_sp_28kb_cust_and_macro__ports_2__width_1 and_rpda_rgt_0 | |
3308 | ( | |
3309 | .din0 (not_reg_d_rgt[4]), | |
3310 | .din1 (en_rgt), | |
3311 | .dout (rpda_rgt[0]) | |
3312 | ); | |
3313 | ||
3314 | //assign rpdb_rgt[3] = en_rgt && ( reg_d_rgt[3]) && ( reg_d_rgt[2]); | |
3315 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdb_rgt_3 | |
3316 | ( | |
3317 | .din0 (reg_d_rgt[2]), | |
3318 | .din1 (en_rgt), | |
3319 | .din2 (reg_d_rgt[3]), | |
3320 | .dout (rpdb_rgt[3]) | |
3321 | ); | |
3322 | ||
3323 | //assign rpdb_rgt[2] = en_rgt && ( reg_d_rgt[3]) && (~reg_d_rgt[2]); | |
3324 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdb_rgt_2 | |
3325 | ( | |
3326 | .din0 (not_reg_d_rgt[2]), | |
3327 | .din1 (en_rgt), | |
3328 | .din2 (reg_d_rgt[3]), | |
3329 | .dout (rpdb_rgt[2]) | |
3330 | ); | |
3331 | ||
3332 | //assign rpdb_rgt[1] = en_rgt && (~reg_d_rgt[3]) && ( reg_d_rgt[2]); | |
3333 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdb_rgt_1 | |
3334 | ( | |
3335 | .din0 (reg_d_rgt[2]), | |
3336 | .din1 (en_rgt), | |
3337 | .din2 (not_reg_d_rgt[3]), | |
3338 | .dout (rpdb_rgt[1]) | |
3339 | ); | |
3340 | ||
3341 | //assign rpdb_rgt[0] = en_rgt && (~reg_d_rgt[3]) && (~reg_d_rgt[2]); | |
3342 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdb_rgt_0 | |
3343 | ( | |
3344 | .din0 (not_reg_d_rgt[2]), | |
3345 | .din1 (en_rgt), | |
3346 | .din2 (not_reg_d_rgt[3]), | |
3347 | .dout (rpdb_rgt[0]) | |
3348 | ); | |
3349 | ||
3350 | //assign rpdc_rgt[3] = en_rgt && ( reg_d_rgt[1]) && ( reg_d_rgt[0]); | |
3351 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdc_rgt_3 | |
3352 | ( | |
3353 | .din0 (reg_d_rgt[1]), | |
3354 | .din1 (en_rgt), | |
3355 | .din2 (reg_d_rgt[0]), | |
3356 | .dout (rpdc_rgt[3]) | |
3357 | ); | |
3358 | ||
3359 | //assign rpdc_rgt[2] = en_rgt && ( reg_d_rgt[1]) && (~reg_d_rgt[0]); | |
3360 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdc_rgt_2 | |
3361 | ( | |
3362 | .din0 (reg_d_rgt[1]), | |
3363 | .din1 (en_rgt), | |
3364 | .din2 (not_reg_d_rgt[0]), | |
3365 | .dout (rpdc_rgt[2]) | |
3366 | ); | |
3367 | ||
3368 | //assign rpdc_rgt[1] = en_rgt && (~reg_d_rgt[1]) && ( reg_d_rgt[0]); | |
3369 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdc_rgt_1 | |
3370 | ( | |
3371 | .din0 (not_reg_d_rgt[1]), | |
3372 | .din1 (en_rgt), | |
3373 | .din2 (reg_d_rgt[0]), | |
3374 | .dout (rpdc_rgt[1]) | |
3375 | ); | |
3376 | ||
3377 | //assign rpdc_rgt[0] = en_rgt && (~reg_d_rgt[1]) && (~reg_d_rgt[0]); | |
3378 | n2_l2t_sp_28kb_cust_and_macro__ports_3__width_1 and_rpdc_rgt_0 | |
3379 | ( | |
3380 | .din0 (not_reg_d_rgt[1]), | |
3381 | .din1 (en_rgt), | |
3382 | .din2 (not_reg_d_rgt[0]), | |
3383 | .dout (rpdc_rgt[0]) | |
3384 | ); | |
3385 | ||
3386 | // --- | |
3387 | ||
3388 | ||
3389 | //assign rpda_lft[1:0] = en_lft ? (reg_d_lft[4] ? 2'b10 : 2'b01 ): 2'b00; | |
3390 | //assign rpdb_lft[3:0] = en_lft ? ((reg_d_lft[3:2] == 2'b11) ? 4'b1000 : | |
3391 | // (reg_d_lft[3:2] == 2'b10) ? 4'b0100 : | |
3392 | // (reg_d_lft[3:2] == 2'b01) ? 4'b0010 : | |
3393 | // 4'b0001 ) : 4'b0000; | |
3394 | //assign rpdc_lft[3:0] = en_lft ? ((reg_d_lft[1:0] == 2'b11) ? 4'b1000 : | |
3395 | // (reg_d_lft[1:0] == 2'b10) ? 4'b0100 : | |
3396 | // (reg_d_lft[1:0] == 2'b01) ? 4'b0010 : | |
3397 | // 4'b0001 ) : 4'b0000; | |
3398 | //assign rpda_rgt[1:0] = en_rgt ? (reg_d_rgt[4] ? 2'b10 : 2'b01 ): 2'b00; | |
3399 | //assign rpdb_rgt[3:0] = en_rgt ? ((reg_d_rgt[3:2] == 2'b11) ? 4'b1000 : | |
3400 | // (reg_d_rgt[3:2] == 2'b10) ? 4'b0100 : | |
3401 | // (reg_d_rgt[3:2] == 2'b01) ? 4'b0010 : | |
3402 | // 4'b0001 ) : 4'b0000; | |
3403 | //assign rpdc_rgt[3:0] = en_rgt ? ((reg_d_rgt[1:0] == 2'b11) ? 4'b1000 : | |
3404 | // (reg_d_rgt[1:0] == 2'b10) ? 4'b0100 : | |
3405 | // (reg_d_rgt[1:0] == 2'b01) ? 4'b0010 : | |
3406 | // 4'b0001 ) : 4'b0000; | |
3407 | ||
3408 | ||
3409 | //--------------------------------------- | |
3410 | // L2T ARRAY INSTANTIATION | |
3411 | //--------------------------------------- | |
3412 | n2_l2t_array l2t_array (/*AUTOINST*/ | |
3413 | // Outputs | |
3414 | .sao_mx0_h (sao_mx0_h[`L2T_ARR_D_WIDTH-1:0]), | |
3415 | .sao_mx0_l (sao_mx0_l[`L2T_ARR_D_WIDTH-1:0]), | |
3416 | .sao_mx1_h (sao_mx1_h[`L2T_ARR_D_WIDTH-1:0]), | |
3417 | .sao_mx1_l (sao_mx1_l[`L2T_ARR_D_WIDTH-1:0]), | |
3418 | // Inputs | |
3419 | .vnw_ary (vnw_ary), | |
3420 | .din (din[`L2T_ARR_D_WIDTH - 1 : 0]), // Templated | |
3421 | .addr_b (addr_b[8:0]), | |
3422 | .l1clk_internal_v1(l1clk_int_v1), // Templated | |
3423 | .l1clk_internal_v2(l1clk_int_v2), // Templated | |
3424 | .ln1clk (ln1clk), | |
3425 | .ln2clk (ln2clk), | |
3426 | .rd_en_b (rd_en_b), | |
3427 | .rd_en_d1_a (rd_en_d1_a), | |
3428 | .rpda_lft (rpda_lft[1:0]), | |
3429 | .rpda_rgt (rpda_rgt[1:0]), | |
3430 | .rpdb_lft (rpdb_lft[3:0]), | |
3431 | .rpdb_rgt (rpdb_rgt[3:0]), | |
3432 | .rpdc_lft (rpdc_lft[3:0]), | |
3433 | .rpdc_rgt (rpdc_rgt[3:0]), | |
3434 | .w_inhibit_l (wr_inhibit_a_l), | |
3435 | .wr_en_b (wr_en_b), | |
3436 | .wr_en_d1_a (wr_en_d1_a), | |
3437 | .wr_way_b (wr_way_b[1:0]), | |
3438 | .wr_way_b_l (wr_way_b_l[1:0])); | |
3439 | ||
3440 | //--------------------------------------- | |
3441 | // SET RESET LATCH FOR SENSE AMP OUT | |
3442 | //--------------------------------------- | |
3443 | ||
3444 | n2_l2t_sr_latch srlatch_sao_mx1_27 (.set (sao_mx1_h[27]), .reset (sao_mx1_l[27]), .out (sao_mx1[27])); | |
3445 | n2_l2t_sr_latch srlatch_sao_mx1_26 (.set (sao_mx1_h[26]), .reset (sao_mx1_l[26]), .out (sao_mx1[26])); | |
3446 | n2_l2t_sr_latch srlatch_sao_mx1_25 (.set (sao_mx1_h[25]), .reset (sao_mx1_l[25]), .out (sao_mx1[25])); | |
3447 | n2_l2t_sr_latch srlatch_sao_mx1_24 (.set (sao_mx1_h[24]), .reset (sao_mx1_l[24]), .out (sao_mx1[24])); | |
3448 | n2_l2t_sr_latch srlatch_sao_mx1_23 (.set (sao_mx1_h[23]), .reset (sao_mx1_l[23]), .out (sao_mx1[23])); | |
3449 | n2_l2t_sr_latch srlatch_sao_mx1_22 (.set (sao_mx1_h[22]), .reset (sao_mx1_l[22]), .out (sao_mx1[22])); | |
3450 | n2_l2t_sr_latch srlatch_sao_mx1_21 (.set (sao_mx1_h[21]), .reset (sao_mx1_l[21]), .out (sao_mx1[21])); | |
3451 | n2_l2t_sr_latch srlatch_sao_mx1_20 (.set (sao_mx1_h[20]), .reset (sao_mx1_l[20]), .out (sao_mx1[20])); | |
3452 | n2_l2t_sr_latch srlatch_sao_mx1_19 (.set (sao_mx1_h[19]), .reset (sao_mx1_l[19]), .out (sao_mx1[19])); | |
3453 | n2_l2t_sr_latch srlatch_sao_mx1_18 (.set (sao_mx1_h[18]), .reset (sao_mx1_l[18]), .out (sao_mx1[18])); | |
3454 | n2_l2t_sr_latch srlatch_sao_mx1_17 (.set (sao_mx1_h[17]), .reset (sao_mx1_l[17]), .out (sao_mx1[17])); | |
3455 | n2_l2t_sr_latch srlatch_sao_mx1_16 (.set (sao_mx1_h[16]), .reset (sao_mx1_l[16]), .out (sao_mx1[16])); | |
3456 | n2_l2t_sr_latch srlatch_sao_mx1_15 (.set (sao_mx1_h[15]), .reset (sao_mx1_l[15]), .out (sao_mx1[15])); | |
3457 | n2_l2t_sr_latch srlatch_sao_mx1_14 (.set (sao_mx1_h[14]), .reset (sao_mx1_l[14]), .out (sao_mx1[14])); | |
3458 | n2_l2t_sr_latch srlatch_sao_mx1_13 (.set (sao_mx1_h[13]), .reset (sao_mx1_l[13]), .out (sao_mx1[13])); | |
3459 | n2_l2t_sr_latch srlatch_sao_mx1_12 (.set (sao_mx1_h[12]), .reset (sao_mx1_l[12]), .out (sao_mx1[12])); | |
3460 | n2_l2t_sr_latch srlatch_sao_mx1_11 (.set (sao_mx1_h[11]), .reset (sao_mx1_l[11]), .out (sao_mx1[11])); | |
3461 | n2_l2t_sr_latch srlatch_sao_mx1_10 (.set (sao_mx1_h[10]), .reset (sao_mx1_l[10]), .out (sao_mx1[10])); | |
3462 | n2_l2t_sr_latch srlatch_sao_mx1_9 (.set (sao_mx1_h[9]), .reset (sao_mx1_l[9]), .out (sao_mx1[9])); | |
3463 | n2_l2t_sr_latch srlatch_sao_mx1_8 (.set (sao_mx1_h[8]), .reset (sao_mx1_l[8]), .out (sao_mx1[8])); | |
3464 | n2_l2t_sr_latch srlatch_sao_mx1_7 (.set (sao_mx1_h[7]), .reset (sao_mx1_l[7]), .out (sao_mx1[7])); | |
3465 | n2_l2t_sr_latch srlatch_sao_mx1_6 (.set (sao_mx1_h[6]), .reset (sao_mx1_l[6]), .out (sao_mx1[6])); | |
3466 | n2_l2t_sr_latch srlatch_sao_mx1_5 (.set (sao_mx1_h[5]), .reset (sao_mx1_l[5]), .out (sao_mx1[5])); | |
3467 | n2_l2t_sr_latch srlatch_sao_mx1_4 (.set (sao_mx1_h[4]), .reset (sao_mx1_l[4]), .out (sao_mx1[4])); | |
3468 | n2_l2t_sr_latch srlatch_sao_mx1_3 (.set (sao_mx1_h[3]), .reset (sao_mx1_l[3]), .out (sao_mx1[3])); | |
3469 | n2_l2t_sr_latch srlatch_sao_mx1_2 (.set (sao_mx1_h[2]), .reset (sao_mx1_l[2]), .out (sao_mx1[2])); | |
3470 | n2_l2t_sr_latch srlatch_sao_mx1_1 (.set (sao_mx1_h[1]), .reset (sao_mx1_l[1]), .out (sao_mx1[1])); | |
3471 | n2_l2t_sr_latch srlatch_sao_mx1_0 (.set (sao_mx1_h[0]), .reset (sao_mx1_l[0 ]), .out (sao_mx1[0])); | |
3472 | ||
3473 | n2_l2t_sr_latch srlatch_sao_mx0_27 (.set (sao_mx0_h[27]), .reset (sao_mx0_l[27]), .out (sao_mx0[27])); | |
3474 | n2_l2t_sr_latch srlatch_sao_mx0_26 (.set (sao_mx0_h[26]), .reset (sao_mx0_l[26]), .out (sao_mx0[26])); | |
3475 | n2_l2t_sr_latch srlatch_sao_mx0_25 (.set (sao_mx0_h[25]), .reset (sao_mx0_l[25]), .out (sao_mx0[25])); | |
3476 | n2_l2t_sr_latch srlatch_sao_mx0_24 (.set (sao_mx0_h[24]), .reset (sao_mx0_l[24]), .out (sao_mx0[24])); | |
3477 | n2_l2t_sr_latch srlatch_sao_mx0_23 (.set (sao_mx0_h[23]), .reset (sao_mx0_l[23]), .out (sao_mx0[23])); | |
3478 | n2_l2t_sr_latch srlatch_sao_mx0_22 (.set (sao_mx0_h[22]), .reset (sao_mx0_l[22]), .out (sao_mx0[22])); | |
3479 | n2_l2t_sr_latch srlatch_sao_mx0_21 (.set (sao_mx0_h[21]), .reset (sao_mx0_l[21]), .out (sao_mx0[21])); | |
3480 | n2_l2t_sr_latch srlatch_sao_mx0_20 (.set (sao_mx0_h[20]), .reset (sao_mx0_l[20]), .out (sao_mx0[20])); | |
3481 | n2_l2t_sr_latch srlatch_sao_mx0_19 (.set (sao_mx0_h[19]), .reset (sao_mx0_l[19]), .out (sao_mx0[19])); | |
3482 | n2_l2t_sr_latch srlatch_sao_mx0_18 (.set (sao_mx0_h[18]), .reset (sao_mx0_l[18]), .out (sao_mx0[18])); | |
3483 | n2_l2t_sr_latch srlatch_sao_mx0_17 (.set (sao_mx0_h[17]), .reset (sao_mx0_l[17]), .out (sao_mx0[17])); | |
3484 | n2_l2t_sr_latch srlatch_sao_mx0_16 (.set (sao_mx0_h[16]), .reset (sao_mx0_l[16]), .out (sao_mx0[16])); | |
3485 | n2_l2t_sr_latch srlatch_sao_mx0_15 (.set (sao_mx0_h[15]), .reset (sao_mx0_l[15]), .out (sao_mx0[15])); | |
3486 | n2_l2t_sr_latch srlatch_sao_mx0_14 (.set (sao_mx0_h[14]), .reset (sao_mx0_l[14]), .out (sao_mx0[14])); | |
3487 | n2_l2t_sr_latch srlatch_sao_mx0_13 (.set (sao_mx0_h[13]), .reset (sao_mx0_l[13]), .out (sao_mx0[13])); | |
3488 | n2_l2t_sr_latch srlatch_sao_mx0_12 (.set (sao_mx0_h[12]), .reset (sao_mx0_l[12]), .out (sao_mx0[12])); | |
3489 | n2_l2t_sr_latch srlatch_sao_mx0_11 (.set (sao_mx0_h[11]), .reset (sao_mx0_l[11]), .out (sao_mx0[11])); | |
3490 | n2_l2t_sr_latch srlatch_sao_mx0_10 (.set (sao_mx0_h[10]), .reset (sao_mx0_l[10]), .out (sao_mx0[10])); | |
3491 | n2_l2t_sr_latch srlatch_sao_mx0_9 (.set (sao_mx0_h[9]), .reset (sao_mx0_l[9]), .out (sao_mx0[9])); | |
3492 | n2_l2t_sr_latch srlatch_sao_mx0_8 (.set (sao_mx0_h[8]), .reset (sao_mx0_l[8]), .out (sao_mx0[8])); | |
3493 | n2_l2t_sr_latch srlatch_sao_mx0_7 (.set (sao_mx0_h[7]), .reset (sao_mx0_l[7]), .out (sao_mx0[7])); | |
3494 | n2_l2t_sr_latch srlatch_sao_mx0_6 (.set (sao_mx0_h[6]), .reset (sao_mx0_l[6]), .out (sao_mx0[6])); | |
3495 | n2_l2t_sr_latch srlatch_sao_mx0_5 (.set (sao_mx0_h[5]), .reset (sao_mx0_l[5]), .out (sao_mx0[5])); | |
3496 | n2_l2t_sr_latch srlatch_sao_mx0_4 (.set (sao_mx0_h[4]), .reset (sao_mx0_l[4]), .out (sao_mx0[4])); | |
3497 | n2_l2t_sr_latch srlatch_sao_mx0_3 (.set (sao_mx0_h[3]), .reset (sao_mx0_l[3]), .out (sao_mx0[3])); | |
3498 | n2_l2t_sr_latch srlatch_sao_mx0_2 (.set (sao_mx0_h[2]), .reset (sao_mx0_l[2]), .out (sao_mx0[2])); | |
3499 | n2_l2t_sr_latch srlatch_sao_mx0_1 (.set (sao_mx0_h[1]), .reset (sao_mx0_l[1]), .out (sao_mx0[1])); | |
3500 | n2_l2t_sr_latch srlatch_sao_mx0_0 (.set (sao_mx0_h[0]), .reset (sao_mx0_l[0]), .out (sao_mx0[0])); | |
3501 | ||
3502 | ||
3503 | ||
3504 | //--------------------------------------- | |
3505 | // L2T 3BIT COMPARE (FIRST STAGE) | |
3506 | //--------------------------------------- | |
3507 | n2_l2t_cmp_3bx2 cmp27to25 ( | |
3508 | .sao_mx1_h (sao_mx1_h[27:25]), | |
3509 | .sao_mx1_l (sao_mx1_l[27:25]), | |
3510 | .sao_mx0_h (sao_mx0_h[27:25]), | |
3511 | .sao_mx0_l (sao_mx0_l[27:25]), | |
3512 | .lkuptag_d1 (lkuptag_d1[27:25]), | |
3513 | .l1clk_d (l1clk_int_v2), | |
3514 | .w1_cmp3b (w1_cmp27to25), | |
3515 | .w0_cmp3b (w0_cmp27to25)); | |
3516 | ||
3517 | n2_l2t_cmp_3bx2 cmp24to22 ( | |
3518 | .sao_mx1_h (sao_mx1_h[24:22]), | |
3519 | .sao_mx1_l (sao_mx1_l[24:22]), | |
3520 | .sao_mx0_h (sao_mx0_h[24:22]), | |
3521 | .sao_mx0_l (sao_mx0_l[24:22]), | |
3522 | .lkuptag_d1 (lkuptag_d1[24:22]), | |
3523 | .l1clk_d (l1clk_int_v2), | |
3524 | .w1_cmp3b (w1_cmp24to22), | |
3525 | .w0_cmp3b (w0_cmp24to22)); | |
3526 | ||
3527 | n2_l2t_cmp_3bx2 cmp21to19 ( | |
3528 | .sao_mx1_h (sao_mx1_h[21:19]), | |
3529 | .sao_mx1_l (sao_mx1_l[21:19]), | |
3530 | .sao_mx0_h (sao_mx0_h[21:19]), | |
3531 | .sao_mx0_l (sao_mx0_l[21:19]), | |
3532 | .lkuptag_d1 (lkuptag_d1[21:19]), | |
3533 | .l1clk_d (l1clk_int_v2), | |
3534 | .w1_cmp3b (w1_cmp21to19), | |
3535 | .w0_cmp3b (w0_cmp21to19)); | |
3536 | ||
3537 | n2_l2t_cmp_3bx2 cmp18to16 ( | |
3538 | .sao_mx1_h (sao_mx1_h[18:16]), | |
3539 | .sao_mx1_l (sao_mx1_l[18:16]), | |
3540 | .sao_mx0_h (sao_mx0_h[18:16]), | |
3541 | .sao_mx0_l (sao_mx0_l[18:16]), | |
3542 | .lkuptag_d1 (lkuptag_d1[18:16]), | |
3543 | .l1clk_d (l1clk_int_v2), | |
3544 | .w1_cmp3b (w1_cmp18to16), | |
3545 | .w0_cmp3b (w0_cmp18to16)); | |
3546 | ||
3547 | n2_l2t_cmp_3bx2 cmp15to13 ( | |
3548 | .sao_mx1_h (sao_mx1_h[15:13]), | |
3549 | .sao_mx1_l (sao_mx1_l[15:13]), | |
3550 | .sao_mx0_h (sao_mx0_h[15:13]), | |
3551 | .sao_mx0_l (sao_mx0_l[15:13]), | |
3552 | .lkuptag_d1 (lkuptag_d1[15:13]), | |
3553 | .l1clk_d (l1clk_int_v2), | |
3554 | .w1_cmp3b (w1_cmp15to13), | |
3555 | .w0_cmp3b (w0_cmp15to13)); | |
3556 | ||
3557 | n2_l2t_cmp_3bx2 cmp12to10 ( | |
3558 | .sao_mx1_h (sao_mx1_h[12:10]), | |
3559 | .sao_mx1_l (sao_mx1_l[12:10]), | |
3560 | .sao_mx0_h (sao_mx0_h[12:10]), | |
3561 | .sao_mx0_l (sao_mx0_l[12:10]), | |
3562 | .lkuptag_d1 (lkuptag_d1[12:10]), | |
3563 | .l1clk_d (l1clk_int_v2), | |
3564 | .w1_cmp3b (w1_cmp12to10), | |
3565 | .w0_cmp3b (w0_cmp12to10)); | |
3566 | ||
3567 | n2_l2t_cmp_3bx2 cmp9to7 ( | |
3568 | .sao_mx1_h (sao_mx1_h[9:7]), | |
3569 | .sao_mx1_l (sao_mx1_l[9:7]), | |
3570 | .sao_mx0_h (sao_mx0_h[9:7]), | |
3571 | .sao_mx0_l (sao_mx0_l[9:7]), | |
3572 | .lkuptag_d1 (lkuptag_d1[9:7]), | |
3573 | .l1clk_d (l1clk_int_v2), | |
3574 | .w1_cmp3b (w1_cmp9to7), | |
3575 | .w0_cmp3b (w0_cmp9to7)); | |
3576 | ||
3577 | ||
3578 | n2_l2t_cmp_3bx2 cmp6to4 ( | |
3579 | .sao_mx1_h (sao_mx1_h[6:4]), | |
3580 | .sao_mx1_l (sao_mx1_l[6:4]), | |
3581 | .sao_mx0_h (sao_mx0_h[6:4]), | |
3582 | .sao_mx0_l (sao_mx0_l[6:4]), | |
3583 | .lkuptag_d1 (lkuptag_d1[6:4]), | |
3584 | .l1clk_d (l1clk_int_v2), | |
3585 | .w1_cmp3b (w1_cmp6to4), | |
3586 | .w0_cmp3b (w0_cmp6to4)); | |
3587 | ||
3588 | ||
3589 | n2_l2t_cmp_3bx2 cmp3to1 ( | |
3590 | .sao_mx1_h (sao_mx1_h[3:1]), | |
3591 | .sao_mx1_l (sao_mx1_l[3:1]), | |
3592 | .sao_mx0_h (sao_mx0_h[3:1]), | |
3593 | .sao_mx0_l (sao_mx0_l[3:1]), | |
3594 | .lkuptag_d1 (lkuptag_d1[3:1]), | |
3595 | .l1clk_d (l1clk_int_v2), | |
3596 | .w1_cmp3b (w1_cmp3to1), | |
3597 | .w0_cmp3b (w0_cmp3to1)); | |
3598 | ||
3599 | ||
3600 | ||
3601 | //************************************************************************ | |
3602 | // REGISTERS SECTION | |
3603 | //************************************************************************ | |
3604 | ||
3605 | // INPUT FLOPS | |
3606 | n2_l2t_sp_28kb_cust_tisram_blb_macro__dmsff_4x__width_2 lat_reg_en_lft | |
3607 | ( | |
3608 | .d_a(reg_en_in[1:0]), | |
3609 | .q_b(reg_en_lft[1:0]), | |
3610 | .l1clk(wen_clk_lft) | |
3611 | ); | |
3612 | ||
3613 | n2_l2t_sp_28kb_cust_tisram_blb_macro__dmsff_4x__width_5 lat_reg_d_lft | |
3614 | ( | |
3615 | .d_a(reg_d_in[4:0]), | |
3616 | .q_b(reg_d_lft[4:0]), | |
3617 | .l1clk(wen_clk_lft) | |
3618 | ); | |
3619 | ||
3620 | n2_l2t_sp_28kb_cust_tisram_blb_macro__dmsff_4x__width_2 lat_reg_en_rgt | |
3621 | ( | |
3622 | .d_a(reg_en_in[1:0]), | |
3623 | .q_b(reg_en_rgt[1:0]), | |
3624 | .l1clk(wen_clk_rgt) | |
3625 | ); | |
3626 | ||
3627 | n2_l2t_sp_28kb_cust_tisram_blb_macro__dmsff_4x__width_5 lat_reg_d_rgt | |
3628 | ( | |
3629 | .d_a(reg_d_in[4:0]), | |
3630 | .q_b(reg_d_rgt[4:0]), | |
3631 | .l1clk(wen_clk_rgt) | |
3632 | ); | |
3633 | ||
3634 | // BLB for rid_lft and rid_rgt: | |
3635 | ||
3636 | n2_l2t_sp_28kb_cust_tisram_blb_macro__dmsff_4x__width_1 lat_rid_lft | |
3637 | ( | |
3638 | .d_a(rid_lft), | |
3639 | .q_b(rid_lft_b), | |
3640 | .l1clk(l1clk_int_v1) | |
3641 | ); | |
3642 | ||
3643 | n2_l2t_sp_28kb_cust_tisram_blb_macro__dmsff_4x__width_1 lat_rid_rgt | |
3644 | ( | |
3645 | .d_a(rid_rgt), | |
3646 | .q_b(rid_rgt_b), | |
3647 | .l1clk(l1clk_int_v1) | |
3648 | ); | |
3649 | ||
3650 | ||
3651 | n2_l2t_sp_28kb_cust_tisram_msff_macro__width_1 reg_addr_b_8 (.scan_in (reg_addr_b_8_scanin), .scan_out(reg_addr_b_8_scanout), | |
3652 | .latout(addr_b[8]), .latout_l(reg_addr_b_8_unused), .l1clk(l1clk_in), .d(index_a[8]), | |
3653 | .siclk(siclk), | |
3654 | .soclk(soclk)); | |
3655 | n2_l2t_sp_28kb_cust_tisram_msff_macro__width_1 reg_addr_b_7 (.scan_in (reg_addr_b_7_scanin), .scan_out(reg_addr_b_7_scanout), | |
3656 | .latout(addr_b[7]), .latout_l(reg_addr_b_7_unused), .l1clk(l1clk_in), .d(index_a[7]), | |
3657 | .siclk(siclk), | |
3658 | .soclk(soclk)); | |
3659 | n2_l2t_sp_28kb_cust_tisram_msff_macro__width_1 reg_addr_b_6 (.scan_in (reg_addr_b_6_scanin), .scan_out(reg_addr_b_6_scanout), | |
3660 | .latout(addr_b[6]), .latout_l(reg_addr_b_6_unused), .l1clk(l1clk_in), .d(index_a[6]), | |
3661 | .siclk(siclk), | |
3662 | .soclk(soclk)); | |
3663 | n2_l2t_sp_28kb_cust_tisram_msff_macro__width_1 reg_addr_b_5 (.scan_in (reg_addr_b_5_scanin), .scan_out(reg_addr_b_5_scanout), | |
3664 | .latout(addr_b[5]), .latout_l(reg_addr_b_5_unused), .l1clk(l1clk_in), .d(index_a[5]), | |
3665 | .siclk(siclk), | |
3666 | .soclk(soclk)); | |
3667 | n2_l2t_sp_28kb_cust_tisram_msff_macro__width_1 reg_addr_b_4 (.scan_in (reg_addr_b_4_scanin), .scan_out(reg_addr_b_4_scanout), | |
3668 | .latout(addr_b[4]), .latout_l(reg_addr_b_4_unused), .l1clk(l1clk_in), .d(index_a[4]), | |
3669 | .siclk(siclk), | |
3670 | .soclk(soclk)); | |
3671 | n2_l2t_sp_28kb_cust_tisram_msff_macro__width_1 reg_addr_b_3 (.scan_in (reg_addr_b_3_scanin), .scan_out(reg_addr_b_3_scanout), | |
3672 | .latout(addr_b[3]), .latout_l(reg_addr_b_3_unused), .l1clk(l1clk_in), .d(index_a[3]), | |
3673 | .siclk(siclk), | |
3674 | .soclk(soclk)); | |
3675 | n2_l2t_sp_28kb_cust_tisram_msff_macro__width_1 reg_addr_b_2 (.scan_in (reg_addr_b_2_scanin), .scan_out(reg_addr_b_2_scanout), | |
3676 | .latout(addr_b[2]), .latout_l(reg_addr_b_2_unused), .l1clk(l1clk_in), .d(index_a[2]), | |
3677 | .siclk(siclk), | |
3678 | .soclk(soclk)); | |
3679 | n2_l2t_sp_28kb_cust_tisram_msff_macro__width_1 reg_addr_b_1 (.scan_in (reg_addr_b_1_scanin), .scan_out(reg_addr_b_1_scanout), | |
3680 | .latout(addr_b[1]), .latout_l(reg_addr_b_1_unused), .l1clk(l1clk_in), .d(index_a[1]), | |
3681 | .siclk(siclk), | |
3682 | .soclk(soclk)); | |
3683 | ||
3684 | n2_l2t_sp_28kb_cust_tisram_msff_macro__width_1 reg_addr_b_0 (.scan_in (reg_addr_b_0_scanin), .scan_out(reg_addr_b_0_scanout), | |
3685 | .latout(addr_b[0]), .latout_l(reg_addr_b_0_unused), .l1clk(l1clk_in), .d(index_a[0]), | |
3686 | .siclk(siclk), | |
3687 | .soclk(soclk)); | |
3688 | ||
3689 | n2_l2t_sp_28kb_cust_tisram_msff_macro__width_2 reg_wr_way_b ( | |
3690 | .scan_in (reg_wr_way_b_scanin), | |
3691 | .scan_out(reg_wr_way_b_scanout), | |
3692 | .latout (wr_way_b[1:0]), | |
3693 | .latout_l(wr_way_b_l[1:0]), | |
3694 | .l1clk(l1clk_in), | |
3695 | .d(way_a[1:0]), | |
3696 | .siclk(siclk), | |
3697 | .soclk(soclk)); | |
3698 | ||
3699 | n2_l2t_sp_28kb_cust_tisram_msff_macro__width_1 reg_wr_en_b ( | |
3700 | .scan_in (reg_wr_en_b_scanin), | |
3701 | .scan_out(reg_wr_en_b_scanout), | |
3702 | .latout(wr_en_b), | |
3703 | .latout_l(reg_wr_en_b_unused), | |
3704 | .l1clk(l1clk_in), | |
3705 | .d(wr_en_a), | |
3706 | .siclk(siclk), | |
3707 | .soclk(soclk)); | |
3708 | ||
3709 | n2_l2t_sp_28kb_cust_tisram_msff_macro__width_1 reg_rd_en_b ( | |
3710 | .scan_in (reg_rd_en_b_scanin), | |
3711 | .scan_out(reg_rd_en_b_scanout), | |
3712 | .latout(rd_en_b), | |
3713 | .latout_l(reg_rd_en_b_unused), | |
3714 | .l1clk(l1clk_in), | |
3715 | .d(rd_en_a), | |
3716 | .siclk(siclk), | |
3717 | .soclk(soclk)); | |
3718 | ||
3719 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_wr_en_a ( | |
3720 | .scan_in(reg_wr_en_a_scanin), | |
3721 | .scan_out(reg_wr_en_a_scanout), | |
3722 | .dout(wr_en_d1_a), | |
3723 | .l1clk(l1clk_in), | |
3724 | .din(wr_en_a), | |
3725 | .siclk(siclk), | |
3726 | .soclk(soclk)); | |
3727 | ||
3728 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_rd_en_a ( | |
3729 | .scan_in(reg_rd_en_a_scanin), | |
3730 | .scan_out(reg_rd_en_a_scanout), | |
3731 | .dout(rd_en_d1_a), | |
3732 | .l1clk(l1clk_in), | |
3733 | .din(rd_en_a), | |
3734 | .siclk(siclk), | |
3735 | .soclk(soclk)); | |
3736 | ||
3737 | //----------------------------------------------------------- | |
3738 | // output | |
3739 | //----------------------------------------------------------- | |
3740 | ||
3741 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_27 (.scan_in(reg_tag_way1_27_scanin), .scan_out(reg_tag_way1_27_scanout), | |
3742 | .din(sao_mx1[27]), .dout(tag_way1[27]), .l1clk(l1clk_out0), | |
3743 | .siclk(siclk), | |
3744 | .soclk(soclk)); | |
3745 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_27 (.scan_in(reg_tag_way0_27_scanin), .scan_out(reg_tag_way0_27_scanout), | |
3746 | .din(sao_mx0[27]), .dout(tag_way0[27]), .l1clk(l1clk_out0), | |
3747 | .siclk(siclk), | |
3748 | .soclk(soclk)); | |
3749 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_26 (.scan_in(reg_tag_way1_26_scanin), .scan_out(reg_tag_way1_26_scanout), | |
3750 | .din(sao_mx1[26]), .dout(tag_way1[26]), .l1clk(l1clk_out0), | |
3751 | .siclk(siclk), | |
3752 | .soclk(soclk)); | |
3753 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_26 (.scan_in(reg_tag_way0_26_scanin), .scan_out(reg_tag_way0_26_scanout), | |
3754 | .din(sao_mx0[26]), .dout(tag_way0[26]), .l1clk(l1clk_out0), | |
3755 | .siclk(siclk), | |
3756 | .soclk(soclk)); | |
3757 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_25 (.scan_in(reg_tag_way1_25_scanin), .scan_out(reg_tag_way1_25_scanout), | |
3758 | .din(sao_mx1[25]), .dout(tag_way1[25]), .l1clk(l1clk_out0), | |
3759 | .siclk(siclk), | |
3760 | .soclk(soclk)); | |
3761 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_25 (.scan_in(reg_tag_way0_25_scanin), .scan_out(reg_tag_way0_25_scanout), | |
3762 | .din(sao_mx0[25]), .dout(tag_way0[25]), .l1clk(l1clk_out0), | |
3763 | .siclk(siclk), | |
3764 | .soclk(soclk)); | |
3765 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_24 (.scan_in(reg_tag_way1_24_scanin), .scan_out(reg_tag_way1_24_scanout), | |
3766 | .din(sao_mx1[24]), .dout(tag_way1[24]), .l1clk(l1clk_out0), | |
3767 | .siclk(siclk), | |
3768 | .soclk(soclk)); | |
3769 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_24 (.scan_in(reg_tag_way0_24_scanin), .scan_out(reg_tag_way0_24_scanout), | |
3770 | .din(sao_mx0[24]), .dout(tag_way0[24]), .l1clk(l1clk_out0), | |
3771 | .siclk(siclk), | |
3772 | .soclk(soclk)); | |
3773 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_23 (.scan_in(reg_tag_way1_23_scanin), .scan_out(reg_tag_way1_23_scanout), | |
3774 | .din(sao_mx1[23]), .dout(tag_way1[23]), .l1clk(l1clk_out0), | |
3775 | .siclk(siclk), | |
3776 | .soclk(soclk)); | |
3777 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_23 (.scan_in(reg_tag_way0_23_scanin), .scan_out(reg_tag_way0_23_scanout), | |
3778 | .din(sao_mx0[23]), .dout(tag_way0[23]), .l1clk(l1clk_out0), | |
3779 | .siclk(siclk), | |
3780 | .soclk(soclk)); | |
3781 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_22 (.scan_in(reg_tag_way1_22_scanin), .scan_out(reg_tag_way1_22_scanout), | |
3782 | .din(sao_mx1[22]), .dout(tag_way1[22]), .l1clk(l1clk_out0), | |
3783 | .siclk(siclk), | |
3784 | .soclk(soclk)); | |
3785 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_22 (.scan_in(reg_tag_way0_22_scanin), .scan_out(reg_tag_way0_22_scanout), | |
3786 | .din(sao_mx0[22]), .dout(tag_way0[22]), .l1clk(l1clk_out0), | |
3787 | .siclk(siclk), | |
3788 | .soclk(soclk)); | |
3789 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_21 (.scan_in(reg_tag_way1_21_scanin), .scan_out(reg_tag_way1_21_scanout), | |
3790 | .din(sao_mx1[21]), .dout(tag_way1[21]), .l1clk(l1clk_out0), | |
3791 | .siclk(siclk), | |
3792 | .soclk(soclk)); | |
3793 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_21 (.scan_in(reg_tag_way0_21_scanin), .scan_out(reg_tag_way0_21_scanout), | |
3794 | .din(sao_mx0[21]), .dout(tag_way0[21]), .l1clk(l1clk_out0), | |
3795 | .siclk(siclk), | |
3796 | .soclk(soclk)); | |
3797 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_20 (.scan_in(reg_tag_way1_20_scanin), .scan_out(reg_tag_way1_20_scanout), | |
3798 | .din(sao_mx1[20]), .dout(tag_way1[20]), .l1clk(l1clk_out0), | |
3799 | .siclk(siclk), | |
3800 | .soclk(soclk)); | |
3801 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_20 (.scan_in(reg_tag_way0_20_scanin), .scan_out(reg_tag_way0_20_scanout), | |
3802 | .din(sao_mx0[20]), .dout(tag_way0[20]), .l1clk(l1clk_out0), | |
3803 | .siclk(siclk), | |
3804 | .soclk(soclk)); | |
3805 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_19 (.scan_in(reg_tag_way1_19_scanin), .scan_out(reg_tag_way1_19_scanout), | |
3806 | .din(sao_mx1[19]), .dout(tag_way1[19]), .l1clk(l1clk_out0), | |
3807 | .siclk(siclk), | |
3808 | .soclk(soclk)); | |
3809 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_19 (.scan_in(reg_tag_way0_19_scanin), .scan_out(reg_tag_way0_19_scanout), | |
3810 | .din(sao_mx0[19]), .dout(tag_way0[19]), .l1clk(l1clk_out0), | |
3811 | .siclk(siclk), | |
3812 | .soclk(soclk)); | |
3813 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_18 (.scan_in(reg_tag_way1_18_scanin), .scan_out(reg_tag_way1_18_scanout), | |
3814 | .din(sao_mx1[18]), .dout(tag_way1[18]), .l1clk(l1clk_out0), | |
3815 | .siclk(siclk), | |
3816 | .soclk(soclk)); | |
3817 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_18 (.scan_in(reg_tag_way0_18_scanin), .scan_out(reg_tag_way0_18_scanout), | |
3818 | .din(sao_mx0[18]), .dout(tag_way0[18]), .l1clk(l1clk_out0), | |
3819 | .siclk(siclk), | |
3820 | .soclk(soclk)); | |
3821 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_17 (.scan_in(reg_tag_way1_17_scanin), .scan_out(reg_tag_way1_17_scanout), | |
3822 | .din(sao_mx1[17]), .dout(tag_way1[17]), .l1clk(l1clk_out0), | |
3823 | .siclk(siclk), | |
3824 | .soclk(soclk)); | |
3825 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_17 (.scan_in(reg_tag_way0_17_scanin), .scan_out(reg_tag_way0_17_scanout), | |
3826 | .din(sao_mx0[17]), .dout(tag_way0[17]), .l1clk(l1clk_out0), | |
3827 | .siclk(siclk), | |
3828 | .soclk(soclk)); | |
3829 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_16 (.scan_in(reg_tag_way1_16_scanin), .scan_out(reg_tag_way1_16_scanout), | |
3830 | .din(sao_mx1[16]), .dout(tag_way1[16]), .l1clk(l1clk_out0), | |
3831 | .siclk(siclk), | |
3832 | .soclk(soclk)); | |
3833 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_16 (.scan_in(reg_tag_way0_16_scanin), .scan_out(reg_tag_way0_16_scanout), | |
3834 | .din(sao_mx0[16]), .dout(tag_way0[16]), .l1clk(l1clk_out0), | |
3835 | .siclk(siclk), | |
3836 | .soclk(soclk)); | |
3837 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_15 (.scan_in(reg_tag_way1_15_scanin), .scan_out(reg_tag_way1_15_scanout), | |
3838 | .din(sao_mx1[15]), .dout(tag_way1[15]), .l1clk(l1clk_out0), | |
3839 | .siclk(siclk), | |
3840 | .soclk(soclk)); | |
3841 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_15 (.scan_in(reg_tag_way0_15_scanin), .scan_out(reg_tag_way0_15_scanout), | |
3842 | .din(sao_mx0[15]), .dout(tag_way0[15]), .l1clk(l1clk_out0), | |
3843 | .siclk(siclk), | |
3844 | .soclk(soclk)); | |
3845 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_14 (.scan_in(reg_tag_way1_14_scanin), .scan_out(reg_tag_way1_14_scanout), | |
3846 | .din(sao_mx1[14]), .dout(tag_way1[14]), .l1clk(l1clk_out0), | |
3847 | .siclk(siclk), | |
3848 | .soclk(soclk)); | |
3849 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_14 (.scan_in(reg_tag_way0_14_scanin), .scan_out(reg_tag_way0_14_scanout), | |
3850 | .din(sao_mx0[14]), .dout(tag_way0[14]), .l1clk(l1clk_out0), | |
3851 | .siclk(siclk), | |
3852 | .soclk(soclk)); | |
3853 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_13 (.scan_in(reg_tag_way1_13_scanin), .scan_out(reg_tag_way1_13_scanout), | |
3854 | .din(sao_mx1[13]), .dout(tag_way1[13]), .l1clk(l1clk_out0), | |
3855 | .siclk(siclk), | |
3856 | .soclk(soclk)); | |
3857 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_13 (.scan_in(reg_tag_way0_13_scanin), .scan_out(reg_tag_way0_13_scanout), | |
3858 | .din(sao_mx0[13]), .dout(tag_way0[13]), .l1clk(l1clk_out0), | |
3859 | .siclk(siclk), | |
3860 | .soclk(soclk)); | |
3861 | ||
3862 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_12 (.scan_in(reg_tag_way1_12_scanin), .scan_out(reg_tag_way1_12_scanout), | |
3863 | .din(sao_mx1[12]), .dout(tag_way1[12]), .l1clk(l1clk_out1), | |
3864 | .siclk(siclk), | |
3865 | .soclk(soclk)); | |
3866 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_12 (.scan_in(reg_tag_way0_12_scanin), .scan_out(reg_tag_way0_12_scanout), | |
3867 | .din(sao_mx0[12]), .dout(tag_way0[12]), .l1clk(l1clk_out1), | |
3868 | .siclk(siclk), | |
3869 | .soclk(soclk)); | |
3870 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_11 (.scan_in(reg_tag_way1_11_scanin), .scan_out(reg_tag_way1_11_scanout), | |
3871 | .din(sao_mx1[11]), .dout(tag_way1[11]), .l1clk(l1clk_out1), | |
3872 | .siclk(siclk), | |
3873 | .soclk(soclk)); | |
3874 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_11 (.scan_in(reg_tag_way0_11_scanin), .scan_out(reg_tag_way0_11_scanout), | |
3875 | .din(sao_mx0[11]), .dout(tag_way0[11]), .l1clk(l1clk_out1), | |
3876 | .siclk(siclk), | |
3877 | .soclk(soclk)); | |
3878 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_10 (.scan_in(reg_tag_way1_10_scanin), .scan_out(reg_tag_way1_10_scanout), | |
3879 | .din(sao_mx1[10]), .dout(tag_way1[10]), .l1clk(l1clk_out1), | |
3880 | .siclk(siclk), | |
3881 | .soclk(soclk)); | |
3882 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_10 (.scan_in(reg_tag_way0_10_scanin), .scan_out(reg_tag_way0_10_scanout), | |
3883 | .din(sao_mx0[10]), .dout(tag_way0[10]), .l1clk(l1clk_out1), | |
3884 | .siclk(siclk), | |
3885 | .soclk(soclk)); | |
3886 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_9 (.scan_in(reg_tag_way1_9_scanin), .scan_out(reg_tag_way1_9_scanout), | |
3887 | .din(sao_mx1[9]), .dout(tag_way1[9]), .l1clk(l1clk_out1), | |
3888 | .siclk(siclk), | |
3889 | .soclk(soclk)); | |
3890 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_9 (.scan_in(reg_tag_way0_9_scanin), .scan_out(reg_tag_way0_9_scanout), | |
3891 | .din(sao_mx0[9]), .dout(tag_way0[9]), .l1clk(l1clk_out1), | |
3892 | .siclk(siclk), | |
3893 | .soclk(soclk)); | |
3894 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_8 (.scan_in(reg_tag_way1_8_scanin), .scan_out(reg_tag_way1_8_scanout), | |
3895 | .din(sao_mx1[8]), .dout(tag_way1[8]), .l1clk(l1clk_out1), | |
3896 | .siclk(siclk), | |
3897 | .soclk(soclk)); | |
3898 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_8 (.scan_in(reg_tag_way0_8_scanin), .scan_out(reg_tag_way0_8_scanout), | |
3899 | .din(sao_mx0[8]), .dout(tag_way0[8]), .l1clk(l1clk_out1), | |
3900 | .siclk(siclk), | |
3901 | .soclk(soclk)); | |
3902 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_7 (.scan_in(reg_tag_way1_7_scanin), .scan_out(reg_tag_way1_7_scanout), | |
3903 | .din(sao_mx1[7]), .dout(tag_way1[7]), .l1clk(l1clk_out1), | |
3904 | .siclk(siclk), | |
3905 | .soclk(soclk)); | |
3906 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_7 (.scan_in(reg_tag_way0_7_scanin), .scan_out(reg_tag_way0_7_scanout), | |
3907 | .din(sao_mx0[7]), .dout(tag_way0[7]), .l1clk(l1clk_out1), | |
3908 | .siclk(siclk), | |
3909 | .soclk(soclk)); | |
3910 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_6 (.scan_in(reg_tag_way1_6_scanin), .scan_out(reg_tag_way1_6_scanout), | |
3911 | .din(sao_mx1[6]), .dout(tag_way1[6]), .l1clk(l1clk_out1), | |
3912 | .siclk(siclk), | |
3913 | .soclk(soclk)); | |
3914 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_6 (.scan_in(reg_tag_way0_6_scanin), .scan_out(reg_tag_way0_6_scanout), | |
3915 | .din(sao_mx0[6]), .dout(tag_way0[6]), .l1clk(l1clk_out1), | |
3916 | .siclk(siclk), | |
3917 | .soclk(soclk)); | |
3918 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_5 (.scan_in(reg_tag_way1_5_scanin), .scan_out(reg_tag_way1_5_scanout), | |
3919 | .din(sao_mx1[5]), .dout(tag_way1[5]), .l1clk(l1clk_out1), | |
3920 | .siclk(siclk), | |
3921 | .soclk(soclk)); | |
3922 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_5 (.scan_in(reg_tag_way0_5_scanin), .scan_out(reg_tag_way0_5_scanout), | |
3923 | .din(sao_mx0[5]), .dout(tag_way0[5]), .l1clk(l1clk_out1), | |
3924 | .siclk(siclk), | |
3925 | .soclk(soclk)); | |
3926 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_4 (.scan_in(reg_tag_way1_4_scanin), .scan_out(reg_tag_way1_4_scanout), | |
3927 | .din(sao_mx1[4]), .dout(tag_way1[4]), .l1clk(l1clk_out1), | |
3928 | .siclk(siclk), | |
3929 | .soclk(soclk)); | |
3930 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_4 (.scan_in(reg_tag_way0_4_scanin), .scan_out(reg_tag_way0_4_scanout), | |
3931 | .din(sao_mx0[4]), .dout(tag_way0[4]), .l1clk(l1clk_out1), | |
3932 | .siclk(siclk), | |
3933 | .soclk(soclk)); | |
3934 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_3 (.scan_in(reg_tag_way1_3_scanin), .scan_out(reg_tag_way1_3_scanout), | |
3935 | .din(sao_mx1[3]), .dout(tag_way1[3]), .l1clk(l1clk_out1), | |
3936 | .siclk(siclk), | |
3937 | .soclk(soclk)); | |
3938 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_3 (.scan_in(reg_tag_way0_3_scanin), .scan_out(reg_tag_way0_3_scanout), | |
3939 | .din(sao_mx0[3]), .dout(tag_way0[3]), .l1clk(l1clk_out1), | |
3940 | .siclk(siclk), | |
3941 | .soclk(soclk)); | |
3942 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_2 (.scan_in(reg_tag_way1_2_scanin), .scan_out(reg_tag_way1_2_scanout), | |
3943 | .din(sao_mx1[2]), .dout(tag_way1[2]), .l1clk(l1clk_out1), | |
3944 | .siclk(siclk), | |
3945 | .soclk(soclk)); | |
3946 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_2 (.scan_in(reg_tag_way0_2_scanin), .scan_out(reg_tag_way0_2_scanout), | |
3947 | .din(sao_mx0[2]), .dout(tag_way0[2]), .l1clk(l1clk_out1), | |
3948 | .siclk(siclk), | |
3949 | .soclk(soclk)); | |
3950 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_1 (.scan_in(reg_tag_way1_1_scanin), .scan_out(reg_tag_way1_1_scanout), | |
3951 | .din(sao_mx1[1]), .dout(tag_way1[1]), .l1clk(l1clk_out1), | |
3952 | .siclk(siclk), | |
3953 | .soclk(soclk)); | |
3954 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_1 (.scan_in(reg_tag_way0_1_scanin), .scan_out(reg_tag_way0_1_scanout), | |
3955 | .din(sao_mx0[1]), .dout(tag_way0[1]), .l1clk(l1clk_out1), | |
3956 | .siclk(siclk), | |
3957 | .soclk(soclk)); | |
3958 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way1_0 (.scan_in(reg_tag_way1_0_scanin), .scan_out(reg_tag_way1_0_scanout), | |
3959 | .din(sao_mx1[0]), .dout(tag_way1[0]), .l1clk(l1clk_out1), | |
3960 | .siclk(siclk), | |
3961 | .soclk(soclk)); | |
3962 | n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 reg_tag_way0_0 (.scan_in(reg_tag_way0_0_scanin), .scan_out(reg_tag_way0_0_scanout), | |
3963 | .din(sao_mx0[0]), .dout(tag_way0[0]), .l1clk(l1clk_out1), | |
3964 | .siclk(siclk), | |
3965 | .soclk(soclk)); | |
3966 | ||
3967 | n2_l2t_sp_28kb_cust_msffi_ctl_macro__clockwidth_0__width_1 reg_way_hit_a0 (.scan_in(reg_way_hit_a0_scanin), .scan_out(reg_way_hit_a0_scanout), | |
3968 | .din(w0_cmp27to1), .q_l(way_hit_a[0]), .l1clk(l1clk_out1), | |
3969 | .siclk(siclk), | |
3970 | .soclk(soclk)); | |
3971 | n2_l2t_sp_28kb_cust_msffi_ctl_macro__clockwidth_0__width_1 reg_way_hit_a1 (.scan_in(reg_way_hit_a1_scanin), .scan_out(reg_way_hit_a1_scanout), | |
3972 | .din(w1_cmp27to1), .q_l(way_hit_a[1]), .l1clk(l1clk_out1), | |
3973 | .siclk(siclk), | |
3974 | .soclk(soclk)); | |
3975 | ||
3976 | ||
3977 | // =============== VERILOG-MODE AUTO TEMPLATES | |
3978 | ||
3979 | /* | |
3980 | ||
3981 | n2_l2t_array AUTO_TEMPLATE ( | |
3982 | .din(din[`L2T_ARR_D_WIDTH - 1 : 0]), | |
3983 | .l1clk_internal_v1 (l1clk_int), | |
3984 | .l1clk_internal_v2 (l1clk_int), | |
3985 | ||
3986 | ); | |
3987 | ||
3988 | */ | |
3989 | // Manual scan hookup : | |
3990 | ||
3991 | assign reg_tag_way1_27_scanin = scan_in ; | |
3992 | assign reg_tag_way0_27_scanin = reg_tag_way1_27_scanout ; | |
3993 | assign reg_tag_way1_26_scanin = reg_tag_way0_27_scanout ; | |
3994 | assign reg_tag_way0_26_scanin = reg_tag_way1_26_scanout ; | |
3995 | assign reg_tag_way1_25_scanin = reg_tag_way0_26_scanout ; | |
3996 | assign reg_tag_way0_25_scanin = reg_tag_way1_25_scanout ; | |
3997 | assign reg_tag_way1_24_scanin = reg_tag_way0_25_scanout ; | |
3998 | assign reg_tag_way0_24_scanin = reg_tag_way1_24_scanout ; | |
3999 | assign reg_tag_way1_23_scanin = reg_tag_way0_24_scanout ; | |
4000 | assign reg_tag_way0_23_scanin = reg_tag_way1_23_scanout ; | |
4001 | assign reg_tag_way1_22_scanin = reg_tag_way0_23_scanout ; | |
4002 | assign reg_tag_way0_22_scanin = reg_tag_way1_22_scanout ; | |
4003 | assign reg_tag_way1_21_scanin = reg_tag_way0_22_scanout ; | |
4004 | assign reg_tag_way0_21_scanin = reg_tag_way1_21_scanout ; | |
4005 | assign reg_tag_way1_20_scanin = reg_tag_way0_21_scanout ; | |
4006 | assign reg_tag_way0_20_scanin = reg_tag_way1_20_scanout ; | |
4007 | assign reg_tag_way1_19_scanin = reg_tag_way0_20_scanout ; | |
4008 | assign reg_tag_way0_19_scanin = reg_tag_way1_19_scanout ; | |
4009 | assign reg_tag_way1_18_scanin = reg_tag_way0_19_scanout ; | |
4010 | assign reg_tag_way0_18_scanin = reg_tag_way1_18_scanout ; | |
4011 | assign reg_tag_way1_17_scanin = reg_tag_way0_18_scanout ; | |
4012 | assign reg_tag_way0_17_scanin = reg_tag_way1_17_scanout ; | |
4013 | assign reg_tag_way1_16_scanin = reg_tag_way0_17_scanout ; | |
4014 | assign reg_tag_way0_16_scanin = reg_tag_way1_16_scanout ; | |
4015 | assign reg_tag_way1_15_scanin = reg_tag_way0_16_scanout ; | |
4016 | assign reg_tag_way0_15_scanin = reg_tag_way1_15_scanout ; | |
4017 | assign reg_tag_way1_14_scanin = reg_tag_way0_15_scanout ; | |
4018 | assign reg_tag_way0_14_scanin = reg_tag_way1_14_scanout ; | |
4019 | assign reg_tag_way1_13_scanin = reg_tag_way0_14_scanout ; | |
4020 | assign reg_tag_way0_13_scanin = reg_tag_way1_13_scanout ; | |
4021 | ||
4022 | ||
4023 | assign reg_way_hit_a0_scanin = reg_tag_way0_13_scanout ; | |
4024 | assign reg_way_hit_a1_scanin = reg_way_hit_a0_scanout ; | |
4025 | ||
4026 | assign reg_addr_b_8_scanin = reg_way_hit_a1_scanout ; | |
4027 | assign reg_addr_b_7_scanin = reg_addr_b_8_scanout ; | |
4028 | assign reg_addr_b_6_scanin = reg_addr_b_7_scanout ; | |
4029 | assign reg_addr_b_5_scanin = reg_addr_b_6_scanout ; | |
4030 | assign reg_addr_b_4_scanin = reg_addr_b_5_scanout ; | |
4031 | assign reg_addr_b_3_scanin = reg_addr_b_4_scanout ; | |
4032 | assign reg_addr_b_2_scanin = reg_addr_b_3_scanout ; | |
4033 | assign reg_addr_b_1_scanin = reg_addr_b_2_scanout ; | |
4034 | ||
4035 | assign reg_wr_way_b_scanin = reg_addr_b_1_scanout ; | |
4036 | assign reg_addr_b_0_scanin = reg_wr_way_b_scanout ; | |
4037 | assign reg_wr_en_b_scanin = reg_addr_b_0_scanout ; | |
4038 | assign reg_rd_en_b_scanin = reg_wr_en_b_scanout ; | |
4039 | assign reg_wr_en_a_scanin = reg_rd_en_b_scanout ; | |
4040 | assign reg_rd_en_a_scanin = reg_wr_en_a_scanout ; | |
4041 | ||
4042 | assign reg_tag_way1_12_scanin = reg_rd_en_a_scanout ; | |
4043 | assign reg_tag_way0_12_scanin = reg_tag_way1_12_scanout ; | |
4044 | assign reg_tag_way1_11_scanin = reg_tag_way0_12_scanout ; | |
4045 | assign reg_tag_way0_11_scanin = reg_tag_way1_11_scanout ; | |
4046 | assign reg_tag_way1_10_scanin = reg_tag_way0_11_scanout ; | |
4047 | assign reg_tag_way0_10_scanin = reg_tag_way1_10_scanout ; | |
4048 | assign reg_tag_way1_9_scanin = reg_tag_way0_10_scanout ; | |
4049 | assign reg_tag_way0_9_scanin = reg_tag_way1_9_scanout ; | |
4050 | assign reg_tag_way1_8_scanin = reg_tag_way0_9_scanout ; | |
4051 | assign reg_tag_way0_8_scanin = reg_tag_way1_8_scanout ; | |
4052 | assign reg_tag_way1_7_scanin = reg_tag_way0_8_scanout ; | |
4053 | assign reg_tag_way0_7_scanin = reg_tag_way1_7_scanout ; | |
4054 | assign reg_tag_way1_6_scanin = reg_tag_way0_7_scanout ; | |
4055 | assign reg_tag_way0_6_scanin = reg_tag_way1_6_scanout ; | |
4056 | assign reg_tag_way1_5_scanin = reg_tag_way0_6_scanout ; | |
4057 | assign reg_tag_way0_5_scanin = reg_tag_way1_5_scanout ; | |
4058 | assign reg_tag_way1_4_scanin = reg_tag_way0_5_scanout ; | |
4059 | assign reg_tag_way0_4_scanin = reg_tag_way1_4_scanout ; | |
4060 | assign reg_tag_way1_3_scanin = reg_tag_way0_4_scanout ; | |
4061 | assign reg_tag_way0_3_scanin = reg_tag_way1_3_scanout ; | |
4062 | assign reg_tag_way1_2_scanin = reg_tag_way0_3_scanout ; | |
4063 | assign reg_tag_way0_2_scanin = reg_tag_way1_2_scanout ; | |
4064 | assign reg_tag_way1_1_scanin = reg_tag_way0_2_scanout ; | |
4065 | assign reg_tag_way0_1_scanin = reg_tag_way1_1_scanout ; | |
4066 | assign reg_tag_way1_0_scanin = reg_tag_way0_1_scanout ; | |
4067 | assign reg_tag_way0_0_scanin = reg_tag_way1_0_scanout ; | |
4068 | ||
4069 | assign scan_out = reg_tag_way0_0_scanout ; | |
4070 | endmodule | |
4071 | ||
4072 | ||
4073 | ||
4074 | ||
4075 | // | |
4076 | // nor macro for ports = 2,3 | |
4077 | // | |
4078 | // | |
4079 | ||
4080 | ||
4081 | ||
4082 | ||
4083 | ||
4084 | module n2_l2t_sp_28kb_cust_nor_macro__ports_3__width_1 ( | |
4085 | din0, | |
4086 | din1, | |
4087 | din2, | |
4088 | dout); | |
4089 | input [0:0] din0; | |
4090 | input [0:0] din1; | |
4091 | input [0:0] din2; | |
4092 | output [0:0] dout; | |
4093 | ||
4094 | ||
4095 | ||
4096 | ||
4097 | ||
4098 | ||
4099 | nor3 #(1) d0_0 ( | |
4100 | .in0(din0[0:0]), | |
4101 | .in1(din1[0:0]), | |
4102 | .in2(din2[0:0]), | |
4103 | .out(dout[0:0]) | |
4104 | ); | |
4105 | ||
4106 | ||
4107 | ||
4108 | ||
4109 | ||
4110 | ||
4111 | ||
4112 | endmodule | |
4113 | ||
4114 | ||
4115 | ||
4116 | ||
4117 | ||
4118 | // | |
4119 | // nand macro for ports = 2,3,4 | |
4120 | // | |
4121 | // | |
4122 | ||
4123 | ||
4124 | ||
4125 | ||
4126 | ||
4127 | module n2_l2t_sp_28kb_cust_nand_macro__ports_4__width_1 ( | |
4128 | din0, | |
4129 | din1, | |
4130 | din2, | |
4131 | din3, | |
4132 | dout); | |
4133 | input [0:0] din0; | |
4134 | input [0:0] din1; | |
4135 | input [0:0] din2; | |
4136 | input [0:0] din3; | |
4137 | output [0:0] dout; | |
4138 | ||
4139 | ||
4140 | ||
4141 | ||
4142 | ||
4143 | ||
4144 | nand4 #(1) d0_0 ( | |
4145 | .in0(din0[0:0]), | |
4146 | .in1(din1[0:0]), | |
4147 | .in2(din2[0:0]), | |
4148 | .in3(din3[0:0]), | |
4149 | .out(dout[0:0]) | |
4150 | ); | |
4151 | ||
4152 | ||
4153 | ||
4154 | ||
4155 | ||
4156 | ||
4157 | ||
4158 | ||
4159 | ||
4160 | endmodule | |
4161 | ||
4162 | ||
4163 | ||
4164 | ||
4165 | ||
4166 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4167 | // also for pass-gate with decoder | |
4168 | ||
4169 | ||
4170 | ||
4171 | ||
4172 | ||
4173 | // any PARAMS parms go into naming of macro | |
4174 | ||
4175 | module n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_5 ( | |
4176 | din0, | |
4177 | sel0, | |
4178 | din1, | |
4179 | sel1, | |
4180 | dout); | |
4181 | wire buffout0; | |
4182 | wire buffout1; | |
4183 | ||
4184 | input [4:0] din0; | |
4185 | input sel0; | |
4186 | input [4:0] din1; | |
4187 | input sel1; | |
4188 | output [4:0] dout; | |
4189 | ||
4190 | ||
4191 | ||
4192 | ||
4193 | ||
4194 | cl_dp1_muxbuff2_8x c0_0 ( | |
4195 | .in0(sel0), | |
4196 | .in1(sel1), | |
4197 | .out0(buffout0), | |
4198 | .out1(buffout1) | |
4199 | ); | |
4200 | mux2s #(5) d0_0 ( | |
4201 | .sel0(buffout0), | |
4202 | .sel1(buffout1), | |
4203 | .in0(din0[4:0]), | |
4204 | .in1(din1[4:0]), | |
4205 | .dout(dout[4:0]) | |
4206 | ); | |
4207 | ||
4208 | ||
4209 | ||
4210 | ||
4211 | ||
4212 | ||
4213 | ||
4214 | ||
4215 | ||
4216 | ||
4217 | ||
4218 | ||
4219 | ||
4220 | endmodule | |
4221 | ||
4222 | ||
4223 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4224 | // also for pass-gate with decoder | |
4225 | ||
4226 | ||
4227 | ||
4228 | ||
4229 | ||
4230 | // any PARAMS parms go into naming of macro | |
4231 | ||
4232 | module n2_l2t_sp_28kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_2 ( | |
4233 | din0, | |
4234 | sel0, | |
4235 | din1, | |
4236 | sel1, | |
4237 | dout); | |
4238 | wire buffout0; | |
4239 | wire buffout1; | |
4240 | ||
4241 | input [1:0] din0; | |
4242 | input sel0; | |
4243 | input [1:0] din1; | |
4244 | input sel1; | |
4245 | output [1:0] dout; | |
4246 | ||
4247 | ||
4248 | ||
4249 | ||
4250 | ||
4251 | cl_dp1_muxbuff2_8x c0_0 ( | |
4252 | .in0(sel0), | |
4253 | .in1(sel1), | |
4254 | .out0(buffout0), | |
4255 | .out1(buffout1) | |
4256 | ); | |
4257 | mux2s #(2) d0_0 ( | |
4258 | .sel0(buffout0), | |
4259 | .sel1(buffout1), | |
4260 | .in0(din0[1:0]), | |
4261 | .in1(din1[1:0]), | |
4262 | .dout(dout[1:0]) | |
4263 | ); | |
4264 | ||
4265 | ||
4266 | ||
4267 | ||
4268 | ||
4269 | ||
4270 | ||
4271 | ||
4272 | ||
4273 | ||
4274 | ||
4275 | ||
4276 | ||
4277 | endmodule | |
4278 | ||
4279 | ||
4280 | // | |
4281 | // invert macro | |
4282 | // | |
4283 | // | |
4284 | ||
4285 | ||
4286 | ||
4287 | ||
4288 | ||
4289 | module n2_l2t_sp_28kb_cust_inv_macro__width_5 ( | |
4290 | din, | |
4291 | dout); | |
4292 | input [4:0] din; | |
4293 | output [4:0] dout; | |
4294 | ||
4295 | ||
4296 | ||
4297 | ||
4298 | ||
4299 | ||
4300 | inv #(5) d0_0 ( | |
4301 | .in(din[4:0]), | |
4302 | .out(dout[4:0]) | |
4303 | ); | |
4304 | ||
4305 | ||
4306 | ||
4307 | ||
4308 | ||
4309 | ||
4310 | ||
4311 | ||
4312 | ||
4313 | endmodule | |
4314 | ||
4315 | ||
4316 | ||
4317 | ||
4318 | ||
4319 | `define L2T_ARR_D_WIDTH 28 | |
4320 | `define L2T_ARR_DEPTH 512 | |
4321 | `define WAY_HIT_WIDTH 16 | |
4322 | `define BADREAD BADBADD | |
4323 | ||
4324 | ||
4325 | `define sh_index_lft 5'b00000 | |
4326 | `define sh_index_rgt 5'b00000 | |
4327 | ||
4328 | module n2_l2t_array ( | |
4329 | din, | |
4330 | addr_b, | |
4331 | l1clk_internal_v1, | |
4332 | l1clk_internal_v2, | |
4333 | ln1clk, | |
4334 | ln2clk, | |
4335 | rd_en_b, | |
4336 | rd_en_d1_a, | |
4337 | rpda_lft, | |
4338 | rpda_rgt, | |
4339 | rpdb_lft, | |
4340 | rpdb_rgt, | |
4341 | rpdc_lft, | |
4342 | rpdc_rgt, | |
4343 | w_inhibit_l, | |
4344 | wr_en_b, | |
4345 | wr_en_d1_a, | |
4346 | wr_way_b, | |
4347 | wr_way_b_l, | |
4348 | vnw_ary, | |
4349 | sao_mx0_h, | |
4350 | sao_mx0_l, | |
4351 | sao_mx1_h, | |
4352 | sao_mx1_l); | |
4353 | wire ln1clk_unused; | |
4354 | wire ln2clk_unused; | |
4355 | wire l1clk_int_v2_unused; | |
4356 | wire rd_en_b_unused; | |
4357 | wire wr_en_b_unused; | |
4358 | wire [1:0] wr_way_b_unused; | |
4359 | wire l1clk_int; | |
4360 | wire rd_en; | |
4361 | wire [4:0] sf_l; | |
4362 | wire [4:0] sf_r; | |
4363 | wire shift_en_lft; | |
4364 | wire shift_en_rgt; | |
4365 | wire redundancy_en; | |
4366 | wire [4:0] sh_index_lft; | |
4367 | wire [4:0] sh_index_rgt; | |
4368 | wire mem_wr_en0; | |
4369 | wire mem_wr_en1; | |
4370 | ||
4371 | ||
4372 | // input l2clk; // cmp clock | |
4373 | // input iol2clk; // io clock | |
4374 | // input scan_in; | |
4375 | // input tcu_pce_ov; // scan signals | |
4376 | // input tcu_clk_stop; | |
4377 | // input tcu_aclk; | |
4378 | // input tcu_bclk; | |
4379 | // input tcu_scan_en; | |
4380 | // input tcu_muxtest; | |
4381 | // input tcu_dectest; | |
4382 | // output scan_out; | |
4383 | ||
4384 | ||
4385 | input [`L2T_ARR_D_WIDTH - 1:0] din; | |
4386 | input [8:0] addr_b; | |
4387 | input l1clk_internal_v1; | |
4388 | input l1clk_internal_v2; | |
4389 | input ln1clk; | |
4390 | input ln2clk; | |
4391 | input rd_en_b; | |
4392 | input rd_en_d1_a; | |
4393 | input [1:0] rpda_lft; | |
4394 | input [1:0] rpda_rgt; | |
4395 | input [3:0] rpdb_lft; | |
4396 | input [3:0] rpdb_rgt; | |
4397 | input [3:0] rpdc_lft; | |
4398 | input [3:0] rpdc_rgt; | |
4399 | input w_inhibit_l; | |
4400 | input wr_en_b; | |
4401 | input wr_en_d1_a; | |
4402 | input [1:0] wr_way_b; | |
4403 | input [1:0] wr_way_b_l; | |
4404 | ||
4405 | // Added vnw_ary pin for n2 for 2.0 | |
4406 | ||
4407 | input vnw_ary; | |
4408 | ||
4409 | output [`L2T_ARR_D_WIDTH - 1:0] sao_mx0_h; | |
4410 | output [`L2T_ARR_D_WIDTH - 1:0] sao_mx0_l; | |
4411 | output [`L2T_ARR_D_WIDTH - 1:0] sao_mx1_h; | |
4412 | output [`L2T_ARR_D_WIDTH - 1:0] sao_mx1_l; | |
4413 | ||
4414 | ||
4415 | reg [`L2T_ARR_D_WIDTH + 2:0] mem_lft[`L2T_ARR_DEPTH - 1 :0]; //one extra bit for redundancy | |
4416 | reg [0:`L2T_ARR_D_WIDTH - 2] mem_rgt[`L2T_ARR_DEPTH - 1 :0]; | |
4417 | reg [`L2T_ARR_D_WIDTH + 2:0] mem_lft_reg ; | |
4418 | reg [0:`L2T_ARR_D_WIDTH - 2] mem_rgt_reg ; // one entry of the memonry | |
4419 | ||
4420 | ||
4421 | reg [`L2T_ARR_D_WIDTH + 2:0] mem_data_lft; | |
4422 | reg [0:`L2T_ARR_D_WIDTH - 2] mem_data_rgt; | |
4423 | ||
4424 | reg [14:0] rdata0_lft; | |
4425 | reg [14:0] rdata1_lft; | |
4426 | reg [0:12] rdata0_rgt; | |
4427 | reg [0:12] rdata1_rgt; | |
4428 | reg [30:0] wdata_lft; | |
4429 | reg [30:0] wdata_rgt; | |
4430 | reg [29:0] tmp_lft; | |
4431 | reg [25:0] tmp_rgt; | |
4432 | ||
4433 | wire [14:0] mem0_lft; | |
4434 | wire [14:0] mem1_lft; | |
4435 | wire [12:0] mem0_rgt; | |
4436 | wire [12:0] mem1_rgt; | |
4437 | wire [30:0] mem_all_lft; | |
4438 | wire [26:0] mem_all_rgt; | |
4439 | wire [30:0] rdata_out_lft; | |
4440 | wire [26:0] rdata_out_rgt; | |
4441 | integer i; | |
4442 | integer j; | |
4443 | integer l; | |
4444 | integer k; | |
4445 | ||
4446 | reg [`L2T_ARR_D_WIDTH - 1:0] sao_mx0_h ; | |
4447 | reg [`L2T_ARR_D_WIDTH - 1:0] sao_mx0_l ; | |
4448 | reg [`L2T_ARR_D_WIDTH - 1:0] sao_mx1_h ; | |
4449 | reg [`L2T_ARR_D_WIDTH - 1:0] sao_mx1_l ; | |
4450 | ||
4451 | wire [`L2T_ARR_D_WIDTH - 1:0] rdata0_out ; | |
4452 | wire [`L2T_ARR_D_WIDTH - 1:0] rdata1_out ; | |
4453 | //----------------------------------------------------------------- | |
4454 | // INITIALIZE MEMORY | |
4455 | //----------------------------------------------------------------- | |
4456 | `ifndef NOINITMEM | |
4457 | initial begin | |
4458 | for (i = 0; i < `L2T_ARR_DEPTH - 1; i = i + 1) | |
4459 | begin | |
4460 | mem_rgt[i]=27'h0; | |
4461 | mem_lft[i]=31'h0; | |
4462 | end | |
4463 | end | |
4464 | `endif | |
4465 | ||
4466 | ||
4467 | //----------------------------------------------------------------- | |
4468 | // UNUSED SIGNALS | |
4469 | //----------------------------------------------------------------- | |
4470 | assign ln1clk_unused = ln1clk; | |
4471 | assign ln2clk_unused = ln2clk; | |
4472 | assign l1clk_int_v2_unused = l1clk_internal_v2; | |
4473 | assign rd_en_b_unused = rd_en_b; | |
4474 | assign wr_en_b_unused = wr_en_b; | |
4475 | assign wr_way_b_unused[1:0] = wr_way_b_l[1:0]; | |
4476 | ||
4477 | ||
4478 | assign l1clk_int = l1clk_internal_v1; | |
4479 | ||
4480 | //----------------------------------------------------------------- | |
4481 | // OUTPUTS | |
4482 | //----------------------------------------------------------------- | |
4483 | // | |
4484 | //always @ (l1clk_int or rd_en) | |
4485 | // if (l1clk_int || ~rd_en) | |
4486 | // begin | |
4487 | // sao_mx0_h [`L2T_ARR_D_WIDTH - 1:0] <= 28'h0; | |
4488 | // sao_mx0_l [`L2T_ARR_D_WIDTH - 1:0] <= 28'h0; | |
4489 | // sao_mx1_h [`L2T_ARR_D_WIDTH - 1:0] <= 28'h0; | |
4490 | // sao_mx1_l [`L2T_ARR_D_WIDTH - 1:0] <= 28'h0; | |
4491 | // end | |
4492 | // | |
4493 | //----------------------------------------------------------------- | |
4494 | // INTERNAL LOGIC | |
4495 | //----------------------------------------------------------------- | |
4496 | // Add vnw_ary high check for read operation for n2_to_2.0 | |
4497 | // assign rd_en = rd_en_d1_a && ~wr_en_d1_a && w_inhibit_l; | |
4498 | assign rd_en = rd_en_d1_a && ~wr_en_d1_a && w_inhibit_l && vnw_ary; | |
4499 | ||
4500 | //----------------------------------------------------------------- | |
4501 | // REDUNDANCY | |
4502 | //----------------------------------------------------------------- | |
4503 | // Use [511:0] way0[29] as the redundancy bit, there are total 512 redundancy | |
4504 | // bits. | |
4505 | // Left side : way0_tmp[29:15] = mem0_lft[14:0] | |
4506 | // way1_tmp[27:13] = mem1_lft[14:0] | |
4507 | // way0_tmp[14] = red_bit_lft (redundancy bit) | |
4508 | // Shift mem1_lft[n] -> mem0_lft[n] , shift mem0_lft[n]->men1_rgt[n-1] | |
4509 | // mem0_lft[0]->redundancy bit = red_bit_lft. | |
4510 | // | |
4511 | // Right side : way0_tmp[12:0] = mem0_rgt[12:0] | |
4512 | // way1_tmp[12:0] = mem1_rgt[12:0] | |
4513 | // way0_tmp[13] = red_bit_rgt (redundancy bit) | |
4514 | // Shift mem1_rgt[n] -> mem0_rgt[n] , shift mem0_rgt[n]->men1_rgt[n+1] | |
4515 | // mem0_rgt[0]->redundancy bit = red_bit_rgt. | |
4516 | // | |
4517 | //----------------------------------------------------------------- | |
4518 | ||
4519 | //----------------------------------------------------------------- | |
4520 | // recover the shift index from rpda, rpdb, rpdc | |
4521 | //----------------------------------------------------------------- | |
4522 | assign sf_l[4] = rpda_lft[1] ; | |
4523 | assign sf_l[3:2] = rpdb_lft[3] ? 2'b11 : | |
4524 | rpdb_lft[2] ? 2'b10 : | |
4525 | rpdb_lft[1] ? 2'b01 : | |
4526 | 2'b00; | |
4527 | assign sf_l[1:0] = rpdc_lft[3] ? 2'b11 : | |
4528 | rpdc_lft[2] ? 2'b10 : | |
4529 | rpdc_lft[1] ? 2'b01 : | |
4530 | 2'b00; | |
4531 | ||
4532 | assign sf_r[4] = rpda_rgt[1] ; | |
4533 | assign sf_r[3:2] = rpdb_rgt[3] ? 2'b11 : | |
4534 | rpdb_rgt[2] ? 2'b10 : | |
4535 | rpdb_rgt[1] ? 2'b01 : | |
4536 | 2'b00; | |
4537 | assign sf_r[1:0] = rpdc_rgt[3] ? 2'b11 : | |
4538 | rpdc_rgt[2] ? 2'b10 : | |
4539 | rpdc_rgt[1] ? 2'b01 : | |
4540 | 2'b00; | |
4541 | ||
4542 | assign shift_en_lft = (sf_l[4:0] < 5'd30) ? (|rpda_lft[1:0]) && (|rpdb_lft[3:0]) && (|rpdc_lft[3:0]) : 1'b0; | |
4543 | assign shift_en_rgt = (sf_r[4:0] < 5'd26) ? (|rpda_rgt[1:0]) && (|rpdb_rgt[3:0]) && (|rpdc_rgt[3:0]) : 1'b0; | |
4544 | ||
4545 | assign redundancy_en = shift_en_lft || shift_en_rgt; | |
4546 | ||
4547 | assign sh_index_lft[4:0] = shift_en_lft && (sf_l[4:0] < 5'd30) ? sf_l[4:0] : 5'b00000; | |
4548 | assign sh_index_rgt[4:0] = shift_en_rgt && (sf_r[4:0] < 5'd26) ? sf_r[4:0] : 5'b00000; | |
4549 | ||
4550 | ||
4551 | ||
4552 | //----------------------------------------------------------------- | |
4553 | // Write Arrays | |
4554 | //----------------------------------------------------------------- | |
4555 | ||
4556 | ||
4557 | //-------------------------------------- | |
4558 | // Write Redundancy Mapping | |
4559 | //-------------------------------------- | |
4560 | // Shifting of redundancy base on the sh_index_lft and sh_index_rgt | |
4561 | ||
4562 | wire [14:0] din_lft ; | |
4563 | wire [0:12] din_rgt ; | |
4564 | assign din_lft[14:0] = din[27:13]; | |
4565 | assign din_rgt[0:12] = din[12:0]; | |
4566 | ||
4567 | // Add vnw_high check for write operation (implemented for n2_to_2.0) | |
4568 | ||
4569 | assign mem_wr_en0 = wr_way_b[0] && wr_en_b && ~rd_en_b && w_inhibit_l && wr_en_d1_a && vnw_ary; | |
4570 | assign mem_wr_en1 = wr_way_b[1] && wr_en_b && ~rd_en_b && w_inhibit_l && wr_en_d1_a && vnw_ary; | |
4571 | ||
4572 | ||
4573 | ||
4574 | ||
4575 | //-------left------- | |
4576 | always @ (sh_index_lft or din_lft[14:0] or shift_en_lft or mem_wr_en0 or mem_wr_en1 | |
4577 | or l1clk_int or addr_b[8:0] ) | |
4578 | ||
4579 | ||
4580 | #0 | |
4581 | ||
4582 | begin | |
4583 | ||
4584 | ||
4585 | mem_lft_reg[`L2T_ARR_D_WIDTH + 2:0] = mem_lft[addr_b] ; | |
4586 | ||
4587 | ||
4588 | ||
4589 | // Write to redundant bit in write cycle for way0 with no redundancy | |
4590 | if (l1clk_int && (~shift_en_lft) && mem_wr_en0) | |
4591 | begin | |
4592 | mem_lft_reg[0] = din_lft[0]; | |
4593 | end | |
4594 | ||
4595 | for (i=14; i >= 0; i=i-1) | |
4596 | begin | |
4597 | if (mem_wr_en0 && l1clk_int) //way0 | |
4598 | begin | |
4599 | if (( sh_index_lft < (2*i)) || ~shift_en_lft) | |
4600 | mem_lft_reg[2*i+1] = din_lft[i]; //no shift | |
4601 | else | |
4602 | begin | |
4603 | mem_lft_reg[2*i] = din_lft[i]; // shift | |
4604 | end | |
4605 | end | |
4606 | if(shift_en_lft) | |
4607 | mem_lft_reg[sh_index_lft+1] = 1'bx; // write "x" to bad bit | |
4608 | end //for | |
4609 | ||
4610 | for (i=14; i >= 0; i=i-1) | |
4611 | begin | |
4612 | if (mem_wr_en1 && l1clk_int ) //way1 | |
4613 | begin | |
4614 | if (( sh_index_lft < (2*i + 1)) || ~shift_en_lft) | |
4615 | mem_lft_reg[2*i+2] = din_lft[i]; //no shift | |
4616 | else | |
4617 | begin | |
4618 | mem_lft_reg[2*i+1] = din_lft[i]; //shift | |
4619 | end | |
4620 | end | |
4621 | if(shift_en_lft) | |
4622 | mem_lft_reg[sh_index_lft+1] = 1'bx; //write "x" to bad bit | |
4623 | end | |
4624 | ||
4625 | if (l1clk_int) mem_lft[addr_b] = mem_lft_reg[`L2T_ARR_D_WIDTH + 2:0] ; | |
4626 | ||
4627 | ||
4628 | end | |
4629 | ||
4630 | //-------right------- | |
4631 | ||
4632 | always @ (sh_index_rgt or din_rgt[0:12] or shift_en_rgt or mem_wr_en0 or mem_wr_en1 | |
4633 | or l1clk_int or addr_b[8:0] ) | |
4634 | ||
4635 | ||
4636 | #0 | |
4637 | ||
4638 | begin | |
4639 | ||
4640 | mem_rgt_reg[0 : `L2T_ARR_D_WIDTH - 2] = mem_rgt[addr_b]; | |
4641 | ||
4642 | ||
4643 | ||
4644 | // Write to redundant bit in write cycle for way0 with no redundancy | |
4645 | if (l1clk_int && (~shift_en_rgt) && mem_wr_en0) | |
4646 | begin | |
4647 | mem_rgt_reg[0] = din_rgt[0]; | |
4648 | end | |
4649 | ||
4650 | for (k=12; k >= 0; k=k-1) | |
4651 | begin | |
4652 | if (mem_wr_en0 && l1clk_int) //WAY0 | |
4653 | begin | |
4654 | if (( sh_index_rgt < (2*k )) || ~shift_en_rgt) | |
4655 | mem_rgt_reg[2*k+1] = din_rgt[k]; //no shift | |
4656 | else | |
4657 | begin | |
4658 | mem_rgt_reg[2*k] = din_rgt[k]; // shift | |
4659 | end | |
4660 | end | |
4661 | if(shift_en_rgt) | |
4662 | mem_rgt_reg[sh_index_rgt+1] = 1'bx; // Write "X" to the bad bit | |
4663 | end //for | |
4664 | ||
4665 | for (k=12; k >= 0; k=k-1) | |
4666 | begin | |
4667 | if (mem_wr_en1 && l1clk_int ) //WAY1 | |
4668 | begin | |
4669 | if (( sh_index_rgt < (2*k + 1)) || ~shift_en_rgt) | |
4670 | mem_rgt_reg[2*k+2] = din_rgt[k]; //no shift | |
4671 | else | |
4672 | begin | |
4673 | mem_rgt_reg[2*k+1] = din_rgt[k]; // shift | |
4674 | end | |
4675 | end | |
4676 | if(shift_en_rgt) | |
4677 | mem_rgt_reg[sh_index_rgt+1] = 1'bx; // Write "X" to the bad bit | |
4678 | end //for | |
4679 | ||
4680 | if (l1clk_int) mem_rgt[addr_b] = mem_rgt_reg[0 : `L2T_ARR_D_WIDTH - 2] ; | |
4681 | ||
4682 | ||
4683 | ||
4684 | end | |
4685 | ||
4686 | //----------------------------------------------------------------- | |
4687 | // Read Arrays | |
4688 | //----------------------------------------------------------------- | |
4689 | ||
4690 | //-------------------------------------- | |
4691 | // Read Redundancy Mapping | |
4692 | //-------------------------------------- | |
4693 | ||
4694 | ||
4695 | //---------Left-------------- | |
4696 | always @ (sh_index_lft or shift_en_lft or rd_en or l1clk_int or addr_b[8:0] ) | |
4697 | begin | |
4698 | if (l1clk_int) | |
4699 | begin | |
4700 | ||
4701 | mem_data_lft[`L2T_ARR_D_WIDTH + 2:0] = ~rd_en ? 31'hx : mem_lft[addr_b] ; | |
4702 | ||
4703 | end | |
4704 | ||
4705 | ||
4706 | if (rd_en && ~l1clk_int) | |
4707 | ||
4708 | ||
4709 | begin | |
4710 | ||
4711 | for (j=14; j >= 0; j=j-1) //WAY0 | |
4712 | begin | |
4713 | if (( sh_index_lft < (2*j )) || ~shift_en_lft) | |
4714 | rdata0_lft[j] = mem_data_lft[2*j+1]; // no shift | |
4715 | else | |
4716 | rdata0_lft[j] = mem_data_lft[2*j]; // shift | |
4717 | end //for | |
4718 | ||
4719 | for (j=14; j >= 0; j=j-1) //WAY1 | |
4720 | begin | |
4721 | if (( sh_index_lft < (2*j + 1)) || ~shift_en_lft) | |
4722 | rdata1_lft[j] = mem_data_lft[2*j+2]; //no shift | |
4723 | else | |
4724 | rdata1_lft[j] = mem_data_lft[2*j+1]; // shift | |
4725 | end | |
4726 | sao_mx0_h[27:13] = rdata0_lft[14:0] & {15{rd_en}}; | |
4727 | sao_mx0_l[27:13] = ~rdata0_lft[14:0] & {15{rd_en}}; | |
4728 | sao_mx1_h[27:13] = rdata1_lft[14:0] & {15{rd_en}}; | |
4729 | sao_mx1_l[27:13] = ~rdata1_lft[14:0] & {15{rd_en}}; | |
4730 | end | |
4731 | else if(l1clk_int || ~rd_en) | |
4732 | begin | |
4733 | sao_mx0_h[27:13] = 15'h0; | |
4734 | sao_mx0_l[27:13] = 15'h0; | |
4735 | sao_mx1_h[27:13] = 15'h0; | |
4736 | sao_mx1_l[27:13] = 15'h0; | |
4737 | end | |
4738 | end | |
4739 | ||
4740 | //---------Right-------------- | |
4741 | ||
4742 | always @ (sh_index_rgt or shift_en_rgt or rd_en or l1clk_int or addr_b[8:0] ) | |
4743 | ||
4744 | begin | |
4745 | if (l1clk_int) | |
4746 | begin | |
4747 | ||
4748 | mem_data_rgt[0: `L2T_ARR_D_WIDTH - 2] = ~rd_en ? 27'hx : mem_rgt[addr_b] ; | |
4749 | ||
4750 | end | |
4751 | ||
4752 | ||
4753 | if (rd_en && ~l1clk_int) | |
4754 | ||
4755 | ||
4756 | begin | |
4757 | ||
4758 | for (l=12; l >= 0; l=l-1) //WAY0 | |
4759 | begin | |
4760 | if (( sh_index_rgt < (2*l)) || ~shift_en_rgt) | |
4761 | rdata0_rgt[l] = mem_data_rgt[2*l+1]; // no shift | |
4762 | else | |
4763 | rdata0_rgt[l] = mem_data_rgt[2*l]; // shift | |
4764 | end //for | |
4765 | ||
4766 | for (l=12; l >= 0; l=l-1) //WAY1 | |
4767 | begin | |
4768 | if (( sh_index_rgt < (2*l + 1)) || ~shift_en_rgt) | |
4769 | rdata1_rgt[l] = mem_data_rgt[2*l+2]; //no shift | |
4770 | else | |
4771 | rdata1_rgt[l] = mem_data_rgt[2*l+1]; // shift | |
4772 | end | |
4773 | sao_mx0_h[12:0] = rdata0_rgt[0:12] & {13{rd_en}}; | |
4774 | sao_mx0_l[12:0] = ~rdata0_rgt[0:12] & {13{rd_en}}; | |
4775 | sao_mx1_h[12:0] = rdata1_rgt[0:12] & {13{rd_en}}; | |
4776 | sao_mx1_l[12:0] = ~rdata1_rgt[0:12] & {13{rd_en}}; | |
4777 | end | |
4778 | else if (l1clk_int || ~rd_en) | |
4779 | begin | |
4780 | sao_mx0_h[12:0] = 13'h0; | |
4781 | sao_mx0_l[12:0] = 13'h0; | |
4782 | sao_mx1_h[12:0] = 13'h0; | |
4783 | sao_mx1_l[12:0] = 13'h0; | |
4784 | end | |
4785 | end | |
4786 | ||
4787 | ||
4788 | endmodule | |
4789 | ||
4790 | ||
4791 | ||
4792 | module n2_l2t_sr_latch ( | |
4793 | set, | |
4794 | reset, | |
4795 | out) ; | |
4796 | ||
4797 | ||
4798 | input set; | |
4799 | input reset; | |
4800 | output out; | |
4801 | ||
4802 | reg out; | |
4803 | ||
4804 | always @(set or reset) | |
4805 | begin | |
4806 | if (reset) out=1'b0; | |
4807 | else if (set) out=1'b1; | |
4808 | end | |
4809 | endmodule // n2_l2t_sr_latch | |
4810 | ||
4811 | ||
4812 | ||
4813 | // Compare sao_mx_h with lkuptag_d1, and sao_mx_l with ~lkuptag_d1. | |
4814 | // Output is "0" for hit and "1" for miss | |
4815 | ||
4816 | module n2_l2t_cmp_3bx2 ( | |
4817 | sao_mx1_h, | |
4818 | sao_mx1_l, | |
4819 | sao_mx0_h, | |
4820 | sao_mx0_l, | |
4821 | lkuptag_d1, | |
4822 | l1clk_d, | |
4823 | w1_cmp3b, | |
4824 | w0_cmp3b) ; | |
4825 | ||
4826 | ||
4827 | input [2:0] sao_mx1_h; | |
4828 | input [2:0] sao_mx1_l; | |
4829 | input [2:0] sao_mx0_h; | |
4830 | input [2:0] sao_mx0_l; | |
4831 | input [2:0] lkuptag_d1; | |
4832 | input l1clk_d; | |
4833 | output w1_cmp3b; | |
4834 | output w0_cmp3b; | |
4835 | ||
4836 | reg w1_cmp3b; | |
4837 | reg w0_cmp3b; | |
4838 | ||
4839 | //Compare ouput is 0 for match and 1 for mismatch | |
4840 | ||
4841 | always @(l1clk_d or sao_mx1_h or sao_mx1_l or sao_mx0_h or sao_mx0_l or lkuptag_d1) | |
4842 | ||
4843 | if (l1clk_d) // Precharge mode | |
4844 | begin | |
4845 | w1_cmp3b = 1'b0; | |
4846 | w0_cmp3b = 1'b0; | |
4847 | end | |
4848 | else | |
4849 | if (~l1clk_d ) // Evaluation mode | |
4850 | begin | |
4851 | w1_cmp3b = (lkuptag_d1[2] && sao_mx1_l[2]) || (~lkuptag_d1[2] && sao_mx1_h[2]) || | |
4852 | (lkuptag_d1[1] && sao_mx1_l[1]) || (~lkuptag_d1[1] && sao_mx1_h[1]) || | |
4853 | (lkuptag_d1[0] && sao_mx1_l[0]) || (~lkuptag_d1[0] && sao_mx1_h[0]); | |
4854 | ||
4855 | w0_cmp3b = (lkuptag_d1[2] && sao_mx0_l[2]) || (~lkuptag_d1[2] && sao_mx0_h[2]) || | |
4856 | (lkuptag_d1[1] && sao_mx0_l[1]) || (~lkuptag_d1[1] && sao_mx0_h[1]) || | |
4857 | (lkuptag_d1[0] && sao_mx0_l[0]) || (~lkuptag_d1[0] && sao_mx0_h[0]); | |
4858 | end | |
4859 | ||
4860 | endmodule // n2_l2t_cmp_3bx2 | |
4861 | ||
4862 | ||
4863 | // | |
4864 | // macro for cl_mc1_tisram_blb_{8,4}x flops | |
4865 | // | |
4866 | // | |
4867 | ||
4868 | ||
4869 | ||
4870 | ||
4871 | ||
4872 | module n2_l2t_sp_28kb_cust_tisram_blb_macro__dmsff_4x__width_2 ( | |
4873 | d_a, | |
4874 | l1clk, | |
4875 | q_b); | |
4876 | input [1:0] d_a; | |
4877 | input l1clk; | |
4878 | output [1:0] q_b; | |
4879 | ||
4880 | ||
4881 | ||
4882 | ||
4883 | ||
4884 | ||
4885 | tisram_blb #(2) d0_0 ( | |
4886 | .d(d_a[1:0]), | |
4887 | .l1clk(l1clk), | |
4888 | .latout_l(q_b[1:0]) | |
4889 | ); | |
4890 | ||
4891 | ||
4892 | ||
4893 | ||
4894 | ||
4895 | ||
4896 | ||
4897 | ||
4898 | ||
4899 | ||
4900 | //place::generic_place($width,$stack,$left); | |
4901 | ||
4902 | endmodule | |
4903 | ||
4904 | ||
4905 | ||
4906 | ||
4907 | ||
4908 | // | |
4909 | // macro for cl_mc1_tisram_blb_{8,4}x flops | |
4910 | // | |
4911 | // | |
4912 | ||
4913 | ||
4914 | ||
4915 | ||
4916 | ||
4917 | module n2_l2t_sp_28kb_cust_tisram_blb_macro__dmsff_4x__width_5 ( | |
4918 | d_a, | |
4919 | l1clk, | |
4920 | q_b); | |
4921 | input [4:0] d_a; | |
4922 | input l1clk; | |
4923 | output [4:0] q_b; | |
4924 | ||
4925 | ||
4926 | ||
4927 | ||
4928 | ||
4929 | ||
4930 | tisram_blb #(5) d0_0 ( | |
4931 | .d(d_a[4:0]), | |
4932 | .l1clk(l1clk), | |
4933 | .latout_l(q_b[4:0]) | |
4934 | ); | |
4935 | ||
4936 | ||
4937 | ||
4938 | ||
4939 | ||
4940 | ||
4941 | ||
4942 | ||
4943 | ||
4944 | ||
4945 | //place::generic_place($width,$stack,$left); | |
4946 | ||
4947 | endmodule | |
4948 | ||
4949 | ||
4950 | ||
4951 | ||
4952 | ||
4953 | // | |
4954 | // macro for cl_mc1_tisram_blb_{8,4}x flops | |
4955 | // | |
4956 | // | |
4957 | ||
4958 | ||
4959 | ||
4960 | ||
4961 | ||
4962 | module n2_l2t_sp_28kb_cust_tisram_blb_macro__dmsff_4x__width_1 ( | |
4963 | d_a, | |
4964 | l1clk, | |
4965 | q_b); | |
4966 | input [0:0] d_a; | |
4967 | input l1clk; | |
4968 | output [0:0] q_b; | |
4969 | ||
4970 | ||
4971 | ||
4972 | ||
4973 | ||
4974 | ||
4975 | tisram_blb #(1) d0_0 ( | |
4976 | .d(d_a[0:0]), | |
4977 | .l1clk(l1clk), | |
4978 | .latout_l(q_b[0:0]) | |
4979 | ); | |
4980 | ||
4981 | ||
4982 | ||
4983 | ||
4984 | ||
4985 | ||
4986 | ||
4987 | ||
4988 | ||
4989 | ||
4990 | //place::generic_place($width,$stack,$left); | |
4991 | ||
4992 | endmodule | |
4993 | ||
4994 | ||
4995 | ||
4996 | ||
4997 | ||
4998 | // | |
4999 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
5000 | // | |
5001 | // | |
5002 | ||
5003 | ||
5004 | ||
5005 | ||
5006 | ||
5007 | module n2_l2t_sp_28kb_cust_tisram_msff_macro__width_1 ( | |
5008 | d, | |
5009 | scan_in, | |
5010 | l1clk, | |
5011 | siclk, | |
5012 | soclk, | |
5013 | scan_out, | |
5014 | latout, | |
5015 | latout_l); | |
5016 | input [0:0] d; | |
5017 | input scan_in; | |
5018 | input l1clk; | |
5019 | input siclk; | |
5020 | input soclk; | |
5021 | output scan_out; | |
5022 | output [0:0] latout; | |
5023 | output [0:0] latout_l; | |
5024 | ||
5025 | ||
5026 | ||
5027 | ||
5028 | ||
5029 | ||
5030 | tisram_msff #(1) d0_0 ( | |
5031 | .d(d[0:0]), | |
5032 | .si(scan_in), | |
5033 | .so(scan_out), | |
5034 | .l1clk(l1clk), | |
5035 | .siclk(siclk), | |
5036 | .soclk(soclk), | |
5037 | .latout(latout[0:0]), | |
5038 | .latout_l(latout_l[0:0]) | |
5039 | ); | |
5040 | ||
5041 | ||
5042 | ||
5043 | ||
5044 | ||
5045 | ||
5046 | ||
5047 | ||
5048 | ||
5049 | ||
5050 | ||
5051 | ||
5052 | //place::generic_place($width,$stack,$left); | |
5053 | ||
5054 | endmodule | |
5055 | ||
5056 | ||
5057 | ||
5058 | ||
5059 | ||
5060 | // | |
5061 | // macro for cl_mc1_tisram_msff_{16,8}x flops | |
5062 | // | |
5063 | // | |
5064 | ||
5065 | ||
5066 | ||
5067 | ||
5068 | ||
5069 | module n2_l2t_sp_28kb_cust_tisram_msff_macro__width_2 ( | |
5070 | d, | |
5071 | scan_in, | |
5072 | l1clk, | |
5073 | siclk, | |
5074 | soclk, | |
5075 | scan_out, | |
5076 | latout, | |
5077 | latout_l); | |
5078 | wire [0:0] so; | |
5079 | ||
5080 | input [1:0] d; | |
5081 | input scan_in; | |
5082 | input l1clk; | |
5083 | input siclk; | |
5084 | input soclk; | |
5085 | output scan_out; | |
5086 | output [1:0] latout; | |
5087 | output [1:0] latout_l; | |
5088 | ||
5089 | ||
5090 | ||
5091 | ||
5092 | ||
5093 | ||
5094 | tisram_msff #(2) d0_0 ( | |
5095 | .d(d[1:0]), | |
5096 | .si({scan_in,so[0:0]}), | |
5097 | .so({so[0:0],scan_out}), | |
5098 | .l1clk(l1clk), | |
5099 | .siclk(siclk), | |
5100 | .soclk(soclk), | |
5101 | .latout(latout[1:0]), | |
5102 | .latout_l(latout_l[1:0]) | |
5103 | ); | |
5104 | ||
5105 | ||
5106 | ||
5107 | ||
5108 | ||
5109 | ||
5110 | ||
5111 | ||
5112 | ||
5113 | ||
5114 | ||
5115 | ||
5116 | //place::generic_place($width,$stack,$left); | |
5117 | ||
5118 | endmodule | |
5119 | ||
5120 | ||
5121 | ||
5122 | ||
5123 | ||
5124 | ||
5125 | ||
5126 | ||
5127 | ||
5128 | // any PARAMS parms go into naming of macro | |
5129 | ||
5130 | module n2_l2t_sp_28kb_cust_msff_ctl_macro__width_1 ( | |
5131 | din, | |
5132 | l1clk, | |
5133 | scan_in, | |
5134 | siclk, | |
5135 | soclk, | |
5136 | dout, | |
5137 | scan_out); | |
5138 | wire [0:0] fdin; | |
5139 | ||
5140 | input [0:0] din; | |
5141 | input l1clk; | |
5142 | input scan_in; | |
5143 | ||
5144 | ||
5145 | input siclk; | |
5146 | input soclk; | |
5147 | ||
5148 | output [0:0] dout; | |
5149 | output scan_out; | |
5150 | assign fdin[0:0] = din[0:0]; | |
5151 | ||
5152 | ||
5153 | ||
5154 | ||
5155 | ||
5156 | ||
5157 | dff #(1) d0_0 ( | |
5158 | .l1clk(l1clk), | |
5159 | .siclk(siclk), | |
5160 | .soclk(soclk), | |
5161 | .d(fdin[0:0]), | |
5162 | .si(scan_in), | |
5163 | .so(scan_out), | |
5164 | .q(dout[0:0]) | |
5165 | ); | |
5166 | ||
5167 | ||
5168 | ||
5169 | ||
5170 | ||
5171 | ||
5172 | ||
5173 | ||
5174 | ||
5175 | ||
5176 | ||
5177 | ||
5178 | endmodule | |
5179 | ||
5180 | ||
5181 | ||
5182 | ||
5183 | ||
5184 | ||
5185 | ||
5186 | ||
5187 | ||
5188 | ||
5189 | ||
5190 | ||
5191 | ||
5192 | // any PARAMS parms go into naming of macro | |
5193 | ||
5194 | module n2_l2t_sp_28kb_cust_msffi_ctl_macro__clockwidth_0__width_1 ( | |
5195 | din, | |
5196 | l1clk, | |
5197 | scan_in, | |
5198 | siclk, | |
5199 | soclk, | |
5200 | q_l, | |
5201 | scan_out); | |
5202 | input [0:0] din; | |
5203 | input l1clk; | |
5204 | input scan_in; | |
5205 | ||
5206 | ||
5207 | input siclk; | |
5208 | input soclk; | |
5209 | ||
5210 | output [0:0] q_l; | |
5211 | output scan_out; | |
5212 | ||
5213 | ||
5214 | ||
5215 | ||
5216 | ||
5217 | ||
5218 | msffi #(1) d0_0 ( | |
5219 | .l1clk(l1clk), | |
5220 | .siclk(siclk), | |
5221 | .soclk(soclk), | |
5222 | .d(din[0:0]), | |
5223 | .si(scan_in), | |
5224 | .so(scan_out), | |
5225 | .q_l(q_l[0:0]) | |
5226 | ); | |
5227 | ||
5228 | ||
5229 | ||
5230 | ||
5231 | ||
5232 | ||
5233 | ||
5234 | ||
5235 | ||
5236 | ||
5237 | ||
5238 | ||
5239 | endmodule | |
5240 | ||
5241 | ||
5242 | ||
5243 | ||
5244 | ||
5245 | ||
5246 | ||
5247 | ||
5248 | ||
5249 | ||
5250 | ||
5251 | ||
5252 | ||
5253 | // any PARAMS parms go into naming of macro | |
5254 | ||
5255 | module n2_l2t_sp_28kb_cust_msff_ctl_macro__width_6 ( | |
5256 | din, | |
5257 | l1clk, | |
5258 | scan_in, | |
5259 | siclk, | |
5260 | soclk, | |
5261 | dout, | |
5262 | scan_out); | |
5263 | wire [5:0] fdin; | |
5264 | wire [4:0] so; | |
5265 | ||
5266 | input [5:0] din; | |
5267 | input l1clk; | |
5268 | input scan_in; | |
5269 | ||
5270 | ||
5271 | input siclk; | |
5272 | input soclk; | |
5273 | ||
5274 | output [5:0] dout; | |
5275 | output scan_out; | |
5276 | assign fdin[5:0] = din[5:0]; | |
5277 | ||
5278 | ||
5279 | ||
5280 | ||
5281 | ||
5282 | ||
5283 | dff #(6) d0_0 ( | |
5284 | .l1clk(l1clk), | |
5285 | .siclk(siclk), | |
5286 | .soclk(soclk), | |
5287 | .d(fdin[5:0]), | |
5288 | .si({scan_in,so[4:0]}), | |
5289 | .so({so[4:0],scan_out}), | |
5290 | .q(dout[5:0]) | |
5291 | ); | |
5292 | ||
5293 | ||
5294 | ||
5295 | ||
5296 | ||
5297 | ||
5298 | ||
5299 | ||
5300 | ||
5301 | ||
5302 | ||
5303 | ||
5304 | endmodule | |
5305 | ||
5306 | ||
5307 | ||
5308 | ||
5309 | ||
5310 | ||
5311 | ||
5312 | ||
5313 | ||
5314 | ||
5315 | ||
5316 | ||
5317 | ||
5318 | // any PARAMS parms go into naming of macro | |
5319 | ||
5320 | module n2_l2t_sp_28kb_cust_msff_ctl_macro__width_4 ( | |
5321 | din, | |
5322 | l1clk, | |
5323 | scan_in, | |
5324 | siclk, | |
5325 | soclk, | |
5326 | dout, | |
5327 | scan_out); | |
5328 | wire [3:0] fdin; | |
5329 | wire [2:0] so; | |
5330 | ||
5331 | input [3:0] din; | |
5332 | input l1clk; | |
5333 | input scan_in; | |
5334 | ||
5335 | ||
5336 | input siclk; | |
5337 | input soclk; | |
5338 | ||
5339 | output [3:0] dout; | |
5340 | output scan_out; | |
5341 | assign fdin[3:0] = din[3:0]; | |
5342 | ||
5343 | ||
5344 | ||
5345 | ||
5346 | ||
5347 | ||
5348 | dff #(4) d0_0 ( | |
5349 | .l1clk(l1clk), | |
5350 | .siclk(siclk), | |
5351 | .soclk(soclk), | |
5352 | .d(fdin[3:0]), | |
5353 | .si({scan_in,so[2:0]}), | |
5354 | .so({so[2:0],scan_out}), | |
5355 | .q(dout[3:0]) | |
5356 | ); | |
5357 | ||
5358 | ||
5359 | ||
5360 | ||
5361 | ||
5362 | ||
5363 | ||
5364 | ||
5365 | ||
5366 | ||
5367 | ||
5368 | ||
5369 | endmodule | |
5370 | ||
5371 | ||
5372 | ||
5373 | ||
5374 | ||
5375 | ||
5376 | ||
5377 |