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1 | # ========== Copyright Header Begin ========================================== |
2 | # | |
3 | # OpenSPARC T2 Processor File: fpga_synth_synplicity_default.prj | |
4 | # Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | # 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | # | |
7 | # * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | # | |
9 | # This program is free software; you can redistribute it and/or modify | |
10 | # it under the terms of the GNU General Public License as published by | |
11 | # the Free Software Foundation; version 2 of the License. | |
12 | # | |
13 | # This program is distributed in the hope that it will be useful, | |
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | # GNU General Public License for more details. | |
17 | # | |
18 | # You should have received a copy of the GNU General Public License | |
19 | # along with this program; if not, write to the Free Software | |
20 | # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | # | |
22 | # For the avoidance of doubt, and except that if any non-GPL license | |
23 | # choice is available it will apply instead, Sun elects to use only | |
24 | # the General Public License version 2 (GPLv2) at this time for any | |
25 | # software where a choice of GPL license versions is made | |
26 | # available with the language indicating that GPLv2 or any later version | |
27 | # may be used, or where a choice of which version of the GPL is applied is | |
28 | # otherwise unspecified. | |
29 | # | |
30 | # Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | # CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | # have any questions. | |
33 | # | |
34 | # ========== Copyright Header End ============================================ | |
35 | ||
36 | ########default synplicity project file/template############ | |
37 | ####top defined by fpga_synth | |
38 | ####flist defined by fpga_synth | |
39 | # Add Constraints file | |
40 | ||
41 | add_file -constraint $DV_ROOT/tools/fpga/fpga_synth_synplicity_mapper.sdc | |
42 | ||
43 | #### | |
44 | ###set_option -top_module "t2" | |
45 | ||
46 | ||
47 | #simulation options | |
48 | set_option -write_verilog 1 | |
49 | ||
50 | ||
51 | #gate output dir | |
52 | impl -add t2_synth -type fpga | |
53 | ||
54 | ||
55 | #compilation/mapping options | |
56 | set_option -default_enum_encoding default | |
57 | set_option -resource_sharing 1 | |
58 | set_option -use_fsm_explorer 0 | |
59 | ||
60 | #map options | |
61 | set_option -frequency 16.000 | |
62 | set_option -run_prop_extract 1 | |
63 | set_option -fanout_limit 10000 | |
64 | set_option -disable_io_insertion 0 | |
65 | set_option -pipe 1 | |
66 | set_option -update_models_cp 0 | |
67 | set_option -enable_prepacking 1 | |
68 | set_option -retiming 0 | |
69 | set_option -no_sequential_opt 0 | |
70 | set_option -fixgatedclocks 3 | |
71 | set_option -fixgeneratedclocks 3 | |
72 | set_option -effort default | |
73 | ||
74 | ||
75 | #sequential_optimizations options | |
76 | set_option -symbolic_fsm_compiler 1 | |
77 | ||
78 | #planner options | |
79 | set_option -write_pp_verilog 1 | |
80 | set_option -write_pp_vhdl 1 | |
81 | set_option -write_pp_mixed 1 | |
82 | set_option -write_pp_srs 1 | |
83 | ||
84 | #simulation options | |
85 | set_option -write_verilog 1 | |
86 | set_option -write_vhdl 0 | |
87 | ||
88 | #VIF options | |
89 | set_option -write_vif 0 | |
90 | ||
91 | #automatic place and route (vendor) options | |
92 | set_option -write_apr_constraint 1 | |
93 | ||
94 | ############################ | |
95 | #implementation attributes | |
96 | # | |
97 | set_option -vlog_std v2001 | |
98 | set_option -dup 0 | |
99 | set_option -auto_constrain_io 1 | |
100 | set_option -project_relative_includes 1 | |
101 | set_option -enable64bit 1 | |
102 | set_option -suppress_remap 1 | |
103 |