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1 | # ========== Copyright Header Begin ========================================== |
2 | # | |
3 | # OpenSPARC T2 Processor File: fpga_synth,1.0 | |
4 | # Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | # 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | # | |
7 | # * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | # | |
9 | # This program is free software; you can redistribute it and/or modify | |
10 | # it under the terms of the GNU General Public License as published by | |
11 | # the Free Software Foundation; version 2 of the License. | |
12 | # | |
13 | # This program is distributed in the hope that it will be useful, | |
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | # GNU General Public License for more details. | |
17 | # | |
18 | # You should have received a copy of the GNU General Public License | |
19 | # along with this program; if not, write to the Free Software | |
20 | # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | # | |
22 | # For the avoidance of doubt, and except that if any non-GPL license | |
23 | # choice is available it will apply instead, Sun elects to use only | |
24 | # the General Public License version 2 (GPLv2) at this time for any | |
25 | # software where a choice of GPL license versions is made | |
26 | # available with the language indicating that GPLv2 or any later version | |
27 | # may be used, or where a choice of which version of the GPL is applied is | |
28 | # otherwise unspecified. | |
29 | # | |
30 | # Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | # CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | # have any questions. | |
33 | # | |
34 | # ========== Copyright Header End ============================================ | |
35 | #!/usr/bin/perl | |
36 | ||
37 | use Cwd; | |
38 | ||
39 | sub Help; | |
40 | sub tee_stdout; | |
41 | ||
42 | $version="1.4"; | |
43 | MAIN: | |
44 | { | |
45 | #// Help | |
46 | if($#ARGV==-1){Help;exit(-1);} | |
47 | ||
48 | #// Parsing arguments | |
49 | my $filelist; | |
50 | my $user_compile_dir; | |
51 | my $synthesis_tool; | |
52 | my $top="t2"; | |
53 | my $device="XC5VLX330"; | |
54 | my $project_file; | |
55 | my $no_run=0; | |
56 | my $clean=0; | |
57 | my $help=0; | |
58 | my $result_output_dir = "t2_synth" ; | |
59 | ||
60 | open(LOG,">fpga_synth.log") ; | |
61 | ||
62 | printf LOG ("Running fpga_synth version $version .... \n"); | |
63 | printf LOG ("\n"); | |
64 | printf LOG ("fpga_synth @ARGV \n"); | |
65 | printf LOG ("\t.....\n"); | |
66 | ||
67 | for(my $i=0;$i<$#ARGV+1;$i++) | |
68 | { | |
69 | if($ARGV[$i] eq "-f") | |
70 | { | |
71 | if($i==$#ARGV){printf (" Missing value for: %s\n",$ARGV[$i]);exit(-1);} | |
72 | $filelist=$ARGV[$i+1]; | |
73 | $i++; | |
74 | } | |
75 | ||
76 | elsif($ARGV[$i] eq "-user_compile_dir") | |
77 | { | |
78 | if($i==$#ARGV){printf(" Missing value for: %s\n",$ARGV[$i]);exit(-1);} | |
79 | $user_compile_dir=$ARGV[$i+1]; | |
80 | $i++; | |
81 | } | |
82 | ||
83 | elsif($ARGV[$i] eq "-synplicity") | |
84 | { | |
85 | $synthesis_tool="synplicity"; | |
86 | } | |
87 | ||
88 | elsif($ARGV[$i] eq "-top") | |
89 | { | |
90 | if($i==$#ARGV){printf(" Missing value for: %s\n",$ARGV[$i]);exit(-1);} | |
91 | $top=$ARGV[$i+1]; | |
92 | $i++; | |
93 | } | |
94 | ||
95 | elsif($ARGV[$i] eq "-device") | |
96 | { | |
97 | if($i==$#ARGV){printf(" Missing value for: %s\n",$ARGV[$i]);exit(-1);} | |
98 | $device=$ARGV[$i+1]; | |
99 | $i++; | |
100 | } | |
101 | ||
102 | elsif($ARGV[$i] eq "-project_file") | |
103 | { | |
104 | if($i==$#ARGV){printf(" Missing value for: %s\n",$ARGV[$i]);exit(-1);} | |
105 | $project_file = $ARGV[$i+1]; | |
106 | $i++; | |
107 | } | |
108 | ||
109 | elsif($ARGV[$i] eq "-no_run") | |
110 | { | |
111 | $no_run=1; | |
112 | } | |
113 | ||
114 | elsif($ARGV[$i] eq "-clean") | |
115 | { | |
116 | $clean=1; | |
117 | } | |
118 | ||
119 | elsif($ARGV[$i] eq "-h") | |
120 | { | |
121 | Help; | |
122 | exit(-1); | |
123 | } | |
124 | ||
125 | else | |
126 | { | |
127 | printf(" Invalid argument: %s\n",$ARGV[$i]); | |
128 | exit(-1); | |
129 | } | |
130 | } | |
131 | ||
132 | ||
133 | if(length($filelist)==0) | |
134 | { | |
135 | if($clean == 0) { | |
136 | printf("Using the default flist , $ENV{DV_ROOT}/design/fpga/rtl/fpga_rtl_synth.flist .\n\n"); | |
137 | printf LOG ("Using the default flist , $ENV{DV_ROOT}/design/fpga/rtl/fpga_rtl_synth.flist .\n\n"); } | |
138 | printf LOG ("\t.....\n"); | |
139 | $filelist="$ENV{DV_ROOT}/design/fpga/rtl/fpga_rtl_synth.flist"; | |
140 | } | |
141 | ||
142 | if(length($user_compile_dir)==0) | |
143 | { | |
144 | if($clean == 0) { | |
145 | printf("Using the default compile dir, $ENV{MODEL_DIR}/fpga_synth .\n\n"); | |
146 | printf LOG ("Using the default compile dir, $ENV{MODEL_DIR}/fpga_synth .\n\n"); } | |
147 | printf LOG ("\t.....\n"); | |
148 | $user_compile_dir="$ENV{MODEL_DIR}/fpga_synth"; | |
149 | } | |
150 | ||
151 | if($clean==1) | |
152 | { | |
153 | system("rm -Rf $user_compile_dir"); | |
154 | exit(0); | |
155 | } | |
156 | ||
157 | if(length($synthesis_tool)==0) | |
158 | { | |
159 | printf(" ERROR: Please specify a synthesis tool.\n\n"); | |
160 | exit(-1); | |
161 | } | |
162 | ||
163 | if(length($ENV{DV_ROOT})==0) | |
164 | { | |
165 | printf(" ERROR: Please set env variable DV_ROOT.\n"); | |
166 | exit(-1); | |
167 | } | |
168 | ||
169 | if(length($ENV{SYNP_HOME})==0 && no_run==0) | |
170 | { | |
171 | printf(" ERROR: Please set env variable SYNP_HOME.\n"); | |
172 | exit(-1); | |
173 | } | |
174 | ||
175 | ||
176 | system("mkdir -p $user_compile_dir"); | |
177 | ||
178 | chdir "$user_compile_dir" or die "Can't access $user_compile_dir"; | |
179 | ||
180 | $result_dir = cwd() ; | |
181 | ||
182 | if(length($project_file)==0) | |
183 | { | |
184 | $project_file="fpga_synth_${synthesis_tool}.prj"; | |
185 | $import_verilog = "import_verilog_${synthesis_tool}.prj"; | |
186 | ||
187 | open g2, ">${import_verilog}" or die "File creation error: ${import_verilog}"; | |
188 | ||
189 | open f1 ,"<${filelist}"; | |
190 | @list = <f1> ; | |
191 | foreach $elem (@list) { | |
192 | $_ = $elem ; | |
193 | chomp ; | |
194 | s/\s*-v\s+// ; | |
195 | s/\s+//; | |
196 | next if (/^\/\//); | |
197 | $elem = $_ ; | |
198 | ||
199 | if($elem =~m/\+incdir\+/) { | |
200 | $_ = $elem ; | |
201 | s/\+incdir\+// ; | |
202 | $elem = $_ ; | |
203 | print g2 "set_option -library_path \"$elem\" \n" ; | |
204 | } | |
205 | elsif ($elem =~m/\+define\+/){ | |
206 | $_ = $elem ; | |
207 | s/\+define\+//g; | |
208 | $elem = $_ ; | |
209 | push(@defines,$elem) ; | |
210 | } | |
211 | else { | |
212 | push(@vfiles,$elem) ; | |
213 | } | |
214 | } | |
215 | ||
216 | print g2 "hdl_define -set \"@defines\" \n"; | |
217 | foreach $elem2 (@vfiles) { | |
218 | print g2 "add_file -verilog \"$elem2\" \n" ; | |
219 | } | |
220 | close g2 ; | |
221 | ||
222 | open g, ">${project_file}" or die "File creation error: ${project_file}"; | |
223 | print g "set DV_ROOT [get_env DV_ROOT]\n"; | |
224 | print g "set_option -top_module \"${top}\"\n"; | |
225 | print g "project -result_file \"t2_synth\/${top}.edf\"\n"; | |
226 | print g "project -log_file \"${top}.srr\"\n"; | |
227 | print g "\n"; | |
228 | print g "source import_verilog_${synthesis_tool}.prj\n" ; | |
229 | print g "source \$DV_ROOT/tools/fpga/fpga_synth_synplicity_default.prj\n" ; | |
230 | if (-e "$ENV{DV_ROOT}/tools/fpga/${device}.prj") | |
231 | { | |
232 | print g "source \$DV_ROOT/tools/fpga/${device}.prj\n"; | |
233 | } | |
234 | close g; | |
235 | ||
236 | } | |
237 | ||
238 | printf LOG ("Created ${project_file} in $result_dir \n"); | |
239 | printf LOG ("\t.....\n"); | |
240 | ||
241 | open g, ">run.script" or die "File creation error: run.script"; | |
242 | print g "\$SYNP_HOME/bin/synplify_pro -batch ${project_file}\n"; | |
243 | close g; | |
244 | system("chmod 0755 run.script"); | |
245 | ||
246 | open g3, ">fpga_gate.flist" or die "File creation error: fpga_gate.flist"; | |
247 | ||
248 | print g3 "\$DV_ROOT/design/fpga/opencores/timescale.v\n" ; | |
249 | print g3 "$result_dir/t2_synth/${top}.vm\n" ; | |
250 | close g3 ; | |
251 | ||
252 | system ("cat $ENV{DV_ROOT}/design/fpga/gate/fpga_gate_tb.flist >> fpga_gate.flist") ; | |
253 | system ("cat $ENV{DV_ROOT}/design/fpga/gate/xilinx_lib.flist >> fpga_gate.flist") ; | |
254 | ||
255 | printf LOG ("Created fpga_gate.flist in $result_dir \n"); | |
256 | printf LOG ("\t.....\n"); | |
257 | printf LOG ("Linking the fpga gate flist to $DV_ROOT/design/fpga/gate/fpga_gate_master.flist \n"); | |
258 | ||
259 | if(-e "$ENV{DV_ROOT}/design/fpga/gate/fpga_gate_master.flist") { | |
260 | system ("rm -Rf $ENV{DV_ROOT}/design/fpga/gate/fpga_gate_master.flist") | |
261 | } ; | |
262 | ||
263 | system ("ln -fs $result_dir/fpga_gate.flist $ENV{DV_ROOT}/design/fpga/gate/fpga_gate_master.flist") ; | |
264 | ||
265 | if($no_run==0) | |
266 | { | |
267 | printf LOG ("\n"); | |
268 | printf LOG ("Running the synthesis script ...\n"); | |
269 | printf LOG ("\t.....\n"); | |
270 | system("./run.script"); | |
271 | } | |
272 | ||
273 | ||
274 | exit(0); | |
275 | } | |
276 | ||
277 | ||
278 | #+-------------+ | |
279 | #| Help menu | | |
280 | #+-------------+ | |
281 | sub Help | |
282 | { | |
283 | printf("fpga_synth -version $version\n"); | |
284 | printf("----------\n"); | |
285 | printf("Utility to synthesize T2 system level environment for FPGA \n"); | |
286 | printf(" -f <flist> : optional, file list , default $DV_ROOT/design/fpga/rtl/fpga_rtl_synth.flist \n"); | |
287 | printf(" -user_compile_dir <dir> : optional, user specified dir , default \$MODEL_DIR/fpga_synth \n"); | |
288 | printf(" -synplicity : required, synthesis tool to use, uses synplify pro\n"); | |
289 | printf(" -top <module> : optional, top module, default t2 \n"); | |
290 | printf(" -device <keyword> : optional, FPGA device, default LX330\n"); | |
291 | printf(" -project_file <file> : optional, user specified project file\n"); | |
292 | printf(" -no_run : optional, does not run synthesis, generates run.script only\n"); | |
293 | printf(" -clean : optional, removes temp directories/files\n"); | |
294 | printf(" -h : optional, help\n"); | |
295 | } | |
296 | ||
297 |