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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / tools / src / nas,5.n2.os.2 / pfe / samfe / RegisterMap.py
CommitLineData
86530b38
AT		 1"""map ni-simics register name to riesling counterpart
2"""
3
4"""
5A reg is an integer register name. It can have any of the following values:
6%r0-%r31
7%g0-%g7 (global registers; same as %r0-%r7)
8%o0-%o7 (out registers; same as %r8-%r15)
9%l0-%l7 (local registers; same as %r16-%r23)
10%i0-%i7 (in registers; same as %r24-%r31)
11%fp (frame pointer; conventionally same as %i6)
12%sp (stack pointer; conventionally same as %o6)
13"""
14
15LEVEL_SYS = 0
16LEVEL_CPU = 1
17LEVEL_CORE = 2
18LEVEL_UCORE = 3
19LEVEL_STRAND = 4
20
21class RegisterMap:
22 """
23 """
24
25 def __init__ (self,arch):
26 """
27 """
28 # maintain a mapping between register names used by this
29 # front end, and the common lower level layer name.
30
31 self.regMap = { }
32 self.regMapArch = {}
33 self.regMapAsi = {}
34
35 self.__regMapN2__ = {}
36
37 self.regMap['g0'] = ['g0',0]
38 self.regMap['g1'] = ['g1',1]
39 self.regMap['g2'] = ['g2',2]
40 self.regMap['g3'] = ['g3',3]
41 self.regMap['g4'] = ['g4',4]
42 self.regMap['g5'] = ['g5',5]
43 self.regMap['g6'] = ['g6',6]
44 self.regMap['g7'] = ['g7',7]
45 self.regMap['o0'] = ['o0',8]
46 self.regMap['o1'] = ['o1',9]
47 self.regMap['o2'] = ['o2',10]
48 self.regMap['o3'] = ['o3',11]
49 self.regMap['o4'] = ['o4',12]
50 self.regMap['o5'] = ['o5',13]
51 self.regMap['o6'] = ['o6',14]
52 self.regMap['o7'] = ['o7',15]
53 self.regMap['l0'] = ['l0',16]
54 self.regMap['l1'] = ['l1',17]
55 self.regMap['l2'] = ['l2',18]
56 self.regMap['l3'] = ['l3',19]
57 self.regMap['l4'] = ['l4',20]
58 self.regMap['l5'] = ['l5',21]
59 self.regMap['l6'] = ['l6',22]
60 self.regMap['l7'] = ['l7',23]
61 self.regMap['i0'] = ['i0',24]
62 self.regMap['i1'] = ['i1',25]
63 self.regMap['i2'] = ['i2',26]
64 self.regMap['i3'] = ['i3',27]
65 self.regMap['i4'] = ['i4',28]
66 self.regMap['i5'] = ['i5',29]
67 self.regMap['i6'] = ['i6',30]
68 self.regMap['i7'] = ['i7',31]
69 self.regMap['pc'] = ['pc',32]
70 self.regMap['npc'] = ['npc',33]
71 self.regMap['y'] = ['y',34]
72 self.regMap['ccr'] = ['ccr',35]
73 self.regMap['fprs'] = ['fprs',36]
74 self.regMap['fsr'] = ['fsr',37]
75 self.regMap['asi'] = ['asi',38]
76 self.regMap['tick'] = ['tick',39]
77 self.regMap['gsr'] = ['gsr',40]
78 self.regMap['tick_cmpr'] = ['tick_cmpr',41]
79 # in Ni/N2 stick is an alias of tick, but archState has separate
80 # variable for each. N2_InstrEmu has stick_ = tick_ so change to
81 # either one will actually change ONLY tick, stick remains 0 always.
82 #self.regMap['stick'] = (42,LEVEL_STRAND,)
83 self.regMap['stick'] = ['stick',42]
84 self.regMap['stick_cmpr'] = ['stick_cmpr',43]
85 self.regMap['pstate'] = ['pstate',44]
86 self.regMap['tl'] = ['tl',45]
87 self.regMap['pil'] = ['pil',46]
88 self.regMap['tpc1'] = ['t[1].tpc',47]
89 self.regMap['tpc2'] = ['t[2].tpc',48]
90 self.regMap['tpc3'] = ['t[3].tpc',49]
91 self.regMap['tpc4'] = ['t[4].tpc',50]
92 self.regMap['tpc5'] = ['t[5].tpc',51]
93 # self.regMap['tpc6'] = ['t[6].tpc',52]
94 self.regMap['tnpc1'] = ['t[1].tnpc',57]
95 self.regMap['tnpc2'] = ['t[2].tnpc',58]
96 self.regMap['tnpc3'] = ['t[3].tnpc',59]
97 self.regMap['tnpc4'] = ['t[4].tnpc',60]
98 self.regMap['tnpc5'] = ['t[5].tnpc',61]
99 # self.regMap['tnpc6'] = ['t[6].tnpc',61] XXX aborts
100 self.regMap['tstate1'] = ['t[1].tstate',67]
101 self.regMap['tstate2'] = ['t[2].tstate',68]
102 self.regMap['tstate3'] = ['t[3].tstate',69]
103 self.regMap['tstate4'] = ['t[4].tstate',70]
104 self.regMap['tstate5'] = ['t[5].tstate',71]
105 # self.regMap['tstate6'] = ['t[6].tstate',72] XXX aborts on this read
106 self.regMap['tt1'] = ['t[1].tt',77]
107 self.regMap['tt2'] = ['t[2].tt',78]
108 self.regMap['tt3'] = ['t[3].tt',79]
109 self.regMap['tt4'] = ['t[4].tt',80]
110 self.regMap['tt5'] = ['t[5].tt',81]
111 # self.regMap['tt6'] = ['t[6].tt',82]
112 self.regMap['tba'] = ['tba',87]
113 self.regMap['ver'] = ['hver',88]
114 self.regMap['cwp'] = ['cwp',89]
115 self.regMap['cansave'] = ['cansave',90]
116 self.regMap['canrestore'] = ['canrestore',91]
117 self.regMap['otherwin'] = ['otherwin',92]
118 self.regMap['wstate'] = ['wstate',93]
119 self.regMap['cleanwin'] = ['cleanwin',94]
120 self.regMap['softint'] = ['softint',95]
121 self.regMap['gl'] = ['gl',107]
122 self.regMap['hpstate'] = ['hpstate',108]
123 self.regMap['htstate1'] = ['t[1].htstate',109]
124 self.regMap['htstate2'] = ['t[2].htstate',110]
125 self.regMap['htstate3'] = ['t[3].htstate',111]
126 self.regMap['htstate4'] = ['t[4].htstate',112]
127 self.regMap['htstate5'] = ['t[5].htstate',113]
128 # self.regMap['htstate6'] = ['t[6].htstate',114] XXX aborts on this read
129 self.regMap['htba'] = ['htba',119]
130 self.regMap['hintp'] = ['hintp',120]
131 self.regMap['hstick_cmpr'] = ['hstick_cmpr',121]
132 self.regMap['fp'] = ['i6',30]
133 self.regMap['sp'] = ['o6',14]
134
135 # these seem to be N2 specific regs.
136 # support is absent in the back end.
137 self.__regMapN2__['ecache_error_enable'] = ['',96]
138 self.__regMapN2__['asynchronous_fault_status'] = ['',97]
139 self.__regMapN2__['asynchronous_fault_address'] = ['',99]
140 self.__regMapN2__['out_intr_data0'] = ['',99]
141 self.__regMapN2__['out_intr_data1'] = ['',100]
142 self.__regMapN2__['out_intr_data2'] = ['',101]
143 self.__regMapN2__['intr_dispatch_status'] = ['',102]
144 self.__regMapN2__['in_intr_data0'] = ['',103]
145 self.__regMapN2__['in_intr_data1'] = ['',104]
146 self.__regMapN2__['in_intr_data2'] = ['',105]
147 self.__regMapN2__['intr_receive'] = ['',106]
148 self.__regMapN2__['tpc6'] = ['t[6].tpc',52]
149 self.__regMapN2__['tnpc6'] = ['t[6].tnpc',62]
150 self.__regMapN2__['tstate6'] = ['t[6].tstate',72]
151 self.__regMapN2__['tt6'] = ['t[6].tt',82]
152 self.__regMapN2__['htstate6'] = ['t[6].htstate',114]
153
154 # asi related registers. All the cmp and mmu related registers
155 # start wil CMP_ & MMU_ respectively. Maintain the same convention
156 # if/when adding new registers.
157 # format dir[regname] = [asi,va]
158 self.__asiRegMapN2__ = {}
159 #####################################################
160 N2_ASI_CMP = 0x41
161 N2_ASI_CMP_CORE_ID = 0x63
162 N2_ASI_CMP_CORE_INTR_ID = 0x63
163 N2_ASI_SCRATCHPAD = 0x20
164 N2_ASI_INTR_RECEIVE = 0x72
165 N2_ASI_INTR_W = 0x73
166 N2_ASI_INTR_R = 0x74
167
168 self.__asiRegMapN2__['CMP_core_available'] = [N2_ASI_CMP,0x0]
169 self.__asiRegMapN2__['CMP_core_enable_status'] = [N2_ASI_CMP,0x10]
170 self.__asiRegMapN2__['CMP_core_enable'] = [N2_ASI_CMP,0x20]
171 self.__asiRegMapN2__['CMP_xir_steering'] = [N2_ASI_CMP,0x30]
172 self.__asiRegMapN2__['CMP_tick_enable'] = [N2_ASI_CMP,0x38]
173 self.__asiRegMapN2__['CMP_running'] = [N2_ASI_CMP,0x50]
174 self.__asiRegMapN2__['CMP_running_status'] = [N2_ASI_CMP,0x58]
175 self.__asiRegMapN2__['CMP_core_id'] = [N2_ASI_CMP_CORE_ID,0x0]
176 self.__asiRegMapN2__['CMP_core_intr_id'] = [N2_ASI_CMP_CORE_INTR_ID,0x10]
177 self.__asiRegMapN2__['scratch-pad0'] = [N2_ASI_SCRATCHPAD,0x0]
178 self.__asiRegMapN2__['scratch-pad1'] = [N2_ASI_SCRATCHPAD,0x10]
179 self.__asiRegMapN2__['scratch-pad2'] = [N2_ASI_SCRATCHPAD,0x18]
180 self.__asiRegMapN2__['scratch-pad3'] = [N2_ASI_SCRATCHPAD,0x20]
181 self.__asiRegMapN2__['scratch-pad4'] = [N2_ASI_SCRATCHPAD,0x30]
182 self.__asiRegMapN2__['intr_recv_reg'] = [N2_ASI_INTR_RECEIVE,0x0]
183 self.__asiRegMapN2__['intr_incoming_reg'] = [N2_ASI_INTR_R,0x0]
184 self.__asiRegMapN2__['MMU_ID_PRIMARY_CTXT_REG_0'] = [0x21,0x8]
185 self.__asiRegMapN2__['MMU_D_SCNDRY_CTXT_REG_0'] = [0x21,0x10]
186 self.__asiRegMapN2__['MMU_ID_PRIMARY_CTXT_REG_1'] = [0x21,0x108]
187 self.__asiRegMapN2__['MMU_D_SCNDRY_CTXT_REG_1'] = [0x21,0x110]
188 self.__asiRegMapN2__['MMU_LSU_CONTROL'] = [0x45,0x0]
189 self.__asiRegMapN2__['MMU_ITSB_TAG_TARGET'] = [0x50,0x0]
190 self.__asiRegMapN2__['MMU_ISFSR'] = [0x50,0x18]
191 self.__asiRegMapN2__['MMU_ITLB_TAG_ACCESS'] = [0x50,0x30]
192 self.__asiRegMapN2__['MMU_IMMU_VA_WATCHPOINT'] = [0x50,0x38]
193 self.__asiRegMapN2__['MMU_MRA_ACCESS'] = [0x51,0x0]
194 self.__asiRegMapN2__['MMU_REAL_RANGE_0'] = [0x52,0x108]
195 self.__asiRegMapN2__['MMU_REAL_RANGE_1'] = [0x52,0x110]
196 self.__asiRegMapN2__['MMU_REAL_RANGE_2'] = [0x52,0x118]
197 self.__asiRegMapN2__['MMU_REAL_RANGE_3'] = [0x52,0x120]
198 self.__asiRegMapN2__['MMU_PHYSICAL_OFFSET_0'] = [0x52,0x208]
199 self.__asiRegMapN2__['MMU_PHYSICAL_OFFSET_1'] = [0x52,0x210]
200 self.__asiRegMapN2__['MMU_PHYSICAL_OFFSET_2'] = [0x52,0x218]
201 self.__asiRegMapN2__['MMU_PHYSICAL_OFFSET_3'] = [0x52,0x220]
202 self.__asiRegMapN2__['MMU_ZERO_CONTEXT_TSB_CONFIG_0'] = [0x54,0x10]
203 self.__asiRegMapN2__['MMU_ZERO_CONTEXT_TSB_CONFIG_1'] = [0x54,0x18]
204 self.__asiRegMapN2__['MMU_ZERO_CONTEXT_TSB_CONFIG_2'] = [0x54,0x20]
205 self.__asiRegMapN2__['MMU_ZERO_CONTEXT_TSB_CONFIG_3'] = [0x54,0x28]
206 self.__asiRegMapN2__['MMU_NONZERO_CONTEXT_TSB_CONFIG_0'] = [0x54,0x30]
207 self.__asiRegMapN2__['MMU_NONZERO_CONTEXT_TSB_CONFIG_1'] = [0x54,0x38]
208 self.__asiRegMapN2__['MMU_NONZERO_CONTEXT_TSB_CONFIG_2'] = [0x54,0x40]
209 self.__asiRegMapN2__['MMU_NONZERO_CONTEXT_TSB_CONFIG_3'] = [0x54,0x48]
210 self.__asiRegMapN2__['MMU_ITSB_PTR_0'] = [0x54,0x50]
211 self.__asiRegMapN2__['MMU_ITSB_PTR_1'] = [0x54,0x58]
212 self.__asiRegMapN2__['MMU_ITSB_PTR_2'] = [0x54,0x60]
213 self.__asiRegMapN2__['MMU_ITSB_PTR_3'] = [0x54,0x68]
214 self.__asiRegMapN2__['MMU_DTSB_PTR_0'] = [0x54,0x70]
215 self.__asiRegMapN2__['MMU_DTSB_PTR_1'] = [0x54,0x78]
216 self.__asiRegMapN2__['MMU_DTSB_PTR_2'] = [0x54,0x80]
217 self.__asiRegMapN2__['MMU_DTSB_PTR_3'] = [0x54,0x88]
218 self.__asiRegMapN2__['MMU_PENDING_TABLEWALK_CONTROL'] = [0x54,0x90]
219 self.__asiRegMapN2__['MMU_PENDING_TABLEWALK_STATUS'] = [0x54,0x98]
220 for i in range(0x0,0x200,0x8):
221 self.__asiRegMapN2__['MMU_ITLB_DATA_ACCESS_REG_%X' % (i,)] = [0x55,i]
222 for i in range(0x0,0x200,0x8):
223 self.__asiRegMapN2__['MMU_ITLB_TAG_READ_REG_%X' % (i,)] = [0x56,i]
224 self.__asiRegMapN2__['MMU_DTSB_TAG_TARGET'] = [0x58,0x0]
225 self.__asiRegMapN2__['MMU_DSFSR'] = [0x58,0x18]
226 self.__asiRegMapN2__['MMU_DSFAR'] = [0x58,0x20]
227 self.__asiRegMapN2__['MMU_DTLB_TAG_ACCESS'] = [0x58,0x30]
228 self.__asiRegMapN2__['MMU_DMMU_WATCHPOINT'] = [0x58,0x38]
229 self.__asiRegMapN2__['MMU_HWTW_CONFIG'] = [0x58,0x40]
230 self.__asiRegMapN2__['MMU_PARTITION_ID'] = [0x58,0x80]
231 for i in range(0x0,0x800,0x8):
232 self.__asiRegMapN2__['MMU_DTLB_DATA_ACCESS_REG_%X' % (i,)] = [0x5d,i]
233 for i in range(0x0,0x800,0x8):
234 self.__asiRegMapN2__['MMU_DTLB_TAG_READ_REG_%X' % (i,)] = [0x5e,i]
235 #####################################################
236
237 #####################################################
238
239 #####################################################
240
241 # assign to regMapArch and asiRegMap based upon the
242 # architecture being simulated
243 if arch == 'n2':
244 self.regMapArch = self.__regMapN2__
245 self.asiRegMap = self.__asiRegMapN2__
246 else:
247 self.regMapArch = None
248 self.asiRegMap = None
249
250
251 def key2id(self,key):
252 if self.regMap.has_key(key):
253 return self.regMap[key][1]
254 elif self.regMapArch.has_key(key):
255 return self.regMapArch[key][1]
256 else:
257 return -1
258
259 def id2key(self,id):
260 """ return the Back end name for register id
261 """
262 for reg in self.regMap.keys():
263 if self.regMap[reg][1] == id:
264 return self.regMap[reg][0]
265
266 for reg in self.regMapArch.keys():
267 if self.regMapArch[reg][1] == id:
268 return self.regMapArch[reg][0]
269
270 return ''
271
272
273 def hasReg(self, name):
274 if self.regMap.has_key(name):
275 return True
276 elif self.regMapArch.has_key(name):
277 return True
278 else:
279 return False
280
281
282 def feName2beName(self,feName):
283 if self.regMap.has_key(feName):
284 return self.regMap[feName][0]
285 elif self.regMapArch.has_key(feName):
286 return self.regMapArch[feName][0]
287 else:
288 return ''
289
Full OpenSPARC design & verification tarball including full HDL.