[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / Drc_Mcu_Io_err.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: Drc_Mcu_Io_err.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"
#include "niu_defines.h"


#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_SADDR      0xfffc000022000000
#define DMA_DATA_BYP_ADDR1      0xfffc000123456700
#define DMA_DATA_BYP_ADDR2      0xfffc000123456780
#define DMA_DATA_BYP_ADDR3      0xfffc000123456800
#define  DRAM_ERR_INJ_REG_0               0x8400000290
#define  DRAM_ERR_INJ_REG_1               0x8400001290
#define  DRAM_ERR_INJ_REG_2               0x8400002290
#define  DRAM_ERR_INJ_REG_3               0x8400003290
#define  L2_ENTRY_PA        0xa000000000


#define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) |IO_ACCESS_PA)

    
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

set_Soc_err_inj_reg:
        set     0x1, %i1
	setx    0x800001248c80040c,%i1,%i2
        setx    SOC_EJR_REG, %l7, %i3
        stx     %i2, [%i3]
        membar  0x40

disable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove bit 2
  andn  %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

set_L2_Direct_Mapped_Mode:
  set   0x80, %l1
  set   0x100,%l2
  set   0x180, %l3
  setx  L2CS_PA0, %l6, %g1      ! Bit 1 in L2 Control Status Register
  add   %g1,%l1,%g2
  add   %g1,%l2,%g3
  add   %g1,%l3,%g4
  mov   0x2, %l0
  stx   %l0, [%g1]
  stx   %l0, [%g2]
  stx   %l0, [%g3]
  stx   %l0, [%g4]


set_DRAM_err_cnt_reg:
  mov  0x1,%l2
  setx  DRAM_ERR_CNT_REG_PA_0,%l1,%g6
  setx  DRAM_ERR_CNT_REG_PA_1,%l1,%g3
  setx  DRAM_ERR_CNT_REG_PA_2,%l1,%g4
  setx  DRAM_ERR_CNT_REG_PA_3,%l1,%g5
  stx   %l2, [%g3]
  stx   %l2, [%g4]
  stx   %l2, [%g5]
  stx   %l2, [%g6]
  membar 0x40

set_DRAM_fbr_count_reg:
        set     0x10000, %g6            !<16>=countone=1
        setx    DRAM_FBR_CNT_REG_PA_0, %l7, %o2
        setx    DRAM_FBR_CNT_REG_PA_1, %l7, %o3
        setx    DRAM_FBR_CNT_REG_PA_2, %l7, %o4
        setx    DRAM_FBR_CNT_REG_PA_3, %l7, %o5
        stx     %g6, [%o2]
        stx     %g6, [%o3]
        stx     %g6, [%o4]
        stx     %g6, [%o5]
        ldx     [%o2], %i1
        ldx     [%o3], %i2
        ldx     [%o4], %i3
        ldx     [%o5], %i4


set_DRAM_error_inject_ch0_dac:
  mov   0x2, %l1                ! ECC Mask (1-bit error)
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_SSHOT, %l3
  or    %l1, %l3, %l1           ! Set single shot ;
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_ENB, %l3
  or    %l1, %l3, %l1           ! Enable error injection for the next write
  setx  DRAM_ERR_INJ_REG_0, %l3, %g3
  setx  DRAM_ERR_INJ_REG_1, %l3, %g4
  setx  DRAM_ERR_INJ_REG_2, %l3, %g5
  setx  DRAM_ERR_INJ_REG_3, %l3, %g6
  stx   %l1, [%g3]
  stx   %l1, [%g4]
  stx   %l1, [%g5]
  stx   %l1, [%g6]
  membar 0x40


store_to_L2_way0_dac:
  set  0x55555555,  %l0
  set  0x22000000,  %g7  ! bits [21:18] select way
  set   0x80, %l1
  set   0x100,%l2
  set   0x180, %l3
  add   %g7,%l1,%g2
  add   %g7,%l2,%g3
  add   %g7,%l3,%g4
  stx   %l0, [%g2]
  membar #Sync
  stx   %l0, [%g3]
  membar #Sync
  stx   %l0, [%g4]
  membar #Sync
  stx   %l0, [%g7]
  membar #Sync

! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0_dac:
  set  0x80,%l1
  set  0x31000000, %i3 ! bits [21:18] select way
  add   %i3,%l1,%i2
  add   %i2,%l1,%i7
  add   %i7,%l1,%i4
  stx %g5, [%i2]
  stx %g5, [%i3]
  stx %g5, [%i4]
  stx %g5, [%i7]
  membar #Sync

XmtUsrEvnt_drc:
        nop         ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt_drc)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_SADDR, "64'h40", 1, *, * )


read_error_address0_dac:
 ldx   [%g2], %l0
 ldx   [%g3], %l1
 ldx   [%g4], %l2
 ldx   [%g7], %l3
  membar #Sync

read_error_address1_dac:
 ldx   [%g2], %l0
 ldx   [%g3], %l1
 ldx   [%g4], %l2
 ldx   [%g7], %l3
  membar #Sync


read_error_address2_dac:
 ldx   [%g2], %l0
 ldx   [%g3], %l1
 ldx   [%g4], %l2
 ldx   [%g7], %l3
  membar #Sync


set_inj_err_src_reg_fbr:
        set     0x3, %g1
        setx    DRAM_FBD_INJ_ERR_SRC_REG_PA_0,%l7, %g3
        setx    DRAM_FBD_INJ_ERR_SRC_REG_PA_1,%l7, %g4
        setx    DRAM_FBD_INJ_ERR_SRC_REG_PA_2,%l7, %g5
        setx    DRAM_FBD_INJ_ERR_SRC_REG_PA_3,%l7, %g6
        stx     %g1, [%g3]
        stx     %g1, [%g4]
        stx     %g1, [%g5]
        stx     %g1, [%g6]
        membar 0x40


      ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

XmtUsrEvnt1: nop;
        ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h20", 1 )
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3


        ! select a CSR in the PIU and transmit the command to NCU

        setx    FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2
set    0x020, %g4

delay_loop_soc:
        ldx     [%g2], %g5
        nop
        nop
        nop
        nop
        dec     %g4
        brnz    %g4, delay_loop_soc
        nop

pio:
        ! select an IO address in PCI address range and transmit the command to NCU
        setx IO_RD_ADDR, %g1, %g2

        ! load byte - all byte offsets within an octlet
        ldub [%g2 + 1*8 + 0], %l0

        set    0x40, %g4
delay_loop_pio:
        nop
        nop
        nop
        nop
        dec     %g4
        brnz    %g4, delay_loop_pio
        nop


Init_flow:
        nop                     ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)

P_TxDMAActivate:
        setx    MAC_ID, %g1, %o0                        ! 1st Parameter
        setx    SetTxDMAActive_list, %g1, %o1           ! 2st parameter
        call    SetTxDMAActive
        nop                                             ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)

P_AddTxChannels :
        nop                                             ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)

        setx    LDGIMGN, %g1, %g2


        ldxa    [%g2]ASI_PRIMARY_LITTLE, %g5            ! Just for delay
        nop

P_SetTxMaxBurst :
        setx    NIU_TxDmaNo,    %g1, %o0                ! 1st parameter :
        setx    SetTxMaxBurst_Data, %g1, %o1            ! 2nd parameter
        call    SetTxMaxBurst
        nop                                             ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)

        ldxa    [%g2]ASI_PRIMARY_LITTLE, %g5            ! Just for delay
        nop

P_InitTxDma:
        setx    NIU_TxDmaNo,    %g1, %o0                ! 1st parameter :
        nop                                             ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
        call    InitTxDma
        nop

        ldxa    [%g2]ASI_PRIMARY_LITTLE, %g5            ! Just for delay
        nop


Gen_Packet:
        nop                     ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT,0,0)
        nop

        setx    0x5, %g1, %g4
delay_loop_tmp:
        ldxa    [%g2]ASI_PRIMARY_LITTLE, %g5
        nop
        nop
        nop
        nop
        dec     %g4
        brnz    %g4, delay_loop_tmp
        nop


SetTxRingKick:
        setx    NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2           ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
        setx    NIU_TxDmaNo,    %g1, %o0
        ldx    [%g2], %g3
        nop
        mulx     %o0, 0x200, %g5
        setx    TX_RING_KICK_Addr, %g1, %g2
        add     %g2, %g5, %g2
        stxa    %g3, [%g2]ASI_PRIMARY_LITTLE
        nop

SetTxCs :
        setx    NIU_TxDmaNo,    %g1, %o0
        setx    TX_CS_Data, %g1, %g3
        mulx     %o0, 0x200, %g5
        setx    TX_CS_Addr, %g1, %g2
        add     %g2, %g5, %g2
        stxa    %g3, [%g2]ASI_PRIMARY_LITTLE
        nop

NIUTx_Pkt_Cnt_Chk:
        setx    MAC_ID, %g1, %o0
        setx    NIU_TX_PKT_CNT, %g1, %o1
        call    NiuTx_check_pkt_cnt
        nop

        setx    loop_count, %g1, %g4
        setx    LDGIMGN, %g1, %g2

delay_loop_end:
        ldxa     [%g2]ASI_PRIMARY_LITTLE, %g5
        nop
        nop
        nop
        nop
        dec     %g4
        brnz    %g4, delay_loop_end
        nop

        setx    0x20, %g1, %g4
delay_ras:
        setx    0x2000000, %g1, %g2
        ldx     [%g2], %g3
        nop
        nop
        dec     %g4
        brnz    %g4, delay_ras
        nop
Check_L2_esr:
        setx  L2ES_PA0, %l6, %g1
        ldx   [%g1], %g2

Verify_L2_esr:
        mov     0x1, %l1
        sllx    %l1, L2ES_MEC, %l0
        sllx    %l1, L2ES_DRC, %l2
        or      %l0, %l2, %l2
        sllx    %l1, L2ES_DSC, %l3
        sllx    %l1, L2ES_VEC, %l4
        or      %l3, %l4, %l4
        or      %l2, %l4, %l4
        cmp     %l4, %g2
        bne     test_failed
        nop


Check_Soc_esr:
        setx    SOC_ESR_REG, %l7, %i0
        ldx     [%i0], %i1
        nop
        nop                     ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)


Verify_Soc_esr:
        setx    0x8000036d8c80040c, %l7, %o3    !valid bit
	cmp     %o3, %i1
        bne     test_failed
        nop

ba test_passed
nop

	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD

/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: Drc_Mcu_Io_err.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define ENABLE_PCIE_LINK_TRAINING
	39	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	40	#define MAIN_PAGE_HV_ALSO
	41
	42	#include "err_defines.h"
	43	#include "hboot.s"
	44	#include "peu_defines.h"
	45	#include "niu_defines.h"
	46
	47
	48	#define DMA_DATA_ADDR 0x0000000123456700
	49	#define DMA_DATA_BYP_SADDR 0xfffc000022000000
	50	#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
	51	#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
	52	#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
	53	#define DRAM_ERR_INJ_REG_0 0x8400000290
	54	#define DRAM_ERR_INJ_REG_1 0x8400001290
	55	#define DRAM_ERR_INJ_REG_2 0x8400002290
	56	#define DRAM_ERR_INJ_REG_3 0x8400003290
	57	#define L2_ENTRY_PA 0xa000000000
	58
	59
	60	#define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) \|IO_ACCESS_PA)
	61
	62
	63	/************************************************************************
	64	Test case code start
65	************************************************************************/
66	.text
67	.global main
68
69	main:
70	ta T_CHANGE_HPRIV
71	nop
72
73	set_Soc_err_inj_reg:
74	set 0x1, %i1
75	setx 0x800001248c80040c,%i1,%i2
76	setx SOC_EJR_REG, %l7, %i3
77	stx %i2, [%i3]
78	membar 0x40
79
80	disable_l1_DCache:
81	ldxa [%g0] ASI_LSU_CONTROL, %l0
82	! Remove bit 2
83	andn %l0, 0x2, %l0
84	stxa %l0, [%g0] ASI_LSU_CONTROL
85
86	set_L2_Direct_Mapped_Mode:
87	set 0x80, %l1
88	set 0x100,%l2
89	set 0x180, %l3
90	setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
91	add %g1,%l1,%g2
92	add %g1,%l2,%g3
93	add %g1,%l3,%g4
94	mov 0x2, %l0
95	stx %l0, [%g1]
96	stx %l0, [%g2]
97	stx %l0, [%g3]
98	stx %l0, [%g4]
99
100
101	set_DRAM_err_cnt_reg:
102	mov 0x1,%l2
103	setx DRAM_ERR_CNT_REG_PA_0,%l1,%g6
104	setx DRAM_ERR_CNT_REG_PA_1,%l1,%g3
105	setx DRAM_ERR_CNT_REG_PA_2,%l1,%g4
106	setx DRAM_ERR_CNT_REG_PA_3,%l1,%g5
107	stx %l2, [%g3]
108	stx %l2, [%g4]
109	stx %l2, [%g5]
110	stx %l2, [%g6]
111	membar 0x40
112
113	set_DRAM_fbr_count_reg:
114	set 0x10000, %g6 !<16>=countone=1
115	setx DRAM_FBR_CNT_REG_PA_0, %l7, %o2
116	setx DRAM_FBR_CNT_REG_PA_1, %l7, %o3
117	setx DRAM_FBR_CNT_REG_PA_2, %l7, %o4
118	setx DRAM_FBR_CNT_REG_PA_3, %l7, %o5
119	stx %g6, [%o2]
120	stx %g6, [%o3]
121	stx %g6, [%o4]
122	stx %g6, [%o5]
123	ldx [%o2], %i1
124	ldx [%o3], %i2
125	ldx [%o4], %i3
126	ldx [%o5], %i4
127
128
129
130	set_DRAM_error_inject_ch0_dac:
131	mov 0x2, %l1 ! ECC Mask (1-bit error)
132	mov 0x1, %l2
133	sllx %l2, DRAM_EI_SSHOT, %l3
134	or %l1, %l3, %l1 ! Set single shot ;
135	mov 0x1, %l2
136	sllx %l2, DRAM_EI_ENB, %l3
137	or %l1, %l3, %l1 ! Enable error injection for the next write
138	setx DRAM_ERR_INJ_REG_0, %l3, %g3
139	setx DRAM_ERR_INJ_REG_1, %l3, %g4
140	setx DRAM_ERR_INJ_REG_2, %l3, %g5
141	setx DRAM_ERR_INJ_REG_3, %l3, %g6
142	stx %l1, [%g3]
143	stx %l1, [%g4]
144	stx %l1, [%g5]
145	stx %l1, [%g6]
146	membar 0x40
147
148
149	store_to_L2_way0_dac:
150	set 0x55555555, %l0
151	set 0x22000000, %g7 ! bits [21:18] select way
152	set 0x80, %l1
153	set 0x100,%l2
154	set 0x180, %l3
155	add %g7,%l1,%g2
156	add %g7,%l2,%g3
157	add %g7,%l3,%g4
158	stx %l0, [%g2]
159	membar #Sync
160	stx %l0, [%g3]
161	membar #Sync
162	stx %l0, [%g4]
163	membar #Sync
164	stx %l0, [%g7]
165	membar #Sync
166
167	! Storing to same L2 way0 but different tag,this will write to mcu
168	write_mcu_channel_0_dac:
169	set 0x80,%l1
170	set 0x31000000, %i3 ! bits [21:18] select way
171	add %i3,%l1,%i2
172	add %i2,%l1,%i7
173	add %i7,%l1,%i4
174	stx %g5, [%i2]
175	stx %g5, [%i3]
176	stx %g5, [%i4]
177	stx %g5, [%i7]
178	membar #Sync
179
180	XmtUsrEvnt_drc:
181	nop ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt_drc)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_SADDR, "64'h40", 1, , )
182
183
184	read_error_address0_dac:
185	ldx [%g2], %l0
186	ldx [%g3], %l1
187	ldx [%g4], %l2
188	ldx [%g7], %l3
189	membar #Sync
190
191	read_error_address1_dac:
192	ldx [%g2], %l0
193	ldx [%g3], %l1
194	ldx [%g4], %l2
195	ldx [%g7], %l3
196	membar #Sync
197
198
199	read_error_address2_dac:
200	ldx [%g2], %l0
201	ldx [%g3], %l1
202	ldx [%g4], %l2
203	ldx [%g7], %l3
204	membar #Sync
205
206
207
208	set_inj_err_src_reg_fbr:
209	set 0x3, %g1
210	setx DRAM_FBD_INJ_ERR_SRC_REG_PA_0,%l7, %g3
211	setx DRAM_FBD_INJ_ERR_SRC_REG_PA_1,%l7, %g4
212	setx DRAM_FBD_INJ_ERR_SRC_REG_PA_2,%l7, %g5
213	setx DRAM_FBD_INJ_ERR_SRC_REG_PA_3,%l7, %g6
214	stx %g1, [%g3]
215	stx %g1, [%g4]
216	stx %g1, [%g5]
217	stx %g1, [%g6]
218	membar 0x40
219
220
221	! enable bypass in IOMMU
222	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
223	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
224	stx %g3, [%g2]
225	ldx [%g2], %g3
226
227	XmtUsrEvnt1: nop;
228	! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h20", 1 )
229	ldx [%g2], %g3
230	ldx [%g2], %g3
231	ldx [%g2], %g3
232	ldx [%g2], %g3
233
234
235	! select a CSR in the PIU and transmit the command to NCU
236
237	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2
238	set 0x020, %g4
239
240	delay_loop_soc:
241	ldx [%g2], %g5
242	nop
243	nop
244	nop
245	nop
246	dec %g4
247	brnz %g4, delay_loop_soc
248	nop
249
250	pio:
251	! select an IO address in PCI address range and transmit the command to NCU
252	setx IO_RD_ADDR, %g1, %g2
253
254	! load byte - all byte offsets within an octlet
255	ldub [%g2 + 1*8 + 0], %l0
256
257	set 0x40, %g4
258	delay_loop_pio:
259	nop
260	nop
261	nop
262	nop
263	dec %g4
264	brnz %g4, delay_loop_pio
265	nop
266
267
268	Init_flow:
269	nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)
270
271	P_TxDMAActivate:
272	setx MAC_ID, %g1, %o0 ! 1st Parameter
273	setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
274	call SetTxDMAActive
275	nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
276
277	P_AddTxChannels :
278	nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
279
280	setx LDGIMGN, %g1, %g2
281
282
283	ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
284	nop
285
286	P_SetTxMaxBurst :
287	setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
288	setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
289	call SetTxMaxBurst
290	nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
291
292	ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
293	nop
294
295	P_InitTxDma:
296	setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
297	nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
298	call InitTxDma
299	nop
300
301	ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
302	nop
303
304
305	Gen_Packet:
306	nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT,0,0)
307	nop
308
309	setx 0x5, %g1, %g4
310	delay_loop_tmp:
311	ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
312	nop
313	nop
314	nop
315	nop
316	dec %g4
317	brnz %g4, delay_loop_tmp
318	nop
319
320
321	SetTxRingKick:
322	setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
323	setx NIU_TxDmaNo, %g1, %o0
324	ldx [%g2], %g3
325	nop
326	mulx %o0, 0x200, %g5
327	setx TX_RING_KICK_Addr, %g1, %g2
328	add %g2, %g5, %g2
329	stxa %g3, [%g2]ASI_PRIMARY_LITTLE
330	nop
331
332	SetTxCs :
333	setx NIU_TxDmaNo, %g1, %o0
334	setx TX_CS_Data, %g1, %g3
335	mulx %o0, 0x200, %g5
336	setx TX_CS_Addr, %g1, %g2
337	add %g2, %g5, %g2
338	stxa %g3, [%g2]ASI_PRIMARY_LITTLE
339	nop
340
341	NIUTx_Pkt_Cnt_Chk:
342	setx MAC_ID, %g1, %o0
343	setx NIU_TX_PKT_CNT, %g1, %o1
344	call NiuTx_check_pkt_cnt
345	nop
346
347	setx loop_count, %g1, %g4
348	setx LDGIMGN, %g1, %g2
349
350	delay_loop_end:
351	ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
352	nop
353	nop
354	nop
355	nop
356	dec %g4
357	brnz %g4, delay_loop_end
358	nop
359
360	setx 0x20, %g1, %g4
361	delay_ras:
362	setx 0x2000000, %g1, %g2
363	ldx [%g2], %g3
364	nop
365	nop
366	dec %g4
367	brnz %g4, delay_ras
368	nop
369	Check_L2_esr:
370	setx L2ES_PA0, %l6, %g1
371	ldx [%g1], %g2
372
373	Verify_L2_esr:
374	mov 0x1, %l1
375	sllx %l1, L2ES_MEC, %l0
376	sllx %l1, L2ES_DRC, %l2
377	or %l0, %l2, %l2
378	sllx %l1, L2ES_DSC, %l3
379	sllx %l1, L2ES_VEC, %l4
380	or %l3, %l4, %l4
381	or %l2, %l4, %l4
382	cmp %l4, %g2
383	bne test_failed
384	nop
385
386
387	Check_Soc_esr:
388	setx SOC_ESR_REG, %l7, %i0
389	ldx [%i0], %i1
390	nop
391	nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)
392
393
394	Verify_Soc_esr:
395	setx 0x8000036d8c80040c, %l7, %o3 !valid bit
396	cmp %o3, %i1
397	bne test_failed
398	nop
399
400	ba test_passed
401	nop
402
403
404	test_passed:
405	EXIT_GOOD
406
407	test_failed:
408	EXIT_BAD
409
410	/************************************************************************
411	Test case data start
412	************************************************************************/
413
414	SECTION .DATA DATA_VA=DMA_DATA_ADDR
415	attr_data {
416	Name = .DATA,
417	hypervisor,
418	compressimage
419	}
420
421	.data
422	.global PCIAddr9
423	.xword 0x0001020304050607
424	.xword 0x08090a0b0c0d0e0f
425	.xword 0x1011121314151617
426	.xword 0x18191a1b1c1d1e1f
427	.xword 0x2021222324252627
428	.xword 0x28292a2b2c2d2e2f
429	.xword 0x3031323334353637
430	.xword 0x38393a3b3c3d3e3f
431
432	.xword 0x4041424344454647
433	.xword 0x48494a4b4c4d4e4f
434	.xword 0x5051525354555657
435	.xword 0x58595a5b5c5d5e5f
436	.xword 0x6061626364656667
437	.xword 0x68696a6b6c6d6e6f
438	.xword 0x7071727374757677
439	.xword 0x78797a7b7c7d7e7f
440
441	.xword 0x8081828384858687
442	.xword 0x88898a8b8c8d8e8f
443	.xword 0x9091929394959697
444	.xword 0x98999a9b9c9d9e9f
445	.xword 0xa0a1a2a3a4a5a6a7
446	.xword 0xa8a9aaabacadaeaf
447	.xword 0xb0b1b2b3b4b5b6b7
448	.xword 0xb8b9babbbcbdbebf
449
450	.xword 0xc0c1c2c3c4c5c6c7
451	.xword 0xc8c9cacbcccdcecf
452	.xword 0xd0d1d2d3d4d5d6d7
453	.xword 0xd8d9dadbdcdddedf
454	.xword 0xe0e1e2e3e4e5e6e7
455	.xword 0xe8e9eaebecedeeef
456	.xword 0xf0f1f2f3f4f5f6f7
457	.xword 0xf8f9fafbfcfdfeff
458
459	.xword 0x0001020304050607
460	.xword 0x08090a0b0c0d0e0f
461	.xword 0x1011121314151617
462	.xword 0x18191a1b1c1d1e1f
463	.xword 0x2021222324252627
464	.xword 0x28292a2b2c2d2e2f
465	.xword 0x3031323334353637
466	.xword 0x38393a3b3c3d3e3f
467
468	.xword 0x4041424344454647
469	.xword 0x48494a4b4c4d4e4f
470	.xword 0x5051525354555657
471	.xword 0x58595a5b5c5d5e5f
472	.xword 0x6061626364656667
473	.xword 0x68696a6b6c6d6e6f
474	.xword 0x7071727374757677
475	.xword 0x78797a7b7c7d7e7f
476
477	.xword 0x8081828384858687
478	.xword 0x88898a8b8c8d8e8f
479	.xword 0x9091929394959697
480	.xword 0x98999a9b9c9d9e9f
481	.xword 0xa0a1a2a3a4a5a6a7
482	.xword 0xa8a9aaabacadaeaf
483	.xword 0xb0b1b2b3b4b5b6b7
484	.xword 0xb8b9babbbcbdbebf
485
486	.xword 0xc0c1c2c3c4c5c6c7
487	.xword 0xc8c9cacbcccdcecf
488	.xword 0xd0d1d2d3d4d5d6d7
489	.xword 0xd8d9dadbdcdddedf
490	.xword 0xe0e1e2e3e4e5e6e7
491	.xword 0xe8e9eaebecedeeef
492	.xword 0xf0f1f2f3f4f5f6f7
493	.xword 0xf8f9fafbfcfdfeff
494
495	/************************************************************************/
496
497
498