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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: Ldac_Mcu_Io_err.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define ENABLE_PCIE_LINK_TRAINING | |
39 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ | |
40 | #define MAIN_PAGE_HV_ALSO | |
41 | ||
42 | #include "err_defines.h" | |
43 | #include "hboot.s" | |
44 | #include "peu_defines.h" | |
45 | #include "niu_defines.h" | |
46 | ||
47 | ||
48 | #define DMA_DATA_ADDR 0x0000000123456700 | |
49 | #define DMA_DATA_BYP_SADDR 0xfffc00003000aa00 | |
50 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456700 | |
51 | #define DMA_DATA_BYP_ADDR2 0xfffc000123456780 | |
52 | #define DMA_DATA_BYP_ADDR3 0xfffc000123456800 | |
53 | #define DRAM_ERR_INJ_REG_0 0x8400000290 | |
54 | #define DRAM_ERR_INJ_REG_1 0x8400001290 | |
55 | #define DRAM_ERR_INJ_REG_2 0x8400002290 | |
56 | #define DRAM_ERR_INJ_REG_3 0x8400003290 | |
57 | #define L2_ENTRY_PA 0xa000000000 | |
58 | ||
59 | ||
60 | #define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) |IO_ACCESS_PA) | |
61 | ||
62 | ||
63 | /************************************************************************ | |
64 | * Test case code start | |
65 | *************************************************************************/ | |
66 | .text | |
67 | .global main | |
68 | ||
69 | main: | |
70 | ta T_CHANGE_HPRIV | |
71 | nop | |
72 | ||
73 | Set_Err_Inj_Reg: | |
74 | set 0x1, %i1 | |
75 | setx 0x800001248c80040c,%i1,%i2 | |
76 | setx SOC_EJR_REG, %l7, %i3 | |
77 | stx %i2, [%i3] | |
78 | membar 0x40 | |
79 | ||
80 | disable_l1_DCache: | |
81 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
82 | ! Remove bit 2 | |
83 | andn %l0, 0x2, %l0 | |
84 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
85 | ||
86 | set_L2_Direct_Mapped_Mode: | |
87 | set 0x80, %l1 | |
88 | set 0x100,%l2 | |
89 | set 0x180, %l3 | |
90 | setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register | |
91 | add %g1,%l1,%g2 | |
92 | add %g1,%l2,%g3 | |
93 | add %g1,%l3,%g4 | |
94 | mov 0x2, %l0 | |
95 | stx %l0, [%g1] | |
96 | stx %l0, [%g2] | |
97 | stx %l0, [%g3] | |
98 | stx %l0, [%g4] | |
99 | ||
100 | ||
101 | store_to_L2_way0_ldac: | |
102 | set 0x5555555, %g5 | |
103 | set 0x3000aa00, %g2 ! bits [21:18] select way | |
104 | stx %g5, [%g2] | |
105 | stx %g5, [%g2+8] | |
106 | membar #Sync | |
107 | ||
108 | mov 0x20,%i4 | |
109 | clr %i3 | |
110 | loop: | |
111 | inc %i3 | |
112 | cmp %i3,%i4 | |
113 | bne loop | |
114 | nop | |
115 | ||
116 | ||
117 | L2_diag_load_ldac: | |
118 | set 0x3ffff8, %l2 ! Mask for extracting [21:3] | |
119 | setx L2_ENTRY_PA, %l0, %g4 | |
120 | and %g2, %l2, %g5 !g2 has L2 PA, | |
121 | or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address | |
122 | ldx [%g5], %g6 | |
123 | membar #Sync | |
124 | ||
125 | ! Flip one bits to inject error | |
126 | xor %g6, 0x200, %g6 | |
127 | stx %g6, [%g5] | |
128 | membar #Sync | |
129 | ||
130 | mov 0x7,%i4 | |
131 | clr %i3 | |
132 | loop_next: | |
133 | inc %i3 | |
134 | cmp %i3,%i4 | |
135 | bne loop_next | |
136 | nop | |
137 | ||
138 | ||
139 | reading_back_0_ldac: !Load to L2 again to get the error | |
140 | setx 0x3000aa00, %l0, %g2 | |
141 | ldx [%g2], %l6 | |
142 | ||
143 | reading_back_1_ldac: !Load to L2 again to get the error | |
144 | ldx [%g2], %l5 | |
145 | ||
146 | reading_back_2_ldac: !Load to L2 again to get the error | |
147 | ldx [%g2], %l7 | |
148 | membar #Sync | |
149 | ||
150 | XmtUsrEvnt: | |
151 | nop ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_SADDR, "64'h40", 1, *, * ) | |
152 | ||
153 | set_DRAM_err_cnt_reg: | |
154 | mov 0x1,%l2 | |
155 | setx DRAM_ERR_CNT_REG_PA_0,%l1,%g6 | |
156 | setx DRAM_ERR_CNT_REG_PA_1,%l1,%g3 | |
157 | setx DRAM_ERR_CNT_REG_PA_2,%l1,%g4 | |
158 | setx DRAM_ERR_CNT_REG_PA_3,%l1,%g5 | |
159 | stx %l2, [%g3] | |
160 | stx %l2, [%g4] | |
161 | stx %l2, [%g5] | |
162 | stx %l2, [%g6] | |
163 | membar 0x40 | |
164 | ||
165 | set_DRAM_fbr_count_reg: | |
166 | set 0x10000, %g6 !<16>=countone=1 | |
167 | setx DRAM_FBR_CNT_REG_PA_0, %l7, %o2 | |
168 | setx DRAM_FBR_CNT_REG_PA_1, %l7, %o3 | |
169 | setx DRAM_FBR_CNT_REG_PA_2, %l7, %o4 | |
170 | setx DRAM_FBR_CNT_REG_PA_3, %l7, %o5 | |
171 | stx %g6, [%o2] | |
172 | stx %g6, [%o3] | |
173 | stx %g6, [%o4] | |
174 | stx %g6, [%o5] | |
175 | ldx [%o2], %i1 | |
176 | ldx [%o3], %i2 | |
177 | ldx [%o4], %i3 | |
178 | ldx [%o5], %i4 | |
179 | ||
180 | ||
181 | ||
182 | set_DRAM_error_inject_ch0_dac: | |
183 | mov 0x2, %l1 ! ECC Mask (1-bit error) | |
184 | mov 0x1, %l2 | |
185 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
186 | or %l1, %l3, %l1 ! Set single shot ; | |
187 | mov 0x1, %l2 | |
188 | sllx %l2, DRAM_EI_ENB, %l3 | |
189 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
190 | setx DRAM_ERR_INJ_REG_0, %l3, %g3 | |
191 | setx DRAM_ERR_INJ_REG_1, %l3, %g4 | |
192 | setx DRAM_ERR_INJ_REG_2, %l3, %g5 | |
193 | setx DRAM_ERR_INJ_REG_3, %l3, %g6 | |
194 | stx %l1, [%g3] | |
195 | stx %l1, [%g4] | |
196 | stx %l1, [%g5] | |
197 | stx %l1, [%g6] | |
198 | membar 0x40 | |
199 | ||
200 | ||
201 | store_to_L2_way0_dac: | |
202 | set 0x55555555, %l0 | |
203 | set 0x22000000, %g7 ! bits [21:18] select way | |
204 | set 0x80, %l1 | |
205 | set 0x100,%l2 | |
206 | set 0x180, %l3 | |
207 | add %g7,%l1,%g2 | |
208 | add %g7,%l2,%g3 | |
209 | add %g7,%l3,%g4 | |
210 | stx %l0, [%g2] | |
211 | membar #Sync | |
212 | stx %l0, [%g3] | |
213 | membar #Sync | |
214 | stx %l0, [%g4] | |
215 | membar #Sync | |
216 | stx %l0, [%g7] | |
217 | membar #Sync | |
218 | ||
219 | ! Storing to same L2 way0 but different tag,this will write to mcu | |
220 | write_mcu_channel_0_dac: | |
221 | set 0x80,%l1 | |
222 | set 0x31000000, %i3 ! bits [21:18] select way | |
223 | add %i3,%l1,%i2 | |
224 | add %i2,%l1,%i7 | |
225 | add %i7,%l1,%i4 | |
226 | stx %g5, [%i2] | |
227 | stx %g5, [%i3] | |
228 | stx %g5, [%i4] | |
229 | stx %g5, [%i7] | |
230 | membar #Sync | |
231 | ||
232 | read_error_address0_dac: | |
233 | ldx [%g2], %l0 | |
234 | ldx [%g3], %l1 | |
235 | ldx [%g4], %l2 | |
236 | ldx [%g7], %l3 | |
237 | membar #Sync | |
238 | ||
239 | read_error_address1_dac: | |
240 | ldx [%g2], %l0 | |
241 | ldx [%g3], %l1 | |
242 | ldx [%g4], %l2 | |
243 | ldx [%g7], %l3 | |
244 | membar #Sync | |
245 | ||
246 | ||
247 | read_error_address2_dac: | |
248 | ldx [%g2], %l0 | |
249 | ldx [%g3], %l1 | |
250 | ldx [%g4], %l2 | |
251 | ldx [%g7], %l3 | |
252 | membar #Sync | |
253 | ||
254 | ||
255 | ||
256 | set_inj_err_src_reg_fbr: | |
257 | set 0x3, %g1 | |
258 | setx DRAM_FBD_INJ_ERR_SRC_REG_PA_0,%l7, %g3 | |
259 | setx DRAM_FBD_INJ_ERR_SRC_REG_PA_1,%l7, %g4 | |
260 | setx DRAM_FBD_INJ_ERR_SRC_REG_PA_2,%l7, %g5 | |
261 | setx DRAM_FBD_INJ_ERR_SRC_REG_PA_3,%l7, %g6 | |
262 | stx %g1, [%g3] | |
263 | stx %g1, [%g4] | |
264 | stx %g1, [%g5] | |
265 | stx %g1, [%g6] | |
266 | membar 0x40 | |
267 | ||
268 | ||
269 | ! enable bypass in IOMMU | |
270 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
271 | setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3 | |
272 | stx %g3, [%g2] | |
273 | ldx [%g2], %g3 | |
274 | ||
275 | XmtUsrEvnt1: nop; | |
276 | ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h20", 1 ) | |
277 | ldx [%g2], %g3 | |
278 | ldx [%g2], %g3 | |
279 | ldx [%g2], %g3 | |
280 | ldx [%g2], %g3 | |
281 | ||
282 | ||
283 | ! select a CSR in the PIU and transmit the command to NCU | |
284 | ||
285 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2 | |
286 | set 0x020, %g4 | |
287 | ||
288 | delay_loop_soc: | |
289 | ldx [%g2], %g5 | |
290 | nop | |
291 | nop | |
292 | nop | |
293 | nop | |
294 | dec %g4 | |
295 | brnz %g4, delay_loop_soc | |
296 | nop | |
297 | ||
298 | pio: | |
299 | ! select an IO address in PCI address range and transmit the command to NCU | |
300 | setx IO_RD_ADDR, %g1, %g2 | |
301 | ||
302 | ! load byte - all byte offsets within an octlet | |
303 | ldub [%g2 + 1*8 + 0], %l0 | |
304 | ||
305 | set 0x40, %g4 | |
306 | delay_loop_pio: | |
307 | nop | |
308 | nop | |
309 | nop | |
310 | nop | |
311 | dec %g4 | |
312 | brnz %g4, delay_loop_pio | |
313 | nop | |
314 | ||
315 | ||
316 | Init_flow: | |
317 | nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN) | |
318 | ||
319 | P_TxDMAActivate: | |
320 | setx MAC_ID, %g1, %o0 ! 1st Parameter | |
321 | setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter | |
322 | call SetTxDMAActive | |
323 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list) | |
324 | ||
325 | P_AddTxChannels : | |
326 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE) | |
327 | ||
328 | setx LDGIMGN, %g1, %g2 | |
329 | ||
330 | ||
331 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay | |
332 | nop | |
333 | ||
334 | P_SetTxMaxBurst : | |
335 | setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter : | |
336 | setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter | |
337 | call SetTxMaxBurst | |
338 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data) | |
339 | ||
340 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay | |
341 | nop | |
342 | ||
343 | P_InitTxDma: | |
344 | setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter : | |
345 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On) | |
346 | call InitTxDma | |
347 | nop | |
348 | ||
349 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay | |
350 | nop | |
351 | ||
352 | ||
353 | Gen_Packet: | |
354 | nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT,0,0) | |
355 | nop | |
356 | ||
357 | setx 0x5, %g1, %g4 | |
358 | delay_loop_tmp: | |
359 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
360 | nop | |
361 | nop | |
362 | nop | |
363 | nop | |
364 | dec %g4 | |
365 | brnz %g4, delay_loop_tmp | |
366 | nop | |
367 | ||
368 | ||
369 | SetTxRingKick: | |
370 | setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE) | |
371 | setx NIU_TxDmaNo, %g1, %o0 | |
372 | ldx [%g2], %g3 | |
373 | nop | |
374 | mulx %o0, 0x200, %g5 | |
375 | setx TX_RING_KICK_Addr, %g1, %g2 | |
376 | add %g2, %g5, %g2 | |
377 | stxa %g3, [%g2]ASI_PRIMARY_LITTLE | |
378 | nop | |
379 | ||
380 | SetTxCs : | |
381 | setx NIU_TxDmaNo, %g1, %o0 | |
382 | setx TX_CS_Data, %g1, %g3 | |
383 | mulx %o0, 0x200, %g5 | |
384 | setx TX_CS_Addr, %g1, %g2 | |
385 | add %g2, %g5, %g2 | |
386 | stxa %g3, [%g2]ASI_PRIMARY_LITTLE | |
387 | nop | |
388 | ||
389 | NIUTx_Pkt_Cnt_Chk: | |
390 | setx MAC_ID, %g1, %o0 | |
391 | setx NIU_TX_PKT_CNT, %g1, %o1 | |
392 | call NiuTx_check_pkt_cnt | |
393 | nop | |
394 | ||
395 | setx loop_count, %g1, %g4 | |
396 | setx LDGIMGN, %g1, %g2 | |
397 | ||
398 | delay_loop_end: | |
399 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
400 | nop | |
401 | nop | |
402 | nop | |
403 | nop | |
404 | dec %g4 | |
405 | brnz %g4, delay_loop_end | |
406 | nop | |
407 | ||
408 | setx 0x20, %g1, %g4 | |
409 | delay_ras: | |
410 | setx 0x2000000, %g1, %g2 | |
411 | ldx [%g2], %g3 | |
412 | nop | |
413 | nop | |
414 | dec %g4 | |
415 | brnz %g4, delay_ras | |
416 | nop | |
417 | ||
418 | Check_L2_esr: | |
419 | setx L2ES_PA0, %l6, %g1 | |
420 | ldx [%g1], %g3 | |
421 | setx 0xfffffffff0000000, %l2, %l3 | |
422 | andcc %l3, %g3, %g2 | |
423 | ||
424 | ||
425 | ||
426 | Verify_L2_esr: | |
427 | mov 0x1, %l1 | |
428 | sllx %l1, L2ES_MEC, %l0 | |
429 | sllx %l1, L2ES_LDAC, %l2 | |
430 | or %l0, %l2, %l2 | |
431 | sllx %l1, L2ES_DSC, %l3 | |
432 | sllx %l1, L2ES_VEC, %l4 | |
433 | or %l3, %l4, %l4 | |
434 | or %l2, %l4, %l4 | |
435 | cmp %l4, %g2 | |
436 | bne test_failed | |
437 | nop | |
438 | ||
439 | Check_Soc_esr: | |
440 | setx SOC_ESR_REG, %l7, %i0 | |
441 | ldx [%i0], %i1 | |
442 | nop | |
443 | ||
444 | ||
445 | Verify_Soc_esr: | |
446 | setx 0x8000036d8c80040c, %l7, %o3 !valid bit | |
447 | cmp %o3, %i1 | |
448 | bne test_failed | |
449 | nop | |
450 | ||
451 | nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID) | |
452 | ba test_passed | |
453 | nop | |
454 | ||
455 | ||
456 | test_passed: | |
457 | EXIT_GOOD | |
458 | ||
459 | test_failed: | |
460 | EXIT_BAD | |
461 | ||
462 | /************************************************************************ | |
463 | Test case data start | |
464 | ************************************************************************/ | |
465 | ||
466 | SECTION .DATA DATA_VA=DMA_DATA_ADDR | |
467 | attr_data { | |
468 | Name = .DATA, | |
469 | hypervisor, | |
470 | compressimage | |
471 | } | |
472 | ||
473 | .data | |
474 | .global PCIAddr9 | |
475 | .xword 0x0001020304050607 | |
476 | .xword 0x08090a0b0c0d0e0f | |
477 | .xword 0x1011121314151617 | |
478 | .xword 0x18191a1b1c1d1e1f | |
479 | .xword 0x2021222324252627 | |
480 | .xword 0x28292a2b2c2d2e2f | |
481 | .xword 0x3031323334353637 | |
482 | .xword 0x38393a3b3c3d3e3f | |
483 | ||
484 | .xword 0x4041424344454647 | |
485 | .xword 0x48494a4b4c4d4e4f | |
486 | .xword 0x5051525354555657 | |
487 | .xword 0x58595a5b5c5d5e5f | |
488 | .xword 0x6061626364656667 | |
489 | .xword 0x68696a6b6c6d6e6f | |
490 | .xword 0x7071727374757677 | |
491 | .xword 0x78797a7b7c7d7e7f | |
492 | ||
493 | .xword 0x8081828384858687 | |
494 | .xword 0x88898a8b8c8d8e8f | |
495 | .xword 0x9091929394959697 | |
496 | .xword 0x98999a9b9c9d9e9f | |
497 | .xword 0xa0a1a2a3a4a5a6a7 | |
498 | .xword 0xa8a9aaabacadaeaf | |
499 | .xword 0xb0b1b2b3b4b5b6b7 | |
500 | .xword 0xb8b9babbbcbdbebf | |
501 | ||
502 | .xword 0xc0c1c2c3c4c5c6c7 | |
503 | .xword 0xc8c9cacbcccdcecf | |
504 | .xword 0xd0d1d2d3d4d5d6d7 | |
505 | .xword 0xd8d9dadbdcdddedf | |
506 | .xword 0xe0e1e2e3e4e5e6e7 | |
507 | .xword 0xe8e9eaebecedeeef | |
508 | .xword 0xf0f1f2f3f4f5f6f7 | |
509 | .xword 0xf8f9fafbfcfdfeff | |
510 | ||
511 | .xword 0x0001020304050607 | |
512 | .xword 0x08090a0b0c0d0e0f | |
513 | .xword 0x1011121314151617 | |
514 | .xword 0x18191a1b1c1d1e1f | |
515 | .xword 0x2021222324252627 | |
516 | .xword 0x28292a2b2c2d2e2f | |
517 | .xword 0x3031323334353637 | |
518 | .xword 0x38393a3b3c3d3e3f | |
519 | ||
520 | .xword 0x4041424344454647 | |
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528 | ||
529 | .xword 0x8081828384858687 | |
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537 | ||
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545 | .xword 0xf8f9fafbfcfdfeff | |
546 | ||
547 | /************************************************************************/ | |
548 | ||
549 | ||
550 |