projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: Ldrc_Mcu_Io_err.s | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #define ENABLE_PCIE_LINK_TRAINING | |
| 39 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ | |
| 40 | #define MAIN_PAGE_HV_ALSO | |
| 41 | ||
| 42 | #include "err_defines.h" | |
| 43 | #include "hboot.s" | |
| 44 | #include "peu_defines.h" | |
| 45 | #include "niu_defines.h" | |
| 46 | ||
| 47 | ||
| 48 | #define DMA_DATA_ADDR 0x0000000123456700 | |
| 49 | #define DMA_DATA_BYP_SADDR 0xfffc00003000aa00 | |
| 50 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456700 | |
| 51 | #define DMA_DATA_BYP_ADDR2 0xfffc000123456780 | |
| 52 | #define DMA_DATA_BYP_ADDR3 0xfffc000123456800 | |
| 53 | #define DRAM_ERR_INJ_REG_0 0x8400000290 | |
| 54 | #define DRAM_ERR_INJ_REG_1 0x8400001290 | |
| 55 | #define DRAM_ERR_INJ_REG_2 0x8400002290 | |
| 56 | #define DRAM_ERR_INJ_REG_3 0x8400003290 | |
| 57 | #define L2_ENTRY_PA 0xa000000000 | |
| 58 | ||
| 59 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
| 60 | ||
| 61 | ||
| 62 | ||
| 63 | #define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) |IO_ACCESS_PA) | |
| 64 | ||
| 65 | ||
| 66 | /************************************************************************ | |
| 67 | Test case code start | |
| 68 | ************************************************************************/ | |
| 69 | .text | |
| 70 | .global main | |
| 71 | ||
| 72 | main: | |
| 73 | ta T_CHANGE_HPRIV | |
| 74 | nop | |
| 75 | ||
| 76 | set_Soc_Err_Inj_reg: | |
| 77 | set 0x1, %i1 | |
| 78 | setx 0x800001248c80040c,%i1,%i2 | |
| 79 | setx SOC_EJR_REG, %l7, %i3 | |
| 80 | stx %i2, [%i3] | |
| 81 | membar 0x40 | |
| 82 | ||
| 83 | disable_l1_DCache: | |
| 84 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
| 85 | ! Remove bit 2 | |
| 86 | andn %l0, 0x2, %l0 | |
| 87 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
| 88 | ||
| 89 | set_L2_Directly_Mapped_Mode: | |
| 90 | set 0x80, %l1 | |
| 91 | set 0x100,%l2 | |
| 92 | set 0x180, %l3 | |
| 93 | setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register | |
| 94 | add %g1,%l1,%g2 | |
| 95 | add %g1,%l2,%g3 | |
| 96 | add %g1,%l3,%g4 | |
| 97 | mov 0x2, %l0 | |
| 98 | stx %l0, [%g1] | |
| 99 | stx %l0, [%g2] | |
| 100 | stx %l0, [%g3] | |
| 101 | stx %l0, [%g4] | |
| 102 | ||
| 103 | ||
| 104 | store_to_L2_way0_ldac: | |
| 105 | set 0x5555555, %g5 | |
| 106 | setx 0x3000aa00, %l0, %g2 ! bits [21:18] select way | |
| 107 | stx %g5, [%g2] | |
| 108 | stx %g5, [%g2+8] | |
| 109 | membar #Sync | |
| 110 | ||
| 111 | mov 0x20,%i4 | |
| 112 | clr %i3 | |
| 113 | loop: | |
| 114 | inc %i3 | |
| 115 | cmp %i3,%i4 | |
| 116 | bne loop | |
| 117 | nop | |
| 118 | ||
| 119 | ||
| 120 | L2_diag_load_ldac: | |
| 121 | set 0x3ffff8, %l2 ! Mask for extracting [21:3] | |
| 122 | setx L2_ENTRY_PA, %l0, %g4 | |
| 123 | and %g2, %l2, %g5 !g2 has L2 PA, | |
| 124 | or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address | |
| 125 | ldx [%g5], %g6 | |
| 126 | membar #Sync | |
| 127 | ||
| 128 | ! Flip one bits to inject error | |
| 129 | xor %g6, 0x200, %g6 | |
| 130 | stx %g6, [%g5] | |
| 131 | membar #Sync | |
| 132 | ||
| 133 | mov 0x7,%i4 | |
| 134 | clr %i3 | |
| 135 | loop_next: | |
| 136 | inc %i3 | |
| 137 | cmp %i3,%i4 | |
| 138 | bne loop_next | |
| 139 | nop | |
| 140 | ||
| 141 | ||
| 142 | reading_back_0_ldac: !Load to L2 again to get the error | |
| 143 | setx 0x3000aa00, %l0, %g2 | |
| 144 | ldx [%g2], %l6 | |
| 145 | ||
| 146 | clear_l2_esr: | |
| 147 | setx L2_ES_W1C_VALUE, %l0, %l1 | |
| 148 | setx L2ES_PA0, %l6, %g1 | |
| 149 | stx %l1, [%g1] | |
| 150 | membar #Sync | |
| 151 | ||
| 152 | XmtUsrEvnt_ldrc: | |
| 153 | nop ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt_ldrc)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_SADDR, "64'h40", 1, *, * ) | |
| 154 | ||
| 155 | XmtUsrEvnt_ldrc_mec: | |
| 156 | nop ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt_ldrc_mec)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_SADDR, "64'h40", 1, *, * ) | |
| 157 | ||
| 158 | ||
| 159 | set_DRAM_err_cnt_reg: | |
| 160 | mov 0x1,%l2 | |
| 161 | setx DRAM_ERR_CNT_REG_PA_0,%l1,%g6 | |
| 162 | setx DRAM_ERR_CNT_REG_PA_1,%l1,%g3 | |
| 163 | setx DRAM_ERR_CNT_REG_PA_2,%l1,%g4 | |
| 164 | setx DRAM_ERR_CNT_REG_PA_3,%l1,%g5 | |
| 165 | stx %l2, [%g3] | |
| 166 | stx %l2, [%g4] | |
| 167 | stx %l2, [%g5] | |
| 168 | stx %l2, [%g6] | |
| 169 | membar 0x40 | |
| 170 | ||
| 171 | set_DRAM_fbr_count_reg: | |
| 172 | set 0x10000, %g6 !<16>=countone=1 | |
| 173 | setx DRAM_FBR_CNT_REG_PA_0, %l7, %o2 | |
| 174 | setx DRAM_FBR_CNT_REG_PA_1, %l7, %o3 | |
| 175 | setx DRAM_FBR_CNT_REG_PA_2, %l7, %o4 | |
| 176 | setx DRAM_FBR_CNT_REG_PA_3, %l7, %o5 | |
| 177 | stx %g6, [%o2] | |
| 178 | stx %g6, [%o3] | |
| 179 | stx %g6, [%o4] | |
| 180 | stx %g6, [%o5] | |
| 181 | ldx [%o2], %i1 | |
| 182 | ldx [%o3], %i2 | |
| 183 | ldx [%o4], %i3 | |
| 184 | ldx [%o5], %i4 | |
| 185 | ||
| 186 | ||
| 187 | ||
| 188 | set_DRAM_error_inject_ch0_dac: | |
| 189 | mov 0x2, %l1 ! ECC Mask (1-bit error) | |
| 190 | mov 0x1, %l2 | |
| 191 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
| 192 | or %l1, %l3, %l1 ! Set single shot ; | |
| 193 | mov 0x1, %l2 | |
| 194 | sllx %l2, DRAM_EI_ENB, %l3 | |
| 195 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
| 196 | setx DRAM_ERR_INJ_REG_0, %l3, %g3 | |
| 197 | setx DRAM_ERR_INJ_REG_1, %l3, %g4 | |
| 198 | setx DRAM_ERR_INJ_REG_2, %l3, %g5 | |
| 199 | setx DRAM_ERR_INJ_REG_3, %l3, %g6 | |
| 200 | stx %l1, [%g3] | |
| 201 | stx %l1, [%g4] | |
| 202 | stx %l1, [%g5] | |
| 203 | stx %l1, [%g6] | |
| 204 | membar 0x40 | |
| 205 | ||
| 206 | ||
| 207 | store_to_L2_way0_dac: | |
| 208 | set 0x55555555, %l0 | |
| 209 | set 0x22000000, %g7 ! bits [21:18] select way | |
| 210 | set 0x80, %l1 | |
| 211 | set 0x100,%l2 | |
| 212 | set 0x180, %l3 | |
| 213 | add %g7,%l1,%g2 | |
| 214 | add %g7,%l2,%g3 | |
| 215 | add %g7,%l3,%g4 | |
| 216 | stx %l0, [%g2] | |
| 217 | membar #Sync | |
| 218 | stx %l0, [%g3] | |
| 219 | membar #Sync | |
| 220 | stx %l0, [%g4] | |
| 221 | membar #Sync | |
| 222 | stx %l0, [%g7] | |
| 223 | membar #Sync | |
| 224 | ||
| 225 | ! Storing to same L2 way0 but different tag,this will write to mcu | |
| 226 | write_mcu_channel_0_dac: | |
| 227 | set 0x80,%l1 | |
| 228 | set 0x31000000, %i3 ! bits [21:18] select way | |
| 229 | add %i3,%l1,%i2 | |
| 230 | add %i2,%l1,%i7 | |
| 231 | add %i7,%l1,%i4 | |
| 232 | stx %g5, [%i2] | |
| 233 | stx %g5, [%i3] | |
| 234 | stx %g5, [%i4] | |
| 235 | stx %g5, [%i7] | |
| 236 | membar #Sync | |
| 237 | ||
| 238 | read_error_address0_dac: | |
| 239 | ldx [%g2], %l0 | |
| 240 | ldx [%g3], %l1 | |
| 241 | ldx [%g4], %l2 | |
| 242 | ldx [%g7], %l3 | |
| 243 | membar #Sync | |
| 244 | ||
| 245 | read_error_address1_dac: | |
| 246 | ldx [%g2], %l0 | |
| 247 | ldx [%g3], %l1 | |
| 248 | ldx [%g4], %l2 | |
| 249 | ldx [%g7], %l3 | |
| 250 | membar #Sync | |
| 251 | ||
| 252 | ||
| 253 | read_error_address2_dac: | |
| 254 | ldx [%g2], %l0 | |
| 255 | ldx [%g3], %l1 | |
| 256 | ldx [%g4], %l2 | |
| 257 | ldx [%g7], %l3 | |
| 258 | membar #Sync | |
| 259 | ||
| 260 | ||
| 261 | ||
| 262 | set_inj_err_src_reg_fbr: | |
| 263 | set 0x3, %g1 | |
| 264 | setx DRAM_FBD_INJ_ERR_SRC_REG_PA_0,%l7, %g3 | |
| 265 | setx DRAM_FBD_INJ_ERR_SRC_REG_PA_1,%l7, %g4 | |
| 266 | setx DRAM_FBD_INJ_ERR_SRC_REG_PA_2,%l7, %g5 | |
| 267 | setx DRAM_FBD_INJ_ERR_SRC_REG_PA_3,%l7, %g6 | |
| 268 | stx %g1, [%g3] | |
| 269 | stx %g1, [%g4] | |
| 270 | stx %g1, [%g5] | |
| 271 | stx %g1, [%g6] | |
| 272 | membar 0x40 | |
| 273 | ||
| 274 | ||
| 275 | ! enable bypass in IOMMU | |
| 276 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
| 277 | setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3 | |
| 278 | stx %g3, [%g2] | |
| 279 | ldx [%g2], %g3 | |
| 280 | ||
| 281 | XmtUsrEvnt1: nop; | |
| 282 | ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h20", 1 ) | |
| 283 | ldx [%g2], %g3 | |
| 284 | ldx [%g2], %g3 | |
| 285 | ldx [%g2], %g3 | |
| 286 | ldx [%g2], %g3 | |
| 287 | ||
| 288 | ||
| 289 | ! select a CSR in the PIU and transmit the command to NCU | |
| 290 | ||
| 291 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2 | |
| 292 | set 0x020, %g4 | |
| 293 | ||
| 294 | delay_loop_soc: | |
| 295 | ldx [%g2], %g5 | |
| 296 | nop | |
| 297 | nop | |
| 298 | nop | |
| 299 | nop | |
| 300 | dec %g4 | |
| 301 | brnz %g4, delay_loop_soc | |
| 302 | nop | |
| 303 | ||
| 304 | pio: | |
| 305 | ! select an IO address in PCI address range and transmit the command to NCU | |
| 306 | setx IO_RD_ADDR, %g1, %g2 | |
| 307 | ||
| 308 | ! load byte - all byte offsets within an octlet | |
| 309 | ldub [%g2 + 1*8 + 0], %l0 | |
| 310 | ||
| 311 | set 0x40, %g4 | |
| 312 | delay_loop_pio: | |
| 313 | nop | |
| 314 | nop | |
| 315 | nop | |
| 316 | nop | |
| 317 | dec %g4 | |
| 318 | brnz %g4, delay_loop_pio | |
| 319 | nop | |
| 320 | ||
| 321 | ||
| 322 | Init_flow: | |
| 323 | nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN) | |
| 324 | ||
| 325 | P_TxDMAActivate: | |
| 326 | setx MAC_ID, %g1, %o0 ! 1st Parameter | |
| 327 | setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter | |
| 328 | call SetTxDMAActive | |
| 329 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list) | |
| 330 | ||
| 331 | P_AddTxChannels : | |
| 332 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE) | |
| 333 | ||
| 334 | setx LDGIMGN, %g1, %g2 | |
| 335 | ||
| 336 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay | |
| 337 | nop | |
| 338 | ||
| 339 | P_SetTxMaxBurst : | |
| 340 | setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter : | |
| 341 | setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter | |
| 342 | call SetTxMaxBurst | |
| 343 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data) | |
| 344 | ||
| 345 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay | |
| 346 | nop | |
| 347 | ||
| 348 | P_InitTxDma: | |
| 349 | setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter : | |
| 350 | nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On) | |
| 351 | call InitTxDma | |
| 352 | nop | |
| 353 | ||
| 354 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay | |
| 355 | nop | |
| 356 | ||
| 357 | ||
| 358 | Gen_Packet: | |
| 359 | nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT,0,0) | |
| 360 | nop | |
| 361 | ||
| 362 | setx 0x5, %g1, %g4 | |
| 363 | delay_loop_tmp: | |
| 364 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
| 365 | nop | |
| 366 | nop | |
| 367 | nop | |
| 368 | nop | |
| 369 | dec %g4 | |
| 370 | brnz %g4, delay_loop_tmp | |
| 371 | nop | |
| 372 | ||
| 373 | ||
| 374 | SetTxRingKick: | |
| 375 | setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE) | |
| 376 | setx NIU_TxDmaNo, %g1, %o0 | |
| 377 | ldx [%g2], %g3 | |
| 378 | nop | |
| 379 | mulx %o0, 0x200, %g5 | |
| 380 | setx TX_RING_KICK_Addr, %g1, %g2 | |
| 381 | add %g2, %g5, %g2 | |
| 382 | stxa %g3, [%g2]ASI_PRIMARY_LITTLE | |
| 383 | nop | |
| 384 | ||
| 385 | SetTxCs : | |
| 386 | setx NIU_TxDmaNo, %g1, %o0 | |
| 387 | setx TX_CS_Data, %g1, %g3 | |
| 388 | mulx %o0, 0x200, %g5 | |
| 389 | setx TX_CS_Addr, %g1, %g2 | |
| 390 | add %g2, %g5, %g2 | |
| 391 | stxa %g3, [%g2]ASI_PRIMARY_LITTLE | |
| 392 | nop | |
| 393 | ||
| 394 | NIUTx_Pkt_Cnt_Chk: | |
| 395 | setx MAC_ID, %g1, %o0 | |
| 396 | setx NIU_TX_PKT_CNT, %g1, %o1 | |
| 397 | call NiuTx_check_pkt_cnt | |
| 398 | nop | |
| 399 | ||
| 400 | setx loop_count, %g1, %g4 | |
| 401 | setx LDGIMGN, %g1, %g2 | |
| 402 | ||
| 403 | delay_loop_end: | |
| 404 | ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 | |
| 405 | nop | |
| 406 | nop | |
| 407 | nop | |
| 408 | nop | |
| 409 | dec %g4 | |
| 410 | brnz %g4, delay_loop_end | |
| 411 | nop | |
| 412 | ||
| 413 | setx 0x20, %g1, %g4 | |
| 414 | delay_ras: | |
| 415 | setx 0x2000000, %g1, %g2 | |
| 416 | ldx [%g2], %g3 | |
| 417 | nop | |
| 418 | nop | |
| 419 | dec %g4 | |
| 420 | brnz %g4, delay_ras | |
| 421 | nop | |
| 422 | ||
| 423 | Check_L2_esr: | |
| 424 | setx L2ES_PA0, %l6, %g1 | |
| 425 | ldx [%g1], %g2 | |
| 426 | ||
| 427 | Verify_L2_esr: | |
| 428 | mov 0x1, %l1 | |
| 429 | sllx %l1, L2ES_MEC, %l0 | |
| 430 | sllx %l1, L2ES_LDRC, %l2 | |
| 431 | or %l0, %l2, %l2 | |
| 432 | sllx %l1, L2ES_DSC, %l3 | |
| 433 | sllx %l1, L2ES_VEC, %l4 | |
| 434 | or %l3, %l4, %l4 | |
| 435 | or %l2, %l4, %l4 | |
| 436 | cmp %l4, %g2 | |
| 437 | bne test_failed | |
| 438 | nop | |
| 439 | ||
| 440 | Check_Soc_esr: | |
| 441 | setx SOC_ESR_REG, %l7, %i0 | |
| 442 | ldx [%i0], %i1 | |
| 443 | nop | |
| 444 | ||
| 445 | ||
| 446 | Verify_Soc_esr: | |
| 447 | setx 0x8000036d8c80040c, %l7, %o3 !valid bit | |
| 448 | cmp %o3, %i1 | |
| 449 | bne test_failed | |
| 450 | nop | |
| 451 | ||
| 452 | nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID) | |
| 453 | ||
| 454 | ||
| 455 | ba test_passed | |
| 456 | nop | |
| 457 | ||
| 458 | ||
| 459 | test_passed: | |
| 460 | EXIT_GOOD | |
| 461 | ||
| 462 | test_failed: | |
| 463 | EXIT_BAD | |
| 464 | ||
| 465 | /************************************************************************ | |
| 466 | Test case data start | |
| 467 | ************************************************************************/ | |
| 468 | ||
| 469 | SECTION .DATA DATA_VA=DMA_DATA_ADDR | |
| 470 | attr_data { | |
| 471 | Name = .DATA, | |
| 472 | hypervisor, | |
| 473 | compressimage | |
| 474 | } | |
| 475 | ||
| 476 | .data | |
| 477 | .global PCIAddr9 | |
| 478 | .xword 0x0001020304050607 | |
| 479 | .xword 0x08090a0b0c0d0e0f | |
| 480 | .xword 0x1011121314151617 | |
| 481 | .xword 0x18191a1b1c1d1e1f | |
| 482 | .xword 0x2021222324252627 | |
| 483 | .xword 0x28292a2b2c2d2e2f | |
| 484 | .xword 0x3031323334353637 | |
| 485 | .xword 0x38393a3b3c3d3e3f | |
| 486 | ||
| 487 | .xword 0x4041424344454647 | |
| 488 | .xword 0x48494a4b4c4d4e4f | |
| 489 | .xword 0x5051525354555657 | |
| 490 | .xword 0x58595a5b5c5d5e5f | |
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| 549 | ||
| 550 | /************************************************************************/ | |
| 551 | ||
| 552 | ||
| 553 |