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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / Lvc_Mcu_Io_err.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: Lvc_Mcu_Io_err.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_PCIE_LINK_TRAINING
39/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
40#define MAIN_PAGE_HV_ALSO
41
42#include "err_defines.h"
43#include "hboot.s"
44#include "peu_defines.h"
45#include "niu_defines.h"
46
47
48#define DMA_DATA_ADDR 0x0000000123456700
49#define DMA_DATA_BYP_SADDR 0xfffc00003300aa00
50#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
51#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
52#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
53#define DRAM_ERR_INJ_REG_0 0x8400000290
54#define DRAM_ERR_INJ_REG_1 0x8400001290
55#define DRAM_ERR_INJ_REG_2 0x8400002290
56#define DRAM_ERR_INJ_REG_3 0x8400003290
57#define L2_ENTRY_PA 0xa000000000
58#define L2ES_LVC 34
59
60
61
62#define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) |IO_ACCESS_PA)
63
64
65/************************************************************************
66 Test case code start
67 ************************************************************************/
68.text
69.global main
70
71main:
72 ta T_CHANGE_HPRIV
73 nop
74
75set_Soc_err_Inj_reg:
76 set 0x1, %i1
77 setx 0x800001248c80040c,%i1,%i2
78 setx SOC_EJR_REG, %l7, %i3
79 stx %i2, [%i3]
80 membar 0x40
81
82
83disable_l1_DCache:
84 ldxa [%g0] ASI_LSU_CONTROL, %l0
85 ! Remove bit 2
86 andn %l0, 0x2, %l0
87 stxa %l0, [%g0] ASI_LSU_CONTROL
88
89set_L2_Directly_Mapped_Mode:
90 set 0x80, %l1
91 set 0x100,%l2
92 set 0x180, %l3
93 setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
94 add %g1,%l1,%g2
95 add %g1,%l2,%g3
96 add %g1,%l3,%g4
97 mov 0x2, %l0
98 stx %l0, [%g1]
99 stx %l0, [%g2]
100 stx %l0, [%g3]
101 stx %l0, [%g4]
102
103
104store_to_L2_way0:
105 set 0x555555, %g5
106 set 0x2200aa00, %g1
107 stx %g5, [%g1]
108 stx %g5, [%g1+8]
109 membar #Sync
110
111
112generate_VD_addr:
113 ! Generate L2 VD Diag read address
114 ! Addressing: [39:32] See PRM, [22] 1 for V/D, [17:8] set, [7:6] bank, [2:0] = 0
115 setx 0x3ffc0, %l0, %l2 ! Mask for extracting [17:6]
116 and %g1, %l2, %l7
117
118 mov 0xb6, %l0
119 sllx %l0, 32, %l0 ! Bits [39:32]
120 or %l7, %l0, %l7
121
122 mov 0x1, %l0
123 sllx %l0, 22, %l0 ! Bit [22]
124 or %l7, %l0, %l7
125
126read_l2_VD_diag:
127 ldx [%l7], %l6
128
129 ! Now confirm it is stored to way 0
130 setx 0xffff, %l0, %l2 ! Mask for [16:0]
131 and %l6, %l2, %l6 ! Valid bits at [31:16]
132
133 clr %g2 ! %g2 will store the "way"
134
135 ! Direct comparison - avoid loops to save run time
136 cmp %l6, 0x1
137 !bne test_failed
138 nop
139
140way_found:
141 ! Read L2 Data Diag - %g2 has the "way"
142 ! Addressing: [39:32] See PRM, [22] odd/even word, [21:18] way, [17:8] set, [7:6] bank, [5:3] D-word, [2:0] = 0
143 setx 0x3fff8, %l0, %l2 ! Mask for extracting [17:3]
144 and %g1, %l2, %g5
145
146 sllx %g2, 18, %l0 ! Position Way
147 or %g5, %l0, %g5
148
149 mov 0xa3, %l0
150 sllx %l0, 32, %l0 ! Bits [39:32]
151 or %g5, %l0, %g5 ! %g5 has L2 Data Diag addressing
152
153
154read_l2_data_diag:
155 ldx [%g5], %g6
156
157 ! Flip one bit from the data field
158 xor %g6, 0x80, %g6 ! save on %g6 for future reference
159write_back_with_error:
160 stx %g6, [%g5]
161
162 ! Now set allocate bits for all other 15 ways (to ensure a write-back later)
163set_allocate:
164 mov 0x1, %l0
165 sllx %l0, 22, %l1 ! L2_VD and L2_UA addressing differ on bit 22
166 xor %l7, %l1, %l7 ! change %l7 from L2_VD to L2_UA address
167
168read_l2_UA_diag:
169 ldx [%l7], %l6
170
171 sllx %l0, %g2, %l1 ! Shift "way" into its bit position
172 not %l1
173 setx 0xffff,%l5, %g2
174 and %l1, %g2 , %l1 ! Allocate bits on [15:0]
175 or %l6, %l1, %l6 ! Write 1 to all other 15 ways' allocate bits
176
177 ! also need to set ECC bits for Allocate bits (Bits [38:32])
178set_ECC_Allocate:
179 mov 0x7f, %l0
180 sllx %l0, 32, %l0
181 xor %l6, %l0, %l1
182 or %l6, %l1, %l6
183
184write_l2_UA_diag:
185 stx %l6, [%l7]
186
187 ! Now do another store with the same index but different tag - to force a Write-Back
188error_address:
189 mov 0x1, %l0
190 sllx %l0, 28, %l0
191 xor %g1, %l0, %l1 ! Flip bit 28 of previous L2 entry PA
192
193 ! This should cause L2 LDWC (bit 51)
194store_to_L2_with_error:
195 st %g3, [%l1]
196 membar #Sync
197
198XmtUsrEvnt_ldrc:
199 nop ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt_ldrc)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_SADDR, "64'h40", 1, *, * )
200
201
202
203set_DRAM_err_cnt_reg:
204 mov 0x1,%l2
205 setx DRAM_ERR_CNT_REG_PA_0,%l1,%g6
206 setx DRAM_ERR_CNT_REG_PA_1,%l1,%g3
207 setx DRAM_ERR_CNT_REG_PA_2,%l1,%g4
208 setx DRAM_ERR_CNT_REG_PA_3,%l1,%g5
209 stx %l2, [%g3]
210 stx %l2, [%g4]
211 stx %l2, [%g5]
212 stx %l2, [%g6]
213 membar 0x40
214
215set_DRAM_fbr_count_reg:
216 set 0x10000, %g6 !<16>=countone=1
217 setx DRAM_FBR_CNT_REG_PA_0, %l7, %o2
218 setx DRAM_FBR_CNT_REG_PA_1, %l7, %o3
219 setx DRAM_FBR_CNT_REG_PA_2, %l7, %o4
220 setx DRAM_FBR_CNT_REG_PA_3, %l7, %o5
221 stx %g6, [%o2]
222 stx %g6, [%o3]
223 stx %g6, [%o4]
224 stx %g6, [%o5]
225 ldx [%o2], %i1
226 ldx [%o3], %i2
227 ldx [%o4], %i3
228 ldx [%o5], %i4
229
230
231
232set_DRAM_error_inject_ch0_dac:
233 mov 0x2, %l1 ! ECC Mask (1-bit error)
234 mov 0x1, %l2
235 sllx %l2, DRAM_EI_SSHOT, %l3
236 or %l1, %l3, %l1 ! Set single shot ;
237 mov 0x1, %l2
238 sllx %l2, DRAM_EI_ENB, %l3
239 or %l1, %l3, %l1 ! Enable error injection for the next write
240 setx DRAM_ERR_INJ_REG_0, %l3, %g3
241 setx DRAM_ERR_INJ_REG_1, %l3, %g4
242 setx DRAM_ERR_INJ_REG_2, %l3, %g5
243 setx DRAM_ERR_INJ_REG_3, %l3, %g6
244 stx %l1, [%g3]
245 stx %l1, [%g4]
246 stx %l1, [%g5]
247 stx %l1, [%g6]
248 membar 0x40
249
250
251store_to_L2_way0_dac:
252 set 0x55555555, %l0
253 set 0x22000000, %g7 ! bits [21:18] select way
254 set 0x80, %l1
255 set 0x100,%l2
256 set 0x180, %l3
257 add %g7,%l1,%g2
258 add %g7,%l2,%g3
259 add %g7,%l3,%g4
260 stx %l0, [%g2]
261 membar #Sync
262 stx %l0, [%g3]
263 membar #Sync
264 stx %l0, [%g4]
265 membar #Sync
266 stx %l0, [%g7]
267 membar #Sync
268
269! Storing to same L2 way0 but different tag,this will write to mcu
270write_mcu_channel_0_dac:
271 set 0x80,%l1
272 set 0x31000000, %i3 ! bits [21:18] select way
273 add %i3,%l1,%i2
274 add %i2,%l1,%i7
275 add %i7,%l1,%i4
276 stx %g5, [%i2]
277 stx %g5, [%i3]
278 stx %g5, [%i4]
279 stx %g5, [%i7]
280 membar #Sync
281
282read_error_address0_dac:
283 ldx [%g2], %l0
284 ldx [%g3], %l1
285 ldx [%g4], %l2
286 ldx [%g7], %l3
287 membar #Sync
288
289read_error_address1_dac:
290 ldx [%g2], %l0
291 ldx [%g3], %l1
292 ldx [%g4], %l2
293 ldx [%g7], %l3
294 membar #Sync
295
296
297read_error_address2_dac:
298 ldx [%g2], %l0
299 ldx [%g3], %l1
300 ldx [%g4], %l2
301 ldx [%g7], %l3
302 membar #Sync
303
304
305
306set_inj_err_src_reg_fbr:
307 set 0x3, %g1
308 setx DRAM_FBD_INJ_ERR_SRC_REG_PA_0,%l7, %g3
309 setx DRAM_FBD_INJ_ERR_SRC_REG_PA_1,%l7, %g4
310 setx DRAM_FBD_INJ_ERR_SRC_REG_PA_2,%l7, %g5
311 setx DRAM_FBD_INJ_ERR_SRC_REG_PA_3,%l7, %g6
312 stx %g1, [%g3]
313 stx %g1, [%g4]
314 stx %g1, [%g5]
315 stx %g1, [%g6]
316 membar 0x40
317
318
319!clear_esr_first_pio:
320! setx SOC_ESR_REG, %l7, %i0
321! stx %g0, [%i0]
322
323!set_ejr_pio:
324! set 0x1, %i1
325! sllx %i1, ERR_FIELD, %i2
326! setx SOC_EJR_REG, %l7, %i3
327! stx %i2, [%i3]
328! membar 0x40
329
330 ! enable bypass in IOMMU
331 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
332 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
333 stx %g3, [%g2]
334 ldx [%g2], %g3
335
336XmtUsrEvnt1: nop;
337 ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h20", 1 )
338 ldx [%g2], %g3
339 ldx [%g2], %g3
340 ldx [%g2], %g3
341 ldx [%g2], %g3
342
343
344 ! select a CSR in the PIU and transmit the command to NCU
345
346 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2
347set 0x020, %g4
348
349delay_loop_soc:
350 ldx [%g2], %g5
351 nop
352 nop
353 nop
354 nop
355 dec %g4
356 brnz %g4, delay_loop_soc
357 nop
358
359pio:
360 ! select an IO address in PCI address range and transmit the command to NCU
361 setx IO_RD_ADDR, %g1, %g2
362
363 ! load byte - all byte offsets within an octlet
364 ldub [%g2 + 1*8 + 0], %l0
365
366 set 0x40, %g4
367delay_loop_pio:
368 nop
369 nop
370 nop
371 nop
372 dec %g4
373 brnz %g4, delay_loop_pio
374 nop
375
376
377Init_flow:
378 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)
379
380P_TxDMAActivate:
381 setx MAC_ID, %g1, %o0 ! 1st Parameter
382 setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
383 call SetTxDMAActive
384 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
385
386P_AddTxChannels :
387 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
388
389 setx LDGIMGN, %g1, %g2
390
391
392 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
393 nop
394
395P_SetTxMaxBurst :
396 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
397 setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
398 call SetTxMaxBurst
399 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
400
401 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
402 nop
403
404P_InitTxDma:
405 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
406 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
407 call InitTxDma
408 nop
409
410 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
411 nop
412
413
414Gen_Packet:
415 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT,0,0)
416 nop
417
418 setx 0x5, %g1, %g4
419delay_loop_tmp:
420 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
421 nop
422 nop
423 nop
424 nop
425 dec %g4
426 brnz %g4, delay_loop_tmp
427 nop
428
429
430SetTxRingKick:
431 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
432 setx NIU_TxDmaNo, %g1, %o0
433 ldx [%g2], %g3
434 nop
435 mulx %o0, 0x200, %g5
436 setx TX_RING_KICK_Addr, %g1, %g2
437 add %g2, %g5, %g2
438 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
439 nop
440
441SetTxCs :
442 setx NIU_TxDmaNo, %g1, %o0
443 setx TX_CS_Data, %g1, %g3
444 mulx %o0, 0x200, %g5
445 setx TX_CS_Addr, %g1, %g2
446 add %g2, %g5, %g2
447 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
448 nop
449
450NIUTx_Pkt_Cnt_Chk:
451 setx MAC_ID, %g1, %o0
452 setx NIU_TX_PKT_CNT, %g1, %o1
453 call NiuTx_check_pkt_cnt
454 nop
455
456 setx loop_count, %g1, %g4
457 setx LDGIMGN, %g1, %g2
458
459delay_loop_end:
460 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
461 nop
462 nop
463 nop
464 nop
465 dec %g4
466 brnz %g4, delay_loop_end
467 nop
468
469 setx 0x20, %g1, %g4
470delay_ras:
471 setx 0x2000000, %g1, %g2
472 ldx [%g2], %g3
473 nop
474 nop
475 dec %g4
476 brnz %g4, delay_ras
477 nop
478
479
480Check_L2_esr:
481 setx L2ES_PA0, %l6, %g1
482 ldx [%g1], %g3
483 setx 0xfffffffff0000000, %l2, %l3
484 andcc %l3, %g3, %g2
485
486Verify_L2_esr:
487 mov 0x1, %l1
488 sllx %l1, L2ES_MEC, %l0
489 sllx %l1, L2ES_LVC, %l2
490 or %l0, %l2, %l2
491 sllx %l1, L2ES_DSC, %l3
492 sllx %l1, L2ES_VEC, %l4
493 or %l3, %l4, %l4
494 or %l2, %l4, %l4
495 cmp %l4, %g2
496 bne test_failed
497 nop
498
499Check_Soc_esr:
500 setx SOC_ESR_REG, %l7, %i0
501 ldx [%i0], %i1
502 nop
503
504
505Verify_Soc_esr:
506 setx 0x8000016d8c80040c, %l7, %o3 !valid bit
507 cmp %o3, %i1
508 bne test_failed
509 nop
510
511 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)
512
513ba test_passed
514nop
515
516
517test_passed:
518 EXIT_GOOD
519
520test_failed:
521 EXIT_BAD
522
523/************************************************************************
524 Test case data start
525************************************************************************/
526
527SECTION .DATA DATA_VA=DMA_DATA_ADDR
528attr_data {
529 Name = .DATA,
530 hypervisor,
531 compressimage
532}
533
534.data
535.global PCIAddr9
536 .xword 0x0001020304050607
537 .xword 0x08090a0b0c0d0e0f
538 .xword 0x1011121314151617
539 .xword 0x18191a1b1c1d1e1f
540 .xword 0x2021222324252627
541 .xword 0x28292a2b2c2d2e2f
542 .xword 0x3031323334353637
543 .xword 0x38393a3b3c3d3e3f
544
545 .xword 0x4041424344454647
546 .xword 0x48494a4b4c4d4e4f
547 .xword 0x5051525354555657
548 .xword 0x58595a5b5c5d5e5f
549 .xword 0x6061626364656667
550 .xword 0x68696a6b6c6d6e6f
551 .xword 0x7071727374757677
552 .xword 0x78797a7b7c7d7e7f
553
554 .xword 0x8081828384858687
555 .xword 0x88898a8b8c8d8e8f
556 .xword 0x9091929394959697
557 .xword 0x98999a9b9c9d9e9f
558 .xword 0xa0a1a2a3a4a5a6a7
559 .xword 0xa8a9aaabacadaeaf
560 .xword 0xb0b1b2b3b4b5b6b7
561 .xword 0xb8b9babbbcbdbebf
562
563 .xword 0xc0c1c2c3c4c5c6c7
564 .xword 0xc8c9cacbcccdcecf
565 .xword 0xd0d1d2d3d4d5d6d7
566 .xword 0xd8d9dadbdcdddedf
567 .xword 0xe0e1e2e3e4e5e6e7
568 .xword 0xe8e9eaebecedeeef
569 .xword 0xf0f1f2f3f4f5f6f7
570 .xword 0xf8f9fafbfcfdfeff
571
572 .xword 0x0001020304050607
573 .xword 0x08090a0b0c0d0e0f
574 .xword 0x1011121314151617
575 .xword 0x18191a1b1c1d1e1f
576 .xword 0x2021222324252627
577 .xword 0x28292a2b2c2d2e2f
578 .xword 0x3031323334353637
579 .xword 0x38393a3b3c3d3e3f
580
581 .xword 0x4041424344454647
582 .xword 0x48494a4b4c4d4e4f
583 .xword 0x5051525354555657
584 .xword 0x58595a5b5c5d5e5f
585 .xword 0x6061626364656667
586 .xword 0x68696a6b6c6d6e6f
587 .xword 0x7071727374757677
588 .xword 0x78797a7b7c7d7e7f
589
590 .xword 0x8081828384858687
591 .xword 0x88898a8b8c8d8e8f
592 .xword 0x9091929394959697
593 .xword 0x98999a9b9c9d9e9f
594 .xword 0xa0a1a2a3a4a5a6a7
595 .xword 0xa8a9aaabacadaeaf
596 .xword 0xb0b1b2b3b4b5b6b7
597 .xword 0xb8b9babbbcbdbebf
598
599 .xword 0xc0c1c2c3c4c5c6c7
600 .xword 0xc8c9cacbcccdcecf
601 .xword 0xd0d1d2d3d4d5d6d7
602 .xword 0xd8d9dadbdcdddedf
603 .xword 0xe0e1e2e3e4e5e6e7
604 .xword 0xe8e9eaebecedeeef
605 .xword 0xf0f1f2f3f4f5f6f7
606 .xword 0xf8f9fafbfcfdfeff
607
608/************************************************************************/
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Full OpenSPARC design & verification tarball including full HDL.