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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_DMUSII_AP.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_DMUSII_AP.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41#define ENABLE_PCIE_LINK_TRAINING
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45#define DRAM_ERR_STAT_REG 0x8400002280
46#define L2_ERR_STAT_REG 0xAB00000100
47
48#include "err_defines.h"
49#include "hboot.s"
50#include "peu_defines.h"
51
52#define DMA_DATA_ADDR 0x0000000123456700
53
54#define DMA_DATA_BYP_ADDR1 0xfffc000123456000
55#define DMA_DATA_BYP_ADDR2 0xfffc000123456040
56#define DMA_DATA_BYP_ADDR3 0xfffc000123456080
57#define DMA_DATA_BYP_ADDR4 0xfffc000123456100
58#define DMA_DATA_BYP_ADDR5 0xfffc000123456140
59#define DMA_DATA_BYP_ADDR6 0xfffc000123456180
60#define DMA_DATA_BYP_ADDR7 0xfffc0001234561c0
61
62
63#define ERR_BITS 0x4000000
64#define ERR_BITS_EXPECT 0x8000000004000000
65
66
67/************************************************************************
68 Test case code start
69 ************************************************************************/
70.text
71.global main
72.global My_Corrected_ECC_error_trap
73.global My_Recoverable_Sw_error_trap
74
75main:
76 ta T_CHANGE_HPRIV
77 nop
78
79 clr %i7
80 clr %o6
81 clr %o7
82
83L2_err_enable:
84 set 0x3, %l1
85 mov 0xaa, %g2
86 sllx %g2, 32, %g2
87 stx %l1, [%g2]
88 stx %l1, [%g2 + 0x40]
89 stx %l1, [%g2 + 0x80]
90 stx %l1, [%g2 + 0xc0]
91 stx %l1, [%g2 + 0x100]
92 stx %l1, [%g2 + 0x140]
93 stx %l1, [%g2 + 0x180]
94 stx %l1, [%g2 + 0x1c0]
95
96dma_uev:
97 ! enable bypass in IOMMU
98 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
99 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
100 stx %g3, [%g2]
101 ldx [%g2], %g3
102
103
104uev3:
105 nop
106
107inj_err3: nop
108 !$EV trig_pc_d(0,@VA(.MAIN.inj_err3)) ->IosErrInj(DMUSII_AP, 0, 123456000)
109
110Wr_Evnt3: nop;
111 ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt3) -> EnablePCIeIgCmd ("DMARD_DROP", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 )
112
113 ldx [%g2], %g3
114esr3:
115 setx 0x8000000000000080, %g7, %g5 !SiiDmuAP
116 setx SOC_ESR_REG, %g7, %g2
117 setx 0x20, %g7, %g6
118esr_loop3:
119 dec %g6
120 cmp %g6, %g0
121 be %xcc, test_failed
122 nop
123
124 ldx [%g2], %g3
125
126 cmp %g3, %g5
127 be %xcc, eie_3
128 nop
129
130 ba esr_loop3
131 nop
132
133eie_3:
134 setx SOC_EIE_REG, %g3, %g2
135 setx 0x80,%g7, %g1 ! SiiDmuAP
136 stx %g1, [%g2]
137 membar 0x40
138
139 set 0x1, %g1 ! 1 Trap;
140 setx 0x20, %g7, %g6
141err_trap_loop3:
142 cmp %g6, %g0
143 be %xcc, test_failed
144 nop
145
146 cmp %g1, %i7
147 be %xcc, test_passed
148 nop
149
150 ba err_trap_loop3
151 nop
152
153test_passed:
154 EXIT_GOOD
155
156test_failed:
157 EXIT_BAD
158
159
160/************************************************************************
161 RAS
162 Trap Handlers
163 ************************************************************************/
164My_Recoverable_Sw_error_trap:
165 inc %i7
166
167check_desr_NcuTrap_tt40:
168 ldxa [%g0]0x4c, %g2
169 nop
170
171 setx 0xb300000000000000, %l0, %g3
172 subcc %g2, %g3, %g4
173 brnz %g4, test_failed
174 nop
175
176check_3_tt40:
177 setx 0x8000000000000080, %g7, %g5
178 setx SOC_PER_REG, %l7, %g1
179 ldx [%g1], %g2
180 sub %g2, %g5, %g3
181 brnz %g3, test_failed
182 nop
183
184
185clear_per_tt40:
186 setx SOC_PER_REG, %l7, %g1
187 stx %g0, [%g1]
188 nop
189
190clear_esr_tt40:
191 setx SOC_ESR_REG, %l7, %g1
192 stx %g0, [%g1]
193 nop
194
195trap_done_tt40:
196 retry
197 nop
198
199
200
201My_Corrected_ECC_error_trap:
202
203 ba test_failed
204 nop
205
206check_desr_tt63:
207 ldxa [%g0]0x4c, %g2
208 nop
209 setx 0x8b00000000000000, %l0, %g3
210 subcc %g2, %g3, %g4
211 brnz %g4, test_failed
212 nop
213
214checks_tt63:
215 mov 0x1, %g1
216 cmp %g1, %i7
217 be check_1_tt63
218 nop
219
220 mov 0x4, %g1
221 cmp %g1, %i7
222 be check_4_tt63
223 nop
224
225
226 mov 0x8, %g1
227 cmp %g1, %i7
228 be check_8_tt63
229 nop
230
231 ba test_failed
232 nop
233
234check_1_tt63:
235 setx 0x8000000000000008, %g7, %g5
236 setx SOC_PER_REG, %l7, %g1
237 ldx [%g1], %g2
238 sub %g2, %g5, %g3
239 brnz %g3, test_failed
240 nop
241
242 ba clear_per_tt63
243 nop
244
245check_4_tt63:
246 setx 0x8000000000000400, %g7, %g5
247 setx SOC_PER_REG, %l7, %g1
248 ldx [%g1], %g2
249 sub %g2, %g5, %g3
250 brnz %g3, test_failed
251 nop
252
253 ba clear_per_tt63
254 nop
255
256check_8_tt63:
257 setx 0x8000000004000000, %g7, %g5
258 setx SOC_PER_REG, %l7, %g1
259 ldx [%g1], %g2
260 sub %g2, %g5, %g3
261 brnz %g3, test_failed
262 nop
263
264 ba clear_per_tt63
265 nop
266
267clear_per_tt63:
268 setx SOC_PER_REG, %l7, %i0
269 stx %g0, [%i0]
270 nop
271
272clear_esr_tt63:
273 setx SOC_ESR_REG, %l7, %i0
274 stx %g0, [%i0]
275 nop
276
277
278 retry
279 nop
280
281/************************************************************************
282 Test case data start
283************************************************************************/
284
285SECTION .DATA DATA_VA=DMA_DATA_ADDR
286attr_data {
287 Name = .DATA,
288 hypervisor,
289 compressimage
290}
291
292.data
293.global PCIAddr9
294 .xword 0x0001020304050607
295 .xword 0x08090a0b0c0d0e0f
296 .xword 0x1011121314151617
297 .xword 0x18191a1b1c1d1e1f
298 .xword 0x2021222324252627
299 .xword 0x28292a2b2c2d2e2f
300 .xword 0x3031323334353637
301 .xword 0x38393a3b3c3d3e3f
302
303 .xword 0x4041424344454647
304 .xword 0x48494a4b4c4d4e4f
305 .xword 0x5051525354555657
306 .xword 0x58595a5b5c5d5e5f
307 .xword 0x6061626364656667
308 .xword 0x68696a6b6c6d6e6f
309 .xword 0x7071727374757677
310 .xword 0x78797a7b7c7d7e7f
311
312 .xword 0x8081828384858687
313 .xword 0x88898a8b8c8d8e8f
314 .xword 0x9091929394959697
315 .xword 0x98999a9b9c9d9e9f
316 .xword 0xa0a1a2a3a4a5a6a7
317 .xword 0xa8a9aaabacadaeaf
318 .xword 0xb0b1b2b3b4b5b6b7
319 .xword 0xb8b9babbbcbdbebf
320
321 .xword 0xc0c1c2c3c4c5c6c7
322 .xword 0xc8c9cacbcccdcecf
323 .xword 0xd0d1d2d3d4d5d6d7
324 .xword 0xd8d9dadbdcdddedf
325 .xword 0xe0e1e2e3e4e5e6e7
326 .xword 0xe8e9eaebecedeeef
327 .xword 0xf0f1f2f3f4f5f6f7
328 .xword 0xf8f9fafbfcfdfeff
329
330 .xword 0x0001020304050607
331 .xword 0x08090a0b0c0d0e0f
332 .xword 0x1011121314151617
333 .xword 0x18191a1b1c1d1e1f
334 .xword 0x2021222324252627
335 .xword 0x28292a2b2c2d2e2f
336 .xword 0x3031323334353637
337 .xword 0x38393a3b3c3d3e3f
338
339 .xword 0x4041424344454647
340 .xword 0x48494a4b4c4d4e4f
341 .xword 0x5051525354555657
342 .xword 0x58595a5b5c5d5e5f
343 .xword 0x6061626364656667
344 .xword 0x68696a6b6c6d6e6f
345 .xword 0x7071727374757677
346 .xword 0x78797a7b7c7d7e7f
347
348 .xword 0x8081828384858687
349 .xword 0x88898a8b8c8d8e8f
350 .xword 0x9091929394959697
351 .xword 0x98999a9b9c9d9e9f
352 .xword 0xa0a1a2a3a4a5a6a7
353 .xword 0xa8a9aaabacadaeaf
354 .xword 0xb0b1b2b3b4b5b6b7
355 .xword 0xb8b9babbbcbdbebf
356
357 .xword 0xc0c1c2c3c4c5c6c7
358 .xword 0xc8c9cacbcccdcecf
359 .xword 0xd0d1d2d3d4d5d6d7
360 .xword 0xd8d9dadbdcdddedf
361 .xword 0xe0e1e2e3e4e5e6e7
362 .xword 0xe8e9eaebecedeeef
363 .xword 0xf0f1f2f3f4f5f6f7
364 .xword 0xf8f9fafbfcfdfeff
365
366/************************************************************************/
367
Full OpenSPARC design & verification tarball including full HDL.