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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_DMUSII_CUE.s
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_DMUSII_CUE.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41#define ENABLE_PCIE_LINK_TRAINING
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45#define DRAM_ERR_STAT_REG 0x8400000280
46#define L2_ERR_STAT_REG 0xAB00000000
47
48#include "err_defines.h"
49#include "hboot.s"
50#include "peu_defines.h"
51
52#define DMA_DATA_ADDR 0x0000000123456700
53#define DMA_DATA_BYP_ADDR1 0xfffc000123456000
54#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
55#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
56
57#define DMA_DATA_ADDR 0x0000000123456700
58#define DMA_DATA_BYP_SADDR 0xfffc000123456700
59#define DMA_DATA_BYP_EADDR 0xfffc000123456800
60
61
62
63#define ERR_BITS 0x2
64#define ERR_BITS_EXPECT 0x8000000000000002
65
66
67#define SOC_NCU_SYN_REG 0x8000003038
68#define SOC_SII_SYN_REG 0x8000003030
69
70/************************************************************************
71 Test case code start
72 ************************************************************************/
73.text
74.global main
75.global My_Corrected_ECC_error_trap
76.global My_Recoverable_Sw_error_trap
77
78main:
79 ta T_CHANGE_HPRIV
80 nop
81
82 clr %i7
83 clr %o6
84 clr %o7
85 clr %i0
86
87L2_err_enable:
88 set 0x3, %l1
89 mov 0xaa, %g2
90 sllx %g2, 32, %g2
91 stx %l1, [%g2]
92 stx %l1, [%g2 + 0x40]
93 stx %l1, [%g2 + 0x80]
94 stx %l1, [%g2 + 0xc0]
95 stx %l1, [%g2 + 0x100]
96 stx %l1, [%g2 + 0x140]
97 stx %l1, [%g2 + 0x180]
98 stx %l1, [%g2 + 0x1c0]
99
100bypass_iommu:
101 ! enable bypass in IOMMU
102 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
103 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
104 stx %g3, [%g2]
105 ldx [%g2], %g3
106
107 /*******************************************************
108 RDD from DMU
109 ********************************************************/
110uev1:
111 nop
112
113inj_err_rdd:
114 nop !$EV trig_pc_d(0,@VA(.MAIN.inj_err_rdd)) ->IosErrInj(ERR_TYPE, 0, 123456000)
115
116
117dma_rdd:
118 nop
119UsrEvnt_rdd:
120 nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_DROP", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1, *, * )
121
122 ldx [%g2], %g3
123 ldx [%g2], %g3
124 ldx [%g2], %g3
125 ldx [%g2], %g3
126
127esr_rdd:
128 set 0x1, %i1
129 sllx %i1, ERR_FIELD, %g1
130 setx 0x8000000000000000, %g7, %g2
131 or %g1, %g2, %g5
132
133! setx ERR_BITS_EXPECT, %g7, %g5
134 setx SOC_ESR_REG, %g7, %g2
135 setx 0x5, %g7, %g6 ! temporarily
136esr_loop_rdd:
137 dec %g6
138 cmp %g6, %g0
139 be %xcc, test_failed
140 nop
141
142 ldx [%g2], %g3
143
144 cmp %g3, %g5
145 be %xcc, eie_reg_ones_rdd
146 nop
147
148 ba esr_loop_rdd
149 nop
150
151
152eie_reg_ones_rdd:
153 setx SOC_EIE_REG, %g3, %g2
154 setx 0xffffffffffffffff, %g3, %g1
155 stx %g1, [%g2]
156 membar 0x40
157
158 set 0x1, %g1 ! 1 Trap for NCU DmuDParity
159 ! Sets E bit
160 ! For RDD, SII does not set PA39, So no trap from L2
161 setx 0x100, %g7, %g6
162err_trap_loop_rdd:
163 cmp %g6, %g0
164 be %xcc, test_failed
165 nop
166
167 cmp %g1, %i7
168 be %xcc, check_tt_rdd
169 nop
170
171 ba err_trap_loop_rdd
172 nop
173
174check_tt_rdd:
175 mov 0x40, %l0
176 cmp %o7, %l0
177 bne %xcc, test_failed
178 nop
179
180
181
182 /*******************************************************
183 WRI from DMU
184 ********************************************************/
185dma_wri:
186 nop
187
188inj_err_wri:
189 nop !$EV trig_pc_d(0,@VA(.MAIN.inj_err_wri)) ->IosErrInj(ERR_TYPE, 0, 123456780)
190
191
192 membar 0x40
193
194UsrEvnt_wri:
195 nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR2, DMA_DATA_BYP_ADDR2, "64'h40", 1, *, * )
196
197 ldx [%g2], %g3
198 ldx [%g2], %g3
199 ldx [%g2], %g3
200 ldx [%g2], %g3
201
202esr_wri:
203 set 0x1, %i1
204 sllx %i1, ERR_FIELD, %g1
205 setx 0x8000000000000000, %g7, %g2
206 or %g1, %g2, %g5
207
208! setx ERR_BITS_EXPECT, %g7, %g5
209 setx SOC_ESR_REG, %g7, %g2
210 setx 0x100, %g7, %g6
211esr_loop_wri:
212 dec %g6
213 cmp %g6, %g0
214 be %xcc, test_failed
215 nop
216
217 ldx [%g2], %g3
218
219 cmp %g3, %g5
220 be %xcc, eie_reg_ones_wri
221 nop
222
223 ba esr_loop_wri
224 nop
225
226eie_reg_ones_wri:
227 setx SOC_EIE_REG, %g3, %g2
228 setx 0xffffffffffffffff, %g3, %g1
229 stx %g1, [%g2]
230 membar 0x40
231
232 set 0x2, %g1 ! 1 trap from rdd; 1 trap from WRI
233 setx 0x100, %g7, %g6
234err_trap_loop_wri:
235 cmp %g6, %g0
236 be %xcc, test_failed
237 nop
238
239 cmp %g1, %i7
240 be %xcc, check_tt_wri
241 nop
242
243 ba err_trap_loop_wri
244 nop
245
246check_tt_wri:
247 mov 0x40, %l0
248 cmp %o7, %l0
249 bne %xcc, test_failed
250 nop
251
252
253 /*******************************************************
254 WRM from DMU
255 ********************************************************/
256dma_wrm:
257 nop
258
259inj_err_wrm:
260 nop !$EV trig_pc_d(0,@VA(.MAIN.inj_err_wrm)) ->IosErrInj(ERR_TYPE, 0, 123456800)
261
262
263
264UsrEvnt_wrm:
265 nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR3, "64'h10", 1, *, * )
266
267 ldx [%g2], %g3
268 ldx [%g2], %g3
269 ldx [%g2], %g3
270 ldx [%g2], %g3
271
272esr_wrm:
273 set 0x1, %i1
274 sllx %i1, ERR_FIELD, %g1
275 setx 0x8000000000000000, %g7, %g2
276 or %g1, %g2, %g5
277! setx ERR_BITS_EXPECT, %g7, %g5
278 setx SOC_ESR_REG, %g7, %g2
279 setx 0x100, %g7, %g6
280esr_loop_wrm:
281 dec %g6
282 cmp %g6, %g0
283 be %xcc, test_failed
284 nop
285
286 ldx [%g2], %g3
287
288 cmp %g3, %g5
289 be %xcc, eie_reg_ones_wrm
290 nop
291
292 ba esr_loop_wrm
293 nop
294
295
296eie_reg_ones_wrm:
297 setx SOC_EIE_REG, %g3, %g2
298 setx 0xffffffffffffffff, %g3, %g1
299 stx %g1, [%g2]
300 membar 0x40
301
302 set 0x4, %g1 ! 1 trap from rdd
303 ! 1 trap from wri
304 ! 2 Traps from WRM ; one for NCU CtagUe another from L2 DAU
305 setx 0x100, %g7, %g6
306err_trap_loop_wrm:
307 cmp %g6, %g0
308 be %xcc, test_failed
309 nop
310
311 cmp %g1, %i7
312 be %xcc, check_tt_wrm
313 nop
314
315 ba err_trap_loop_wrm
316 nop
317
318check_tt_wrm:
319 mov 0x40, %l0
320 cmp %o7, %l0
321 bne %xcc, test_failed
322 nop
323
324check_l2_trap_cnt:
325 set 0x1, %l0
326 cmp %i0, %l0
327 bne test_failed
328 nop
329
330test_passed:
331 EXIT_GOOD
332
333test_failed:
334 EXIT_BAD
335
336
337/************************************************************************
338 RAS
339 Trap Handlers
340 ************************************************************************/
341My_Recoverable_Sw_error_trap:
342 ! Signal trap taken
343 setx EXECUTED, %l0, %o6
344 ! save trap type value
345 rdpr %tt, %o7
346
347 inc %i7
348
349/*
350check_Syndromes:
351 setx SOC_SII_SYN_REG, %g7, %g1
352 ldx [%g1], %g2
353
354 setx SII_SYND, %g7, %g3
355
356 cmp %g2, %g3
357 bne %xcc, test_failed
358 nop
359*/
360
361
362check_desr_NcuTrap_tt40:
363 ldxa [%g0]0x4c, %g2
364 nop
365
366 setx 0xb300000000000000, %l0, %g3
367 subcc %g2, %g3, %g4
368 brnz %g4, l2_trap
369 nop
370
371check_per_tt40:
372 set 0x1, %i1
373 sllx %i1, ERR_FIELD, %g1
374 setx 0x8000000000000000, %g7, %g2
375 or %g1, %g2, %g5
376
377! setx ERR_BITS_EXPECT, %g7, %g5 !valid bit
378
379 setx SOC_PER_REG, %l7, %g1
380 ldx [%g1], %g2
381
382 sub %g2, %g5, %g3
383 brnz %g3, test_failed
384 nop
385
386clear_per_tt40:
387 setx SOC_PER_REG, %l7, %g1
388 stx %g0, [%g1]
389 nop
390
391clear_ejr_tt40:
392 setx SOC_EJR_REG, %l7, %g1
393 stx %g0, [%g1]
394 nop
395
396clear_eie_tt40:
397 setx SOC_EIE_REG, %l7, %g1
398 stx %g0, [%g1]
399 nop
400
401clear_siisynd_tt40:
402 setx SOC_SII_ERR_SYND_REG, %l7, %g1
403 stx %g0, [%g1]
404 nop
405
406 ba trap_done_tt40
407 nop
408
409
410l2_trap:
411 nop
412 inc %i0
413
414check_desr_L2Trap_tt40:
415 setx 0xb000000000000000, %l0, %g3
416 subcc %g2, %g3, %g4
417 brnz %g4, test_failed
418 nop
419
420check_mcu2_esr_L2Trap_tt40:
421 mov 0x1, %l1
422 sllx %l1, DRAM_ES_DBU, %l0
423
424 setx DRAM_ERR_STAT_REG, %l3, %g5
425 ldx [%g5], %l3
426
427 setx 0xffffffffffff0000, %l2, %l1
428 andcc %l1, %l3, %l4 ! Donot check SYND bits
429
430 sub %l0, %l4, %i4
431 brnz %i4, test_failed
432 nop
433
434clear_mcu_esr_L2Trap_tt40:
435 stx %g0, [%g5]
436
437
438check_L2_4_ESR_L2Trap_tt40:
439 setx L2_ERR_STAT_REG, %l3, %g5
440 ldx [%g5], %l6
441
442 setx 0xfffffffff0000000, %l3, %l0
443 andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits
444
445 mov 0x1, %l1
446 sllx %l1, L2ES_DAU, %l0
447
448 mov 0x1, %l1
449 sllx %l1, L2ES_VEU, %l2
450
451 or %l0, %l2, %i4
452
453 cmp %l5, %i4
454 bne %xcc, test_failed
455 nop
456
457clear_l2_esr_L2Trap_tt40:
458 stx %g0, [%g5]
459
460trap_done_tt40:
461 retry
462 nop
463
464
465
466My_Corrected_ECC_error_trap:
467 ba test_failed
468 nop
469
470
471/************************************************************************
472 Test case data start
473************************************************************************/
474
475SECTION .DATA DATA_VA=DMA_DATA_ADDR
476attr_data {
477 Name = .DATA,
478 hypervisor,
479 compressimage
480}
481
482.data
483.global PCIAddr9
484 .xword 0x0001020304050607
485 .xword 0x08090a0b0c0d0e0f
486 .xword 0x1011121314151617
487 .xword 0x18191a1b1c1d1e1f
488 .xword 0x2021222324252627
489 .xword 0x28292a2b2c2d2e2f
490 .xword 0x3031323334353637
491 .xword 0x38393a3b3c3d3e3f
492
493 .xword 0x4041424344454647
494 .xword 0x48494a4b4c4d4e4f
495 .xword 0x5051525354555657
496 .xword 0x58595a5b5c5d5e5f
497 .xword 0x6061626364656667
498 .xword 0x68696a6b6c6d6e6f
499 .xword 0x7071727374757677
500 .xword 0x78797a7b7c7d7e7f
501
502 .xword 0x8081828384858687
503 .xword 0x88898a8b8c8d8e8f
504 .xword 0x9091929394959697
505 .xword 0x98999a9b9c9d9e9f
506 .xword 0xa0a1a2a3a4a5a6a7
507 .xword 0xa8a9aaabacadaeaf
508 .xword 0xb0b1b2b3b4b5b6b7
509 .xword 0xb8b9babbbcbdbebf
510
511 .xword 0xc0c1c2c3c4c5c6c7
512 .xword 0xc8c9cacbcccdcecf
513 .xword 0xd0d1d2d3d4d5d6d7
514 .xword 0xd8d9dadbdcdddedf
515 .xword 0xe0e1e2e3e4e5e6e7
516 .xword 0xe8e9eaebecedeeef
517 .xword 0xf0f1f2f3f4f5f6f7
518 .xword 0xf8f9fafbfcfdfeff
519
520 .xword 0x0001020304050607
521 .xword 0x08090a0b0c0d0e0f
522 .xword 0x1011121314151617
523 .xword 0x18191a1b1c1d1e1f
524 .xword 0x2021222324252627
525 .xword 0x28292a2b2c2d2e2f
526 .xword 0x3031323334353637
527 .xword 0x38393a3b3c3d3e3f
528
529 .xword 0x4041424344454647
530 .xword 0x48494a4b4c4d4e4f
531 .xword 0x5051525354555657
532 .xword 0x58595a5b5c5d5e5f
533 .xword 0x6061626364656667
534 .xword 0x68696a6b6c6d6e6f
535 .xword 0x7071727374757677
536 .xword 0x78797a7b7c7d7e7f
537
538 .xword 0x8081828384858687
539 .xword 0x88898a8b8c8d8e8f
540 .xword 0x9091929394959697
541 .xword 0x98999a9b9c9d9e9f
542 .xword 0xa0a1a2a3a4a5a6a7
543 .xword 0xa8a9aaabacadaeaf
544 .xword 0xb0b1b2b3b4b5b6b7
545 .xword 0xb8b9babbbcbdbebf
546
547 .xword 0xc0c1c2c3c4c5c6c7
548 .xword 0xc8c9cacbcccdcecf
549 .xword 0xd0d1d2d3d4d5d6d7
550 .xword 0xd8d9dadbdcdddedf
551 .xword 0xe0e1e2e3e4e5e6e7
552 .xword 0xe8e9eaebecedeeef
553 .xword 0xf0f1f2f3f4f5f6f7
554 .xword 0xf8f9fafbfcfdfeff
555
556/************************************************************************/
557
Full OpenSPARC design & verification tarball including full HDL.