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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_DmuRd_mult_ce.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_DmuRd_mult_ce.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41#define ENABLE_PCIE_LINK_TRAINING
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45#define DRAM_ERR_STAT_REG 0x8400002280
46#define L2_ERR_STAT_REG 0xAB00000100
47
48#include "err_defines.h"
49#include "hboot.s"
50#include "peu_defines.h"
51
52#define DMA_DATA_ADDR 0x0000000123456700
53#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
54#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
55#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
56
57
58
59#define ERR_BITS 0x4000408
60#define ERR_BITS_EXPECT 0x8000000004000408
61
62
63/************************************************************************
64 Test case code start
65 ************************************************************************/
66.text
67.global main
68.global My_Corrected_ECC_error_trap
69.global My_Recoverable_Sw_error_trap
70
71main:
72 ta T_CHANGE_HPRIV
73 nop
74
75 clr %i7
76 clr %o6
77 clr %o7
78
79L2_err_enable:
80 set 0x3, %l1
81 mov 0xaa, %g2
82 sllx %g2, 32, %g2
83 stx %l1, [%g2]
84 stx %l1, [%g2 + 0x40]
85 stx %l1, [%g2 + 0x80]
86 stx %l1, [%g2 + 0xc0]
87 stx %l1, [%g2 + 0x100]
88 stx %l1, [%g2 + 0x140]
89 stx %l1, [%g2 + 0x180]
90 stx %l1, [%g2 + 0x1c0]
91
92set_ejr:
93 setx ERR_BITS, %l7, %g5
94
95 setx SOC_EJR_REG, %l7, %i3
96 stx %g5, [%i3]
97 membar 0x40
98
99
100dma_uev:
101 ! enable bypass in IOMMU
102 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
103 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
104 stx %g3, [%g2]
105 ldx [%g2], %g3
106
107Rd_Evnt: nop;
108 ! $EV trig_pc_d(1, @VA(.MAIN.Rd_Evnt) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR2, "64'h40", 1 )
109
110 ldx [%g2], %g3
111 ldx [%g2], %g3
112 ldx [%g2], %g3
113 ldx [%g2], %g3
114
115
116esr:
117 setx ERR_BITS_EXPECT, %g7, %g5
118 setx SOC_ESR_REG, %g7, %g2
119 setx 0x100, %g7, %g6
120esr_loop:
121 dec %g6
122 cmp %g6, %g0
123 be %xcc, test_failed
124 nop
125
126 ldx [%g2], %g3
127
128 cmp %g3, %g5
129 be %xcc, eie_reg_ones
130 nop
131
132 ba esr_loop
133 nop
134
135eie_reg_ones:
136 setx SOC_EIE_REG, %g3, %g2
137 setx ERR_BITS, %g3, %g1
138 stx %g1, [%g2]
139 membar 0x40
140
141 set 0x1, %g1
142 setx 0x100, %g7, %g6
143err_trap_loop:
144 cmp %g6, %g0
145 be %xcc, test_failed
146 nop
147
148 cmp %g1, %i7
149 be check_tt
150 nop
151
152 ba err_trap_loop
153 nop
154
155check_tt:
156 mov 0x63, %l0
157 cmp %o7, %l0
158 bne test_failed
159 nop
160
161test_passed:
162 EXIT_GOOD
163
164test_failed:
165 EXIT_BAD
166
167
168/************************************************************************
169 RAS
170 Trap Handlers
171 ************************************************************************/
172My_Recoverable_Sw_error_trap:
173 ba test_failed
174 nop
175
176
177
178My_Corrected_ECC_error_trap:
179 ! Signal trap taken
180 setx EXECUTED, %g7, %o6
181 ! save trap type value
182 rdpr %tt, %o7
183
184 inc %i7
185
186check_desr_tt63:
187 ldxa [%g0]0x4c, %g2
188 nop
189 setx 0x8b00000000000000, %l0, %g3
190 subcc %g2, %g3, %g4
191 brnz %g4, test_failed
192 nop
193check_tt63:
194 setx ERR_BITS_EXPECT, %g7, %g5
195 setx SOC_PER_REG, %g7, %g1
196 ldx [%g1], %g2
197 sub %g2, %g5, %g3
198 brnz %g3, test_failed
199 nop
200
201clear_per_tt63:
202 setx SOC_PER_REG, %l7, %i0
203 stx %g0, [%i0]
204 nop
205
206clear_esr_tt63:
207 setx SOC_ESR_REG, %l7, %i0
208 stx %g0, [%i0]
209 nop
210
211
212 retry
213 nop
214
215
216/************************************************************************
217 Test case data start
218************************************************************************/
219
220SECTION .DATA DATA_VA=DMA_DATA_ADDR
221attr_data {
222 Name = .DATA,
223 hypervisor,
224 compressimage
225}
226
227.data
228.global PCIAddr9
229 .xword 0x0001020304050607
230 .xword 0x08090a0b0c0d0e0f
231 .xword 0x1011121314151617
232 .xword 0x18191a1b1c1d1e1f
233 .xword 0x2021222324252627
234 .xword 0x28292a2b2c2d2e2f
235 .xword 0x3031323334353637
236 .xword 0x38393a3b3c3d3e3f
237
238 .xword 0x4041424344454647
239 .xword 0x48494a4b4c4d4e4f
240 .xword 0x5051525354555657
241 .xword 0x58595a5b5c5d5e5f
242 .xword 0x6061626364656667
243 .xword 0x68696a6b6c6d6e6f
244 .xword 0x7071727374757677
245 .xword 0x78797a7b7c7d7e7f
246
247 .xword 0x8081828384858687
248 .xword 0x88898a8b8c8d8e8f
249 .xword 0x9091929394959697
250 .xword 0x98999a9b9c9d9e9f
251 .xword 0xa0a1a2a3a4a5a6a7
252 .xword 0xa8a9aaabacadaeaf
253 .xword 0xb0b1b2b3b4b5b6b7
254 .xword 0xb8b9babbbcbdbebf
255
256 .xword 0xc0c1c2c3c4c5c6c7
257 .xword 0xc8c9cacbcccdcecf
258 .xword 0xd0d1d2d3d4d5d6d7
259 .xword 0xd8d9dadbdcdddedf
260 .xword 0xe0e1e2e3e4e5e6e7
261 .xword 0xe8e9eaebecedeeef
262 .xword 0xf0f1f2f3f4f5f6f7
263 .xword 0xf8f9fafbfcfdfeff
264
265 .xword 0x0001020304050607
266 .xword 0x08090a0b0c0d0e0f
267 .xword 0x1011121314151617
268 .xword 0x18191a1b1c1d1e1f
269 .xword 0x2021222324252627
270 .xword 0x28292a2b2c2d2e2f
271 .xword 0x3031323334353637
272 .xword 0x38393a3b3c3d3e3f
273
274 .xword 0x4041424344454647
275 .xword 0x48494a4b4c4d4e4f
276 .xword 0x5051525354555657
277 .xword 0x58595a5b5c5d5e5f
278 .xword 0x6061626364656667
279 .xword 0x68696a6b6c6d6e6f
280 .xword 0x7071727374757677
281 .xword 0x78797a7b7c7d7e7f
282
283 .xword 0x8081828384858687
284 .xword 0x88898a8b8c8d8e8f
285 .xword 0x9091929394959697
286 .xword 0x98999a9b9c9d9e9f
287 .xword 0xa0a1a2a3a4a5a6a7
288 .xword 0xa8a9aaabacadaeaf
289 .xword 0xb0b1b2b3b4b5b6b7
290 .xword 0xb8b9babbbcbdbebf
291
292 .xword 0xc0c1c2c3c4c5c6c7
293 .xword 0xc8c9cacbcccdcecf
294 .xword 0xd0d1d2d3d4d5d6d7
295 .xword 0xd8d9dadbdcdddedf
296 .xword 0xe0e1e2e3e4e5e6e7
297 .xword 0xe8e9eaebecedeeef
298 .xword 0xf0f1f2f3f4f5f6f7
299 .xword 0xf8f9fafbfcfdfeff
300
301/************************************************************************/
302
Full OpenSPARC design & verification tarball including full HDL.