[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_DmuWrRd_mult_err.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_adv_DmuWrRd_mult_err.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#define  DRAM_ERR_STAT_REG              0x8400002280
#define  L2_ERR_STAT_REG                0xAB00000100

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_ADDR1      0xfffc000123456700
#define DMA_DATA_BYP_ADDR2      0xfffc000123456780
#define DMA_DATA_BYP_ADDR3      0xfffc000123456800


#define ERR_BITS                0x2c82
#define ERR_BITS_EXPECT         0x8000000000002c82

    
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

	clr	%i7
	clr	%o6
	clr	%o7

L2_4_err_enable:
        set	0x3, %l1 
        mov     0xaa, %g2
        sllx    %g2, 32, %g2
        stx     %l1, [%g2 + 0x100]


set_ejr:
        setx   	ERR_BITS, %l7, %g5

        setx    SOC_EJR_REG, %l7, %i3
        stx     %g5, [%i3]
        membar  0x40


dma_uev:
        ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

Rd_Evnt: nop;
        ! $EV trig_pc_d(1, @VA(.MAIN.Rd_Evnt) -> EnablePCIeIgCmd ("DMARD_DROP", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR2, "64'h40", 1 )

        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3


esr:
        setx    ERR_BITS_EXPECT, %g7, %g5
        setx    SOC_ESR_REG, %g7, %g2
        setx    0x100, %g7, %g6
esr_loop:
        dec     %g6
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop

        ldx     [%g2], %g3

        cmp     %g3, %g5
        be      %xcc, eie_reg_ones
        nop

        ba      esr_loop
        nop

eie_reg_ones:
        setx    SOC_EIE_REG, %g3, %g2
        setx    ERR_BITS, %g3, %g1
        stx     %g1, [%g2]
        membar  0x40

	set	0x1, %g1
        setx    0x100, %g7, %g6
err_trap_loop:
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop

	cmp	%g1, %i7
	be	check_tt
	nop

	ba	err_trap_loop
	nop

check_tt:
        mov     0x40, %l0
        cmp     %o7, %l0
        bne     test_failed
        nop

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

        inc	%i7

check_desr_NcuTrap_tt40:
        ldxa  [%g0]0x4c, %g2
        nop

        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, l2_trap 
	nop

check_per_tt40:
        setx    ERR_BITS_EXPECT, %g7, %g5

        setx    SOC_PER_REG, %l7, %g1
        ldx     [%g1], %g2

        sub     %g2, %g5, %g3
        brnz    %g3, test_failed
        nop

clear_per_tt40:
        setx    SOC_PER_REG, %l7, %g1
        stx     %g0, [%g1]
        nop

	ba	trap_done_tt40
	nop


l2_trap:
	nop
check_desr_L2Trap_tt40:
        setx    0xb000000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 
        nop

check_mcu2_esr_L2Trap_tt40:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_DBU, %l0

        setx  DRAM_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l3

        setx  0xffffffffffff0000, %l2, %l1
        andcc %l1, %l3, %l4                   ! Donot check SYND bits

        sub     %l0, %l4, %i4
        brnz    %i4, test_failed
        nop

clear_mcu_esr_L2Trap_tt40:
        stx     %g0, [%g5]


check_L2_4_ESR_L2Trap_tt40:
        setx  	L2_ERR_STAT_REG, %l3, %g5  
        ldx   	[%g5], %l6

        setx  	0xfffffffff0000000, %l3, %l0
        andcc 	%l0, %l6, %l5                   ! Donot check L2ESR SYND bits

        mov   	0x1, %l1
        sllx  	%l1, L2ES_DRU, %l0

        mov   	0x1, %l1
        sllx  	%l1, L2ES_VEU, %l2

        or    	%l0, %l2, %i4

        cmp   	%l5, %i4
        bne   	%xcc, test_failed
        nop

clear_l2_esr_L2Trap_tt40:
	stx	%g0, [%g5]

trap_done_tt40:
       	done 
        nop


My_Corrected_ECC_error_trap:
	ba	test_failed
        nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_adv_DmuWrRd_mult_err.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#define DRAM_ERR_STAT_REG 0x8400002280
	46	#define L2_ERR_STAT_REG 0xAB00000100
	47
	48	#include "err_defines.h"
	49	#include "hboot.s"
	50	#include "peu_defines.h"
	51
	52	#define DMA_DATA_ADDR 0x0000000123456700
	53	#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
	54	#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
	55	#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
	56
	57
	58
	59	#define ERR_BITS 0x2c82
	60	#define ERR_BITS_EXPECT 0x8000000000002c82
	61
	62
	63	/************************************************************************
	64	Test case code start
65	************************************************************************/
66	.text
67	.global main
68	.global My_Corrected_ECC_error_trap
69	.global My_Recoverable_Sw_error_trap
70
71	main:
72	ta T_CHANGE_HPRIV
73	nop
74
75	clr %i7
76	clr %o6
77	clr %o7
78
79	L2_4_err_enable:
80	set 0x3, %l1
81	mov 0xaa, %g2
82	sllx %g2, 32, %g2
83	stx %l1, [%g2 + 0x100]
84
85
86	set_ejr:
87	setx ERR_BITS, %l7, %g5
88
89	setx SOC_EJR_REG, %l7, %i3
90	stx %g5, [%i3]
91	membar 0x40
92
93
94	dma_uev:
95	! enable bypass in IOMMU
96	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
97	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
98	stx %g3, [%g2]
99	ldx [%g2], %g3
100
101	Rd_Evnt: nop;
102	! $EV trig_pc_d(1, @VA(.MAIN.Rd_Evnt) -> EnablePCIeIgCmd ("DMARD_DROP", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR2, "64'h40", 1 )
103
104	ldx [%g2], %g3
105	ldx [%g2], %g3
106	ldx [%g2], %g3
107	ldx [%g2], %g3
108
109
110	esr:
111	setx ERR_BITS_EXPECT, %g7, %g5
112	setx SOC_ESR_REG, %g7, %g2
113	setx 0x100, %g7, %g6
114	esr_loop:
115	dec %g6
116	cmp %g6, %g0
117	be %xcc, test_failed
118	nop
119
120	ldx [%g2], %g3
121
122	cmp %g3, %g5
123	be %xcc, eie_reg_ones
124	nop
125
126	ba esr_loop
127	nop
128
129	eie_reg_ones:
130	setx SOC_EIE_REG, %g3, %g2
131	setx ERR_BITS, %g3, %g1
132	stx %g1, [%g2]
133	membar 0x40
134
135	set 0x1, %g1
136	setx 0x100, %g7, %g6
137	err_trap_loop:
138	cmp %g6, %g0
139	be %xcc, test_failed
140	nop
141
142	cmp %g1, %i7
143	be check_tt
144	nop
145
146	ba err_trap_loop
147	nop
148
149	check_tt:
150	mov 0x40, %l0
151	cmp %o7, %l0
152	bne test_failed
153	nop
154
155	test_passed:
156	EXIT_GOOD
157
158	test_failed:
159	EXIT_BAD
160
161
162	/************************************************************************
163	RAS
164	Trap Handlers
165	************************************************************************/
166	My_Recoverable_Sw_error_trap:
167	! Signal trap taken
168	setx EXECUTED, %l0, %o6
169	! save trap type value
170	rdpr %tt, %o7
171
172	inc %i7
173
174	check_desr_NcuTrap_tt40:
175	ldxa [%g0]0x4c, %g2
176	nop
177
178	setx 0xb300000000000000, %l0, %g3
179	subcc %g2, %g3, %g4
180	brnz %g4, l2_trap
181	nop
182
183	check_per_tt40:
184	setx ERR_BITS_EXPECT, %g7, %g5
185
186	setx SOC_PER_REG, %l7, %g1
187	ldx [%g1], %g2
188
189	sub %g2, %g5, %g3
190	brnz %g3, test_failed
191	nop
192
193	clear_per_tt40:
194	setx SOC_PER_REG, %l7, %g1
195	stx %g0, [%g1]
196	nop
197
198	ba trap_done_tt40
199	nop
200
201
202	l2_trap:
203	nop
204	check_desr_L2Trap_tt40:
205	setx 0xb000000000000000, %l0, %g3
206	subcc %g2, %g3, %g4
207	brnz %g4, test_failed
208	nop
209
210	check_mcu2_esr_L2Trap_tt40:
211	mov 0x1, %l1
212	sllx %l1, DRAM_ES_DBU, %l0
213
214	setx DRAM_ERR_STAT_REG, %l3, %g5
215	ldx [%g5], %l3
216
217	setx 0xffffffffffff0000, %l2, %l1
218	andcc %l1, %l3, %l4 ! Donot check SYND bits
219
220	sub %l0, %l4, %i4
221	brnz %i4, test_failed
222	nop
223
224	clear_mcu_esr_L2Trap_tt40:
225	stx %g0, [%g5]
226
227
228	check_L2_4_ESR_L2Trap_tt40:
229	setx L2_ERR_STAT_REG, %l3, %g5
230	ldx [%g5], %l6
231
232	setx 0xfffffffff0000000, %l3, %l0
233	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits
234
235	mov 0x1, %l1
236	sllx %l1, L2ES_DRU, %l0
237
238	mov 0x1, %l1
239	sllx %l1, L2ES_VEU, %l2
240
241	or %l0, %l2, %i4
242
243	cmp %l5, %i4
244	bne %xcc, test_failed
245	nop
246
247	clear_l2_esr_L2Trap_tt40:
248	stx %g0, [%g5]
249
250	trap_done_tt40:
251	done
252	nop
253
254
255
256	My_Corrected_ECC_error_trap:
257	ba test_failed
258	nop
259
260
261	/************************************************************************
262	Test case data start
263	************************************************************************/
264
265	SECTION .DATA DATA_VA=DMA_DATA_ADDR
266	attr_data {
267	Name = .DATA,
268	hypervisor,
269	compressimage
270	}
271
272	.data
273	.global PCIAddr9
274	.xword 0x0001020304050607
275	.xword 0x08090a0b0c0d0e0f
276	.xword 0x1011121314151617
277	.xword 0x18191a1b1c1d1e1f
278	.xword 0x2021222324252627
279	.xword 0x28292a2b2c2d2e2f
280	.xword 0x3031323334353637
281	.xword 0x38393a3b3c3d3e3f
282
283	.xword 0x4041424344454647
284	.xword 0x48494a4b4c4d4e4f
285	.xword 0x5051525354555657
286	.xword 0x58595a5b5c5d5e5f
287	.xword 0x6061626364656667
288	.xword 0x68696a6b6c6d6e6f
289	.xword 0x7071727374757677
290	.xword 0x78797a7b7c7d7e7f
291
292	.xword 0x8081828384858687
293	.xword 0x88898a8b8c8d8e8f
294	.xword 0x9091929394959697
295	.xword 0x98999a9b9c9d9e9f
296	.xword 0xa0a1a2a3a4a5a6a7
297	.xword 0xa8a9aaabacadaeaf
298	.xword 0xb0b1b2b3b4b5b6b7
299	.xword 0xb8b9babbbcbdbebf
300
301	.xword 0xc0c1c2c3c4c5c6c7
302	.xword 0xc8c9cacbcccdcecf
303	.xword 0xd0d1d2d3d4d5d6d7
304	.xword 0xd8d9dadbdcdddedf
305	.xword 0xe0e1e2e3e4e5e6e7
306	.xword 0xe8e9eaebecedeeef
307	.xword 0xf0f1f2f3f4f5f6f7
308	.xword 0xf8f9fafbfcfdfeff
309
310	.xword 0x0001020304050607
311	.xword 0x08090a0b0c0d0e0f
312	.xword 0x1011121314151617
313	.xword 0x18191a1b1c1d1e1f
314	.xword 0x2021222324252627
315	.xword 0x28292a2b2c2d2e2f
316	.xword 0x3031323334353637
317	.xword 0x38393a3b3c3d3e3f
318
319	.xword 0x4041424344454647
320	.xword 0x48494a4b4c4d4e4f
321	.xword 0x5051525354555657
322	.xword 0x58595a5b5c5d5e5f
323	.xword 0x6061626364656667
324	.xword 0x68696a6b6c6d6e6f
325	.xword 0x7071727374757677
326	.xword 0x78797a7b7c7d7e7f
327
328	.xword 0x8081828384858687
329	.xword 0x88898a8b8c8d8e8f
330	.xword 0x9091929394959697
331	.xword 0x98999a9b9c9d9e9f
332	.xword 0xa0a1a2a3a4a5a6a7
333	.xword 0xa8a9aaabacadaeaf
334	.xword 0xb0b1b2b3b4b5b6b7
335	.xword 0xb8b9babbbcbdbebf
336
337	.xword 0xc0c1c2c3c4c5c6c7
338	.xword 0xc8c9cacbcccdcecf
339	.xword 0xd0d1d2d3d4d5d6d7
340	.xword 0xd8d9dadbdcdddedf
341	.xword 0xe0e1e2e3e4e5e6e7
342	.xword 0xe8e9eaebecedeeef
343	.xword 0xf0f1f2f3f4f5f6f7
344	.xword 0xf8f9fafbfcfdfeff
345
346	/************************************************************************/
347