[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_DmuWri_DP.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_adv_DmuWri_DP.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap
#define H_HT0_Data_access_error_0x32  My_Precise_data_access_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#define  DRAM_ERR_STAT_REG              0x8400002280
#define  L2_ERR_STAT_REG                0xAB00000100

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_ADDR1      0xfffc000123456700
#define DMA_DATA_BYP_ADDR2      0xfffc000123456780
#define DMA_DATA_BYP_ADDR3      0xfffc000123456800


#define ERR_BITS                0x20
#define ERR_BITS_EXPECT         0x8000000000000020

    
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap
.global  My_Precise_data_access_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

	clr	%i7
	clr	%o6
	clr	%o7
	clr	%i6

L2_4_err_enable:
        set	0x3, %l1 
        mov     0xaa, %g2
        sllx    %g2, 32, %g2
        stx     %l1, [%g2 + 0x100]


set_ejr:
        set    	ERR_BITS, %g5

        setx    SOC_EJR_REG, %l7, %i3
        stx     %g5, [%i3]
        membar  0x40


dma_uev:
        ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

XmtUsrEvnt1: nop;
        ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 )
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3

esr:
        setx    ERR_BITS_EXPECT, %g7, %g5
        setx    SOC_ESR_REG, %g7, %g2
        setx    0x100, %g7, %g6
esr_loop:
        dec     %g6
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop

        ldx     [%g2], %g3

        cmp     %g3, %g5
        be      %xcc, Core_read
        nop

        ba      esr_loop
        nop

Core_read:
	setx	DMA_DATA_ADDR, %g7, %g1
        ldx     [%g1], %i1
	membar	0x40


read_l2_esr:
        setx    L2_ERR_STAT_REG, %l3, %g5  
        ldx     [%g5], %l6
	
eie_reg_ones:
        setx    SOC_EIE_REG, %g3, %g2
        set     ERR_BITS, %g1
        stx     %g1, [%g2]
        membar  0x40


	! 2 TT=0x40 taken
	set	0x2, %g1 	!While executing this instr, gets the trap; does not complete it
				!at the completion goes to the next instruction as it has the 'done'
				!instruction there; so %g1 never gets 0x2;
				!solution: use 'retry' not 'done' 
        setx    0x200, %g7, %g6		! TEMPORIRILY ; increase to 0x200 after bug fix
err_trap_loop:
	dec	%g6

        cmp     %g6, %g0
        be      %xcc, test_failed
        nop

	cmp	%g1, %i7
	be	check_tt
	nop

	ba	err_trap_loop
	nop

check_tt:
        mov     0x40, %l0
        cmp     %o7, %l0
        bne     test_failed
        nop

check_tt32_taken:
	set	0x1, %g1
	cmp	%g1, %i6
	bne	test_failed
	nop
	nop
	nop

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

        inc	%i7

check_desr_NcuTrap_tt40:
        ldxa  [%g0]0x4c, %g2
        nop

        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, l2_trap 
	nop

check_per_tt40:
        set     0x1, %g1
        sllx    %g1, SiiDmuDParity, %g2

        setx    0x8000000000000000, %g7, %g4    !valid bit
        or      %g2, %g4, %g5

        setx    SOC_PER_REG, %l7, %g1
        ldx     [%g1], %g2

        sub     %g2, %g5, %g3
        brnz    %g3, test_failed
        nop

clear_per_tt40:
        setx    SOC_PER_REG, %l7, %g1
        stx     %g0, [%g1]
        nop

	ba	trap_done_tt40
	nop


l2_trap:
	nop
check_desr_L2Trap_tt40:
        setx    0xb000000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 
        nop


check_mcu2_esr_L2Trap_tt40:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_DAU, %l0

        setx  DRAM_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l3

        setx  0x7fffffffffff0000, %l2, %l1
        andcc %l1, %l3, %l4                   ! Donot check SYND bits and MEU

        sub     %l0, %l4, %i4
        brnz    %i4, test_failed
        nop

clear_mcu_esr_L2Trap_tt40:
        stx     %g0, [%g5]

check_L2_4_ESR_L2Trap_tt40:
        setx  	L2_ERR_STAT_REG, %l3, %g5  
        ldx   	[%g5], %l6

        setx  	0x7ffffffff0000000, %l3, %l0
        andcc 	%l0, %l6, %l5                   ! Donot check L2ESR SYND bits and MEU bit

        mov   	0x1, %l1
        sllx  	%l1, L2ES_DAU, %l0

        mov   	0x1, %l1
        sllx  	%l1, L2ES_VEU, %l2

        or    	%l0, %l2, %i4

        cmp   	%l5, %i4
        bne   	%xcc, test_failed
        nop

clear_l2_esr_L2Trap_tt40:
	stx	%g0, [%g5]


trap_done_tt40:
       	retry 
        nop


/***********************************************************/
My_Corrected_ECC_error_trap:
	ba	test_failed
        nop


/***********************************************************/
My_Precise_data_access_error_trap:
	nop

	inc	%i6
check_L2Notdata_reg:
	setx  	0xAE00000000, %l7, %g3
	ldx  	[%g3], %g2

        setx    0xAE00000040, %l7, %g3
        ldx     [%g3], %g2

        setx    0xAE00000080, %l7, %g3
        ldx     [%g3], %g2

        setx    0xAE000000c0, %l7, %g3
        ldx     [%g3], %g2

        setx    0xAE00000100, %l7, %g3
        ldx     [%g3], %g2

        setx    0xAE00000140, %l7, %g3
        ldx     [%g3], %g2

        setx    0xAE00000180, %l7, %g3
        ldx     [%g3], %g2

        setx    0xAE000001c0, %l7, %g3
        ldx     [%g3], %g2


check_DSFSR:
	set  0x18, %g3
	ldxa  [%g3] 0x58, %g2

	set 0xf, %l1
	and  %g2, %l1, %l3
	mov  0x1, %l5
	cmp  %l5, %l3
	bne  test_failed
	nop


check_mcu_esr_L2Trap_tt32:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_DAU, %l0

        setx  DRAM_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l3

        setx  0x7fffffffffff0000, %l2, %l1
        andcc %l1, %l3, %l4                   ! Donot check SYND bits and MEU

        sub     %l0, %l4, %i4
        brnz    %i4, test_failed
        nop

clear_mcu_esr_L2Trap_tt32:
        stx     %g0, [%g5]

check_L2_4_ESR_L2Trap_tt32:
        setx    L2_ERR_STAT_REG, %l3, %g5  
        ldx     [%g5], %l6

        setx    0x7ffffffff0000000, %l3, %l0
        andcc   %l0, %l6, %l5                   ! Donot check L2ESR SYND bits and MEU

        mov     0x1, %l1
        sllx    %l1, L2ES_DAU, %l0

        mov     0x1, %l1
        sllx    %l1, L2ES_VEU, %l2

        or      %l0, %l2, %i4

        cmp     %l5, %i4
        bne     %xcc, test_failed
        nop

clear_l2_esr_L2Trap_tt32:
        stx     %g0, [%g5]


trap_done_tt32:
       	done 
        nop

/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_adv_DmuWri_DP.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40	#define H_HT0_Data_access_error_0x32 My_Precise_data_access_error_trap
	41
	42	#define ENABLE_PCIE_LINK_TRAINING
	43	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	44	#define MAIN_PAGE_HV_ALSO
	45
	46	#define DRAM_ERR_STAT_REG 0x8400002280
	47	#define L2_ERR_STAT_REG 0xAB00000100
	48
	49	#include "err_defines.h"
	50	#include "hboot.s"
	51	#include "peu_defines.h"
	52
	53	#define DMA_DATA_ADDR 0x0000000123456700
	54	#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
	55	#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
	56	#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
	57
	58
	59
	60	#define ERR_BITS 0x20
	61	#define ERR_BITS_EXPECT 0x8000000000000020
	62
	63
	64	/************************************************************************
65	Test case code start
66	************************************************************************/
67	.text
68	.global main
69	.global My_Corrected_ECC_error_trap
70	.global My_Recoverable_Sw_error_trap
71	.global My_Precise_data_access_error_trap
72
73	main:
74	ta T_CHANGE_HPRIV
75	nop
76
77	clr %i7
78	clr %o6
79	clr %o7
80	clr %i6
81
82	L2_4_err_enable:
83	set 0x3, %l1
84	mov 0xaa, %g2
85	sllx %g2, 32, %g2
86	stx %l1, [%g2 + 0x100]
87
88
89	set_ejr:
90	set ERR_BITS, %g5
91
92	setx SOC_EJR_REG, %l7, %i3
93	stx %g5, [%i3]
94	membar 0x40
95
96
97	dma_uev:
98	! enable bypass in IOMMU
99	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
100	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
101	stx %g3, [%g2]
102	ldx [%g2], %g3
103
104	XmtUsrEvnt1: nop;
105	! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 )
106	ldx [%g2], %g3
107	ldx [%g2], %g3
108	ldx [%g2], %g3
109	ldx [%g2], %g3
110
111	esr:
112	setx ERR_BITS_EXPECT, %g7, %g5
113	setx SOC_ESR_REG, %g7, %g2
114	setx 0x100, %g7, %g6
115	esr_loop:
116	dec %g6
117	cmp %g6, %g0
118	be %xcc, test_failed
119	nop
120
121	ldx [%g2], %g3
122
123	cmp %g3, %g5
124	be %xcc, Core_read
125	nop
126
127	ba esr_loop
128	nop
129
130	Core_read:
131	setx DMA_DATA_ADDR, %g7, %g1
132	ldx [%g1], %i1
133	membar 0x40
134
135
136	read_l2_esr:
137	setx L2_ERR_STAT_REG, %l3, %g5
138	ldx [%g5], %l6
139
140	eie_reg_ones:
141	setx SOC_EIE_REG, %g3, %g2
142	set ERR_BITS, %g1
143	stx %g1, [%g2]
144	membar 0x40
145
146
147	! 2 TT=0x40 taken
148	set 0x2, %g1 !While executing this instr, gets the trap; does not complete it
149	!at the completion goes to the next instruction as it has the 'done'
150	!instruction there; so %g1 never gets 0x2;
151	!solution: use 'retry' not 'done'
152	setx 0x200, %g7, %g6 ! TEMPORIRILY ; increase to 0x200 after bug fix
153	err_trap_loop:
154	dec %g6
155
156	cmp %g6, %g0
157	be %xcc, test_failed
158	nop
159
160	cmp %g1, %i7
161	be check_tt
162	nop
163
164	ba err_trap_loop
165	nop
166
167	check_tt:
168	mov 0x40, %l0
169	cmp %o7, %l0
170	bne test_failed
171	nop
172
173	check_tt32_taken:
174	set 0x1, %g1
175	cmp %g1, %i6
176	bne test_failed
177	nop
178	nop
179	nop
180
181	test_passed:
182	EXIT_GOOD
183
184	test_failed:
185	EXIT_BAD
186
187
188	/************************************************************************
189	RAS
190	Trap Handlers
191	************************************************************************/
192	My_Recoverable_Sw_error_trap:
193	! Signal trap taken
194	setx EXECUTED, %l0, %o6
195	! save trap type value
196	rdpr %tt, %o7
197
198	inc %i7
199
200	check_desr_NcuTrap_tt40:
201	ldxa [%g0]0x4c, %g2
202	nop
203
204	setx 0xb300000000000000, %l0, %g3
205	subcc %g2, %g3, %g4
206	brnz %g4, l2_trap
207	nop
208
209	check_per_tt40:
210	set 0x1, %g1
211	sllx %g1, SiiDmuDParity, %g2
212
213	setx 0x8000000000000000, %g7, %g4 !valid bit
214	or %g2, %g4, %g5
215
216	setx SOC_PER_REG, %l7, %g1
217	ldx [%g1], %g2
218
219	sub %g2, %g5, %g3
220	brnz %g3, test_failed
221	nop
222
223	clear_per_tt40:
224	setx SOC_PER_REG, %l7, %g1
225	stx %g0, [%g1]
226	nop
227
228	ba trap_done_tt40
229	nop
230
231
232	l2_trap:
233	nop
234	check_desr_L2Trap_tt40:
235	setx 0xb000000000000000, %l0, %g3
236	subcc %g2, %g3, %g4
237	brnz %g4, test_failed
238	nop
239
240
241	check_mcu2_esr_L2Trap_tt40:
242	mov 0x1, %l1
243	sllx %l1, DRAM_ES_DAU, %l0
244
245	setx DRAM_ERR_STAT_REG, %l3, %g5
246	ldx [%g5], %l3
247
248	setx 0x7fffffffffff0000, %l2, %l1
249	andcc %l1, %l3, %l4 ! Donot check SYND bits and MEU
250
251	sub %l0, %l4, %i4
252	brnz %i4, test_failed
253	nop
254
255	clear_mcu_esr_L2Trap_tt40:
256	stx %g0, [%g5]
257
258	check_L2_4_ESR_L2Trap_tt40:
259	setx L2_ERR_STAT_REG, %l3, %g5
260	ldx [%g5], %l6
261
262	setx 0x7ffffffff0000000, %l3, %l0
263	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEU bit
264
265	mov 0x1, %l1
266	sllx %l1, L2ES_DAU, %l0
267
268	mov 0x1, %l1
269	sllx %l1, L2ES_VEU, %l2
270
271	or %l0, %l2, %i4
272
273	cmp %l5, %i4
274	bne %xcc, test_failed
275	nop
276
277	clear_l2_esr_L2Trap_tt40:
278	stx %g0, [%g5]
279
280
281	trap_done_tt40:
282	retry
283	nop
284
285
286	/***********************************************************/
287	My_Corrected_ECC_error_trap:
288	ba test_failed
289	nop
290
291
292
293
294
295
296	/***********************************************************/
297	My_Precise_data_access_error_trap:
298	nop
299
300	inc %i6
301	check_L2Notdata_reg:
302	setx 0xAE00000000, %l7, %g3
303	ldx [%g3], %g2
304
305	setx 0xAE00000040, %l7, %g3
306	ldx [%g3], %g2
307
308	setx 0xAE00000080, %l7, %g3
309	ldx [%g3], %g2
310
311	setx 0xAE000000c0, %l7, %g3
312	ldx [%g3], %g2
313
314	setx 0xAE00000100, %l7, %g3
315	ldx [%g3], %g2
316
317	setx 0xAE00000140, %l7, %g3
318	ldx [%g3], %g2
319
320	setx 0xAE00000180, %l7, %g3
321	ldx [%g3], %g2
322
323	setx 0xAE000001c0, %l7, %g3
324	ldx [%g3], %g2
325
326
327	check_DSFSR:
328	set 0x18, %g3
329	ldxa [%g3] 0x58, %g2
330
331	set 0xf, %l1
332	and %g2, %l1, %l3
333	mov 0x1, %l5
334	cmp %l5, %l3
335	bne test_failed
336	nop
337
338
339	check_mcu_esr_L2Trap_tt32:
340	mov 0x1, %l1
341	sllx %l1, DRAM_ES_DAU, %l0
342
343	setx DRAM_ERR_STAT_REG, %l3, %g5
344	ldx [%g5], %l3
345
346	setx 0x7fffffffffff0000, %l2, %l1
347	andcc %l1, %l3, %l4 ! Donot check SYND bits and MEU
348
349	sub %l0, %l4, %i4
350	brnz %i4, test_failed
351	nop
352
353	clear_mcu_esr_L2Trap_tt32:
354	stx %g0, [%g5]
355
356	check_L2_4_ESR_L2Trap_tt32:
357	setx L2_ERR_STAT_REG, %l3, %g5
358	ldx [%g5], %l6
359
360	setx 0x7ffffffff0000000, %l3, %l0
361	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEU
362
363	mov 0x1, %l1
364	sllx %l1, L2ES_DAU, %l0
365
366	mov 0x1, %l1
367	sllx %l1, L2ES_VEU, %l2
368
369	or %l0, %l2, %i4
370
371	cmp %l5, %i4
372	bne %xcc, test_failed
373	nop
374
375	clear_l2_esr_L2Trap_tt32:
376	stx %g0, [%g5]
377
378
379	trap_done_tt32:
380	done
381	nop
382
383	/************************************************************************
384	Test case data start
385	************************************************************************/
386
387	SECTION .DATA DATA_VA=DMA_DATA_ADDR
388	attr_data {
389	Name = .DATA,
390	hypervisor,
391	compressimage
392	}
393
394	.data
395	.global PCIAddr9
396	.xword 0x0001020304050607
397	.xword 0x08090a0b0c0d0e0f
398	.xword 0x1011121314151617
399	.xword 0x18191a1b1c1d1e1f
400	.xword 0x2021222324252627
401	.xword 0x28292a2b2c2d2e2f
402	.xword 0x3031323334353637
403	.xword 0x38393a3b3c3d3e3f
404
405	.xword 0x4041424344454647
406	.xword 0x48494a4b4c4d4e4f
407	.xword 0x5051525354555657
408	.xword 0x58595a5b5c5d5e5f
409	.xword 0x6061626364656667
410	.xword 0x68696a6b6c6d6e6f
411	.xword 0x7071727374757677
412	.xword 0x78797a7b7c7d7e7f
413
414	.xword 0x8081828384858687
415	.xword 0x88898a8b8c8d8e8f
416	.xword 0x9091929394959697
417	.xword 0x98999a9b9c9d9e9f
418	.xword 0xa0a1a2a3a4a5a6a7
419	.xword 0xa8a9aaabacadaeaf
420	.xword 0xb0b1b2b3b4b5b6b7
421	.xword 0xb8b9babbbcbdbebf
422
423	.xword 0xc0c1c2c3c4c5c6c7
424	.xword 0xc8c9cacbcccdcecf
425	.xword 0xd0d1d2d3d4d5d6d7
426	.xword 0xd8d9dadbdcdddedf
427	.xword 0xe0e1e2e3e4e5e6e7
428	.xword 0xe8e9eaebecedeeef
429	.xword 0xf0f1f2f3f4f5f6f7
430	.xword 0xf8f9fafbfcfdfeff
431
432	.xword 0x0001020304050607
433	.xword 0x08090a0b0c0d0e0f
434	.xword 0x1011121314151617
435	.xword 0x18191a1b1c1d1e1f
436	.xword 0x2021222324252627
437	.xword 0x28292a2b2c2d2e2f
438	.xword 0x3031323334353637
439	.xword 0x38393a3b3c3d3e3f
440
441	.xword 0x4041424344454647
442	.xword 0x48494a4b4c4d4e4f
443	.xword 0x5051525354555657
444	.xword 0x58595a5b5c5d5e5f
445	.xword 0x6061626364656667
446	.xword 0x68696a6b6c6d6e6f
447	.xword 0x7071727374757677
448	.xword 0x78797a7b7c7d7e7f
449
450	.xword 0x8081828384858687
451	.xword 0x88898a8b8c8d8e8f
452	.xword 0x9091929394959697
453	.xword 0x98999a9b9c9d9e9f
454	.xword 0xa0a1a2a3a4a5a6a7
455	.xword 0xa8a9aaabacadaeaf
456	.xword 0xb0b1b2b3b4b5b6b7
457	.xword 0xb8b9babbbcbdbebf
458
459	.xword 0xc0c1c2c3c4c5c6c7
460	.xword 0xc8c9cacbcccdcecf
461	.xword 0xd0d1d2d3d4d5d6d7
462	.xword 0xd8d9dadbdcdddedf
463	.xword 0xe0e1e2e3e4e5e6e7
464	.xword 0xe8e9eaebecedeeef
465	.xword 0xf0f1f2f3f4f5f6f7
466	.xword 0xf8f9fafbfcfdfeff
467
468	/************************************************************************/
469