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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_adv_Dmu_AP.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | #define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap | |
40 | ||
41 | #define ENABLE_PCIE_LINK_TRAINING | |
42 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ | |
43 | #define MAIN_PAGE_HV_ALSO | |
44 | ||
45 | #ifdef BANK0 | |
46 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
47 | #define L2_ERR_STAT_REG 0xAB00000000 | |
48 | #endif | |
49 | ||
50 | #ifdef BANK1 | |
51 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
52 | #define L2_ERR_STAT_REG 0xAB00000040 | |
53 | #endif | |
54 | ||
55 | #ifdef BANK2 | |
56 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
57 | #define L2_ERR_STAT_REG 0xAB00000080 | |
58 | #endif | |
59 | ||
60 | #ifdef BANK3 | |
61 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
62 | #define L2_ERR_STAT_REG 0xAB000000c0 | |
63 | #endif | |
64 | ||
65 | #ifdef BANK4 | |
66 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
67 | #define L2_ERR_STAT_REG 0xAB00000100 | |
68 | #endif | |
69 | ||
70 | #ifdef BANK5 | |
71 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
72 | #define L2_ERR_STAT_REG 0xAB00000140 | |
73 | #endif | |
74 | ||
75 | #ifdef BANK6 | |
76 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
77 | #define L2_ERR_STAT_REG 0xAB00000180 | |
78 | #endif | |
79 | ||
80 | #ifdef BANK7 | |
81 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
82 | #define L2_ERR_STAT_REG 0xAB000001c0 | |
83 | #endif | |
84 | ||
85 | ||
86 | #include "err_defines.h" | |
87 | #include "hboot.s" | |
88 | #include "peu_defines.h" | |
89 | ||
90 | #define DMA_DATA_ADDR 0x0000000123456700 | |
91 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456700 | |
92 | #define DMA_DATA_BYP_ADDR2 0xfffc000123456780 | |
93 | #define DMA_DATA_BYP_ADDR3 0xfffc000123456800 | |
94 | ||
95 | #define DMA_DATA_ADDR 0x0000000123456700 | |
96 | #define DMA_DATA_BYP_SADDR 0xfffc000123456700 | |
97 | #define DMA_DATA_BYP_EADDR 0xfffc000123456800 | |
98 | ||
99 | #ifdef BANK0 | |
100 | #define DMA_DATA_BYP_ADDR1 0xfffc000123450000 | |
101 | #endif | |
102 | ||
103 | #ifdef BANK1 | |
104 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456040 | |
105 | #endif | |
106 | ||
107 | #ifdef BANK2 | |
108 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456080 | |
109 | #endif | |
110 | ||
111 | #ifdef BANK3 | |
112 | #define DMA_DATA_BYP_ADDR1 0xfffc0001234560c0 | |
113 | #endif | |
114 | ||
115 | #ifdef BANK4 | |
116 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456100 | |
117 | #endif | |
118 | ||
119 | #ifdef BANK5 | |
120 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456140 | |
121 | #endif | |
122 | ||
123 | #ifdef BANK6 | |
124 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456180 | |
125 | #endif | |
126 | ||
127 | #ifdef BANK7 | |
128 | #define DMA_DATA_BYP_ADDR1 0xfffc0001234561c0 | |
129 | #endif | |
130 | ||
131 | ||
132 | ||
133 | #define ERR_BITS 0x80 | |
134 | #define ERR_BITS_EXPECT 0x8000000000000080 | |
135 | ||
136 | ||
137 | /************************************************************************ | |
138 | Test case code start | |
139 | ************************************************************************/ | |
140 | .text | |
141 | .global main | |
142 | .global My_Corrected_ECC_error_trap | |
143 | .global My_Recoverable_Sw_error_trap | |
144 | ||
145 | main: | |
146 | ta T_CHANGE_HPRIV | |
147 | nop | |
148 | ||
149 | clr %i7 | |
150 | clr %o6 | |
151 | clr %o7 | |
152 | clr %i0 | |
153 | ||
154 | L2_err_enable: | |
155 | set 0x3, %l1 | |
156 | mov 0xaa, %g2 | |
157 | sllx %g2, 32, %g2 | |
158 | stx %l1, [%g2] | |
159 | stx %l1, [%g2 + 0x40] | |
160 | stx %l1, [%g2 + 0x80] | |
161 | stx %l1, [%g2 + 0xc0] | |
162 | stx %l1, [%g2 + 0x100] | |
163 | stx %l1, [%g2 + 0x140] | |
164 | stx %l1, [%g2 + 0x180] | |
165 | stx %l1, [%g2 + 0x1c0] | |
166 | ||
167 | bypass_iommu: | |
168 | ! enable bypass in IOMMU | |
169 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
170 | setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3 | |
171 | stx %g3, [%g2] | |
172 | ldx [%g2], %g3 | |
173 | ||
174 | /******************************************************* | |
175 | RDD from DMU | |
176 | ********************************************************/ | |
177 | set_ejr_rdd: | |
178 | set ERR_BITS, %g5 | |
179 | ||
180 | setx SOC_EJR_REG, %l7, %i3 | |
181 | stx %g5, [%i3] | |
182 | membar 0x40 | |
183 | ||
184 | dma_rdd: | |
185 | nop | |
186 | UsrEvnt_rdd: | |
187 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1, *, * ) | |
188 | ||
189 | ldx [%g2], %g3 | |
190 | ldx [%g2], %g3 | |
191 | ldx [%g2], %g3 | |
192 | ldx [%g2], %g3 | |
193 | ||
194 | esr_rdd: | |
195 | setx ERR_BITS_EXPECT, %g7, %g5 | |
196 | setx SOC_ESR_REG, %g7, %g2 | |
197 | setx 0x100, %g7, %g6 | |
198 | esr_loop_rdd: | |
199 | dec %g6 | |
200 | cmp %g6, %g0 | |
201 | be %xcc, test_failed | |
202 | nop | |
203 | ||
204 | ldx [%g2], %g3 | |
205 | ||
206 | cmp %g3, %g5 | |
207 | be %xcc, eie_reg_ones_rdd | |
208 | nop | |
209 | ||
210 | ba esr_loop_rdd | |
211 | nop | |
212 | ||
213 | ||
214 | eie_reg_ones_rdd: | |
215 | setx SOC_EIE_REG, %g3, %g2 | |
216 | set ERR_BITS, %g1 | |
217 | stx %g1, [%g2] | |
218 | membar 0x40 | |
219 | ||
220 | set 0x1, %g1 ! 1 Trap; only for NCU DmuDParity | |
221 | ! For RDD SIU does not send PA39, only sets E bit | |
222 | ! So no trap from L2 | |
223 | setx 0x100, %g7, %g6 | |
224 | err_trap_loop_rdd: | |
225 | cmp %g6, %g0 | |
226 | be %xcc, test_failed | |
227 | nop | |
228 | ||
229 | cmp %g1, %i7 | |
230 | be %xcc, check_tt_rdd | |
231 | nop | |
232 | ||
233 | ba err_trap_loop_rdd | |
234 | nop | |
235 | ||
236 | check_tt_rdd: | |
237 | mov 0x40, %l0 | |
238 | cmp %o7, %l0 | |
239 | bne %xcc, test_failed | |
240 | nop | |
241 | ||
242 | ||
243 | ||
244 | /******************************************************* | |
245 | WRI from DMU | |
246 | ********************************************************/ | |
247 | dma_wri: | |
248 | nop | |
249 | ||
250 | set_ejr_wri: | |
251 | set ERR_BITS, %g5 | |
252 | ||
253 | setx SOC_EJR_REG, %l7, %i3 | |
254 | stx %g5, [%i3] | |
255 | membar 0x40 | |
256 | ||
257 | UsrEvnt_wri: | |
258 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1, *, * ) | |
259 | ||
260 | ldx [%g2], %g3 | |
261 | ldx [%g2], %g3 | |
262 | ldx [%g2], %g3 | |
263 | ldx [%g2], %g3 | |
264 | ||
265 | esr_wri: | |
266 | setx ERR_BITS_EXPECT, %g7, %g5 | |
267 | setx SOC_ESR_REG, %g7, %g2 | |
268 | setx 0x100, %g7, %g6 | |
269 | esr_loop_wri: | |
270 | dec %g6 | |
271 | cmp %g6, %g0 | |
272 | be %xcc, test_failed | |
273 | nop | |
274 | ||
275 | ldx [%g2], %g3 | |
276 | ||
277 | cmp %g3, %g5 | |
278 | be %xcc, eie_reg_ones_wri | |
279 | nop | |
280 | ||
281 | ba esr_loop_wri | |
282 | nop | |
283 | ||
284 | eie_reg_ones_wri: | |
285 | setx SOC_EIE_REG, %g3, %g2 | |
286 | set ERR_BITS, %g1 | |
287 | stx %g1, [%g2] | |
288 | membar 0x40 | |
289 | ||
290 | set 0x2, %g1 ! 1 traps from rdd; 1 trap from WRI | |
291 | setx 0x100, %g7, %g6 | |
292 | err_trap_loop_wri: | |
293 | cmp %g6, %g0 | |
294 | be %xcc, test_failed | |
295 | nop | |
296 | ||
297 | cmp %g1, %i7 | |
298 | be %xcc, check_tt_wri | |
299 | nop | |
300 | ||
301 | ba err_trap_loop_wri | |
302 | nop | |
303 | ||
304 | check_tt_wri: | |
305 | mov 0x40, %l0 | |
306 | cmp %o7, %l0 | |
307 | bne %xcc, test_failed | |
308 | nop | |
309 | ||
310 | ||
311 | /******************************************************* | |
312 | WRM from DMU | |
313 | ********************************************************/ | |
314 | dma_wrm: | |
315 | nop | |
316 | ||
317 | set_ejr_wrm: | |
318 | set ERR_BITS, %g5 | |
319 | ||
320 | setx SOC_EJR_REG, %l7, %i3 | |
321 | stx %g5, [%i3] | |
322 | membar 0x40 | |
323 | ||
324 | ||
325 | UsrEvnt_wrm: | |
326 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h10", 1, *, * ) | |
327 | ||
328 | ldx [%g2], %g3 | |
329 | ldx [%g2], %g3 | |
330 | ldx [%g2], %g3 | |
331 | ldx [%g2], %g3 | |
332 | ||
333 | esr_wrm: | |
334 | setx ERR_BITS_EXPECT, %g7, %g5 | |
335 | setx SOC_ESR_REG, %g7, %g2 | |
336 | setx 0x100, %g7, %g6 | |
337 | esr_loop_wrm: | |
338 | dec %g6 | |
339 | cmp %g6, %g0 | |
340 | be %xcc, test_failed | |
341 | nop | |
342 | ||
343 | ldx [%g2], %g3 | |
344 | ||
345 | cmp %g3, %g5 | |
346 | be %xcc, eie_reg_ones_wrm | |
347 | nop | |
348 | ||
349 | ba esr_loop_wrm | |
350 | nop | |
351 | ||
352 | ||
353 | eie_reg_ones_wrm: | |
354 | setx SOC_EIE_REG, %g3, %g2 | |
355 | set ERR_BITS, %g1 | |
356 | stx %g1, [%g2] | |
357 | membar 0x40 | |
358 | ||
359 | set 0x4, %g1 ! 2 traps already from rdd and wri | |
360 | ! 2 Traps ; one for NCU DmuDParity | |
361 | ! another for L2 DRU | |
362 | setx 0x100, %g7, %g6 | |
363 | err_trap_loop_wrm: | |
364 | cmp %g6, %g0 | |
365 | be %xcc, test_failed | |
366 | nop | |
367 | ||
368 | cmp %g1, %i7 | |
369 | be %xcc, check_tt_wrm | |
370 | nop | |
371 | ||
372 | ba err_trap_loop_wrm | |
373 | nop | |
374 | ||
375 | check_tt_wrm: | |
376 | mov 0x40, %l0 | |
377 | cmp %o7, %l0 | |
378 | bne %xcc, test_failed | |
379 | nop | |
380 | ||
381 | check_l2_trap_cnt: | |
382 | set 0x1, %l0 | |
383 | cmp %i0, %l0 | |
384 | bne test_failed | |
385 | nop | |
386 | ||
387 | test_passed: | |
388 | EXIT_GOOD | |
389 | ||
390 | test_failed: | |
391 | EXIT_BAD | |
392 | ||
393 | ||
394 | /************************************************************************ | |
395 | RAS | |
396 | Trap Handlers | |
397 | ************************************************************************/ | |
398 | My_Recoverable_Sw_error_trap: | |
399 | ! Signal trap taken | |
400 | setx EXECUTED, %l0, %o6 | |
401 | ! save trap type value | |
402 | rdpr %tt, %o7 | |
403 | ||
404 | inc %i7 | |
405 | ||
406 | check_desr_NcuTrap_tt40: | |
407 | ldxa [%g0]0x4c, %g2 | |
408 | nop | |
409 | ||
410 | setx 0xb300000000000000, %l0, %g3 | |
411 | subcc %g2, %g3, %g4 | |
412 | brnz %g4, l2_trap | |
413 | nop | |
414 | ||
415 | check_per_tt40: | |
416 | setx ERR_BITS_EXPECT, %g7, %g5 !valid bit | |
417 | ||
418 | setx SOC_PER_REG, %l7, %g1 | |
419 | ldx [%g1], %g2 | |
420 | ||
421 | sub %g2, %g5, %g3 | |
422 | brnz %g3, test_failed | |
423 | nop | |
424 | ||
425 | clear_per_tt40: | |
426 | setx SOC_PER_REG, %l7, %g1 | |
427 | stx %g0, [%g1] | |
428 | nop | |
429 | ||
430 | clear_ejr_tt40: | |
431 | setx SOC_EJR_REG, %l7, %g1 | |
432 | stx %g0, [%g1] | |
433 | nop | |
434 | ||
435 | clear_eie_tt40: | |
436 | setx SOC_EIE_REG, %l7, %g1 | |
437 | stx %g0, [%g1] | |
438 | nop | |
439 | ||
440 | ba trap_done_tt40 | |
441 | nop | |
442 | ||
443 | ||
444 | l2_trap: | |
445 | nop | |
446 | inc %i0 | |
447 | ||
448 | check_desr_L2Trap_tt40: | |
449 | setx 0xb000000000000000, %l0, %g3 | |
450 | subcc %g2, %g3, %g4 | |
451 | brnz %g4, test_failed | |
452 | nop | |
453 | ||
454 | check_mcu2_esr_L2Trap_tt40: | |
455 | mov 0x1, %l1 | |
456 | sllx %l1, DRAM_ES_DBU, %l0 | |
457 | ||
458 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
459 | ldx [%g5], %l3 | |
460 | ||
461 | setx 0xffffffffffff0000, %l2, %l1 | |
462 | andcc %l1, %l3, %l4 ! Donot check SYND bits | |
463 | ||
464 | sub %l0, %l4, %i4 | |
465 | brnz %i4, test_failed | |
466 | nop | |
467 | ||
468 | clear_mcu_esr_L2Trap_tt40: | |
469 | stx %g0, [%g5] | |
470 | ||
471 | ||
472 | check_L2_4_ESR_L2Trap_tt40: | |
473 | setx L2_ERR_STAT_REG, %l3, %g5 | |
474 | ldx [%g5], %l6 | |
475 | ||
476 | setx 0xfffffffff0000000, %l3, %l0 | |
477 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits | |
478 | ||
479 | mov 0x1, %l1 | |
480 | sllx %l1, L2ES_DAU, %l0 | |
481 | ||
482 | mov 0x1, %l1 | |
483 | sllx %l1, L2ES_VEU, %l2 | |
484 | ||
485 | or %l0, %l2, %i4 | |
486 | ||
487 | cmp %l5, %i4 | |
488 | bne %xcc, test_failed | |
489 | nop | |
490 | ||
491 | clear_l2_esr_L2Trap_tt40: | |
492 | stx %g0, [%g5] | |
493 | ||
494 | trap_done_tt40: | |
495 | retry | |
496 | nop | |
497 | ||
498 | ||
499 | ||
500 | My_Corrected_ECC_error_trap: | |
501 | ba test_failed | |
502 | nop | |
503 | ||
504 | ||
505 | /************************************************************************ | |
506 | Test case data start | |
507 | ************************************************************************/ | |
508 | ||
509 | SECTION .DATA DATA_VA=DMA_DATA_ADDR | |
510 | attr_data { | |
511 | Name = .DATA, | |
512 | hypervisor, | |
513 | compressimage | |
514 | } | |
515 | ||
516 | .data | |
517 | .global PCIAddr9 | |
518 | .xword 0x0001020304050607 | |
519 | .xword 0x08090a0b0c0d0e0f | |
520 | .xword 0x1011121314151617 | |
521 | .xword 0x18191a1b1c1d1e1f | |
522 | .xword 0x2021222324252627 | |
523 | .xword 0x28292a2b2c2d2e2f | |
524 | .xword 0x3031323334353637 | |
525 | .xword 0x38393a3b3c3d3e3f | |
526 | ||
527 | .xword 0x4041424344454647 | |
528 | .xword 0x48494a4b4c4d4e4f | |
529 | .xword 0x5051525354555657 | |
530 | .xword 0x58595a5b5c5d5e5f | |
531 | .xword 0x6061626364656667 | |
532 | .xword 0x68696a6b6c6d6e6f | |
533 | .xword 0x7071727374757677 | |
534 | .xword 0x78797a7b7c7d7e7f | |
535 | ||
536 | .xword 0x8081828384858687 | |
537 | .xword 0x88898a8b8c8d8e8f | |
538 | .xword 0x9091929394959697 | |
539 | .xword 0x98999a9b9c9d9e9f | |
540 | .xword 0xa0a1a2a3a4a5a6a7 | |
541 | .xword 0xa8a9aaabacadaeaf | |
542 | .xword 0xb0b1b2b3b4b5b6b7 | |
543 | .xword 0xb8b9babbbcbdbebf | |
544 | ||
545 | .xword 0xc0c1c2c3c4c5c6c7 | |
546 | .xword 0xc8c9cacbcccdcecf | |
547 | .xword 0xd0d1d2d3d4d5d6d7 | |
548 | .xword 0xd8d9dadbdcdddedf | |
549 | .xword 0xe0e1e2e3e4e5e6e7 | |
550 | .xword 0xe8e9eaebecedeeef | |
551 | .xword 0xf0f1f2f3f4f5f6f7 | |
552 | .xword 0xf8f9fafbfcfdfeff | |
553 | ||
554 | .xword 0x0001020304050607 | |
555 | .xword 0x08090a0b0c0d0e0f | |
556 | .xword 0x1011121314151617 | |
557 | .xword 0x18191a1b1c1d1e1f | |
558 | .xword 0x2021222324252627 | |
559 | .xword 0x28292a2b2c2d2e2f | |
560 | .xword 0x3031323334353637 | |
561 | .xword 0x38393a3b3c3d3e3f | |
562 | ||
563 | .xword 0x4041424344454647 | |
564 | .xword 0x48494a4b4c4d4e4f | |
565 | .xword 0x5051525354555657 | |
566 | .xword 0x58595a5b5c5d5e5f | |
567 | .xword 0x6061626364656667 | |
568 | .xword 0x68696a6b6c6d6e6f | |
569 | .xword 0x7071727374757677 | |
570 | .xword 0x78797a7b7c7d7e7f | |
571 | ||
572 | .xword 0x8081828384858687 | |
573 | .xword 0x88898a8b8c8d8e8f | |
574 | .xword 0x9091929394959697 | |
575 | .xword 0x98999a9b9c9d9e9f | |
576 | .xword 0xa0a1a2a3a4a5a6a7 | |
577 | .xword 0xa8a9aaabacadaeaf | |
578 | .xword 0xb0b1b2b3b4b5b6b7 | |
579 | .xword 0xb8b9babbbcbdbebf | |
580 | ||
581 | .xword 0xc0c1c2c3c4c5c6c7 | |
582 | .xword 0xc8c9cacbcccdcecf | |
583 | .xword 0xd0d1d2d3d4d5d6d7 | |
584 | .xword 0xd8d9dadbdcdddedf | |
585 | .xword 0xe0e1e2e3e4e5e6e7 | |
586 | .xword 0xe8e9eaebecedeeef | |
587 | .xword 0xf0f1f2f3f4f5f6f7 | |
588 | .xword 0xf8f9fafbfcfdfeff | |
589 | ||
590 | /************************************************************************/ | |
591 |