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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_Dmu_AP_synd.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_Dmu_AP_synd.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41#define ENABLE_PCIE_LINK_TRAINING
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45#define DRAM_ERR_STAT_REG 0x8400002280
46#define L2_ERR_STAT_REG 0xAB00000100
47
48#include "err_defines.h"
49#include "hboot.s"
50#include "peu_defines.h"
51
52#define DMA_DATA_ADDR 0x0000000123456700
53#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
54#define DMA_DATA_BYP_ADDR2 0xfffc0001234e6700
55#define DMA_DATA_BYP_ADDR3 0xfffc0001234f6700
56
57#define DMA_DATA_ADDR 0x0000000123456700
58#define DMA_DATA_BYP_SADDR 0xfffc000123456700
59#define DMA_DATA_BYP_EADDR 0xfffc000123456800
60
61
62
63#define ERR_BITS 0x80
64#define ERR_BITS_EXPECT 0x8000000000000080
65
66
67/************************************************************************
68 Test case code start
69 ************************************************************************/
70.text
71.global main
72.global My_Corrected_ECC_error_trap
73.global My_Recoverable_Sw_error_trap
74
75main:
76 ta T_CHANGE_HPRIV
77 nop
78
79 clr %i7
80 clr %o6
81 clr %o7
82 clr %i0
83
84L2_err_enable:
85 set 0x3, %l1
86 mov 0xaa, %g2
87 sllx %g2, 32, %g2
88 stx %l1, [%g2]
89 stx %l1, [%g2 + 0x40]
90 stx %l1, [%g2 + 0x80]
91 stx %l1, [%g2 + 0xc0]
92 stx %l1, [%g2 + 0x100]
93 stx %l1, [%g2 + 0x140]
94 stx %l1, [%g2 + 0x180]
95 stx %l1, [%g2 + 0x1c0]
96
97bypass_iommu:
98 ! enable bypass in IOMMU
99 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
100 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
101 stx %g3, [%g2]
102 ldx [%g2], %g3
103
104 /*******************************************************
105 RDD from DMU
106 ********************************************************/
107set_ejr_rdd:
108 set ERR_BITS, %g5
109
110 setx SOC_EJR_REG, %l7, %i3
111 stx %g5, [%i3]
112 membar 0x40
113
114dma_rdd:
115 nop
116UsrEvnt_rdd:
117 nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_DROP", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1, *, * )
118
119 ldx [%g2], %g3
120 ldx [%g2], %g3
121 ldx [%g2], %g3
122 ldx [%g2], %g3
123
124esr_rdd:
125 setx ERR_BITS_EXPECT, %g7, %g5
126 setx SOC_ESR_REG, %g7, %g2
127 setx 0x100, %g7, %g6
128esr_loop_rdd:
129 dec %g6
130 cmp %g6, %g0
131 be %xcc, test_failed
132 nop
133
134 ldx [%g2], %g3
135
136 cmp %g3, %g5
137 be %xcc, eie_reg_ones_rdd
138 nop
139
140 ba esr_loop_rdd
141 nop
142
143
144eie_reg_ones_rdd:
145 setx SOC_EIE_REG, %g3, %g2
146 set ERR_BITS, %g1
147 stx %g1, [%g2]
148 membar 0x40
149
150 set 0x1, %g1 ! 1 Trap; only for NCU DmuDParity
151 ! For RDD SIU does not send PA39, only sets E bit
152 ! So no trap from L2
153 setx 0x100, %g7, %g6
154err_trap_loop_rdd:
155 cmp %g6, %g0
156 be %xcc, test_failed
157 nop
158
159 cmp %g1, %i7
160 be %xcc, check_tt_rdd
161 nop
162
163 ba err_trap_loop_rdd
164 nop
165
166check_tt_rdd:
167 mov 0x40, %l0
168 cmp %o7, %l0
169 bne %xcc, test_failed
170 nop
171
172
173
174 /*******************************************************
175 WRI from DMU
176 ********************************************************/
177dma_wri:
178 nop
179
180set_ejr_wri:
181 set ERR_BITS, %g5
182
183 setx SOC_EJR_REG, %l7, %i3
184 stx %g5, [%i3]
185 membar 0x40
186
187UsrEvnt_wri:
188 nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR2, DMA_DATA_BYP_ADDR2, "64'h40", 1, *, * )
189
190 ldx [%g2], %g3
191 ldx [%g2], %g3
192 ldx [%g2], %g3
193 ldx [%g2], %g3
194
195esr_wri:
196 setx ERR_BITS_EXPECT, %g7, %g5
197 setx SOC_ESR_REG, %g7, %g2
198 setx 0x100, %g7, %g6
199esr_loop_wri:
200 dec %g6
201 cmp %g6, %g0
202 be %xcc, test_failed
203 nop
204
205 ldx [%g2], %g3
206
207 cmp %g3, %g5
208 be %xcc, eie_reg_ones_wri
209 nop
210
211 ba esr_loop_wri
212 nop
213
214eie_reg_ones_wri:
215 setx SOC_EIE_REG, %g3, %g2
216 set ERR_BITS, %g1
217 stx %g1, [%g2]
218 membar 0x40
219
220 set 0x2, %g1 ! 1 traps from rdd; 1 trap from WRI
221 setx 0x100, %g7, %g6
222err_trap_loop_wri:
223 cmp %g6, %g0
224 be %xcc, test_failed
225 nop
226
227 cmp %g1, %i7
228 be %xcc, check_tt_wri
229 nop
230
231 ba err_trap_loop_wri
232 nop
233
234check_tt_wri:
235 mov 0x40, %l0
236 cmp %o7, %l0
237 bne %xcc, test_failed
238 nop
239
240
241 /*******************************************************
242 WRM from DMU
243 ********************************************************/
244dma_wrm:
245 nop
246
247set_ejr_wrm:
248 set ERR_BITS, %g5
249
250 setx SOC_EJR_REG, %l7, %i3
251 stx %g5, [%i3]
252 membar 0x40
253
254
255UsrEvnt_wrm:
256 nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR3, "64'h10", 1, *, * )
257
258 ldx [%g2], %g3
259 ldx [%g2], %g3
260 ldx [%g2], %g3
261 ldx [%g2], %g3
262
263esr_wrm:
264 setx ERR_BITS_EXPECT, %g7, %g5
265 setx SOC_ESR_REG, %g7, %g2
266 setx 0x100, %g7, %g6
267esr_loop_wrm:
268 dec %g6
269 cmp %g6, %g0
270 be %xcc, test_failed
271 nop
272
273 ldx [%g2], %g3
274
275 cmp %g3, %g5
276 be %xcc, eie_reg_ones_wrm
277 nop
278
279 ba esr_loop_wrm
280 nop
281
282
283eie_reg_ones_wrm:
284 setx SOC_EIE_REG, %g3, %g2
285 set ERR_BITS, %g1
286 stx %g1, [%g2]
287 membar 0x40
288
289 set 0x4, %g1 ! 2 traps already from rdd and wri
290 ! 2 Traps ; one for NCU DmuDParity
291 ! another for L2 DRU
292 setx 0x100, %g7, %g6
293err_trap_loop_wrm:
294 cmp %g6, %g0
295 be %xcc, test_failed
296 nop
297
298 cmp %g1, %i7
299 be %xcc, check_tt_wrm
300 nop
301
302 ba err_trap_loop_wrm
303 nop
304
305check_tt_wrm:
306 mov 0x40, %l0
307 cmp %o7, %l0
308 bne %xcc, test_failed
309 nop
310
311check_l2_trap_cnt:
312 set 0x1, %l0
313 cmp %i0, %l0
314 bne test_failed
315 nop
316
317test_passed:
318 EXIT_GOOD
319
320test_failed:
321 EXIT_BAD
322
323
324/************************************************************************
325 RAS
326 Trap Handlers
327 ************************************************************************/
328My_Recoverable_Sw_error_trap:
329 ! Signal trap taken
330 setx EXECUTED, %l0, %o6
331 ! save trap type value
332 rdpr %tt, %o7
333
334 inc %i7
335
336check_desr_NcuTrap_tt40:
337 ldxa [%g0]0x4c, %g2
338 nop
339
340 setx 0xb300000000000000, %l0, %g3
341 subcc %g2, %g3, %g4
342 brnz %g4, l2_trap
343 nop
344
345check_per_tt40:
346 setx ERR_BITS_EXPECT, %g7, %g5 !valid bit
347
348 setx SOC_PER_REG, %l7, %g1
349 ldx [%g1], %g2
350
351 sub %g2, %g5, %g3
352 brnz %g3, test_failed
353 nop
354
355cmp_err_cnt_tt40:
356 mov 0x1, %g1
357 cmp %i7, %g1
358 be synd_rdd_err_tt40
359 nop
360
361 mov 0x2, %g1
362 cmp %i7, %g1
363 be synd_wri_err_tt40
364 nop
365
366 mov 0x3, %g1
367 cmp %i7, %g1
368 be synd_wrm_err_tt40
369 nop
370
371 mov 0x4, %g1
372 cmp %i7, %g1
373 be synd_wrm_err_tt40
374 nop
375
376 ba test_failed
377 nop
378
379synd_rdd_err_tt40:
380 setx SOC_SII_ERR_SYND_REG, %g7, %g5
381 ldx [%g5], %g1
382 setx 0x8700010123456500, %g7, %g2
383 cmp %g1, %g2
384 bne %xcc, test_failed
385 nop
386
387 ba clear_per_tt40
388 nop
389
390synd_wri_err_tt40:
391 setx SOC_SII_ERR_SYND_REG, %g7, %g5
392 ldx [%g5], %g1
393 setx 0xff0000ffffffffff, %g7, %g6
394 and %g1, %g6, %g4
395 setx 0x87000001234e6500, %g7, %g2
396 cmp %g4, %g2
397 bne %xcc, test_failed
398 nop
399
400 ba clear_per_tt40
401 nop
402
403synd_wrm_err_tt40:
404 setx SOC_SII_ERR_SYND_REG, %g7, %g5
405 ldx [%g5], %g1
406 setx 0xff0000ffffffffff, %g7, %g6
407 and %g1, %g6, %g4
408 setx 0x87000001234f6500, %g7, %g2
409 cmp %g4, %g2
410 bne %xcc, test_failed
411 nop
412
413 ba clear_per_tt40
414 nop
415
416clear_per_tt40:
417 setx SOC_PER_REG, %l7, %g1
418 stx %g0, [%g1]
419 nop
420
421clear_ejr_tt40:
422 setx SOC_EJR_REG, %l7, %g1
423 stx %g0, [%g1]
424 nop
425
426clear_eie_tt40:
427 setx SOC_EIE_REG, %l7, %g1
428 stx %g0, [%g1]
429 nop
430
431clear_siisynd:
432 setx SOC_SII_ERR_SYND_REG, %l7, %g1
433 stx %g0, [%g1]
434 nop
435
436 ba trap_done_tt40
437 nop
438
439
440l2_trap:
441 nop
442 inc %i0
443
444check_desr_L2Trap_tt40:
445 setx 0xb000000000000000, %l0, %g3
446 subcc %g2, %g3, %g4
447 brnz %g4, test_failed
448 nop
449
450check_mcu2_esr_L2Trap_tt40:
451 mov 0x1, %l1
452 sllx %l1, DRAM_ES_DBU, %l0
453
454 setx DRAM_ERR_STAT_REG, %l3, %g5
455 ldx [%g5], %l3
456
457 setx 0xffffffffffff0000, %l2, %l1
458 andcc %l1, %l3, %l4 ! Donot check SYND bits
459
460 sub %l0, %l4, %i4
461 brnz %i4, test_failed
462 nop
463
464clear_mcu_esr_L2Trap_tt40:
465 stx %g0, [%g5]
466
467
468check_L2_4_ESR_L2Trap_tt40:
469 setx L2_ERR_STAT_REG, %l3, %g5
470 ldx [%g5], %l6
471
472 setx 0xfffffffff0000000, %l3, %l0
473 andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits
474
475 mov 0x1, %l1
476 sllx %l1, L2ES_DAU, %l0
477
478 mov 0x1, %l1
479 sllx %l1, L2ES_VEU, %l2
480
481 or %l0, %l2, %i4
482
483 cmp %l5, %i4
484 bne %xcc, test_failed
485 nop
486
487clear_l2_esr_L2Trap_tt40:
488 stx %g0, [%g5]
489
490trap_done_tt40:
491 retry
492 nop
493
494
495
496My_Corrected_ECC_error_trap:
497 ba test_failed
498 nop
499
500
501/************************************************************************
502 Test case data start
503************************************************************************/
504
505SECTION .DATA DATA_VA=DMA_DATA_ADDR
506attr_data {
507 Name = .DATA,
508 hypervisor,
509 compressimage
510}
511
512.data
513.global PCIAddr9
514 .xword 0x0001020304050607
515 .xword 0x08090a0b0c0d0e0f
516 .xword 0x1011121314151617
517 .xword 0x18191a1b1c1d1e1f
518 .xword 0x2021222324252627
519 .xword 0x28292a2b2c2d2e2f
520 .xword 0x3031323334353637
521 .xword 0x38393a3b3c3d3e3f
522
523 .xword 0x4041424344454647
524 .xword 0x48494a4b4c4d4e4f
525 .xword 0x5051525354555657
526 .xword 0x58595a5b5c5d5e5f
527 .xword 0x6061626364656667
528 .xword 0x68696a6b6c6d6e6f
529 .xword 0x7071727374757677
530 .xword 0x78797a7b7c7d7e7f
531
532 .xword 0x8081828384858687
533 .xword 0x88898a8b8c8d8e8f
534 .xword 0x9091929394959697
535 .xword 0x98999a9b9c9d9e9f
536 .xword 0xa0a1a2a3a4a5a6a7
537 .xword 0xa8a9aaabacadaeaf
538 .xword 0xb0b1b2b3b4b5b6b7
539 .xword 0xb8b9babbbcbdbebf
540
541 .xword 0xc0c1c2c3c4c5c6c7
542 .xword 0xc8c9cacbcccdcecf
543 .xword 0xd0d1d2d3d4d5d6d7
544 .xword 0xd8d9dadbdcdddedf
545 .xword 0xe0e1e2e3e4e5e6e7
546 .xword 0xe8e9eaebecedeeef
547 .xword 0xf0f1f2f3f4f5f6f7
548 .xword 0xf8f9fafbfcfdfeff
549
550 .xword 0x0001020304050607
551 .xword 0x08090a0b0c0d0e0f
552 .xword 0x1011121314151617
553 .xword 0x18191a1b1c1d1e1f
554 .xword 0x2021222324252627
555 .xword 0x28292a2b2c2d2e2f
556 .xword 0x3031323334353637
557 .xword 0x38393a3b3c3d3e3f
558
559 .xword 0x4041424344454647
560 .xword 0x48494a4b4c4d4e4f
561 .xword 0x5051525354555657
562 .xword 0x58595a5b5c5d5e5f
563 .xword 0x6061626364656667
564 .xword 0x68696a6b6c6d6e6f
565 .xword 0x7071727374757677
566 .xword 0x78797a7b7c7d7e7f
567
568 .xword 0x8081828384858687
569 .xword 0x88898a8b8c8d8e8f
570 .xword 0x9091929394959697
571 .xword 0x98999a9b9c9d9e9f
572 .xword 0xa0a1a2a3a4a5a6a7
573 .xword 0xa8a9aaabacadaeaf
574 .xword 0xb0b1b2b3b4b5b6b7
575 .xword 0xb8b9babbbcbdbebf
576
577 .xword 0xc0c1c2c3c4c5c6c7
578 .xword 0xc8c9cacbcccdcecf
579 .xword 0xd0d1d2d3d4d5d6d7
580 .xword 0xd8d9dadbdcdddedf
581 .xword 0xe0e1e2e3e4e5e6e7
582 .xword 0xe8e9eaebecedeeef
583 .xword 0xf0f1f2f3f4f5f6f7
584 .xword 0xf8f9fafbfcfdfeff
585
586/************************************************************************/
587
Full OpenSPARC design & verification tarball including full HDL.