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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_Dmu_AP_wrmreset.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_Dmu_AP_wrmreset.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41#define ENABLE_PCIE_LINK_TRAINING
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45#define RESET_STAT_CHECK
46
47#define DRAM_0_ERR_STAT_REG 0x8400000280
48#define DRAM_1_ERR_STAT_REG 0x8400001280
49#define DRAM_2_ERR_STAT_REG 0x8400002280
50#define DRAM_3_ERR_STAT_REG 0x8400003280
51
52#define L2_0_ERR_STAT_REG 0xAB00000000
53#define L2_1_ERR_STAT_REG 0xAB00000040
54#define L2_2_ERR_STAT_REG 0xAB00000080
55#define L2_3_ERR_STAT_REG 0xAB000000c0
56
57#define L2_4_ERR_STAT_REG 0xAB00000100
58#define L2_5_ERR_STAT_REG 0xAB00000140
59#define L2_6_ERR_STAT_REG 0xAB00000180
60#define L2_7_ERR_STAT_REG 0xAB000001c0
61
62#ifdef BANK0
63#define DRAM_ERR_STAT_REG 0x8400000280
64#define L2_ERR_STAT_REG 0xAB00000000
65#endif
66
67#ifdef BANK1
68#define DRAM_ERR_STAT_REG 0x8400000280
69#define L2_ERR_STAT_REG 0xAB00000040
70#endif
71
72#ifdef BANK2
73#define DRAM_ERR_STAT_REG 0x8400001280
74#define L2_ERR_STAT_REG 0xAB00000080
75#endif
76
77#ifdef BANK3
78#define DRAM_ERR_STAT_REG 0x8400001280
79#define L2_ERR_STAT_REG 0xAB000000c0
80#endif
81
82#ifdef BANK4
83#define DRAM_ERR_STAT_REG 0x8400002280
84#define L2_ERR_STAT_REG 0xAB00000100
85#endif
86
87#ifdef BANK5
88#define DRAM_ERR_STAT_REG 0x8400002280
89#define L2_ERR_STAT_REG 0xAB00000140
90#endif
91
92#ifdef BANK6
93#define DRAM_ERR_STAT_REG 0x8400003280
94#define L2_ERR_STAT_REG 0xAB00000180
95#endif
96
97#ifdef BANK7
98#define DRAM_ERR_STAT_REG 0x8400003280
99#define L2_ERR_STAT_REG 0xAB000001c0
100#endif
101
102
103#include "err_defines.h"
104#include "hboot.s"
105#include "peu_defines.h"
106
107#define DMA_DATA_ADDR 0x0000000123456700
108#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
109#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
110#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
111
112#define DMA_DATA_ADDR 0x0000000123456700
113#define DMA_DATA_BYP_SADDR 0xfffc000123456700
114#define DMA_DATA_BYP_EADDR 0xfffc000123456800
115
116#ifdef BANK0
117#define DMA_DATA_BYP_ADDR1 0xfffc000123450000
118#endif
119
120#ifdef BANK1
121#define DMA_DATA_BYP_ADDR1 0xfffc000123456040
122#endif
123
124#ifdef BANK2
125#define DMA_DATA_BYP_ADDR1 0xfffc000123456080
126#endif
127
128#ifdef BANK3
129#define DMA_DATA_BYP_ADDR1 0xfffc0001234560c0
130#endif
131
132#ifdef BANK4
133#define DMA_DATA_BYP_ADDR1 0xfffc000123456100
134#endif
135
136#ifdef BANK5
137#define DMA_DATA_BYP_ADDR1 0xfffc000123456140
138#endif
139
140#ifdef BANK6
141#define DMA_DATA_BYP_ADDR1 0xfffc000123456180
142#endif
143
144#ifdef BANK7
145#define DMA_DATA_BYP_ADDR1 0xfffc0001234561c0
146#endif
147
148
149
150#define ERR_BITS 0x80
151#define ERR_BITS_EXPECT 0x8000000000000080
152
153
154/************************************************************************
155 Test case code start
156 ************************************************************************/
157.text
158.global main
159.global My_Corrected_ECC_error_trap
160.global My_Recoverable_Sw_error_trap
161
162main:
163 ta T_CHANGE_HPRIV
164 nop
165
166clear_esr:
167 setx 0xc03ffffc00000000, %g7, %g1
168
169 setx L2_0_ERR_STAT_REG, %g7, %g2
170 stx %g1, [%g2]
171 setx L2_1_ERR_STAT_REG, %g7, %g2
172 stx %g1, [%g2]
173 setx L2_2_ERR_STAT_REG, %g7, %g2
174 stx %g1, [%g2]
175 setx L2_3_ERR_STAT_REG, %g7, %g2
176 stx %g1, [%g2]
177 setx L2_4_ERR_STAT_REG, %g7, %g2
178 stx %g1, [%g2]
179 setx L2_5_ERR_STAT_REG, %g7, %g2
180 stx %g1, [%g2]
181 setx L2_6_ERR_STAT_REG, %g7, %g2
182 stx %g1, [%g2]
183 setx L2_7_ERR_STAT_REG, %g7, %g2
184 stx %g1, [%g2]
185
186 setx 0xffc0000000000000, %g7, %g1
187
188 setx DRAM_0_ERR_STAT_REG, %g7, %g2
189 stx %g1, [%g2]
190 setx DRAM_1_ERR_STAT_REG, %g7, %g2
191 stx %g1, [%g2]
192 setx DRAM_2_ERR_STAT_REG, %g7, %g2
193 stx %g1, [%g2]
194 setx DRAM_3_ERR_STAT_REG, %g7, %g2
195 stx %g1, [%g2]
196
197 /************************************************************
198 Check if this is the first time thru here
199 ************************************************************/
200reset_decide:
201 setx test_entered, %g1, %g2
202 ldx [%g2], %g3
203 brnz %g3, After_Warm_Reset
204 nop
205
206 ! First time thru, Store a non-zero value there
207 dec %g3
208 stx %g3, [%g2]
209
210clearing:
211 clr %i7
212 clr %o6
213 clr %o7
214 clr %i0
215
216
217fee_reg_ones_rdd:
218 setx SOC_FEE_REG, %g3, %g2
219 set ERR_BITS, %g1
220 stx %g1, [%g2]
221 membar 0x4
222
223L2_err_enable:
224 set 0x3, %l1
225 mov 0xaa, %g2
226 sllx %g2, 32, %g2
227 stx %l1, [%g2]
228 stx %l1, [%g2 + 0x40]
229 stx %l1, [%g2 + 0x80]
230 stx %l1, [%g2 + 0xc0]
231 stx %l1, [%g2 + 0x100]
232 stx %l1, [%g2 + 0x140]
233 stx %l1, [%g2 + 0x180]
234 stx %l1, [%g2 + 0x1c0]
235
236
237bypass_iommu:
238 ! enable bypass in IOMMU
239 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
240 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
241 stx %g3, [%g2]
242 ldx [%g2], %g3
243
244 /*******************************************************
245 RDD from DMU
246 ********************************************************/
247set_ejr_rdd:
248 set ERR_BITS, %g5
249
250 setx SOC_EJR_REG, %l7, %i3
251 stx %g5, [%i3]
252 membar 0x40
253
254dma_rdd:
255 nop
256UsrEvnt_rdd:
257 nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1, *, * )
258
259 ldx [%g2], %g3
260 ldx [%g2], %g3
261 ldx [%g2], %g3
262 ldx [%g2], %g3
263
264After_Warm_Reset:
265 nop
266
267esr_rdd:
268 setx ERR_BITS_EXPECT, %g7, %g5
269 setx SOC_ESR_REG, %g7, %g2
270 setx 0x100, %g7, %g6
271esr_loop_rdd:
272 dec %g6
273 cmp %g6, %g0
274 be %xcc, test_failed
275 nop
276
277 ldx [%g2], %g3
278
279 cmp %g3, %g5
280 be %xcc, check_trap_cnt
281 nop
282
283 ba esr_loop_rdd
284 nop
285
286
287check_trap_cnt:
288 cmp %i0, %g0
289 bne test_failed
290 nop
291
292 ba test_passed
293 nop
294
295
296test_passed:
297 EXIT_GOOD
298
299test_failed:
300 EXIT_BAD
301
302
303/************************************************************************
304 RAS
305 Trap Handlers
306 ************************************************************************/
307My_Recoverable_Sw_error_trap:
308 ba test_failed
309 nop
310
311
312
313My_Corrected_ECC_error_trap:
314 ba test_failed
315 nop
316
317
318/************************************************************************
319 Test case data start
320************************************************************************/
321 .align 64
322test_entered:
323 .xword 0
324
325
326SECTION .DATA DATA_VA=DMA_DATA_ADDR
327attr_data {
328 Name = .DATA,
329 hypervisor,
330 compressimage
331}
332
333.data
334.global PCIAddr9
335 .xword 0x0001020304050607
336 .xword 0x08090a0b0c0d0e0f
337 .xword 0x1011121314151617
338 .xword 0x18191a1b1c1d1e1f
339 .xword 0x2021222324252627
340 .xword 0x28292a2b2c2d2e2f
341 .xword 0x3031323334353637
342 .xword 0x38393a3b3c3d3e3f
343
344 .xword 0x4041424344454647
345 .xword 0x48494a4b4c4d4e4f
346 .xword 0x5051525354555657
347 .xword 0x58595a5b5c5d5e5f
348 .xword 0x6061626364656667
349 .xword 0x68696a6b6c6d6e6f
350 .xword 0x7071727374757677
351 .xword 0x78797a7b7c7d7e7f
352
353 .xword 0x8081828384858687
354 .xword 0x88898a8b8c8d8e8f
355 .xword 0x9091929394959697
356 .xword 0x98999a9b9c9d9e9f
357 .xword 0xa0a1a2a3a4a5a6a7
358 .xword 0xa8a9aaabacadaeaf
359 .xword 0xb0b1b2b3b4b5b6b7
360 .xword 0xb8b9babbbcbdbebf
361
362 .xword 0xc0c1c2c3c4c5c6c7
363 .xword 0xc8c9cacbcccdcecf
364 .xword 0xd0d1d2d3d4d5d6d7
365 .xword 0xd8d9dadbdcdddedf
366 .xword 0xe0e1e2e3e4e5e6e7
367 .xword 0xe8e9eaebecedeeef
368 .xword 0xf0f1f2f3f4f5f6f7
369 .xword 0xf8f9fafbfcfdfeff
370
371 .xword 0x0001020304050607
372 .xword 0x08090a0b0c0d0e0f
373 .xword 0x1011121314151617
374 .xword 0x18191a1b1c1d1e1f
375 .xword 0x2021222324252627
376 .xword 0x28292a2b2c2d2e2f
377 .xword 0x3031323334353637
378 .xword 0x38393a3b3c3d3e3f
379
380 .xword 0x4041424344454647
381 .xword 0x48494a4b4c4d4e4f
382 .xword 0x5051525354555657
383 .xword 0x58595a5b5c5d5e5f
384 .xword 0x6061626364656667
385 .xword 0x68696a6b6c6d6e6f
386 .xword 0x7071727374757677
387 .xword 0x78797a7b7c7d7e7f
388
389 .xword 0x8081828384858687
390 .xword 0x88898a8b8c8d8e8f
391 .xword 0x9091929394959697
392 .xword 0x98999a9b9c9d9e9f
393 .xword 0xa0a1a2a3a4a5a6a7
394 .xword 0xa8a9aaabacadaeaf
395 .xword 0xb0b1b2b3b4b5b6b7
396 .xword 0xb8b9babbbcbdbebf
397
398 .xword 0xc0c1c2c3c4c5c6c7
399 .xword 0xc8c9cacbcccdcecf
400 .xword 0xd0d1d2d3d4d5d6d7
401 .xword 0xd8d9dadbdcdddedf
402 .xword 0xe0e1e2e3e4e5e6e7
403 .xword 0xe8e9eaebecedeeef
404 .xword 0xf0f1f2f3f4f5f6f7
405 .xword 0xf8f9fafbfcfdfeff
406
407
408
409/************************************************************************/
410
Full OpenSPARC design & verification tarball including full HDL.