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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_L2SIO_DP.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_L2SIO_DP.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41#define ENABLE_PCIE_LINK_TRAINING
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45#define DRAM_ERR_STAT_REG 0x8400002280
46#define L2_ERR_STAT_REG 0xAB00000100
47
48#include "err_defines.h"
49#include "hboot.s"
50#include "peu_defines.h"
51
52#define DMA_DATA_ADDR 0x0000000123456700
53
54#define DMA_DATA_BYP_ADDR1 0xfffc000123456000
55#define DMA_DATA_BYP_ADDR2 0xfffc000123456040
56#define DMA_DATA_BYP_ADDR3 0xfffc000123456080
57#define DMA_DATA_BYP_ADDR4 0xfffc000123456100
58#define DMA_DATA_BYP_ADDR5 0xfffc000123456140
59#define DMA_DATA_BYP_ADDR6 0xfffc000123456180
60#define DMA_DATA_BYP_ADDR7 0xfffc0001234561c0
61
62
63#define ERR_BITS 0x4000000
64#define ERR_BITS_EXPECT 0x8000000004000000
65
66
67/************************************************************************
68 Test case code start
69 ************************************************************************/
70.text
71.global main
72.global My_Corrected_ECC_error_trap
73.global My_Recoverable_Sw_error_trap
74
75main:
76 ta T_CHANGE_HPRIV
77 nop
78
79 clr %i7
80 clr %o6
81 clr %o7
82
83L2_err_enable:
84 set 0x3, %l1
85 mov 0xaa, %g2
86 sllx %g2, 32, %g2
87 stx %l1, [%g2]
88 stx %l1, [%g2 + 0x40]
89 stx %l1, [%g2 + 0x80]
90 stx %l1, [%g2 + 0xc0]
91 stx %l1, [%g2 + 0x100]
92 stx %l1, [%g2 + 0x140]
93 stx %l1, [%g2 + 0x180]
94 stx %l1, [%g2 + 0x1c0]
95
96dma_uev:
97 ! enable bypass in IOMMU
98 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
99 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
100 stx %g3, [%g2]
101 ldx [%g2], %g3
102
103
104uev2:
105 nop
106
107inj_err2:
108 nop !$EV trig_pc_d(0,@VA(.MAIN.inj_err2)) ->IosErrInj(L2SIO_DP, 0001, 123456000)
109
110Wr_Evnt2: nop;
111 ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt2) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 )
112
113 ldx [%g2], %g3
114esr2:
115 setx 0x8000000000002000, %g7, %g5 !SiiDmuCtagUe
116 setx SOC_ESR_REG, %g7, %g2
117 setx 0x20, %g7, %g6
118esr_loop2:
119 dec %g6
120 cmp %g6, %g0
121 be %xcc, test_failed
122 nop
123
124 ldx [%g2], %g3
125
126 cmp %g3, %g5
127 be %xcc, eie_2
128 nop
129
130 ba esr_loop2
131 nop
132
133eie_2:
134 setx SOC_EIE_REG, %g3, %g2
135 set 0x2000, %g1 ! SiiDmuCtagUe
136 stx %g1, [%g2]
137 membar 0x40
138
139 set 0x1, %g1 ! 1 Trap;
140 setx 0x20, %g7, %g6
141err_trap_loop2:
142 cmp %g6, %g0
143 be %xcc, test_failed
144 nop
145
146 cmp %g1, %i7
147 be %xcc, test_passed
148 nop
149
150 ba err_trap_loop2
151 nop
152
153
154test_passed:
155 EXIT_GOOD
156
157test_failed:
158 EXIT_BAD
159
160
161/************************************************************************
162 RAS
163 Trap Handlers
164 ************************************************************************/
165My_Recoverable_Sw_error_trap:
166 inc %i7
167
168check_desr_NcuTrap_tt40:
169 ldxa [%g0]0x4c, %g2
170 nop
171
172 setx 0xb300000000000000, %l0, %g3
173 subcc %g2, %g3, %g4
174 brnz %g4, test_failed
175 nop
176
177check_tt40:
178 setx 0x8000000000002000, %g7, %g5
179 setx SOC_PER_REG, %l7, %g1
180 ldx [%g1], %g2
181 sub %g2, %g5, %g3
182 brnz %g3, test_failed
183 nop
184
185
186clear_per_tt40:
187 setx SOC_PER_REG, %l7, %g1
188 stx %g0, [%g1]
189 nop
190
191clear_esr_tt40:
192 setx SOC_ESR_REG, %l7, %g1
193 stx %g0, [%g1]
194 nop
195
196trap_done_tt40:
197 retry
198 nop
199
200My_Corrected_ECC_error_trap:
201 ba test_failed
202 nop
203
204 retry
205 nop
206
207/************************************************************************
208 Test case data start
209************************************************************************/
210
211SECTION .DATA DATA_VA=DMA_DATA_ADDR
212attr_data {
213 Name = .DATA,
214 hypervisor,
215 compressimage
216}
217
218.data
219.global PCIAddr9
220 .xword 0x0001020304050607
221 .xword 0x08090a0b0c0d0e0f
222 .xword 0x1011121314151617
223 .xword 0x18191a1b1c1d1e1f
224 .xword 0x2021222324252627
225 .xword 0x28292a2b2c2d2e2f
226 .xword 0x3031323334353637
227 .xword 0x38393a3b3c3d3e3f
228
229 .xword 0x4041424344454647
230 .xword 0x48494a4b4c4d4e4f
231 .xword 0x5051525354555657
232 .xword 0x58595a5b5c5d5e5f
233 .xword 0x6061626364656667
234 .xword 0x68696a6b6c6d6e6f
235 .xword 0x7071727374757677
236 .xword 0x78797a7b7c7d7e7f
237
238 .xword 0x8081828384858687
239 .xword 0x88898a8b8c8d8e8f
240 .xword 0x9091929394959697
241 .xword 0x98999a9b9c9d9e9f
242 .xword 0xa0a1a2a3a4a5a6a7
243 .xword 0xa8a9aaabacadaeaf
244 .xword 0xb0b1b2b3b4b5b6b7
245 .xword 0xb8b9babbbcbdbebf
246
247 .xword 0xc0c1c2c3c4c5c6c7
248 .xword 0xc8c9cacbcccdcecf
249 .xword 0xd0d1d2d3d4d5d6d7
250 .xword 0xd8d9dadbdcdddedf
251 .xword 0xe0e1e2e3e4e5e6e7
252 .xword 0xe8e9eaebecedeeef
253 .xword 0xf0f1f2f3f4f5f6f7
254 .xword 0xf8f9fafbfcfdfeff
255
256 .xword 0x0001020304050607
257 .xword 0x08090a0b0c0d0e0f
258 .xword 0x1011121314151617
259 .xword 0x18191a1b1c1d1e1f
260 .xword 0x2021222324252627
261 .xword 0x28292a2b2c2d2e2f
262 .xword 0x3031323334353637
263 .xword 0x38393a3b3c3d3e3f
264
265 .xword 0x4041424344454647
266 .xword 0x48494a4b4c4d4e4f
267 .xword 0x5051525354555657
268 .xword 0x58595a5b5c5d5e5f
269 .xword 0x6061626364656667
270 .xword 0x68696a6b6c6d6e6f
271 .xword 0x7071727374757677
272 .xword 0x78797a7b7c7d7e7f
273
274 .xword 0x8081828384858687
275 .xword 0x88898a8b8c8d8e8f
276 .xword 0x9091929394959697
277 .xword 0x98999a9b9c9d9e9f
278 .xword 0xa0a1a2a3a4a5a6a7
279 .xword 0xa8a9aaabacadaeaf
280 .xword 0xb0b1b2b3b4b5b6b7
281 .xword 0xb8b9babbbcbdbebf
282
283 .xword 0xc0c1c2c3c4c5c6c7
284 .xword 0xc8c9cacbcccdcecf
285 .xword 0xd0d1d2d3d4d5d6d7
286 .xword 0xd8d9dadbdcdddedf
287 .xword 0xe0e1e2e3e4e5e6e7
288 .xword 0xe8e9eaebecedeeef
289 .xword 0xf0f1f2f3f4f5f6f7
290 .xword 0xf8f9fafbfcfdfeff
291
292/************************************************************************/
293
Full OpenSPARC design & verification tarball including full HDL.