projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: n2_err_adv_SIIDMU_WRACK_P.s | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
| 39 | #define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap | |
| 40 | ||
| 41 | #define ENABLE_PCIE_LINK_TRAINING | |
| 42 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ | |
| 43 | #define MAIN_PAGE_HV_ALSO | |
| 44 | ||
| 45 | #ifdef BANK0 | |
| 46 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
| 47 | #define L2_ERR_STAT_REG 0xAB00000000 | |
| 48 | #endif | |
| 49 | ||
| 50 | #ifdef BANK1 | |
| 51 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
| 52 | #define L2_ERR_STAT_REG 0xAB00000040 | |
| 53 | #endif | |
| 54 | ||
| 55 | #ifdef BANK2 | |
| 56 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
| 57 | #define L2_ERR_STAT_REG 0xAB00000080 | |
| 58 | #endif | |
| 59 | ||
| 60 | #ifdef BANK3 | |
| 61 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
| 62 | #define L2_ERR_STAT_REG 0xAB000000c0 | |
| 63 | #endif | |
| 64 | ||
| 65 | #ifdef BANK4 | |
| 66 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
| 67 | #define L2_ERR_STAT_REG 0xAB00000100 | |
| 68 | #endif | |
| 69 | ||
| 70 | #ifdef BANK5 | |
| 71 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
| 72 | #define L2_ERR_STAT_REG 0xAB00000140 | |
| 73 | #endif | |
| 74 | ||
| 75 | #ifdef BANK6 | |
| 76 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
| 77 | #define L2_ERR_STAT_REG 0xAB00000180 | |
| 78 | #endif | |
| 79 | ||
| 80 | #ifdef BANK7 | |
| 81 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
| 82 | #define L2_ERR_STAT_REG 0xAB000001c0 | |
| 83 | #endif | |
| 84 | ||
| 85 | ||
| 86 | #include "err_defines.h" | |
| 87 | #include "hboot.s" | |
| 88 | #include "peu_defines.h" | |
| 89 | ||
| 90 | #define DMA_DATA_ADDR 0x0000000123456700 | |
| 91 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456700 | |
| 92 | #define DMA_DATA_BYP_ADDR2 0xfffc000123456780 | |
| 93 | #define DMA_DATA_BYP_ADDR3 0xfffc000123456800 | |
| 94 | ||
| 95 | #define DMA_DATA_ADDR 0x0000000123456700 | |
| 96 | #define DMA_DATA_BYP_SADDR 0xfffc000123456700 | |
| 97 | #define DMA_DATA_BYP_EADDR 0xfffc000123456800 | |
| 98 | ||
| 99 | #ifdef BANK0 | |
| 100 | #define DMA_DATA_BYP_ADDR1 0xfffc000123450000 | |
| 101 | #endif | |
| 102 | ||
| 103 | #ifdef BANK1 | |
| 104 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456040 | |
| 105 | #endif | |
| 106 | ||
| 107 | #ifdef BANK2 | |
| 108 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456080 | |
| 109 | #endif | |
| 110 | ||
| 111 | #ifdef BANK3 | |
| 112 | #define DMA_DATA_BYP_ADDR1 0xfffc0001234560c0 | |
| 113 | #endif | |
| 114 | ||
| 115 | #ifdef BANK4 | |
| 116 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456100 | |
| 117 | #endif | |
| 118 | ||
| 119 | #ifdef BANK5 | |
| 120 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456140 | |
| 121 | #endif | |
| 122 | ||
| 123 | #ifdef BANK6 | |
| 124 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456180 | |
| 125 | #endif | |
| 126 | ||
| 127 | #ifdef BANK7 | |
| 128 | #define DMA_DATA_BYP_ADDR1 0xfffc0001234561c0 | |
| 129 | #endif | |
| 130 | ||
| 131 | ||
| 132 | ||
| 133 | #define ERR_BITS 0x1000 | |
| 134 | #define ERR_BITS_EXPECT 0x8000000000001000 | |
| 135 | ||
| 136 | ||
| 137 | /************************************************************************ | |
| 138 | Test case code start | |
| 139 | ************************************************************************/ | |
| 140 | .text | |
| 141 | .global main | |
| 142 | .global My_Corrected_ECC_error_trap | |
| 143 | .global My_Recoverable_Sw_error_trap | |
| 144 | ||
| 145 | main: | |
| 146 | ta T_CHANGE_HPRIV | |
| 147 | nop | |
| 148 | ||
| 149 | clr %i7 | |
| 150 | clr %o6 | |
| 151 | clr %o7 | |
| 152 | clr %i0 | |
| 153 | ||
| 154 | L2_err_enable: | |
| 155 | set 0x3, %l1 | |
| 156 | mov 0xaa, %g2 | |
| 157 | sllx %g2, 32, %g2 | |
| 158 | stx %l1, [%g2] | |
| 159 | stx %l1, [%g2 + 0x40] | |
| 160 | stx %l1, [%g2 + 0x80] | |
| 161 | stx %l1, [%g2 + 0xc0] | |
| 162 | stx %l1, [%g2 + 0x100] | |
| 163 | stx %l1, [%g2 + 0x140] | |
| 164 | stx %l1, [%g2 + 0x180] | |
| 165 | stx %l1, [%g2 + 0x1c0] | |
| 166 | ||
| 167 | bypass_iommu: | |
| 168 | ! enable bypass in IOMMU | |
| 169 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
| 170 | setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3 | |
| 171 | stx %g3, [%g2] | |
| 172 | ldx [%g2], %g3 | |
| 173 | ||
| 174 | /******************************************************* | |
| 175 | WRI from DMU | |
| 176 | ********************************************************/ | |
| 177 | dma_wri: | |
| 178 | nop | |
| 179 | ||
| 180 | ||
| 181 | inj_err4: | |
| 182 | nop !$EV trig_pc_d(0,@VA(.MAIN.inj_err4)) ->IosErrInj(SIIDMU_WRACK_P, 0000, 123450000) | |
| 183 | ||
| 184 | ||
| 185 | membar 0x40 | |
| 186 | ||
| 187 | UsrEvnt_wri: | |
| 188 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1, *, * ) | |
| 189 | ||
| 190 | ldx [%g2], %g3 | |
| 191 | ldx [%g2], %g3 | |
| 192 | ldx [%g2], %g3 | |
| 193 | ldx [%g2], %g3 | |
| 194 | ||
| 195 | esr_wri: | |
| 196 | setx ERR_BITS_EXPECT, %g7, %g5 | |
| 197 | setx SOC_ESR_REG, %g7, %g2 | |
| 198 | setx 0x100, %g7, %g6 | |
| 199 | esr_loop_wri: | |
| 200 | dec %g6 | |
| 201 | cmp %g6, %g0 | |
| 202 | be %xcc, test_failed | |
| 203 | nop | |
| 204 | ||
| 205 | ldx [%g2], %g3 | |
| 206 | ||
| 207 | cmp %g3, %g5 | |
| 208 | be %xcc, eie_reg_ones_wri | |
| 209 | nop | |
| 210 | ||
| 211 | ba esr_loop_wri | |
| 212 | nop | |
| 213 | ||
| 214 | eie_reg_ones_wri: | |
| 215 | setx SOC_EIE_REG, %g3, %g2 | |
| 216 | set ERR_BITS, %g1 | |
| 217 | stx %g1, [%g2] | |
| 218 | membar 0x40 | |
| 219 | ||
| 220 | set 0x1, %g1 ! 1 traps from rdd; 1 trap from WRI | |
| 221 | setx 0x100, %g7, %g6 | |
| 222 | err_trap_loop_wri: | |
| 223 | cmp %g6, %g0 | |
| 224 | be %xcc, test_failed | |
| 225 | nop | |
| 226 | ||
| 227 | cmp %g1, %i7 | |
| 228 | be %xcc, check_tt_wri | |
| 229 | nop | |
| 230 | ||
| 231 | ba err_trap_loop_wri | |
| 232 | nop | |
| 233 | ||
| 234 | check_tt_wri: | |
| 235 | mov 0x40, %l0 | |
| 236 | cmp %o7, %l0 | |
| 237 | bne %xcc, test_failed | |
| 238 | nop | |
| 239 | ||
| 240 | ||
| 241 | /******************************************************* | |
| 242 | WRM from DMU | |
| 243 | ********************************************************/ | |
| 244 | dma_wrm: | |
| 245 | nop | |
| 246 | ||
| 247 | set_ejr_wrm: | |
| 248 | set ERR_BITS, %g5 | |
| 249 | ||
| 250 | setx SOC_EJR_REG, %l7, %i3 | |
| 251 | stx %g5, [%i3] | |
| 252 | membar 0x40 | |
| 253 | ||
| 254 | ||
| 255 | UsrEvnt_wrm: | |
| 256 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h10", 1, *, * ) | |
| 257 | ||
| 258 | ldx [%g2], %g3 | |
| 259 | ldx [%g2], %g3 | |
| 260 | ldx [%g2], %g3 | |
| 261 | ldx [%g2], %g3 | |
| 262 | ||
| 263 | esr_wrm: | |
| 264 | setx ERR_BITS_EXPECT, %g7, %g5 | |
| 265 | setx SOC_ESR_REG, %g7, %g2 | |
| 266 | setx 0x100, %g7, %g6 | |
| 267 | esr_loop_wrm: | |
| 268 | dec %g6 | |
| 269 | cmp %g6, %g0 | |
| 270 | be %xcc, test_failed | |
| 271 | nop | |
| 272 | ||
| 273 | ldx [%g2], %g3 | |
| 274 | ||
| 275 | cmp %g3, %g5 | |
| 276 | be %xcc, eie_reg_ones_wrm | |
| 277 | nop | |
| 278 | ||
| 279 | ba esr_loop_wrm | |
| 280 | nop | |
| 281 | ||
| 282 | ||
| 283 | eie_reg_ones_wrm: | |
| 284 | setx SOC_EIE_REG, %g3, %g2 | |
| 285 | set ERR_BITS, %g1 | |
| 286 | stx %g1, [%g2] | |
| 287 | membar 0x40 | |
| 288 | ||
| 289 | set 0x2, %g1 | |
| 290 | setx 0x100, %g7, %g6 | |
| 291 | err_trap_loop_wrm: | |
| 292 | cmp %g6, %g0 | |
| 293 | be %xcc, test_failed | |
| 294 | nop | |
| 295 | ||
| 296 | cmp %g1, %i7 | |
| 297 | be %xcc, check_tt_wrm | |
| 298 | nop | |
| 299 | ||
| 300 | ba err_trap_loop_wrm | |
| 301 | nop | |
| 302 | ||
| 303 | check_tt_wrm: | |
| 304 | mov 0x40, %l0 | |
| 305 | cmp %o7, %l0 | |
| 306 | bne %xcc, test_failed | |
| 307 | nop | |
| 308 | ||
| 309 | ||
| 310 | test_passed: | |
| 311 | EXIT_GOOD | |
| 312 | ||
| 313 | test_failed: | |
| 314 | EXIT_BAD | |
| 315 | ||
| 316 | ||
| 317 | /************************************************************************ | |
| 318 | RAS | |
| 319 | Trap Handlers | |
| 320 | ************************************************************************/ | |
| 321 | My_Recoverable_Sw_error_trap: | |
| 322 | ! Signal trap taken | |
| 323 | setx EXECUTED, %l0, %o6 | |
| 324 | ! save trap type value | |
| 325 | rdpr %tt, %o7 | |
| 326 | ||
| 327 | inc %i7 | |
| 328 | ||
| 329 | check_desr_NcuTrap_tt40: | |
| 330 | ldxa [%g0]0x4c, %g2 | |
| 331 | nop | |
| 332 | ||
| 333 | setx 0xb300000000000000, %l0, %g3 | |
| 334 | subcc %g2, %g3, %g4 | |
| 335 | brnz %g4, l2_trap | |
| 336 | nop | |
| 337 | ||
| 338 | check_per_tt40: | |
| 339 | setx ERR_BITS_EXPECT, %g7, %g5 !valid bit | |
| 340 | ||
| 341 | setx SOC_PER_REG, %l7, %g1 | |
| 342 | ldx [%g1], %g2 | |
| 343 | ||
| 344 | sub %g2, %g5, %g3 | |
| 345 | brnz %g3, test_failed | |
| 346 | nop | |
| 347 | ||
| 348 | clear_per_tt40: | |
| 349 | setx SOC_PER_REG, %l7, %g1 | |
| 350 | stx %g0, [%g1] | |
| 351 | nop | |
| 352 | ||
| 353 | clear_ejr_tt40: | |
| 354 | setx SOC_EJR_REG, %l7, %g1 | |
| 355 | stx %g0, [%g1] | |
| 356 | nop | |
| 357 | ||
| 358 | clear_eie_tt40: | |
| 359 | setx SOC_EIE_REG, %l7, %g1 | |
| 360 | stx %g0, [%g1] | |
| 361 | nop | |
| 362 | ||
| 363 | ba trap_done_tt40 | |
| 364 | nop | |
| 365 | ||
| 366 | ||
| 367 | l2_trap: | |
| 368 | nop | |
| 369 | inc %i0 | |
| 370 | ||
| 371 | check_desr_L2Trap_tt40: | |
| 372 | setx 0xb000000000000000, %l0, %g3 | |
| 373 | subcc %g2, %g3, %g4 | |
| 374 | brnz %g4, test_failed | |
| 375 | nop | |
| 376 | ||
| 377 | check_mcu2_esr_L2Trap_tt40: | |
| 378 | mov 0x1, %l1 | |
| 379 | sllx %l1, DRAM_ES_DBU, %l0 | |
| 380 | ||
| 381 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
| 382 | ldx [%g5], %l3 | |
| 383 | ||
| 384 | setx 0xffffffffffff0000, %l2, %l1 | |
| 385 | andcc %l1, %l3, %l4 ! Donot check SYND bits | |
| 386 | ||
| 387 | sub %l0, %l4, %i4 | |
| 388 | brnz %i4, test_failed | |
| 389 | nop | |
| 390 | ||
| 391 | clear_mcu_esr_L2Trap_tt40: | |
| 392 | stx %g0, [%g5] | |
| 393 | ||
| 394 | ||
| 395 | check_L2_4_ESR_L2Trap_tt40: | |
| 396 | setx L2_ERR_STAT_REG, %l3, %g5 | |
| 397 | ldx [%g5], %l6 | |
| 398 | ||
| 399 | setx 0xfffffffff0000000, %l3, %l0 | |
| 400 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits | |
| 401 | ||
| 402 | mov 0x1, %l1 | |
| 403 | sllx %l1, L2ES_DAU, %l0 | |
| 404 | ||
| 405 | mov 0x1, %l1 | |
| 406 | sllx %l1, L2ES_VEU, %l2 | |
| 407 | ||
| 408 | or %l0, %l2, %i4 | |
| 409 | ||
| 410 | cmp %l5, %i4 | |
| 411 | bne %xcc, test_failed | |
| 412 | nop | |
| 413 | ||
| 414 | clear_l2_esr_L2Trap_tt40: | |
| 415 | stx %g0, [%g5] | |
| 416 | ||
| 417 | trap_done_tt40: | |
| 418 | retry | |
| 419 | nop | |
| 420 | ||
| 421 | ||
| 422 | ||
| 423 | My_Corrected_ECC_error_trap: | |
| 424 | ba test_failed | |
| 425 | nop | |
| 426 | ||
| 427 | ||
| 428 | /************************************************************************ | |
| 429 | Test case data start | |
| 430 | ************************************************************************/ | |
| 431 | ||
| 432 | SECTION .DATA DATA_VA=DMA_DATA_ADDR | |
| 433 | attr_data { | |
| 434 | Name = .DATA, | |
| 435 | hypervisor, | |
| 436 | compressimage | |
| 437 | } | |
| 438 | ||
| 439 | .data | |
| 440 | .global PCIAddr9 | |
| 441 | .xword 0x0001020304050607 | |
| 442 | .xword 0x08090a0b0c0d0e0f | |
| 443 | .xword 0x1011121314151617 | |
| 444 | .xword 0x18191a1b1c1d1e1f | |
| 445 | .xword 0x2021222324252627 | |
| 446 | .xword 0x28292a2b2c2d2e2f | |
| 447 | .xword 0x3031323334353637 | |
| 448 | .xword 0x38393a3b3c3d3e3f | |
| 449 | ||
| 450 | .xword 0x4041424344454647 | |
| 451 | .xword 0x48494a4b4c4d4e4f | |
| 452 | .xword 0x5051525354555657 | |
| 453 | .xword 0x58595a5b5c5d5e5f | |
| 454 | .xword 0x6061626364656667 | |
| 455 | .xword 0x68696a6b6c6d6e6f | |
| 456 | .xword 0x7071727374757677 | |
| 457 | .xword 0x78797a7b7c7d7e7f | |
| 458 | ||
| 459 | .xword 0x8081828384858687 | |
| 460 | .xword 0x88898a8b8c8d8e8f | |
| 461 | .xword 0x9091929394959697 | |
| 462 | .xword 0x98999a9b9c9d9e9f | |
| 463 | .xword 0xa0a1a2a3a4a5a6a7 | |
| 464 | .xword 0xa8a9aaabacadaeaf | |
| 465 | .xword 0xb0b1b2b3b4b5b6b7 | |
| 466 | .xword 0xb8b9babbbcbdbebf | |
| 467 | ||
| 468 | .xword 0xc0c1c2c3c4c5c6c7 | |
| 469 | .xword 0xc8c9cacbcccdcecf | |
| 470 | .xword 0xd0d1d2d3d4d5d6d7 | |
| 471 | .xword 0xd8d9dadbdcdddedf | |
| 472 | .xword 0xe0e1e2e3e4e5e6e7 | |
| 473 | .xword 0xe8e9eaebecedeeef | |
| 474 | .xword 0xf0f1f2f3f4f5f6f7 | |
| 475 | .xword 0xf8f9fafbfcfdfeff | |
| 476 | ||
| 477 | .xword 0x0001020304050607 | |
| 478 | .xword 0x08090a0b0c0d0e0f | |
| 479 | .xword 0x1011121314151617 | |
| 480 | .xword 0x18191a1b1c1d1e1f | |
| 481 | .xword 0x2021222324252627 | |
| 482 | .xword 0x28292a2b2c2d2e2f | |
| 483 | .xword 0x3031323334353637 | |
| 484 | .xword 0x38393a3b3c3d3e3f | |
| 485 | ||
| 486 | .xword 0x4041424344454647 | |
| 487 | .xword 0x48494a4b4c4d4e4f | |
| 488 | .xword 0x5051525354555657 | |
| 489 | .xword 0x58595a5b5c5d5e5f | |
| 490 | .xword 0x6061626364656667 | |
| 491 | .xword 0x68696a6b6c6d6e6f | |
| 492 | .xword 0x7071727374757677 | |
| 493 | .xword 0x78797a7b7c7d7e7f | |
| 494 | ||
| 495 | .xword 0x8081828384858687 | |
| 496 | .xword 0x88898a8b8c8d8e8f | |
| 497 | .xword 0x9091929394959697 | |
| 498 | .xword 0x98999a9b9c9d9e9f | |
| 499 | .xword 0xa0a1a2a3a4a5a6a7 | |
| 500 | .xword 0xa8a9aaabacadaeaf | |
| 501 | .xword 0xb0b1b2b3b4b5b6b7 | |
| 502 | .xword 0xb8b9babbbcbdbebf | |
| 503 | ||
| 504 | .xword 0xc0c1c2c3c4c5c6c7 | |
| 505 | .xword 0xc8c9cacbcccdcecf | |
| 506 | .xword 0xd0d1d2d3d4d5d6d7 | |
| 507 | .xword 0xd8d9dadbdcdddedf | |
| 508 | .xword 0xe0e1e2e3e4e5e6e7 | |
| 509 | .xword 0xe8e9eaebecedeeef | |
| 510 | .xword 0xf0f1f2f3f4f5f6f7 | |
| 511 | .xword 0xf8f9fafbfcfdfeff | |
| 512 | ||
| 513 | /************************************************************************/ | |
| 514 |