[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_mcuUe_SiiDmuctagUe.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_adv_mcuUe_SiiDmuctagUe.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_ADDR1      0xfffc000123456700
#define DMA_DATA_BYP_ADDR2      0xfffc000123456780
#define DMA_DATA_BYP_ADDR3      0xfffc000123456800

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_SADDR      0xfffc000123456700
#define DMA_DATA_BYP_EADDR      0xfffc000123456800

#define TEST_DATA1		0x55555555
#define PA1                     0x2000aa00
#define PA2                     0x1000aa00

#define  DRAM_ERR_INJ_REG   	0x8400000290
#define L2_ERR_STAT_REG        	0xAB00000000

#define ERR_BITS                0x2

   
#ifdef L2_0
#define ADDR1                   0xfffc00002000aa00
#define DRAM_ERR_STAT_REG	0x8400000280
#define DRAM_ERR_INJ_REG	0x8400000290
#define L2_BANK_ADDR		0x00
#endif
  
#ifdef L2_1
#define ADDR1                   0xfffc00002000aa40
#define DRAM_ERR_STAT_REG       0x8400000280
#define DRAM_ERR_INJ_REG        0x8400000290
#define L2_BANK_ADDR            0x40

#endif

#ifdef L2_2
#define ADDR1                   0xfffc00002000aa80
#define DRAM_ERR_STAT_REG       0x8400001280
#define DRAM_ERR_INJ_REG        0x8400001290
#define L2_BANK_ADDR            0x80

#endif

#ifdef L2_3
#define ADDR1                   0xfffc00002000aac0
#define DRAM_ERR_STAT_REG       0x8400001280
#define DRAM_ERR_INJ_REG        0x8400001290
#define L2_BANK_ADDR            0xc0

#endif
  
#ifdef L2_4
#define ADDR1                   0xfffc00002000ab00
#define DRAM_ERR_STAT_REG       0x8400002280
#define DRAM_ERR_INJ_REG        0x8400002290
#define L2_BANK_ADDR            0x100

#endif

#ifdef L2_5
#define ADDR1                   0xfffc00002000ab40
#define DRAM_ERR_STAT_REG       0x8400002280
#define DRAM_ERR_INJ_REG        0x8400002290
#define L2_BANK_ADDR            0x140

#endif

#ifdef L2_6
#define ADDR1                   0xfffc00002000ab80
#define DRAM_ERR_STAT_REG       0x8400003280
#define DRAM_ERR_INJ_REG        0x8400003290
#define L2_BANK_ADDR            0x180

#endif

#ifdef L2_7
#define ADDR1                   0xfffc00002000abc0
#define DRAM_ERR_STAT_REG       0x8400003280
#define DRAM_ERR_INJ_REG        0x8400003290
#define L2_BANK_ADDR            0x1c0

#endif
 
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

	clr	%i7
	clr	%o6
	clr	%o7
	clr	%i0

disable_l1:
  	ldxa  [%g0] ASI_LSU_CONTROL, %l0
  	! Remove the lower 2 bits (I-Cache and D-Cache enables)
  	andn  %l0, 0x3, %l0
  	stxa  %l0, [%g0] ASI_LSU_CONTROL

set_DRAM_error_inject_ch0:
	mov   0x606, %l1                ! ECC Mask (2-bit error)
	mov   0x1, %l2
	sllx  %l2, DRAM_EI_SSHOT, %l3
	Or    %l1, %l3, %l1           ! Set single shot ;
	mov   0x1, %l2
	sllx  %l2, DRAM_EI_ENB, %l3
	or    %l1, %l3, %l1           ! Enable error injection for the next write
	setx  DRAM_ERR_INJ_REG, %l3, %g6
	stx   %l1, [%g6]
	membar 0x40

L2_err_enable:
        set     0x3, %l1
        mov     0xaa, %g2
        sllx    %g2, 32, %g2
        stx     %l1, [%g2]
        stx     %l1, [%g2 + 0x40]
        stx     %l1, [%g2 + 0x80]
        stx     %l1, [%g2 + 0xc0]
        stx     %l1, [%g2 + 0x100]
        stx     %l1, [%g2 + 0x140]
        stx     %l1, [%g2 + 0x180]
        stx     %l1, [%g2 + 0x1c0]

set_L2_Directly_Mapped_Mode:
	setx  L2CS_PA0, %l6, %g1
	add   %g1, L2_BANK_ADDR, %g1
	mov   0x2, %l0
	stx   %l0, [%g1]

store_to_L2_way0:
	set  TEST_DATA1, %g5
	set  PA1, %g2  ! bits [21:18] select way
        add   %g2, L2_BANK_ADDR, %g2

	stx %g5, [%g2]
	membar #Sync

	! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
	set  PA2, %g3 ! bits [21:18] select way
        add   %g3, L2_BANK_ADDR, %g3

	stx %g5, [%g3]
	membar #Sync

piu_iommu:
        ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

	/*******************************************************
		RDD from DMU
	********************************************************/

set_ejr_rdd:
	set	ERR_BITS, %g5

	setx	SOC_EJR_REG, %l7, %i3
	stx	%g5, [%i3]
	membar	0x40

dma_rdd:
	nop
UsrEvnt_rdd:
        nop         ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_DROP", ADDR1, ADDR1, "64'h40", 1, *, * )

        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3

l2_esr:
        mov     0x1, %g1
        sllx    %g1, L2ES_DRU, %g2

        mov     0x1, %g1
        sllx    %g1, L2ES_VEU, %g3

        or      %g2, %g3, %g4

        setx	0x7ffffffff0000000, %g7, %g5
	setx	0x30, %g7, %g6
check_l2_esr:
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop
	dec	%g6

	setx	L2_ERR_STAT_REG, %g7, %g1  
        add     %g1, L2_BANK_ADDR, %g1

	ldx	[%g1], %g2
	andcc	%g2, %g5, %g3			! Donot check L2ESR SYND bits and MEC

	cmp	%g3, %g4
	bne	%xcc, check_l2_esr 
	nop

cause_trap:
	set	0x2000a000, %g1
        add     %g1, L2_BANK_ADDR, %g1
	stx	%g0, [%g1]

	set	0x800bb000, %g1
        add     %g1, L2_BANK_ADDR, %g1
	ldx	[%g1], %g2

	set	0x8300b000, %g1
        add     %g1, L2_BANK_ADDR, %g1
	setx	0x2222222222222222, %g3, %g2	
	stx	%g2, [%g1]	

	set	 0x6300b000, %g1	
        add     %g1, L2_BANK_ADDR, %g1
	ldx	[%g1], %g2

!eie_reg_ones_rdd:
!        setx    SOC_EIE_REG, %g3, %g2
!        setx 	0xffffffffffffffff, %g3, %g1
!        stx     %g1, [%g2]
!        membar  0x40

	set	0x1, %g1
        mov     0x30, %g6
err_trap_loop_rdd:
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop

	cmp	%g1, %i7
	be	%xcc, check_tt_rdd
	nop

	ba	err_trap_loop_rdd
	nop

check_tt_rdd:
        mov     0x40, %l0
        cmp     %o7, %l0
        bne     %xcc, test_failed
        nop


check_l2_trap_cnt:
	set	0x1, %l0
	cmp	%i0, %l0
	bne	test_failed
	nop

	setx	0x200, %g1, %g2
delay_loop:
	dec	%g2
	cmp	%g2, %g0
	bne	%xcc, delay_loop
	nop
	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

        inc	%i7

check_desr_NcuTrap_tt40:
        ldxa  [%g0]0x4c, %g2
        nop

        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, l2_trap 
	nop

check_per_tt40:
	ba	test_failed
	nop


l2_trap:
	nop
	inc	%i0

check_desr_L2Trap_tt40:
        setx    0xb000000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 
        nop

check_mcu2_esr_L2Trap_tt40:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_DAU, %l0

        setx  DRAM_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l3

        setx  0xffffffffffff0000, %l2, %l1
        andcc %l1, %l3, %l4                   ! Donot check SYND bits

        sub     %l0, %l4, %i4
        brnz    %i4, test_failed
        nop

clear_mcu_esr_L2Trap_tt40:
        stx     %g0, [%g5]


check_L2_4_ESR_L2Trap_tt40:
        setx  	L2_ERR_STAT_REG, %l3, %g5  
        add   %g5, L2_BANK_ADDR, %g5

        ldx   	[%g5], %l6

        setx  	0x7ffffffff0000000, %l3, %l0
        andcc 	%l0, %l6, %l5                   ! Donot check L2ESR SYND bits and MEU

        mov   	0x1, %l1
        sllx  	%l1, L2ES_DRU, %l0

        mov   	0x1, %l1
        sllx  	%l1, L2ES_VEU, %l2

        or    	%l0, %l2, %i4

        cmp   	%l5, %i4
        bne   	%xcc, test_failed
        nop

clear_l2_esr_L2Trap_tt40:
	stx	%g0, [%g5]

trap_done_tt40:
       	retry 
        nop


My_Corrected_ECC_error_trap:
	ba	test_failed
        nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_adv_mcuUe_SiiDmuctagUe.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#include "err_defines.h"
	46	#include "hboot.s"
	47	#include "peu_defines.h"
	48
	49	#define DMA_DATA_ADDR 0x0000000123456700
	50	#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
	51	#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
	52	#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
	53
	54	#define DMA_DATA_ADDR 0x0000000123456700
	55	#define DMA_DATA_BYP_SADDR 0xfffc000123456700
	56	#define DMA_DATA_BYP_EADDR 0xfffc000123456800
	57
	58	#define TEST_DATA1 0x55555555
	59	#define PA1 0x2000aa00
	60	#define PA2 0x1000aa00
	61
	62	#define DRAM_ERR_INJ_REG 0x8400000290
	63	#define L2_ERR_STAT_REG 0xAB00000000
	64
65	#define ERR_BITS 0x2
66
67
68	#ifdef L2_0
69	#define ADDR1 0xfffc00002000aa00
70	#define DRAM_ERR_STAT_REG 0x8400000280
71	#define DRAM_ERR_INJ_REG 0x8400000290
72	#define L2_BANK_ADDR 0x00
73	#endif
74
75	#ifdef L2_1
76	#define ADDR1 0xfffc00002000aa40
77	#define DRAM_ERR_STAT_REG 0x8400000280
78	#define DRAM_ERR_INJ_REG 0x8400000290
79	#define L2_BANK_ADDR 0x40
80
81	#endif
82
83	#ifdef L2_2
84	#define ADDR1 0xfffc00002000aa80
85	#define DRAM_ERR_STAT_REG 0x8400001280
86	#define DRAM_ERR_INJ_REG 0x8400001290
87	#define L2_BANK_ADDR 0x80
88
89	#endif
90
91	#ifdef L2_3
92	#define ADDR1 0xfffc00002000aac0
93	#define DRAM_ERR_STAT_REG 0x8400001280
94	#define DRAM_ERR_INJ_REG 0x8400001290
95	#define L2_BANK_ADDR 0xc0
96
97	#endif
98
99	#ifdef L2_4
100	#define ADDR1 0xfffc00002000ab00
101	#define DRAM_ERR_STAT_REG 0x8400002280
102	#define DRAM_ERR_INJ_REG 0x8400002290
103	#define L2_BANK_ADDR 0x100
104
105	#endif
106
107	#ifdef L2_5
108	#define ADDR1 0xfffc00002000ab40
109	#define DRAM_ERR_STAT_REG 0x8400002280
110	#define DRAM_ERR_INJ_REG 0x8400002290
111	#define L2_BANK_ADDR 0x140
112
113	#endif
114
115	#ifdef L2_6
116	#define ADDR1 0xfffc00002000ab80
117	#define DRAM_ERR_STAT_REG 0x8400003280
118	#define DRAM_ERR_INJ_REG 0x8400003290
119	#define L2_BANK_ADDR 0x180
120
121	#endif
122
123	#ifdef L2_7
124	#define ADDR1 0xfffc00002000abc0
125	#define DRAM_ERR_STAT_REG 0x8400003280
126	#define DRAM_ERR_INJ_REG 0x8400003290
127	#define L2_BANK_ADDR 0x1c0
128
129	#endif
130
131	/************************************************************************
132	Test case code start
133	************************************************************************/
134	.text
135	.global main
136	.global My_Corrected_ECC_error_trap
137	.global My_Recoverable_Sw_error_trap
138
139	main:
140	ta T_CHANGE_HPRIV
141	nop
142
143	clr %i7
144	clr %o6
145	clr %o7
146	clr %i0
147
148	disable_l1:
149	ldxa [%g0] ASI_LSU_CONTROL, %l0
150	! Remove the lower 2 bits (I-Cache and D-Cache enables)
151	andn %l0, 0x3, %l0
152	stxa %l0, [%g0] ASI_LSU_CONTROL
153
154	set_DRAM_error_inject_ch0:
155	mov 0x606, %l1 ! ECC Mask (2-bit error)
156	mov 0x1, %l2
157	sllx %l2, DRAM_EI_SSHOT, %l3
158	Or %l1, %l3, %l1 ! Set single shot ;
159	mov 0x1, %l2
160	sllx %l2, DRAM_EI_ENB, %l3
161	or %l1, %l3, %l1 ! Enable error injection for the next write
162	setx DRAM_ERR_INJ_REG, %l3, %g6
163	stx %l1, [%g6]
164	membar 0x40
165
166	L2_err_enable:
167	set 0x3, %l1
168	mov 0xaa, %g2
169	sllx %g2, 32, %g2
170	stx %l1, [%g2]
171	stx %l1, [%g2 + 0x40]
172	stx %l1, [%g2 + 0x80]
173	stx %l1, [%g2 + 0xc0]
174	stx %l1, [%g2 + 0x100]
175	stx %l1, [%g2 + 0x140]
176	stx %l1, [%g2 + 0x180]
177	stx %l1, [%g2 + 0x1c0]
178
179	set_L2_Directly_Mapped_Mode:
180	setx L2CS_PA0, %l6, %g1
181	add %g1, L2_BANK_ADDR, %g1
182	mov 0x2, %l0
183	stx %l0, [%g1]
184
185	store_to_L2_way0:
186	set TEST_DATA1, %g5
187	set PA1, %g2 ! bits [21:18] select way
188	add %g2, L2_BANK_ADDR, %g2
189
190	stx %g5, [%g2]
191	membar #Sync
192
193	! Storing to same L2 way0 but different tag,this will write to mcu
194	write_mcu_channel_0:
195	set PA2, %g3 ! bits [21:18] select way
196	add %g3, L2_BANK_ADDR, %g3
197
198	stx %g5, [%g3]
199	membar #Sync
200
201	piu_iommu:
202	! enable bypass in IOMMU
203	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
204	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
205	stx %g3, [%g2]
206	ldx [%g2], %g3
207
208	/*******************************************************
209	RDD from DMU
210	********************************************************/
211
212	set_ejr_rdd:
213	set ERR_BITS, %g5
214
215	setx SOC_EJR_REG, %l7, %i3
216	stx %g5, [%i3]
217	membar 0x40
218
219	dma_rdd:
220	nop
221	UsrEvnt_rdd:
222	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_DROP", ADDR1, ADDR1, "64'h40", 1, , )
223
224	ldx [%g2], %g3
225	ldx [%g2], %g3
226	ldx [%g2], %g3
227	ldx [%g2], %g3
228
229	l2_esr:
230	mov 0x1, %g1
231	sllx %g1, L2ES_DRU, %g2
232
233	mov 0x1, %g1
234	sllx %g1, L2ES_VEU, %g3
235
236	or %g2, %g3, %g4
237
238	setx 0x7ffffffff0000000, %g7, %g5
239	setx 0x30, %g7, %g6
240	check_l2_esr:
241	cmp %g6, %g0
242	be %xcc, test_failed
243	nop
244	dec %g6
245
246	setx L2_ERR_STAT_REG, %g7, %g1
247	add %g1, L2_BANK_ADDR, %g1
248
249	ldx [%g1], %g2
250	andcc %g2, %g5, %g3 ! Donot check L2ESR SYND bits and MEC
251
252	cmp %g3, %g4
253	bne %xcc, check_l2_esr
254	nop
255
256	cause_trap:
257	set 0x2000a000, %g1
258	add %g1, L2_BANK_ADDR, %g1
259	stx %g0, [%g1]
260
261	set 0x800bb000, %g1
262	add %g1, L2_BANK_ADDR, %g1
263	ldx [%g1], %g2
264
265	set 0x8300b000, %g1
266	add %g1, L2_BANK_ADDR, %g1
267	setx 0x2222222222222222, %g3, %g2
268	stx %g2, [%g1]
269
270	set 0x6300b000, %g1
271	add %g1, L2_BANK_ADDR, %g1
272	ldx [%g1], %g2
273
274	!eie_reg_ones_rdd:
275	! setx SOC_EIE_REG, %g3, %g2
276	! setx 0xffffffffffffffff, %g3, %g1
277	! stx %g1, [%g2]
278	! membar 0x40
279
280	set 0x1, %g1
281	mov 0x30, %g6
282	err_trap_loop_rdd:
283	cmp %g6, %g0
284	be %xcc, test_failed
285	nop
286
287	cmp %g1, %i7
288	be %xcc, check_tt_rdd
289	nop
290
291	ba err_trap_loop_rdd
292	nop
293
294	check_tt_rdd:
295	mov 0x40, %l0
296	cmp %o7, %l0
297	bne %xcc, test_failed
298	nop
299
300
301	check_l2_trap_cnt:
302	set 0x1, %l0
303	cmp %i0, %l0
304	bne test_failed
305	nop
306
307	setx 0x200, %g1, %g2
308	delay_loop:
309	dec %g2
310	cmp %g2, %g0
311	bne %xcc, delay_loop
312	nop
313
314	test_passed:
315	EXIT_GOOD
316
317	test_failed:
318	EXIT_BAD
319
320
321	/************************************************************************
322	RAS
323	Trap Handlers
324	************************************************************************/
325	My_Recoverable_Sw_error_trap:
326	! Signal trap taken
327	setx EXECUTED, %l0, %o6
328	! save trap type value
329	rdpr %tt, %o7
330
331	inc %i7
332
333	check_desr_NcuTrap_tt40:
334	ldxa [%g0]0x4c, %g2
335	nop
336
337	setx 0xb300000000000000, %l0, %g3
338	subcc %g2, %g3, %g4
339	brnz %g4, l2_trap
340	nop
341
342	check_per_tt40:
343	ba test_failed
344	nop
345
346
347	l2_trap:
348	nop
349	inc %i0
350
351	check_desr_L2Trap_tt40:
352	setx 0xb000000000000000, %l0, %g3
353	subcc %g2, %g3, %g4
354	brnz %g4, test_failed
355	nop
356
357	check_mcu2_esr_L2Trap_tt40:
358	mov 0x1, %l1
359	sllx %l1, DRAM_ES_DAU, %l0
360
361	setx DRAM_ERR_STAT_REG, %l3, %g5
362	ldx [%g5], %l3
363
364	setx 0xffffffffffff0000, %l2, %l1
365	andcc %l1, %l3, %l4 ! Donot check SYND bits
366
367	sub %l0, %l4, %i4
368	brnz %i4, test_failed
369	nop
370
371	clear_mcu_esr_L2Trap_tt40:
372	stx %g0, [%g5]
373
374
375	check_L2_4_ESR_L2Trap_tt40:
376	setx L2_ERR_STAT_REG, %l3, %g5
377	add %g5, L2_BANK_ADDR, %g5
378
379	ldx [%g5], %l6
380
381	setx 0x7ffffffff0000000, %l3, %l0
382	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEU
383
384	mov 0x1, %l1
385	sllx %l1, L2ES_DRU, %l0
386
387	mov 0x1, %l1
388	sllx %l1, L2ES_VEU, %l2
389
390	or %l0, %l2, %i4
391
392	cmp %l5, %i4
393	bne %xcc, test_failed
394	nop
395
396	clear_l2_esr_L2Trap_tt40:
397	stx %g0, [%g5]
398
399	trap_done_tt40:
400	retry
401	nop
402
403
404
405	My_Corrected_ECC_error_trap:
406	ba test_failed
407	nop
408
409
410	/************************************************************************
411	Test case data start
412	************************************************************************/
413
414	SECTION .DATA DATA_VA=DMA_DATA_ADDR
415	attr_data {
416	Name = .DATA,
417	hypervisor,
418	compressimage
419	}
420
421	.data
422	.global PCIAddr9
423	.xword 0x0001020304050607
424	.xword 0x08090a0b0c0d0e0f
425	.xword 0x1011121314151617
426	.xword 0x18191a1b1c1d1e1f
427	.xword 0x2021222324252627
428	.xword 0x28292a2b2c2d2e2f
429	.xword 0x3031323334353637
430	.xword 0x38393a3b3c3d3e3f
431
432	.xword 0x4041424344454647
433	.xword 0x48494a4b4c4d4e4f
434	.xword 0x5051525354555657
435	.xword 0x58595a5b5c5d5e5f
436	.xword 0x6061626364656667
437	.xword 0x68696a6b6c6d6e6f
438	.xword 0x7071727374757677
439	.xword 0x78797a7b7c7d7e7f
440
441	.xword 0x8081828384858687
442	.xword 0x88898a8b8c8d8e8f
443	.xword 0x9091929394959697
444	.xword 0x98999a9b9c9d9e9f
445	.xword 0xa0a1a2a3a4a5a6a7
446	.xword 0xa8a9aaabacadaeaf
447	.xword 0xb0b1b2b3b4b5b6b7
448	.xword 0xb8b9babbbcbdbebf
449
450	.xword 0xc0c1c2c3c4c5c6c7
451	.xword 0xc8c9cacbcccdcecf
452	.xword 0xd0d1d2d3d4d5d6d7
453	.xword 0xd8d9dadbdcdddedf
454	.xword 0xe0e1e2e3e4e5e6e7
455	.xword 0xe8e9eaebecedeeef
456	.xword 0xf0f1f2f3f4f5f6f7
457	.xword 0xf8f9fafbfcfdfeff
458
459	.xword 0x0001020304050607
460	.xword 0x08090a0b0c0d0e0f
461	.xword 0x1011121314151617
462	.xword 0x18191a1b1c1d1e1f
463	.xword 0x2021222324252627
464	.xword 0x28292a2b2c2d2e2f
465	.xword 0x3031323334353637
466	.xword 0x38393a3b3c3d3e3f
467
468	.xword 0x4041424344454647
469	.xword 0x48494a4b4c4d4e4f
470	.xword 0x5051525354555657
471	.xword 0x58595a5b5c5d5e5f
472	.xword 0x6061626364656667
473	.xword 0x68696a6b6c6d6e6f
474	.xword 0x7071727374757677
475	.xword 0x78797a7b7c7d7e7f
476
477	.xword 0x8081828384858687
478	.xword 0x88898a8b8c8d8e8f
479	.xword 0x9091929394959697
480	.xword 0x98999a9b9c9d9e9f
481	.xword 0xa0a1a2a3a4a5a6a7
482	.xword 0xa8a9aaabacadaeaf
483	.xword 0xb0b1b2b3b4b5b6b7
484	.xword 0xb8b9babbbcbdbebf
485
486	.xword 0xc0c1c2c3c4c5c6c7
487	.xword 0xc8c9cacbcccdcecf
488	.xword 0xd0d1d2d3d4d5d6d7
489	.xword 0xd8d9dadbdcdddedf
490	.xword 0xe0e1e2e3e4e5e6e7
491	.xword 0xe8e9eaebecedeeef
492	.xword 0xf0f1f2f3f4f5f6f7
493	.xword 0xf8f9fafbfcfdfeff
494
495	/************************************************************************/
496