[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_mcuUe_piuRd.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_adv_mcuUe_piuRd.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_ADDR1      0xfffc000123456700
#define DMA_DATA_BYP_ADDR2      0xfffc000123456780
#define DMA_DATA_BYP_ADDR3      0xfffc000123456800

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_SADDR      0xfffc000123456700
#define DMA_DATA_BYP_EADDR      0xfffc000123456800

#define ADDR1      		0xfffc00002000aa00
#define TEST_DATA1		0xaaaaaaaaaaaaaaaa
#define  DRAM_ERR_INJ_REG   	0x8400000290

#define ERR_BITS                0x2
#define ERR_BITS_EXPECT         0x8000000000000002


#ifdef L2_0
#define L2CS_REG		0xA900000000
#define L2_ERR_STAT_REG         0xAB00000000

#define DRAM_ERR_INJ_REG	0x8400000290
#define DRAM_ERR_STAT_REG	0x8400000280
   
#define L2_ADDR1                0x2000aa00
#define L2_ADDR2                0x1000aa00

#define ADDR1                   0xfffc00002000aa00
#endif


#ifdef L2_1
#define L2CS_REG		0xA900000040
#define L2_ERR_STAT_REG         0xAB00000040

#define DRAM_ERR_INJ_REG	0x8400000290
#define DRAM_ERR_STAT_REG	0x8400000280
   
#define L2_ADDR1                0x2000aa40
#define L2_ADDR2                0x1000aa40

#define ADDR1                   0xfffc00002000aa40
#endif

#ifdef L2_2
#define L2CS_REG		0xA900000080
#define L2_ERR_STAT_REG         0xAB00000080

#define DRAM_ERR_INJ_REG	0x8400001290
#define DRAM_ERR_STAT_REG	0x8400001280
   
#define L2_ADDR1                0x2000aa80
#define L2_ADDR2                0x1000aa80

#define ADDR1                   0xfffc00002000aa80
#endif


#ifdef L2_3
#define L2CS_REG		0xA9000000c0
#define L2_ERR_STAT_REG         0xAB000000c0

#define DRAM_ERR_INJ_REG	0x8400001290
#define DRAM_ERR_STAT_REG	0x8400001280
   
#define L2_ADDR1                0x2000aac0
#define L2_ADDR2                0x1000aac0

#define ADDR1                   0xfffc00002000aac0
#endif

#ifdef L2_4
#define L2CS_REG		0xA900000100
#define L2_ERR_STAT_REG         0xAB00000100

#define DRAM_ERR_INJ_REG	0x8400002290
#define DRAM_ERR_STAT_REG	0x8400002280
   
#define L2_ADDR1                0x2000ab00
#define L2_ADDR2                0x1000ab00

#define ADDR1                   0xfffc00002000ab00
#endif

#ifdef L2_5
#define L2CS_REG		0xA900000140
#define L2_ERR_STAT_REG         0xAB00000140

#define DRAM_ERR_INJ_REG	0x8400002290
#define DRAM_ERR_STAT_REG	0x8400002280
   
#define L2_ADDR1                0x2000ab40
#define L2_ADDR2                0x1000ab40

#define ADDR1                   0xfffc00002000ab40
#endif

#ifdef L2_6
#define L2CS_REG		0xA900000180
#define L2_ERR_STAT_REG         0xAB00000180

#define DRAM_ERR_INJ_REG	0x8400003290
#define DRAM_ERR_STAT_REG	0x8400003280
   
#define L2_ADDR1                0x2000ab80
#define L2_ADDR2                0x1000ab80

#define ADDR1                   0xfffc00002000ab80
#endif

#ifdef L2_7
#define L2CS_REG		0xA9000001c0
#define L2_ERR_STAT_REG         0xAB000001c0

#define DRAM_ERR_INJ_REG	0x8400003290
#define DRAM_ERR_STAT_REG	0x8400003280
   
#define L2_ADDR1                0x2000abc0
#define L2_ADDR2                0x1000abc0

#define ADDR1                   0xfffc00002000abc0
#endif


/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

	clr	%i7
	clr	%o6
	clr	%o7
	clr	%i0

disable_l1:
  	ldxa  [%g0] ASI_LSU_CONTROL, %l0
  	! Remove the lower 2 bits (I-Cache and D-Cache enables)
  	andn  %l0, 0x3, %l0
  	stxa  %l0, [%g0] ASI_LSU_CONTROL

set_DRAM_error_inject_ch0:
	mov   0x606, %l1                ! ECC Mask (2-bit error)
	mov   0x1, %l2
	sllx  %l2, DRAM_EI_SSHOT, %l3
	Or    %l1, %l3, %l1           ! Set single shot ;
	mov   0x1, %l2
	sllx  %l2, DRAM_EI_ENB, %l3
	or    %l1, %l3, %l1           ! Enable error injection for the next write
	setx  DRAM_ERR_INJ_REG, %l3, %g6
	stx   %l1, [%g6]
	membar 0x40

L2_err_enable:
        set     0x3, %l1
        mov     0xaa, %g2
        sllx    %g2, 32, %g2
        stx     %l1, [%g2]
        stx     %l1, [%g2 + 0x40]
        stx     %l1, [%g2 + 0x80]
        stx     %l1, [%g2 + 0xc0]
        stx     %l1, [%g2 + 0x100]
        stx     %l1, [%g2 + 0x140]
        stx     %l1, [%g2 + 0x180]
        stx     %l1, [%g2 + 0x1c0]

set_L2_Directly_Mapped_Mode:
	setx  L2CS_REG, %l6, %g1
	mov   0x2, %l0
	stx   %l0, [%g1]

store_to_L2_way0:
	setx  TEST_DATA1, %l0, %g5
!	setx  0x2000aa00, %l0, %g2  ! bits [21:18] select way
	setx  L2_ADDR1, %l0, %g2  ! bits [21:18] select way
	stx %g5, [%g2]
	membar #Sync

	! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
!	setx  0x1000aa00, %l0, %g3 ! bits [21:18] select way
	setx  L2_ADDR2, %l0, %g3 ! bits [21:18] select way
	stx %g5, [%g3]
	membar #Sync

piu_iommu:
        ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

	/*******************************************************
		RDD from DMU
	********************************************************/

dma_rdd:
	nop
UsrEvnt_rdd:
        nop         ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, *, * )

        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3

l2_esr:
        mov     0x1, %g1
        sllx    %g1, L2ES_DRU, %g2

        mov     0x1, %g1
        sllx    %g1, L2ES_VEU, %g3

        or      %g2, %g3, %g4

        setx	0x7ffffffff0000000, %g7, %g5
	setx	0x30, %g7, %g6
check_l2_esr:
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop
	dec	%g6

	setx	L2_ERR_STAT_REG, %g7, %g1  
	ldx	[%g1], %g2
	andcc	%g2, %g5, %g3			! Donot check L2ESR SYND bits and MEC

	cmp	%g3, %g4
	bne	%xcc, check_l2_esr 
	nop

cause_trap:
	setx	0x2222222222222222, %g3, %g2
	setx	0x20008000, %g3, %g1
	stx	%g2, [%g1]
	setx	0x80080000, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000040, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80080040, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000080, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80080000, %g3, %g1
	ldx	[%g1], %g2

	setx	0x200080c0, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x800800c0, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000100, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80000100, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000140, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80000140, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000180, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80000180, %g3, %g1
	ldx	[%g1], %g2

	setx	0x200001c0, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x800001c0, %g3, %g1
	ldx	[%g1], %g2


eie_reg_ones_rdd:
        setx    SOC_EIE_REG, %g3, %g2
        setx 	0xffffffffffffffff, %g3, %g1
        stx     %g1, [%g2]
        membar  0x40

	set	0x1, %g1
        setx    0x30, %g7, %g6
err_trap_loop_rdd:
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop

	cmp	%g1, %i7
	be	%xcc, check_tt_rdd
	nop

	ba	err_trap_loop_rdd
	nop

check_tt_rdd:
        mov     0x40, %l0
        cmp     %o7, %l0
        bne     %xcc, test_failed
        nop


check_l2_trap_cnt:
	set	0x1, %l0
	cmp	%i0, %l0
	bne	test_failed
	nop

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

        inc	%i7

check_desr_NcuTrap_tt40:
        ldxa  [%g0]0x4c, %g2
        nop

        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, l2_trap 
	nop

check_per_tt40:
	ba	test_failed
	nop


l2_trap:
	nop
	inc	%i0

check_desr_L2Trap_tt40:
        setx    0xb000000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 
        nop

check_mcu2_esr_L2Trap_tt40:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_DAU, %l0

        setx  DRAM_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l3

        setx  0xffffffffffff0000, %l2, %l1
        andcc %l1, %l3, %l4                   ! Donot check SYND bits

        sub     %l0, %l4, %i4
        brnz    %i4, test_failed
        nop

clear_mcu_esr_L2Trap_tt40:
        stx     %g0, [%g5]


check_L2_4_ESR_L2Trap_tt40:
        setx  	L2_ERR_STAT_REG, %l3, %g5  
        ldx   	[%g5], %l6

        setx  	0x7ffffffff0000000, %l3, %l0
        andcc 	%l0, %l6, %l5                   ! Donot check L2ESR SYND bits and MEU

        mov   	0x1, %l1
        sllx  	%l1, L2ES_DRU, %l0

        mov   	0x1, %l1
        sllx  	%l1, L2ES_VEU, %l2

        or    	%l0, %l2, %i4

        cmp   	%l5, %i4
        bne   	%xcc, test_failed
        nop

clear_l2_esr_L2Trap_tt40:
	stx	%g0, [%g5]

trap_done_tt40:
       	retry 
        nop


My_Corrected_ECC_error_trap:
	ba	test_failed
        nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_adv_mcuUe_piuRd.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#include "err_defines.h"
	46	#include "hboot.s"
	47	#include "peu_defines.h"
	48
	49	#define DMA_DATA_ADDR 0x0000000123456700
	50	#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
	51	#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
	52	#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
	53
	54	#define DMA_DATA_ADDR 0x0000000123456700
	55	#define DMA_DATA_BYP_SADDR 0xfffc000123456700
	56	#define DMA_DATA_BYP_EADDR 0xfffc000123456800
	57
	58	#define ADDR1 0xfffc00002000aa00
	59	#define TEST_DATA1 0xaaaaaaaaaaaaaaaa
	60	#define DRAM_ERR_INJ_REG 0x8400000290
	61
	62	#define ERR_BITS 0x2
	63	#define ERR_BITS_EXPECT 0x8000000000000002
	64
65
66	#ifdef L2_0
67	#define L2CS_REG 0xA900000000
68	#define L2_ERR_STAT_REG 0xAB00000000
69
70	#define DRAM_ERR_INJ_REG 0x8400000290
71	#define DRAM_ERR_STAT_REG 0x8400000280
72
73	#define L2_ADDR1 0x2000aa00
74	#define L2_ADDR2 0x1000aa00
75
76	#define ADDR1 0xfffc00002000aa00
77	#endif
78
79
80	#ifdef L2_1
81	#define L2CS_REG 0xA900000040
82	#define L2_ERR_STAT_REG 0xAB00000040
83
84	#define DRAM_ERR_INJ_REG 0x8400000290
85	#define DRAM_ERR_STAT_REG 0x8400000280
86
87	#define L2_ADDR1 0x2000aa40
88	#define L2_ADDR2 0x1000aa40
89
90	#define ADDR1 0xfffc00002000aa40
91	#endif
92
93	#ifdef L2_2
94	#define L2CS_REG 0xA900000080
95	#define L2_ERR_STAT_REG 0xAB00000080
96
97	#define DRAM_ERR_INJ_REG 0x8400001290
98	#define DRAM_ERR_STAT_REG 0x8400001280
99
100	#define L2_ADDR1 0x2000aa80
101	#define L2_ADDR2 0x1000aa80
102
103	#define ADDR1 0xfffc00002000aa80
104	#endif
105
106
107	#ifdef L2_3
108	#define L2CS_REG 0xA9000000c0
109	#define L2_ERR_STAT_REG 0xAB000000c0
110
111	#define DRAM_ERR_INJ_REG 0x8400001290
112	#define DRAM_ERR_STAT_REG 0x8400001280
113
114	#define L2_ADDR1 0x2000aac0
115	#define L2_ADDR2 0x1000aac0
116
117	#define ADDR1 0xfffc00002000aac0
118	#endif
119
120	#ifdef L2_4
121	#define L2CS_REG 0xA900000100
122	#define L2_ERR_STAT_REG 0xAB00000100
123
124	#define DRAM_ERR_INJ_REG 0x8400002290
125	#define DRAM_ERR_STAT_REG 0x8400002280
126
127	#define L2_ADDR1 0x2000ab00
128	#define L2_ADDR2 0x1000ab00
129
130	#define ADDR1 0xfffc00002000ab00
131	#endif
132
133	#ifdef L2_5
134	#define L2CS_REG 0xA900000140
135	#define L2_ERR_STAT_REG 0xAB00000140
136
137	#define DRAM_ERR_INJ_REG 0x8400002290
138	#define DRAM_ERR_STAT_REG 0x8400002280
139
140	#define L2_ADDR1 0x2000ab40
141	#define L2_ADDR2 0x1000ab40
142
143	#define ADDR1 0xfffc00002000ab40
144	#endif
145
146	#ifdef L2_6
147	#define L2CS_REG 0xA900000180
148	#define L2_ERR_STAT_REG 0xAB00000180
149
150	#define DRAM_ERR_INJ_REG 0x8400003290
151	#define DRAM_ERR_STAT_REG 0x8400003280
152
153	#define L2_ADDR1 0x2000ab80
154	#define L2_ADDR2 0x1000ab80
155
156	#define ADDR1 0xfffc00002000ab80
157	#endif
158
159	#ifdef L2_7
160	#define L2CS_REG 0xA9000001c0
161	#define L2_ERR_STAT_REG 0xAB000001c0
162
163	#define DRAM_ERR_INJ_REG 0x8400003290
164	#define DRAM_ERR_STAT_REG 0x8400003280
165
166	#define L2_ADDR1 0x2000abc0
167	#define L2_ADDR2 0x1000abc0
168
169	#define ADDR1 0xfffc00002000abc0
170	#endif
171
172
173
174
175	/************************************************************************
176	Test case code start
177	************************************************************************/
178	.text
179	.global main
180	.global My_Corrected_ECC_error_trap
181	.global My_Recoverable_Sw_error_trap
182
183	main:
184	ta T_CHANGE_HPRIV
185	nop
186
187	clr %i7
188	clr %o6
189	clr %o7
190	clr %i0
191
192	disable_l1:
193	ldxa [%g0] ASI_LSU_CONTROL, %l0
194	! Remove the lower 2 bits (I-Cache and D-Cache enables)
195	andn %l0, 0x3, %l0
196	stxa %l0, [%g0] ASI_LSU_CONTROL
197
198	set_DRAM_error_inject_ch0:
199	mov 0x606, %l1 ! ECC Mask (2-bit error)
200	mov 0x1, %l2
201	sllx %l2, DRAM_EI_SSHOT, %l3
202	Or %l1, %l3, %l1 ! Set single shot ;
203	mov 0x1, %l2
204	sllx %l2, DRAM_EI_ENB, %l3
205	or %l1, %l3, %l1 ! Enable error injection for the next write
206	setx DRAM_ERR_INJ_REG, %l3, %g6
207	stx %l1, [%g6]
208	membar 0x40
209
210	L2_err_enable:
211	set 0x3, %l1
212	mov 0xaa, %g2
213	sllx %g2, 32, %g2
214	stx %l1, [%g2]
215	stx %l1, [%g2 + 0x40]
216	stx %l1, [%g2 + 0x80]
217	stx %l1, [%g2 + 0xc0]
218	stx %l1, [%g2 + 0x100]
219	stx %l1, [%g2 + 0x140]
220	stx %l1, [%g2 + 0x180]
221	stx %l1, [%g2 + 0x1c0]
222
223	set_L2_Directly_Mapped_Mode:
224	setx L2CS_REG, %l6, %g1
225	mov 0x2, %l0
226	stx %l0, [%g1]
227
228	store_to_L2_way0:
229	setx TEST_DATA1, %l0, %g5
230	! setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way
231	setx L2_ADDR1, %l0, %g2 ! bits [21:18] select way
232	stx %g5, [%g2]
233	membar #Sync
234
235	! Storing to same L2 way0 but different tag,this will write to mcu
236	write_mcu_channel_0:
237	! setx 0x1000aa00, %l0, %g3 ! bits [21:18] select way
238	setx L2_ADDR2, %l0, %g3 ! bits [21:18] select way
239	stx %g5, [%g3]
240	membar #Sync
241
242	piu_iommu:
243	! enable bypass in IOMMU
244	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
245	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
246	stx %g3, [%g2]
247	ldx [%g2], %g3
248
249	/*******************************************************
250	RDD from DMU
251	********************************************************/
252
253	dma_rdd:
254	nop
255	UsrEvnt_rdd:
256	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, , )
257
258	ldx [%g2], %g3
259	ldx [%g2], %g3
260	ldx [%g2], %g3
261	ldx [%g2], %g3
262
263	l2_esr:
264	mov 0x1, %g1
265	sllx %g1, L2ES_DRU, %g2
266
267	mov 0x1, %g1
268	sllx %g1, L2ES_VEU, %g3
269
270	or %g2, %g3, %g4
271
272	setx 0x7ffffffff0000000, %g7, %g5
273	setx 0x30, %g7, %g6
274	check_l2_esr:
275	cmp %g6, %g0
276	be %xcc, test_failed
277	nop
278	dec %g6
279
280	setx L2_ERR_STAT_REG, %g7, %g1
281	ldx [%g1], %g2
282	andcc %g2, %g5, %g3 ! Donot check L2ESR SYND bits and MEC
283
284	cmp %g3, %g4
285	bne %xcc, check_l2_esr
286	nop
287
288	cause_trap:
289	setx 0x2222222222222222, %g3, %g2
290	setx 0x20008000, %g3, %g1
291	stx %g2, [%g1]
292	setx 0x80080000, %g3, %g1
293	ldx [%g1], %g2
294
295	setx 0x20000040, %g3, %g1
296	stx %g2, [%g1]
297	setx 0x80080040, %g3, %g1
298	ldx [%g1], %g2
299
300	setx 0x20000080, %g3, %g1
301	stx %g2, [%g1]
302	setx 0x80080000, %g3, %g1
303	ldx [%g1], %g2
304
305	setx 0x200080c0, %g3, %g1
306	stx %g2, [%g1]
307	setx 0x800800c0, %g3, %g1
308	ldx [%g1], %g2
309
310	setx 0x20000100, %g3, %g1
311	stx %g2, [%g1]
312	setx 0x80000100, %g3, %g1
313	ldx [%g1], %g2
314
315	setx 0x20000140, %g3, %g1
316	stx %g2, [%g1]
317	setx 0x80000140, %g3, %g1
318	ldx [%g1], %g2
319
320	setx 0x20000180, %g3, %g1
321	stx %g2, [%g1]
322	setx 0x80000180, %g3, %g1
323	ldx [%g1], %g2
324
325	setx 0x200001c0, %g3, %g1
326	stx %g2, [%g1]
327	setx 0x800001c0, %g3, %g1
328	ldx [%g1], %g2
329
330
331	eie_reg_ones_rdd:
332	setx SOC_EIE_REG, %g3, %g2
333	setx 0xffffffffffffffff, %g3, %g1
334	stx %g1, [%g2]
335	membar 0x40
336
337	set 0x1, %g1
338	setx 0x30, %g7, %g6
339	err_trap_loop_rdd:
340	cmp %g6, %g0
341	be %xcc, test_failed
342	nop
343
344	cmp %g1, %i7
345	be %xcc, check_tt_rdd
346	nop
347
348	ba err_trap_loop_rdd
349	nop
350
351	check_tt_rdd:
352	mov 0x40, %l0
353	cmp %o7, %l0
354	bne %xcc, test_failed
355	nop
356
357
358	check_l2_trap_cnt:
359	set 0x1, %l0
360	cmp %i0, %l0
361	bne test_failed
362	nop
363
364	test_passed:
365	EXIT_GOOD
366
367	test_failed:
368	EXIT_BAD
369
370
371	/************************************************************************
372	RAS
373	Trap Handlers
374	************************************************************************/
375	My_Recoverable_Sw_error_trap:
376	! Signal trap taken
377	setx EXECUTED, %l0, %o6
378	! save trap type value
379	rdpr %tt, %o7
380
381	inc %i7
382
383	check_desr_NcuTrap_tt40:
384	ldxa [%g0]0x4c, %g2
385	nop
386
387	setx 0xb300000000000000, %l0, %g3
388	subcc %g2, %g3, %g4
389	brnz %g4, l2_trap
390	nop
391
392	check_per_tt40:
393	ba test_failed
394	nop
395
396
397	l2_trap:
398	nop
399	inc %i0
400
401	check_desr_L2Trap_tt40:
402	setx 0xb000000000000000, %l0, %g3
403	subcc %g2, %g3, %g4
404	brnz %g4, test_failed
405	nop
406
407	check_mcu2_esr_L2Trap_tt40:
408	mov 0x1, %l1
409	sllx %l1, DRAM_ES_DAU, %l0
410
411	setx DRAM_ERR_STAT_REG, %l3, %g5
412	ldx [%g5], %l3
413
414	setx 0xffffffffffff0000, %l2, %l1
415	andcc %l1, %l3, %l4 ! Donot check SYND bits
416
417	sub %l0, %l4, %i4
418	brnz %i4, test_failed
419	nop
420
421	clear_mcu_esr_L2Trap_tt40:
422	stx %g0, [%g5]
423
424
425	check_L2_4_ESR_L2Trap_tt40:
426	setx L2_ERR_STAT_REG, %l3, %g5
427	ldx [%g5], %l6
428
429	setx 0x7ffffffff0000000, %l3, %l0
430	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEU
431
432	mov 0x1, %l1
433	sllx %l1, L2ES_DRU, %l0
434
435	mov 0x1, %l1
436	sllx %l1, L2ES_VEU, %l2
437
438	or %l0, %l2, %i4
439
440	cmp %l5, %i4
441	bne %xcc, test_failed
442	nop
443
444	clear_l2_esr_L2Trap_tt40:
445	stx %g0, [%g5]
446
447	trap_done_tt40:
448	retry
449	nop
450
451
452
453	My_Corrected_ECC_error_trap:
454	ba test_failed
455	nop
456
457
458	/************************************************************************
459	Test case data start
460	************************************************************************/
461
462	SECTION .DATA DATA_VA=DMA_DATA_ADDR
463	attr_data {
464	Name = .DATA,
465	hypervisor,
466	compressimage
467	}
468
469	.data
470	.global PCIAddr9
471	.xword 0x0001020304050607
472	.xword 0x08090a0b0c0d0e0f
473	.xword 0x1011121314151617
474	.xword 0x18191a1b1c1d1e1f
475	.xword 0x2021222324252627
476	.xword 0x28292a2b2c2d2e2f
477	.xword 0x3031323334353637
478	.xword 0x38393a3b3c3d3e3f
479
480	.xword 0x4041424344454647
481	.xword 0x48494a4b4c4d4e4f
482	.xword 0x5051525354555657
483	.xword 0x58595a5b5c5d5e5f
484	.xword 0x6061626364656667
485	.xword 0x68696a6b6c6d6e6f
486	.xword 0x7071727374757677
487	.xword 0x78797a7b7c7d7e7f
488
489	.xword 0x8081828384858687
490	.xword 0x88898a8b8c8d8e8f
491	.xword 0x9091929394959697
492	.xword 0x98999a9b9c9d9e9f
493	.xword 0xa0a1a2a3a4a5a6a7
494	.xword 0xa8a9aaabacadaeaf
495	.xword 0xb0b1b2b3b4b5b6b7
496	.xword 0xb8b9babbbcbdbebf
497
498	.xword 0xc0c1c2c3c4c5c6c7
499	.xword 0xc8c9cacbcccdcecf
500	.xword 0xd0d1d2d3d4d5d6d7
501	.xword 0xd8d9dadbdcdddedf
502	.xword 0xe0e1e2e3e4e5e6e7
503	.xword 0xe8e9eaebecedeeef
504	.xword 0xf0f1f2f3f4f5f6f7
505	.xword 0xf8f9fafbfcfdfeff
506
507	.xword 0x0001020304050607
508	.xword 0x08090a0b0c0d0e0f
509	.xword 0x1011121314151617
510	.xword 0x18191a1b1c1d1e1f
511	.xword 0x2021222324252627
512	.xword 0x28292a2b2c2d2e2f
513	.xword 0x3031323334353637
514	.xword 0x38393a3b3c3d3e3f
515
516	.xword 0x4041424344454647
517	.xword 0x48494a4b4c4d4e4f
518	.xword 0x5051525354555657
519	.xword 0x58595a5b5c5d5e5f
520	.xword 0x6061626364656667
521	.xword 0x68696a6b6c6d6e6f
522	.xword 0x7071727374757677
523	.xword 0x78797a7b7c7d7e7f
524
525	.xword 0x8081828384858687
526	.xword 0x88898a8b8c8d8e8f
527	.xword 0x9091929394959697
528	.xword 0x98999a9b9c9d9e9f
529	.xword 0xa0a1a2a3a4a5a6a7
530	.xword 0xa8a9aaabacadaeaf
531	.xword 0xb0b1b2b3b4b5b6b7
532	.xword 0xb8b9babbbcbdbebf
533
534	.xword 0xc0c1c2c3c4c5c6c7
535	.xword 0xc8c9cacbcccdcecf
536	.xword 0xd0d1d2d3d4d5d6d7
537	.xword 0xd8d9dadbdcdddedf
538	.xword 0xe0e1e2e3e4e5e6e7
539	.xword 0xe8e9eaebecedeeef
540	.xword 0xf0f1f2f3f4f5f6f7
541	.xword 0xf8f9fafbfcfdfeff
542
543	/************************************************************************/
544