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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_adv_peu_piord_uev.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Data_access_error_0x32 My_Precise_data_access_error_trap | |
39 | ||
40 | #define ENABLE_PCIE_LINK_TRAINING | |
41 | #define MAIN_PAGE_HV_ALSO | |
42 | ||
43 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
44 | #define L2_ERR_STAT_REG 0xAB00000000 | |
45 | ||
46 | #include "err_defines.h" | |
47 | #include "hboot.s" | |
48 | #include "peu_defines.h" | |
49 | ||
50 | ||
51 | #define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) | IO_ACCESS_PA) | |
52 | ||
53 | /************************************************************************ | |
54 | Test case code start | |
55 | ************************************************************************/ | |
56 | .text | |
57 | .global main | |
58 | .global My_Precise_data_access_error_trap | |
59 | ||
60 | main: | |
61 | ta T_CHANGE_HPRIV | |
62 | nop | |
63 | ||
64 | clr %o7 | |
65 | clr %i7 | |
66 | ||
67 | inj_err_rdd: | |
68 | nop !$EV trig_pc_d(0,@VA(.MAIN.inj_err_rdd)) ->IosErrInj(ERR_TYPE, 8000, 0) | |
69 | ||
70 | pio: | |
71 | ! select an IO address in PCI address range and transmit the command to NCU | |
72 | setx IO_RD_ADDR, %g1, %g2 | |
73 | ||
74 | ! load byte - all byte offsets within an octlet | |
75 | ldub [%g2 + 1*8 + 0], %l0 | |
76 | membar 0x40 | |
77 | ||
78 | setx 0x20, %l1, %g4 | |
79 | delay_loop: | |
80 | nop | |
81 | nop | |
82 | nop | |
83 | nop | |
84 | dec %g4 | |
85 | brnz %g4, delay_loop | |
86 | nop | |
87 | ||
88 | count_number_traps: | |
89 | set 0x1, %i1 | |
90 | cmp %i1, %i7 | |
91 | bne %xcc, test_failed | |
92 | nop | |
93 | ||
94 | check_trap_type: | |
95 | setx 0x32, %g7, %i1 | |
96 | cmp %i1, %o7 | |
97 | bne %xcc, test_failed | |
98 | nop | |
99 | ||
100 | test_passed: | |
101 | EXIT_GOOD | |
102 | ||
103 | test_failed: | |
104 | EXIT_BAD | |
105 | ||
106 | ||
107 | /***********************************************************/ | |
108 | My_Precise_data_access_error_trap: | |
109 | rdpr %tt, %o7 | |
110 | inc %i7 | |
111 | ||
112 | ||
113 | check_DSFSR: | |
114 | set 0x18, %g3 | |
115 | ldxa [%g3] 0x58, %g2 | |
116 | ||
117 | set 0xf, %l1 | |
118 | and %g2, %l1, %l3 | |
119 | mov 0x4, %l5 ! content of D-SFSR Error type field = 0x4 (SOCU) | |
120 | cmp %l5, %l3 | |
121 | bne %xcc, test_failed | |
122 | nop | |
123 | ||
124 | ||
125 | check_mcu_esr_L2Trap_tt32: | |
126 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
127 | ldx [%g5], %l3 | |
128 | cmp %g0, %l3 | |
129 | bne %xcc, test_failed | |
130 | nop | |
131 | ||
132 | check_L2_4_ESR_L2Trap_tt32: | |
133 | setx L2_ERR_STAT_REG, %l3, %g5 | |
134 | ldx [%g5], %l6 | |
135 | ||
136 | cmp %l6, %g0 | |
137 | bne %xcc, test_failed | |
138 | nop | |
139 | ||
140 | check_mcu_esr_ncuesr_tt32: | |
141 | setx SOC_ESR_REG, %l3, %g5 | |
142 | ldx [%g5], %l3 | |
143 | cmp %g0, %l3 | |
144 | bne %xcc, test_failed | |
145 | nop | |
146 | ||
147 | ||
148 | trap_done_tt32: | |
149 | done | |
150 | nop | |
151 | ||
152 | /************************************************************************ | |
153 | Test case data start | |
154 | ************************************************************************/ | |
155 | ||
156 | SECTION .DATA DATA_VA=IO_RD_ADDR | |
157 | attr_data { | |
158 | Name = .DATA, | |
159 | hypervisor, | |
160 | compressimage | |
161 | } | |
162 | ||
163 | .data | |
164 | .xword 0xdeadbeefdeadbeef | |
165 | ||
166 | .xword 0x1101010101010101 | |
167 | .xword 0x0122010101010101 | |
168 | .xword 0x0101330101010101 | |
169 | .xword 0x0101014401010101 | |
170 | .xword 0x0101010155010101 | |
171 | .xword 0x0101010101660101 | |
172 | .xword 0x0101010101017701 | |
173 | .xword 0x0101010101010188 | |
174 | ||
175 | .xword 0x1122010101010101 | |
176 | .xword 0x0101334401010101 | |
177 | .xword 0x0101010155660101 | |
178 | .xword 0x0101010101017788 | |
179 | ||
180 | .xword 0x1122334401010101 | |
181 | .xword 0x0101010155667788 | |
182 | ||
183 | .xword 0xdeadbeefdeadbeef | |
184 | ||
185 | /************************************************************************/ |