[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_piu_int_ejr_nomondo.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_adv_piu_int_ejr_nomondo.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Sw_Recoverable_Error_0x40	 My_Recoverable_Sw_error_trap
    
#define MAIN_PAGE_HV_ALSO

#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
        call    my_trap_code; \
        nop; \
        retry; \
        nop; 

#define SOC_NCU_SYN_REG	 0x8000003038

#include "hboot.s"
#include "peu_defines.h"
#include "ncu_defines.h"

	
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global	 My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

lear_esr_first:
	setx	SOC_ESR_REG, %l7, %i0
	stx	%g0, [%i0]

set_ejr:
        set	0x1, %i1
	sllx	%i1, ERR_FIELD, %i2
	setx	SOC_EJR_REG, %l7, %i3
	stx	%i2, [%i3]
	membar	0x40


/*      Initialize the NCU for the interrupt.   */

        ! Disable interrupts


no_intr:
        rdpr    %pstate, %g7
        xor     %g7, 0x2, %g7           ! Reset interrupt enable
        wrpr    %g7, %pstate

	! Initialize NCU's Mondo Interrupt Vector Register
	! VECTOR = 63

ncu_mondo_int_vec:
	set	63, %g1
	setx	MONDO_INT_VEC, %g2, %g3
	stx	%g1, [%g3]

	! Clear NCU's Mondo Interrupt Busy registers.

ncu_mondo_int_busy:
	setx	MONDO_INT_ABUSY, %g1, %g2
	stx	%g0, [%g2]

	! Enable in MMU, TTE_INV_P, primary TTE valid bit not set error.

mmu_intr_enable_reg_init:
	setx	PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
	set	PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g3
	set	1, %g4
	sllx	%g4, %g3, %g4
	stx	%g4, [%g2]

	! Enable in IMU, MSI_MAL_ERR_P, malformed MSI message error.

imu_intr_enable_reg_init:
	setx	PCI_E_IMU_INT_ENB_ADDR, %g1, %g2
	set	PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g3
	set	1, %g4
	sllx	%g4, %g3, %g4
	stx	%g4, [%g2]

        ! Initialize Interrupt Mapping register
	! Valid, thread ID 0, no interrupt controller

pci_intr_map_reg_init:
        setx    PCI_E_INT_MAP_ADDR, %g1, %g7
        setx    PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
        add     %g7, %g3, %g7
        setx    0x80000040, %g1, %g6            ! valid = 1, thread id = 0
        stx     %g6, [%g7]                      ! interrupt controller = 1

yes_intr:
        rdpr    %pstate, %g7
        or      %g7, 0x2, %g7           ! Set interrupt enable
        wrpr    %g7, %pstate

	! Enable IMU, MMU interrupts in the DMU Core and Block
	! Interrupt Enable register.

dmu_core_block_enable:
	setx	PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
	setx	PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK, %g1, %g3
	setx	PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK, %g1, %g4
	or	%g3, %g4, %g4
	setx	PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK, %g1, %g3
	or	%g3, %g4, %g4
	stx	%g4, [%g2]
	membar	#Sync

	! Generate an interrupt from the IMU block.

gen_imu_intr:
	setx	PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
	set	1, %g6
	setx	PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g1, %g3
	sllx	%g6, %g3, %g6
	stx	%g6, [%g2]
	membar	#Sync

	! Wait for the interrupt trap

intr_wait1:
	setx	0x200, %g1, %g2			! timeout count
	setx	user_data_start, %g1, %g7

intr_wait_loop1:
	cmp	%g2, %g0
	be	read_esr
	nop

	dec	%g2

	ld	[%g7], %g5
	cmp	%g5, 1
	be	test_failed		! INT should not be sent to cross bar; so no INT
	nop

	ba	intr_wait_loop1
	nop

	/******************************
		Error Check
	******************************/
read_esr:
        setx	SOC_ESR_REG, %l7, %i0
	ldx	[%i0], %i1
	nop

	setx	0x8000000000000000, %l7, %o3	!valid bit
	set	0x1, %i2
	sllx	%i2, ERR_FIELD, %i3
	or	%i3, %o3, %i4
	sub	%i1, %i4, %i5
	brnz	%i5, test_failed
	nop

eie_reg_ones:
	setx    SOC_EIE_REG, %g3, %g2
	set	0x1, %i1
	sllx	%i1, ERR_FIELD, %g1
	stx	%g1, [%g2]
	membar	0x40

	setx	0x40, %g7, %g6
	set	0x1, %g1			! 1 Trap
err_trap_loop:
	cmp	    %g6, %g0
	be	%xcc, test_failed
	nop

	cmp	%g1, %i7
	be	%xcc, check_tt
	nop

	ba	err_trap_loop
	nop

check_tt:
        mov	0x40, %l0
	cmp	%o7,  %l0
	bne	%xcc, test_failed
	nop


	/********************************/


test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/**********************************************************************
   Interrupt trap handler.
**********************************************************************/

.global my_trap_code

my_trap_code:
	ba 	test_failed
	nop


/************************************************************************
	RAS
	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
	! Signal trap taken
	setx	EXECUTED, %l0, %o6
	! save trap type value
	rdpr	%tt, %o7

	inc	%i7

check_NcuSynd_tt40:
	setx	SOC_NCU_SYN_REG, %g7, %g1
	ldx	[%g1], %g2

	setx	0xfff8000000000000, %g7, %g1
	and	%g1, %g2, %g3

	setx	0xc070000000000000, %g7, %g2

	cmp	%g3, %g2
	bne	%xcc, test_failed
	nop

check_desr_tt40:
	ldxa  [%g0]0x4c, %g2
	nop
	setx	0xb300000000000000, %l0, %g3
	subcc	%g2, %g3, %g4
	brnz	%g4, test_failed 
	nop

check_DSFSR_tt32:
	set	0x18, %g1
	ldxa	[%g1]0x58, %g2
	nop
/*
	set	0x4, %g3
	subcc	%g2, %g3, %g4
	brnz	%g4, test_failed
	nop
*/


check_per_tt40:
	setx	SOC_PER_REG, %l7, %g1
	ldx	[%g1], %g2
	setx	0x8000000000000000, %g7, %g1
	set	0x1, %g3
	sllx	%g3, ERR_FIELD, %g4
	or	%g1, %g4, %g3
	sub	%g2, %g3, %g5
	brnz	%g5, test_failed
	nop

clear_per_tt40:
	setx	SOC_PER_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

clear_ejr_tt40:
	setx	SOC_EJR_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

clear_eie_tt40:
	setx	SOC_EIE_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

trap_done_tt40:
	done
	nop


/************************************************************************
   Test case data start
************************************************************************/

.align  1024
.data
user_data_start:
        .word   0x0
        .word   0x0
        .word   0x0
        .word   0x0
user_data_end:
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_adv_piu_int_ejr_nomondo.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	39
	40	#define MAIN_PAGE_HV_ALSO
	41
	42	#define H_HT0_Interrupt_0x60
	43	#define My_HT0_Interrupt_0x60 \
	44	call my_trap_code; \
	45	nop; \
	46	retry; \
	47	nop;
	48
	49	#define SOC_NCU_SYN_REG 0x8000003038
	50
	51	#include "hboot.s"
	52	#include "peu_defines.h"
	53	#include "ncu_defines.h"
	54
	55
	56	/************************************************************************
	57	Test case code start
	58	************************************************************************/
	59	.text
	60	.global main
	61	.global My_Recoverable_Sw_error_trap
	62
	63	main:
	64	ta T_CHANGE_HPRIV
65	nop
66
67	lear_esr_first:
68	setx SOC_ESR_REG, %l7, %i0
69	stx %g0, [%i0]
70
71	set_ejr:
72	set 0x1, %i1
73	sllx %i1, ERR_FIELD, %i2
74	setx SOC_EJR_REG, %l7, %i3
75	stx %i2, [%i3]
76	membar 0x40
77
78
79	/* Initialize the NCU for the interrupt. */
80
81	! Disable interrupts
82
83
84	no_intr:
85	rdpr %pstate, %g7
86	xor %g7, 0x2, %g7 ! Reset interrupt enable
87	wrpr %g7, %pstate
88
89	! Initialize NCU's Mondo Interrupt Vector Register
90	! VECTOR = 63
91
92	ncu_mondo_int_vec:
93	set 63, %g1
94	setx MONDO_INT_VEC, %g2, %g3
95	stx %g1, [%g3]
96
97	! Clear NCU's Mondo Interrupt Busy registers.
98
99	ncu_mondo_int_busy:
100	setx MONDO_INT_ABUSY, %g1, %g2
101	stx %g0, [%g2]
102
103	! Enable in MMU, TTE_INV_P, primary TTE valid bit not set error.
104
105	mmu_intr_enable_reg_init:
106	setx PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
107	set PCI_E_MMU_INT_EN_TTE_INV_P_SHIFT, %g3
108	set 1, %g4
109	sllx %g4, %g3, %g4
110	stx %g4, [%g2]
111
112	! Enable in IMU, MSI_MAL_ERR_P, malformed MSI message error.
113
114	imu_intr_enable_reg_init:
115	setx PCI_E_IMU_INT_ENB_ADDR, %g1, %g2
116	set PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g3
117	set 1, %g4
118	sllx %g4, %g3, %g4
119	stx %g4, [%g2]
120
121	! Initialize Interrupt Mapping register
122	! Valid, thread ID 0, no interrupt controller
123
124	pci_intr_map_reg_init:
125	setx PCI_E_INT_MAP_ADDR, %g1, %g7
126	setx PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
127	add %g7, %g3, %g7
128	setx 0x80000040, %g1, %g6 ! valid = 1, thread id = 0
129	stx %g6, [%g7] ! interrupt controller = 1
130
131	yes_intr:
132	rdpr %pstate, %g7
133	or %g7, 0x2, %g7 ! Set interrupt enable
134	wrpr %g7, %pstate
135
136	! Enable IMU, MMU interrupts in the DMU Core and Block
137	! Interrupt Enable register.
138
139	dmu_core_block_enable:
140	setx PCI_E_DMU_CORE_BLK_INT_ENB_ADDR, %g1, %g2
141	setx PCI_E_DMU_CORE_BLK_INT_EN_DMC_MASK, %g1, %g3
142	setx PCI_E_DMU_CORE_BLK_INT_EN_MMU_MASK, %g1, %g4
143	or %g3, %g4, %g4
144	setx PCI_E_DMU_CORE_BLK_INT_EN_IMU_MASK, %g1, %g3
145	or %g3, %g4, %g4
146	stx %g4, [%g2]
147	membar #Sync
148
149	! Generate an interrupt from the IMU block.
150
151	gen_imu_intr:
152	setx PCI_E_IMU_ERR_STAT_SET_ADDR, %g1, %g2
153	set 1, %g6
154	setx PCI_E_IMU_INT_EN_MSI_MAL_ERR_P_SHIFT, %g1, %g3
155	sllx %g6, %g3, %g6
156	stx %g6, [%g2]
157	membar #Sync
158
159	! Wait for the interrupt trap
160
161	intr_wait1:
162	setx 0x200, %g1, %g2 ! timeout count
163	setx user_data_start, %g1, %g7
164
165	intr_wait_loop1:
166	cmp %g2, %g0
167	be read_esr
168	nop
169
170	dec %g2
171
172	ld [%g7], %g5
173	cmp %g5, 1
174	be test_failed ! INT should not be sent to cross bar; so no INT
175	nop
176
177	ba intr_wait_loop1
178	nop
179
180	/******************************
181	Error Check
182	******************************/
183	read_esr:
184	setx SOC_ESR_REG, %l7, %i0
185	ldx [%i0], %i1
186	nop
187
188	setx 0x8000000000000000, %l7, %o3 !valid bit
189	set 0x1, %i2
190	sllx %i2, ERR_FIELD, %i3
191	or %i3, %o3, %i4
192	sub %i1, %i4, %i5
193	brnz %i5, test_failed
194	nop
195
196	eie_reg_ones:
197	setx SOC_EIE_REG, %g3, %g2
198	set 0x1, %i1
199	sllx %i1, ERR_FIELD, %g1
200	stx %g1, [%g2]
201	membar 0x40
202
203	setx 0x40, %g7, %g6
204	set 0x1, %g1 ! 1 Trap
205	err_trap_loop:
206	cmp %g6, %g0
207	be %xcc, test_failed
208	nop
209
210	cmp %g1, %i7
211	be %xcc, check_tt
212	nop
213
214	ba err_trap_loop
215	nop
216
217	check_tt:
218	mov 0x40, %l0
219	cmp %o7, %l0
220	bne %xcc, test_failed
221	nop
222
223
224	/********************************/
225
226
227	test_passed:
228	EXIT_GOOD
229
230	test_failed:
231	EXIT_BAD
232
233
234	/**********************************************************************
235	Interrupt trap handler.
236	**********************************************************************/
237
238	.global my_trap_code
239
240	my_trap_code:
241	ba test_failed
242	nop
243
244
245
246	/************************************************************************
247	RAS
248	Trap Handlers
249	************************************************************************/
250	My_Recoverable_Sw_error_trap:
251	! Signal trap taken
252	setx EXECUTED, %l0, %o6
253	! save trap type value
254	rdpr %tt, %o7
255
256	inc %i7
257
258	check_NcuSynd_tt40:
259	setx SOC_NCU_SYN_REG, %g7, %g1
260	ldx [%g1], %g2
261
262	setx 0xfff8000000000000, %g7, %g1
263	and %g1, %g2, %g3
264
265	setx 0xc070000000000000, %g7, %g2
266
267	cmp %g3, %g2
268	bne %xcc, test_failed
269	nop
270
271	check_desr_tt40:
272	ldxa [%g0]0x4c, %g2
273	nop
274	setx 0xb300000000000000, %l0, %g3
275	subcc %g2, %g3, %g4
276	brnz %g4, test_failed
277	nop
278
279	check_DSFSR_tt32:
280	set 0x18, %g1
281	ldxa [%g1]0x58, %g2
282	nop
283	/*
284	set 0x4, %g3
285	subcc %g2, %g3, %g4
286	brnz %g4, test_failed
287	nop
288	*/
289
290
291	check_per_tt40:
292	setx SOC_PER_REG, %l7, %g1
293	ldx [%g1], %g2
294	setx 0x8000000000000000, %g7, %g1
295	set 0x1, %g3
296	sllx %g3, ERR_FIELD, %g4
297	or %g1, %g4, %g3
298	sub %g2, %g3, %g5
299	brnz %g5, test_failed
300	nop
301
302	clear_per_tt40:
303	setx SOC_PER_REG, %l7, %g1
304	stx %g0, [%g1]
305	nop
306
307	clear_ejr_tt40:
308	setx SOC_EJR_REG, %l7, %g1
309	stx %g0, [%g1]
310	nop
311
312	clear_eie_tt40:
313	setx SOC_EIE_REG, %l7, %g1
314	stx %g0, [%g1]
315	nop
316
317	trap_done_tt40:
318	done
319	nop
320
321
322	/************************************************************************
323	Test case data start
324	************************************************************************/
325
326	.align 1024
327	.data
328	user_data_start:
329	.word 0x0
330	.word 0x0
331	.word 0x0
332	.word 0x0
333	user_data_end:
334	.end
335