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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_adv_piu_strm_rdd_ejr.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | #define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap | |
40 | ||
41 | #define ENABLE_PCIE_LINK_TRAINING | |
42 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ | |
43 | #define MAIN_PAGE_HV_ALSO | |
44 | ||
45 | #define DRAM_0_ERR_STAT_REG 0x8400000280 | |
46 | #define DRAM_1_ERR_STAT_REG 0x8400001280 | |
47 | #define DRAM_2_ERR_STAT_REG 0x8400002280 | |
48 | #define DRAM_3_ERR_STAT_REG 0x8400003280 | |
49 | ||
50 | #define L2_0_ERR_STAT_REG 0xAB00000000 | |
51 | #define L2_1_ERR_STAT_REG 0xAB00000040 | |
52 | #define L2_2_ERR_STAT_REG 0xAB00000080 | |
53 | #define L2_3_ERR_STAT_REG 0xAB000000c0 | |
54 | #define L2_4_ERR_STAT_REG 0xAB00000100 | |
55 | #define L2_5_ERR_STAT_REG 0xAB00000140 | |
56 | #define L2_6_ERR_STAT_REG 0xAB00000180 | |
57 | #define L2_7_ERR_STAT_REG 0xAB000001c0 | |
58 | ||
59 | ||
60 | #include "err_defines.h" | |
61 | #include "hboot.s" | |
62 | #include "peu_defines.h" | |
63 | ||
64 | #define DMA_DATA_ADDR 0x0000000123456700 | |
65 | ||
66 | #define DMA_DATA_BYP_ADDR1 0xfffc000123410000 | |
67 | #define DMA_DATA_BYP_ADDR2 0xfffc000123410200 | |
68 | #define DMA_DATA_BYP_ADDR3 0xfffc000123410400 | |
69 | #define DMA_DATA_BYP_ADDR4 0xfffc000123410600 | |
70 | #define DMA_DATA_BYP_ADDR5 0xfffc000123410800 | |
71 | #define DMA_DATA_BYP_ADDR6 0xfffc000123410a00 | |
72 | #define DMA_DATA_BYP_ADDR7 0xfffc000123410c00 | |
73 | #define DMA_DATA_BYP_ADDR8 0xfffc000123410e00 | |
74 | #define DMA_DATA_BYP_ADDR9 0xfffc000123411000 | |
75 | #define DMA_DATA_BYP_ADDR10 0xfffc000123411200 | |
76 | #define DMA_DATA_BYP_ADDR11 0xfffc000123411400 | |
77 | #define DMA_DATA_BYP_ADDR12 0xfffc000123411600 | |
78 | #define DMA_DATA_BYP_ADDR13 0xfffc000123411800 | |
79 | #define DMA_DATA_BYP_ADDR14 0xfffc000123411a00 | |
80 | #define DMA_DATA_BYP_ADDR15 0xfffc000123411c00 | |
81 | #define DMA_DATA_BYP_ADDR16 0xfffc000123411e00 | |
82 | #define DMA_DATA_BYP_ADDR17 0xfffc000123412000 | |
83 | #define DMA_DATA_BYP_ADDR18 0xfffc000123412200 | |
84 | #define DMA_DATA_BYP_ADDR19 0xfffc000123412400 | |
85 | #define DMA_DATA_BYP_ADDR20 0xfffc000123412600 | |
86 | #define DMA_DATA_BYP_ADDR21 0xfffc000123412800 | |
87 | #define DMA_DATA_BYP_ADDR22 0xfffc000123412a00 | |
88 | #define DMA_DATA_BYP_ADDR23 0xfffc000123412c00 | |
89 | ||
90 | #define SOC_SII_SYN_REG 0x8000003030 | |
91 | ||
92 | /************************************************************************ | |
93 | Test case code start | |
94 | ************************************************************************/ | |
95 | .text | |
96 | .global main | |
97 | .global My_Corrected_ECC_error_trap | |
98 | .global My_Recoverable_Sw_error_trap | |
99 | ||
100 | main: | |
101 | ta T_CHANGE_HPRIV | |
102 | nop | |
103 | ||
104 | clr %i7 | |
105 | clr %o6 | |
106 | clr %o7 | |
107 | clr %i0 | |
108 | ||
109 | ||
110 | L2_err_enable: | |
111 | set 0x3, %l1 | |
112 | mov 0xaa, %g2 | |
113 | sllx %g2, 32, %g2 | |
114 | stx %l1, [%g2] | |
115 | stx %l1, [%g2 + 0x40] | |
116 | stx %l1, [%g2 + 0x80] | |
117 | stx %l1, [%g2 + 0xc0] | |
118 | stx %l1, [%g2 + 0x100] | |
119 | stx %l1, [%g2 + 0x140] | |
120 | stx %l1, [%g2 + 0x180] | |
121 | stx %l1, [%g2 + 0x1c0] | |
122 | ||
123 | bypass_iommu: | |
124 | ! enable bypass in IOMMU | |
125 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
126 | setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3 | |
127 | stx %g3, [%g2] | |
128 | ldx [%g2], %g3 | |
129 | ||
130 | /******************************************************* | |
131 | RDD from DMU | |
132 | ********************************************************/ | |
133 | set_eie_rdd: | |
134 | mov 0x1, %g1 | |
135 | sllx %g1, ERR_FIELD, %g2 | |
136 | setx SOC_EIE_REG, %g7, %g3 | |
137 | stx %g2, [%g3] | |
138 | membar 0x40 | |
139 | ||
140 | ||
141 | set_ejr_1: | |
142 | setx SOC_EJR_REG, %g7, %g6 | |
143 | stx %g2, [%g6] | |
144 | membar 0x40 | |
145 | ||
146 | ||
147 | PIO1_noexp: nop; | |
148 | ! $EV trig_pc_d(1, @VA(.MAIN.PIO1_noexp)) -> EnablePCIeIgCmd ("PIO_NOEXP",0,0,0,1) | |
149 | ||
150 | PIO1: nop; nop; nop; nop; nop; nop; nop; nop;nop; nop; nop; nop; | |
151 | ||
152 | ||
153 | ||
154 | ||
155 | UsrEvnt_rdd_1: | |
156 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_1)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1, *, * ) | |
157 | ||
158 | ||
159 | setx 0x100, %g7, %g5 | |
160 | chk_ejr_1: | |
161 | cmp %g5, %g0 | |
162 | be %xcc, test_failed | |
163 | nop | |
164 | ||
165 | ldx [%g6], %g1 | |
166 | cmp %g1, %g0 | |
167 | be %xcc, UsrEvnt_rdd_2 | |
168 | nop | |
169 | ||
170 | dec %g5 | |
171 | ||
172 | ba chk_ejr_1 | |
173 | nop | |
174 | ||
175 | UsrEvnt_rdd_2: | |
176 | nop | |
177 | nop | |
178 | nop | |
179 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_2)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR2, DMA_DATA_BYP_ADDR2, "64'h40", 1, *, * ) | |
180 | ||
181 | UsrEvnt_rdd_3: | |
182 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_3)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR3, "64'h40", 1, *, * ) | |
183 | ||
184 | UsrEvnt_rdd_4: | |
185 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_4)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR4, DMA_DATA_BYP_ADDR4, "64'h40", 1, *, * ) | |
186 | ||
187 | UsrEvnt_rdd_5: | |
188 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_5)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR5, DMA_DATA_BYP_ADDR5, "64'h40", 1, *, * ) | |
189 | ||
190 | UsrEvnt_rdd_6: | |
191 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_6)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR6, DMA_DATA_BYP_ADDR6, "64'h40", 1, *, * ) | |
192 | ||
193 | UsrEvnt_rdd_7: | |
194 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_7)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR7, DMA_DATA_BYP_ADDR7, "64'h40", 1, *, * ) | |
195 | ||
196 | ||
197 | ||
198 | ||
199 | set_ejr_2: | |
200 | stx %g2, [%g6] | |
201 | membar 0x40 | |
202 | ||
203 | PIO2_noexp: nop; | |
204 | ! $EV trig_pc_d(1, @VA(.MAIN.PIO2_noexp)) -> EnablePCIeIgCmd ("PIO_NOEXP",0,0,0,1) | |
205 | ||
206 | PIO2: nop; nop; nop; nop; nop; nop; nop; nop;nop; nop; nop; nop; | |
207 | ||
208 | ||
209 | ||
210 | ||
211 | UsrEvnt_rdd_8: | |
212 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_8)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR8, DMA_DATA_BYP_ADDR8, "64'h40", 1, *, * ) | |
213 | ||
214 | ||
215 | setx 0x100, %g7, %g5 | |
216 | chk_ejr_2: | |
217 | cmp %g5, %g0 | |
218 | be %xcc, test_failed | |
219 | nop | |
220 | ||
221 | ldx [%g6], %g1 | |
222 | cmp %g1, %g0 | |
223 | be %xcc, UsrEvnt_rdd_9 | |
224 | nop | |
225 | ||
226 | dec %g5 | |
227 | ||
228 | ba chk_ejr_2 | |
229 | nop | |
230 | ||
231 | UsrEvnt_rdd_9: | |
232 | nop | |
233 | nop | |
234 | nop | |
235 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_9)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR9, DMA_DATA_BYP_ADDR9, "64'h40", 1, *, * ) | |
236 | ||
237 | UsrEvnt_rdd_10: | |
238 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_10)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR10, DMA_DATA_BYP_ADDR10, "64'h40", 1, *, * ) | |
239 | ||
240 | UsrEvnt_rdd_11: | |
241 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_11)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR11, DMA_DATA_BYP_ADDR11, "64'h40", 1, *, * ) | |
242 | ||
243 | UsrEvnt_rdd_12: | |
244 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_12)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR12, DMA_DATA_BYP_ADDR12, "64'h40", 1, *, * ) | |
245 | ||
246 | UsrEvnt_rdd_13: | |
247 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_13)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR13, DMA_DATA_BYP_ADDR13, "64'h40", 1, *, * ) | |
248 | ||
249 | ||
250 | ||
251 | ||
252 | set_ejr_3: | |
253 | stx %g2, [%g6] | |
254 | membar 0x40 | |
255 | ||
256 | ||
257 | PIO3_noexp: nop; | |
258 | ! $EV trig_pc_d(1, @VA(.MAIN.PIO3_noexp)) -> EnablePCIeIgCmd ("PIO_NOEXP",0,0,0,1) | |
259 | ||
260 | PIO3: nop; nop; nop; nop; nop; nop; nop; nop;nop; nop; nop; nop; nop; nop; nop; nop; | |
261 | ||
262 | UsrEvnt_rdd_14: | |
263 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_14)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR14, DMA_DATA_BYP_ADDR14, "64'h40", 1, *, * ) | |
264 | ||
265 | ||
266 | setx 0x100, %g7, %g5 | |
267 | chk_ejr_3: | |
268 | cmp %g5, %g0 | |
269 | be %xcc, test_failed | |
270 | nop | |
271 | ||
272 | ldx [%g6], %g1 | |
273 | cmp %g1, %g0 | |
274 | be %xcc, UsrEvnt_rdd_15 | |
275 | nop | |
276 | ||
277 | dec %g5 | |
278 | ||
279 | ba chk_ejr_3 | |
280 | nop | |
281 | ||
282 | UsrEvnt_rdd_15: | |
283 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_15)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR15, DMA_DATA_BYP_ADDR15, "64'h40", 1, *, * ) | |
284 | ||
285 | UsrEvnt_rdd_16: | |
286 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_16)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR16, DMA_DATA_BYP_ADDR16, "64'h40", 1, *, * ) | |
287 | ||
288 | UsrEvnt_rdd_17: | |
289 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_17)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR17, DMA_DATA_BYP_ADDR17, "64'h40", 1, *, * ) | |
290 | ||
291 | UsrEvnt_rdd_18: | |
292 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_18)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR18, DMA_DATA_BYP_ADDR18, "64'h40", 1, *, * ) | |
293 | ||
294 | UsrEvnt_rdd_19: | |
295 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_19)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR19, DMA_DATA_BYP_ADDR19, "64'h40", 1, *, * ) | |
296 | ||
297 | UsrEvnt_rdd_20: | |
298 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_20)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR20, DMA_DATA_BYP_ADDR20, "64'h40", 1, *, * ) | |
299 | ||
300 | UsrEvnt_rdd_21: | |
301 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_21)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR21, DMA_DATA_BYP_ADDR21, "64'h40", 1, *, * ) | |
302 | ||
303 | pios: | |
304 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
305 | ||
306 | ldx [%g2], %g3 | |
307 | ldx [%g2], %g3 | |
308 | ldx [%g2], %g3 | |
309 | ldx [%g2], %g3 | |
310 | ||
311 | !only checks that at least one trap taken | |
312 | err_trap_loop_rdd: | |
313 | cmp %g0, %i7 | |
314 | be %xcc, test_failed | |
315 | nop | |
316 | ||
317 | check_mcu_esr: | |
318 | setx DRAM_0_ERR_STAT_REG, %g7, %g6 | |
319 | ldx [%g6], %g3 | |
320 | sub %g3, %g0, %g1 | |
321 | brnz %g1, test_failed | |
322 | nop | |
323 | ||
324 | setx DRAM_1_ERR_STAT_REG, %g7, %g6 | |
325 | ldx [%g6], %g3 | |
326 | sub %g3, %g0, %g1 | |
327 | brnz %g1, test_failed | |
328 | nop | |
329 | ||
330 | setx DRAM_2_ERR_STAT_REG, %g7, %g6 | |
331 | ldx [%g6], %g3 | |
332 | sub %g3, %g0, %g1 | |
333 | brnz %g1, test_failed | |
334 | nop | |
335 | ||
336 | setx DRAM_3_ERR_STAT_REG, %g7, %g6 | |
337 | ldx [%g6], %g3 | |
338 | sub %g3, %g0, %g1 | |
339 | brnz %g1, test_failed | |
340 | nop | |
341 | ||
342 | check_L2_ESR: | |
343 | setx L2_0_ERR_STAT_REG, %l3, %g5 | |
344 | ldx [%g5], %g3 | |
345 | sub %g3, %g0, %g1 | |
346 | brnz %g1, test_failed | |
347 | nop | |
348 | ||
349 | setx L2_1_ERR_STAT_REG, %l3, %g5 | |
350 | ldx [%g5], %g3 | |
351 | sub %g3, %g0, %g1 | |
352 | brnz %g1, test_failed | |
353 | nop | |
354 | ||
355 | setx L2_2_ERR_STAT_REG, %l3, %g5 | |
356 | ldx [%g5], %g3 | |
357 | sub %g3, %g0, %g1 | |
358 | brnz %g1, test_failed | |
359 | nop | |
360 | ||
361 | setx L2_3_ERR_STAT_REG, %l3, %g5 | |
362 | ldx [%g5], %g3 | |
363 | sub %g3, %g0, %g1 | |
364 | brnz %g1, test_failed | |
365 | nop | |
366 | ||
367 | setx L2_4_ERR_STAT_REG, %l3, %g5 | |
368 | ldx [%g5], %g3 | |
369 | sub %g3, %g0, %g1 | |
370 | brnz %g1, test_failed | |
371 | nop | |
372 | ||
373 | setx L2_5_ERR_STAT_REG, %l3, %g5 | |
374 | ldx [%g5], %g3 | |
375 | sub %g3, %g0, %g1 | |
376 | brnz %g1, test_failed | |
377 | nop | |
378 | ||
379 | setx L2_6_ERR_STAT_REG, %l3, %g5 | |
380 | ldx [%g5], %g3 | |
381 | sub %g3, %g0, %g1 | |
382 | brnz %g1, test_failed | |
383 | nop | |
384 | ||
385 | setx L2_7_ERR_STAT_REG, %l3, %g5 | |
386 | ldx [%g5], %g3 | |
387 | sub %g3, %g0, %g1 | |
388 | brnz %g1, test_failed | |
389 | nop | |
390 | ||
391 | ||
392 | check_tt_rdd: | |
393 | mov 0x40, %l0 | |
394 | cmp %o7, %l0 | |
395 | bne %xcc, test_failed | |
396 | nop | |
397 | ||
398 | test_passed: | |
399 | EXIT_GOOD | |
400 | ||
401 | test_failed: | |
402 | EXIT_BAD | |
403 | ||
404 | ||
405 | /************************************************************************ | |
406 | RAS | |
407 | Trap Handlers | |
408 | ************************************************************************/ | |
409 | My_Recoverable_Sw_error_trap: | |
410 | ! Signal trap taken | |
411 | setx EXECUTED, %l0, %o6 | |
412 | ! save trap type value | |
413 | rdpr %tt, %o7 | |
414 | ||
415 | inc %i7 | |
416 | ||
417 | check_desr_NcuTrap_tt40: | |
418 | ldxa [%g0]0x4c, %g2 | |
419 | nop | |
420 | ||
421 | setx 0xb300000000000000, %l0, %g3 | |
422 | subcc %g2, %g3, %g4 | |
423 | brnz %g4, test_failed | |
424 | nop | |
425 | ||
426 | /* | |
427 | avoid syndrome chk as error injection is not controlled | |
428 | check_synd: | |
429 | setx SOC_SII_SYN_REG, %g7, %g1 | |
430 | ldx [%g1], %g2 | |
431 | setx 0x8700000000000000, %g7, %g1 | |
432 | and %g2, %g1, %g3 | |
433 | setx SII_SYND, %g7, %g4 | |
434 | cmp %g3, %g4 | |
435 | bne %xcc, test_failed | |
436 | nop | |
437 | */ | |
438 | ||
439 | clear_synd_reg: | |
440 | setx SOC_SII_SYN_REG, %g7, %g1 | |
441 | stx %g0, [%g1] | |
442 | nop | |
443 | ||
444 | check_per_tt40: | |
445 | mov 0x1, %g1 | |
446 | sllx %g1, ERR_FIELD, %g2 | |
447 | setx 0x8000000000000000, %g7, %g3 | |
448 | or %g2, %g3, %g1 | |
449 | ||
450 | setx SOC_PER_REG, %g7, %g2 | |
451 | ldx [%g2], %g3 | |
452 | ||
453 | cmp %g1, %g3 | |
454 | bne %xcc, test_failed | |
455 | nop | |
456 | ||
457 | clear_per_tt40: | |
458 | setx SOC_PER_REG, %l7, %g1 | |
459 | stx %g0, [%g1] | |
460 | nop | |
461 | ||
462 | clear_ejr_tt40: | |
463 | setx SOC_EJR_REG, %l7, %g1 | |
464 | stx %g0, [%g1] | |
465 | nop | |
466 | ||
467 | trap_done_tt40: | |
468 | retry | |
469 | nop | |
470 | ||
471 | ||
472 | ||
473 | My_Corrected_ECC_error_trap: | |
474 | ba test_failed | |
475 | nop | |
476 | ||
477 | ||
478 | /************************************************************************ | |
479 | Test case data start | |
480 | ************************************************************************/ | |
481 | ||
482 | SECTION .DATA DATA_VA=DMA_DATA_ADDR | |
483 | attr_data { | |
484 | Name = .DATA, | |
485 | hypervisor, | |
486 | compressimage | |
487 | } | |
488 | ||
489 | .data | |
490 | .global PCIAddr9 | |
491 | .xword 0x0001020304050607 | |
492 | .xword 0x08090a0b0c0d0e0f | |
493 | .xword 0x1011121314151617 | |
494 | .xword 0x18191a1b1c1d1e1f | |
495 | .xword 0x2021222324252627 | |
496 | .xword 0x28292a2b2c2d2e2f | |
497 | .xword 0x3031323334353637 | |
498 | .xword 0x38393a3b3c3d3e3f | |
499 | ||
500 | .xword 0x4041424344454647 | |
501 | .xword 0x48494a4b4c4d4e4f | |
502 | .xword 0x5051525354555657 | |
503 | .xword 0x58595a5b5c5d5e5f | |
504 | .xword 0x6061626364656667 | |
505 | .xword 0x68696a6b6c6d6e6f | |
506 | .xword 0x7071727374757677 | |
507 | .xword 0x78797a7b7c7d7e7f | |
508 | ||
509 | .xword 0x8081828384858687 | |
510 | .xword 0x88898a8b8c8d8e8f | |
511 | .xword 0x9091929394959697 | |
512 | .xword 0x98999a9b9c9d9e9f | |
513 | .xword 0xa0a1a2a3a4a5a6a7 | |
514 | .xword 0xa8a9aaabacadaeaf | |
515 | .xword 0xb0b1b2b3b4b5b6b7 | |
516 | .xword 0xb8b9babbbcbdbebf | |
517 | ||
518 | .xword 0xc0c1c2c3c4c5c6c7 | |
519 | .xword 0xc8c9cacbcccdcecf | |
520 | .xword 0xd0d1d2d3d4d5d6d7 | |
521 | .xword 0xd8d9dadbdcdddedf | |
522 | .xword 0xe0e1e2e3e4e5e6e7 | |
523 | .xword 0xe8e9eaebecedeeef | |
524 | .xword 0xf0f1f2f3f4f5f6f7 | |
525 | .xword 0xf8f9fafbfcfdfeff | |
526 | ||
527 | .xword 0x0001020304050607 | |
528 | .xword 0x08090a0b0c0d0e0f | |
529 | .xword 0x1011121314151617 | |
530 | .xword 0x18191a1b1c1d1e1f | |
531 | .xword 0x2021222324252627 | |
532 | .xword 0x28292a2b2c2d2e2f | |
533 | .xword 0x3031323334353637 | |
534 | .xword 0x38393a3b3c3d3e3f | |
535 | ||
536 | .xword 0x4041424344454647 | |
537 | .xword 0x48494a4b4c4d4e4f | |
538 | .xword 0x5051525354555657 | |
539 | .xword 0x58595a5b5c5d5e5f | |
540 | .xword 0x6061626364656667 | |
541 | .xword 0x68696a6b6c6d6e6f | |
542 | .xword 0x7071727374757677 | |
543 | .xword 0x78797a7b7c7d7e7f | |
544 | ||
545 | .xword 0x8081828384858687 | |
546 | .xword 0x88898a8b8c8d8e8f | |
547 | .xword 0x9091929394959697 | |
548 | .xword 0x98999a9b9c9d9e9f | |
549 | .xword 0xa0a1a2a3a4a5a6a7 | |
550 | .xword 0xa8a9aaabacadaeaf | |
551 | .xword 0xb0b1b2b3b4b5b6b7 | |
552 | .xword 0xb8b9babbbcbdbebf | |
553 | ||
554 | .xword 0xc0c1c2c3c4c5c6c7 | |
555 | .xword 0xc8c9cacbcccdcecf | |
556 | .xword 0xd0d1d2d3d4d5d6d7 | |
557 | .xword 0xd8d9dadbdcdddedf | |
558 | .xword 0xe0e1e2e3e4e5e6e7 | |
559 | .xword 0xe8e9eaebecedeeef | |
560 | .xword 0xf0f1f2f3f4f5f6f7 | |
561 | .xword 0xf8f9fafbfcfdfeff | |
562 | ||
563 | /************************************************************************/ | |
564 |