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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_piu_strm_wri_DMUSII_UEV.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_piu_strm_wri_DMUSII_UEV.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41#define ENABLE_PCIE_LINK_TRAINING
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45#define DRAM_0_ERR_STAT_REG 0x8400000280
46#define DRAM_1_ERR_STAT_REG 0x8400001280
47#define DRAM_2_ERR_STAT_REG 0x8400002280
48#define DRAM_3_ERR_STAT_REG 0x8400003280
49
50#define L2_0_ERR_STAT_REG 0xAB00000000
51#define L2_1_ERR_STAT_REG 0xAB00000040
52#define L2_2_ERR_STAT_REG 0xAB00000080
53#define L2_3_ERR_STAT_REG 0xAB000000c0
54#define L2_4_ERR_STAT_REG 0xAB00000100
55#define L2_5_ERR_STAT_REG 0xAB00000140
56#define L2_6_ERR_STAT_REG 0xAB00000180
57#define L2_7_ERR_STAT_REG 0xAB000001c0
58
59
60#include "err_defines.h"
61#include "hboot.s"
62#include "peu_defines.h"
63
64#define DMA_DATA_ADDR 0x0000000123456700
65
66#define DMA_DATA_BYP_ADDR1 0xfffc000123410000
67#define DMA_DATA_BYP_ADDR2 0xfffc000123410200
68#define DMA_DATA_BYP_ADDR3 0xfffc000123410400
69#define DMA_DATA_BYP_ADDR4 0xfffc000123410600
70#define DMA_DATA_BYP_ADDR5 0xfffc000123410800
71#define DMA_DATA_BYP_ADDR6 0xfffc000123410a00
72#define DMA_DATA_BYP_ADDR7 0xfffc000123410c00
73#define DMA_DATA_BYP_ADDR8 0xfffc000123410e00
74#define DMA_DATA_BYP_ADDR9 0xfffc000123411000
75#define DMA_DATA_BYP_ADDR10 0xfffc000123411200
76#define DMA_DATA_BYP_ADDR11 0xfffc000123411400
77#define DMA_DATA_BYP_ADDR12 0xfffc000123411600
78#define DMA_DATA_BYP_ADDR13 0xfffc000123411800
79#define DMA_DATA_BYP_ADDR14 0xfffc000123411a00
80#define DMA_DATA_BYP_ADDR15 0xfffc000123411c00
81#define DMA_DATA_BYP_ADDR16 0xfffc000123411e00
82
83
84
85/************************************************************************
86 Test case code start
87 ************************************************************************/
88.text
89.global main
90.global My_Corrected_ECC_error_trap
91.global My_Recoverable_Sw_error_trap
92
93main:
94 ta T_CHANGE_HPRIV
95 nop
96
97 clr %i7
98 clr %o6
99 clr %o7
100 clr %i0
101
102L2_err_enable:
103 set 0x3, %l1
104 mov 0xaa, %g2
105 sllx %g2, 32, %g2
106 stx %l1, [%g2]
107 stx %l1, [%g2 + 0x40]
108 stx %l1, [%g2 + 0x80]
109 stx %l1, [%g2 + 0xc0]
110 stx %l1, [%g2 + 0x100]
111 stx %l1, [%g2 + 0x140]
112 stx %l1, [%g2 + 0x180]
113 stx %l1, [%g2 + 0x1c0]
114
115bypass_iommu:
116 ! enable bypass in IOMMU
117 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
118 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
119 stx %g3, [%g2]
120 ldx [%g2], %g3
121
122 /*******************************************************
123 RDD from DMU
124 ********************************************************/
125set_eie_rdd:
126 mov 0x1, %g1
127 sllx %g1, ERR_FIELD, %g2
128 setx SOC_EIE_REG, %g7, %g3
129 stx %g2, [%g3]
130 membar 0x40
131
132
133inj_err1: nop
134 !$EV trig_pc_d(0,@VA(.MAIN.inj_err1)) ->IosErrInj(ERR_TYPE, 0, 123410000)
135 nop; nop; nop; nop; nop; nop; nop; nop; nop;
136 nop; nop; nop;nop; nop; nop;nop; nop; nop
137UsrEvnt_wri_1:
138 nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1, *, * )
139
140
141UsrEvnt_wri_2:
142 nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_2)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR2, DMA_DATA_BYP_ADDR3, "64'h40", 5, *, * )
143
144
145inj_err3: nop
146 !$EV trig_pc_d(0,@VA(.MAIN.inj_err3)) ->IosErrInj(ERR_TYPE, 0, 123410600)
147 nop; nop; nop; nop; nop; nop; nop; nop; nop;
148 nop; nop; nop;nop; nop; nop;nop; nop; nop;
149UsrEvnt_wri_3:
150 nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_3)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR4, DMA_DATA_BYP_ADDR4, "64'h40", 1, *, * )
151
152
153UsrEvnt_wri_4:
154 nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_4)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR5, DMA_DATA_BYP_ADDR6, "64'h40", 5, *, * )
155
156
157inj_err5: nop
158 !$EV trig_pc_d(0,@VA(.MAIN.inj_err5)) ->IosErrInj(ERR_TYPE, 0, 123410c00)
159 nop; nop; nop; nop; nop; nop; nop; nop; nop;
160 nop; nop; nop;nop; nop; nop;nop; nop; nop;
161UsrEvnt_wri_5:
162 nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_5)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR7, DMA_DATA_BYP_ADDR7, "64'h40", 1, *, * )
163
164
165
166 ldx [%g2], %g3
167 ldx [%g2], %g3
168 ldx [%g2], %g3
169 ldx [%g2], %g3
170
171
172 set 0x3, %g1 ! 1 Trap; only for NCU DmuDParity
173 ! For RDD SIU does not send PA39, only sets E bit
174 ! So no trap from L2
175
176 setx 0x100, %g7, %g6
177err_trap_loop_rdd:
178 cmp %g6, %g0
179 be %xcc, test_failed
180 nop
181
182 cmp %g1, %i7
183 be %xcc, check_mcu_esr
184 nop
185
186 dec %g6
187
188 ba err_trap_loop_rdd
189 nop
190
191
192check_mcu_esr:
193 setx DRAM_0_ERR_STAT_REG, %g7, %g6
194 ldx [%g6], %g3
195 sub %g3, %g0, %g1
196 brnz %g1, test_failed
197 nop
198
199 setx DRAM_1_ERR_STAT_REG, %g7, %g6
200 ldx [%g6], %g3
201 sub %g3, %g0, %g1
202 brnz %g1, test_failed
203 nop
204
205 setx DRAM_2_ERR_STAT_REG, %g7, %g6
206 ldx [%g6], %g3
207 sub %g3, %g0, %g1
208 brnz %g1, test_failed
209 nop
210
211 setx DRAM_3_ERR_STAT_REG, %g7, %g6
212 ldx [%g6], %g3
213 sub %g3, %g0, %g1
214 brnz %g1, test_failed
215 nop
216
217check_L2_4_ESR_L2Trap_tt40:
218 setx L2_0_ERR_STAT_REG, %l3, %g5
219 ldx [%g5], %g3
220 sub %g3, %g0, %g1
221 brnz %g1, test_failed
222 nop
223
224 setx L2_1_ERR_STAT_REG, %l3, %g5
225 ldx [%g5], %g3
226 sub %g3, %g0, %g1
227 brnz %g1, test_failed
228 nop
229
230 setx L2_2_ERR_STAT_REG, %l3, %g5
231 ldx [%g5], %g3
232 sub %g3, %g0, %g1
233 brnz %g1, test_failed
234 nop
235
236 setx L2_3_ERR_STAT_REG, %l3, %g5
237 ldx [%g5], %g3
238 sub %g3, %g0, %g1
239 brnz %g1, test_failed
240 nop
241
242 setx L2_4_ERR_STAT_REG, %l3, %g5
243 ldx [%g5], %g3
244 sub %g3, %g0, %g1
245 brnz %g1, test_failed
246 nop
247
248 setx L2_5_ERR_STAT_REG, %l3, %g5
249 ldx [%g5], %g3
250 sub %g3, %g0, %g1
251 brnz %g1, test_failed
252 nop
253
254 setx L2_6_ERR_STAT_REG, %l3, %g5
255 ldx [%g5], %g3
256 sub %g3, %g0, %g1
257 brnz %g1, test_failed
258 nop
259
260 setx L2_7_ERR_STAT_REG, %l3, %g5
261 ldx [%g5], %g3
262 sub %g3, %g0, %g1
263 brnz %g1, test_failed
264 nop
265
266
267check_tt_rdd:
268 mov 0x40, %l0
269 cmp %o7, %l0
270 bne %xcc, test_failed
271 nop
272
273test_passed:
274 EXIT_GOOD
275
276test_failed:
277 EXIT_BAD
278
279
280/************************************************************************
281 RAS
282 Trap Handlers
283 ************************************************************************/
284My_Recoverable_Sw_error_trap:
285 ! Signal trap taken
286 setx EXECUTED, %l0, %o6
287 ! save trap type value
288 rdpr %tt, %o7
289
290 inc %i7
291
292check_desr_NcuTrap_tt40:
293 ldxa [%g0]0x4c, %g2
294 nop
295
296 setx 0xb300000000000000, %l0, %g3
297 subcc %g2, %g3, %g4
298 brnz %g4, test_failed
299 nop
300
301check_per_tt40:
302 mov 0x1, %g1
303 sllx %g1, ERR_FIELD, %g2
304 setx 0x8000000000000000, %g7, %g3
305 or %g2, %g3, %g1
306
307 setx SOC_PER_REG, %g7, %g2
308 ldx [%g2], %g3
309
310 cmp %g1, %g3
311 bne %xcc, test_failed
312 nop
313
314
315clear_per_tt40:
316 setx SOC_PER_REG, %l7, %g1
317 stx %g0, [%g1]
318 nop
319
320
321clear_siisynd_tt40:
322 setx SOC_SII_ERR_SYND_REG, %l7, %g1
323 stx %g0, [%g1]
324 nop
325
326trap_done_tt40:
327 retry
328 nop
329
330
331
332My_Corrected_ECC_error_trap:
333 ba test_failed
334 nop
335
336
337/************************************************************************
338 Test case data start
339************************************************************************/
340
341SECTION .DATA DATA_VA=DMA_DATA_ADDR
342attr_data {
343 Name = .DATA,
344 hypervisor,
345 compressimage
346}
347
348.data
349.global PCIAddr9
350 .xword 0x0001020304050607
351 .xword 0x08090a0b0c0d0e0f
352 .xword 0x1011121314151617
353 .xword 0x18191a1b1c1d1e1f
354 .xword 0x2021222324252627
355 .xword 0x28292a2b2c2d2e2f
356 .xword 0x3031323334353637
357 .xword 0x38393a3b3c3d3e3f
358
359 .xword 0x4041424344454647
360 .xword 0x48494a4b4c4d4e4f
361 .xword 0x5051525354555657
362 .xword 0x58595a5b5c5d5e5f
363 .xword 0x6061626364656667
364 .xword 0x68696a6b6c6d6e6f
365 .xword 0x7071727374757677
366 .xword 0x78797a7b7c7d7e7f
367
368 .xword 0x8081828384858687
369 .xword 0x88898a8b8c8d8e8f
370 .xword 0x9091929394959697
371 .xword 0x98999a9b9c9d9e9f
372 .xword 0xa0a1a2a3a4a5a6a7
373 .xword 0xa8a9aaabacadaeaf
374 .xword 0xb0b1b2b3b4b5b6b7
375 .xword 0xb8b9babbbcbdbebf
376
377 .xword 0xc0c1c2c3c4c5c6c7
378 .xword 0xc8c9cacbcccdcecf
379 .xword 0xd0d1d2d3d4d5d6d7
380 .xword 0xd8d9dadbdcdddedf
381 .xword 0xe0e1e2e3e4e5e6e7
382 .xword 0xe8e9eaebecedeeef
383 .xword 0xf0f1f2f3f4f5f6f7
384 .xword 0xf8f9fafbfcfdfeff
385
386 .xword 0x0001020304050607
387 .xword 0x08090a0b0c0d0e0f
388 .xword 0x1011121314151617
389 .xword 0x18191a1b1c1d1e1f
390 .xword 0x2021222324252627
391 .xword 0x28292a2b2c2d2e2f
392 .xword 0x3031323334353637
393 .xword 0x38393a3b3c3d3e3f
394
395 .xword 0x4041424344454647
396 .xword 0x48494a4b4c4d4e4f
397 .xword 0x5051525354555657
398 .xword 0x58595a5b5c5d5e5f
399 .xword 0x6061626364656667
400 .xword 0x68696a6b6c6d6e6f
401 .xword 0x7071727374757677
402 .xword 0x78797a7b7c7d7e7f
403
404 .xword 0x8081828384858687
405 .xword 0x88898a8b8c8d8e8f
406 .xword 0x9091929394959697
407 .xword 0x98999a9b9c9d9e9f
408 .xword 0xa0a1a2a3a4a5a6a7
409 .xword 0xa8a9aaabacadaeaf
410 .xword 0xb0b1b2b3b4b5b6b7
411 .xword 0xb8b9babbbcbdbebf
412
413 .xword 0xc0c1c2c3c4c5c6c7
414 .xword 0xc8c9cacbcccdcecf
415 .xword 0xd0d1d2d3d4d5d6d7
416 .xword 0xd8d9dadbdcdddedf
417 .xword 0xe0e1e2e3e4e5e6e7
418 .xword 0xe8e9eaebecedeeef
419 .xword 0xf0f1f2f3f4f5f6f7
420 .xword 0xf8f9fafbfcfdfeff
421
422/************************************************************************/
423
Full OpenSPARC design & verification tarball including full HDL.