projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: n2_err_adv_piu_strm_wri_ejr.s | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
| 39 | #define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap | |
| 40 | ||
| 41 | #define ENABLE_PCIE_LINK_TRAINING | |
| 42 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ | |
| 43 | #define MAIN_PAGE_HV_ALSO | |
| 44 | ||
| 45 | #define DRAM_0_ERR_STAT_REG 0x8400000280 | |
| 46 | #define DRAM_1_ERR_STAT_REG 0x8400001280 | |
| 47 | #define DRAM_2_ERR_STAT_REG 0x8400002280 | |
| 48 | #define DRAM_3_ERR_STAT_REG 0x8400003280 | |
| 49 | ||
| 50 | #define L2_0_ERR_STAT_REG 0xAB00000000 | |
| 51 | #define L2_1_ERR_STAT_REG 0xAB00000040 | |
| 52 | #define L2_2_ERR_STAT_REG 0xAB00000080 | |
| 53 | #define L2_3_ERR_STAT_REG 0xAB000000c0 | |
| 54 | #define L2_4_ERR_STAT_REG 0xAB00000100 | |
| 55 | #define L2_5_ERR_STAT_REG 0xAB00000140 | |
| 56 | #define L2_6_ERR_STAT_REG 0xAB00000180 | |
| 57 | #define L2_7_ERR_STAT_REG 0xAB000001c0 | |
| 58 | ||
| 59 | ||
| 60 | #include "err_defines.h" | |
| 61 | #include "hboot.s" | |
| 62 | #include "peu_defines.h" | |
| 63 | ||
| 64 | #define DMA_DATA_ADDR 0x0000000123456700 | |
| 65 | ||
| 66 | #define DMA_DATA_BYP_ADDR1 0xfffc000123410000 | |
| 67 | #define DMA_DATA_BYP_ADDR2 0xfffc000123410200 | |
| 68 | #define DMA_DATA_BYP_ADDR3 0xfffc000123410400 | |
| 69 | #define DMA_DATA_BYP_ADDR4 0xfffc000123410600 | |
| 70 | #define DMA_DATA_BYP_ADDR5 0xfffc000123410800 | |
| 71 | #define DMA_DATA_BYP_ADDR6 0xfffc000123410a00 | |
| 72 | #define DMA_DATA_BYP_ADDR7 0xfffc000123410c00 | |
| 73 | #define DMA_DATA_BYP_ADDR8 0xfffc000123410e00 | |
| 74 | #define DMA_DATA_BYP_ADDR9 0xfffc000123411000 | |
| 75 | #define DMA_DATA_BYP_ADDR10 0xfffc000123411200 | |
| 76 | #define DMA_DATA_BYP_ADDR11 0xfffc000123411400 | |
| 77 | #define DMA_DATA_BYP_ADDR12 0xfffc000123411600 | |
| 78 | #define DMA_DATA_BYP_ADDR13 0xfffc000123411800 | |
| 79 | #define DMA_DATA_BYP_ADDR14 0xfffc000123411a00 | |
| 80 | #define DMA_DATA_BYP_ADDR15 0xfffc000123411c00 | |
| 81 | #define DMA_DATA_BYP_ADDR16 0xfffc000123411e00 | |
| 82 | #define DMA_DATA_BYP_ADDR17 0xfffc000123412000 | |
| 83 | #define DMA_DATA_BYP_ADDR18 0xfffc000123412200 | |
| 84 | #define DMA_DATA_BYP_ADDR19 0xfffc000123412400 | |
| 85 | #define DMA_DATA_BYP_ADDR20 0xfffc000123412600 | |
| 86 | #define DMA_DATA_BYP_ADDR21 0xfffc000123412800 | |
| 87 | #define DMA_DATA_BYP_ADDR22 0xfffc000123412a00 | |
| 88 | #define DMA_DATA_BYP_ADDR23 0xfffc000123412c00 | |
| 89 | ||
| 90 | #define SOC_SII_SYN_REG 0x8000003030 | |
| 91 | ||
| 92 | /************************************************************************ | |
| 93 | Test case code start | |
| 94 | ************************************************************************/ | |
| 95 | .text | |
| 96 | .global main | |
| 97 | .global My_Corrected_ECC_error_trap | |
| 98 | .global My_Recoverable_Sw_error_trap | |
| 99 | ||
| 100 | main: | |
| 101 | ta T_CHANGE_HPRIV | |
| 102 | nop | |
| 103 | ||
| 104 | clr %i7 | |
| 105 | clr %o6 | |
| 106 | clr %o7 | |
| 107 | clr %i0 | |
| 108 | ||
| 109 | clear_mem: | |
| 110 | setx 0x123410c00, %g7, %g1 | |
| 111 | stx %g0, [%g1] | |
| 112 | setx 0x123411800, %g7, %g1 | |
| 113 | stx %g0, [%g1] | |
| 114 | ||
| 115 | L2_err_enable: | |
| 116 | set 0x3, %l1 | |
| 117 | mov 0xaa, %g2 | |
| 118 | sllx %g2, 32, %g2 | |
| 119 | stx %l1, [%g2] | |
| 120 | stx %l1, [%g2 + 0x40] | |
| 121 | stx %l1, [%g2 + 0x80] | |
| 122 | stx %l1, [%g2 + 0xc0] | |
| 123 | stx %l1, [%g2 + 0x100] | |
| 124 | stx %l1, [%g2 + 0x140] | |
| 125 | stx %l1, [%g2 + 0x180] | |
| 126 | stx %l1, [%g2 + 0x1c0] | |
| 127 | ||
| 128 | bypass_iommu: | |
| 129 | ! enable bypass in IOMMU | |
| 130 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
| 131 | setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3 | |
| 132 | stx %g3, [%g2] | |
| 133 | ldx [%g2], %g3 | |
| 134 | ||
| 135 | /******************************************************* | |
| 136 | RDD from DMU | |
| 137 | ********************************************************/ | |
| 138 | set_eie: | |
| 139 | mov 0x1, %g1 | |
| 140 | sllx %g1, ERR_FIELD, %g2 | |
| 141 | setx SOC_EIE_REG, %g7, %g3 | |
| 142 | stx %g2, [%g3] | |
| 143 | membar 0x40 | |
| 144 | ||
| 145 | ||
| 146 | set_ejr_1: | |
| 147 | setx SOC_EJR_REG, %g7, %g6 | |
| 148 | stx %g2, [%g6] | |
| 149 | membar 0x40 | |
| 150 | ||
| 151 | ||
| 152 | UsrEvnt_wri_1: | |
| 153 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 ) | |
| 154 | ||
| 155 | setx 0x100, %g7, %g5 | |
| 156 | chk_ejr_1: | |
| 157 | cmp %g5, %g0 | |
| 158 | be %xcc, test_failed | |
| 159 | nop | |
| 160 | ||
| 161 | ldx [%g6], %g1 | |
| 162 | cmp %g1, %g0 | |
| 163 | be %xcc, UsrEvnt_wri_2 | |
| 164 | nop | |
| 165 | ||
| 166 | dec %g5 | |
| 167 | ||
| 168 | ba chk_ejr_1 | |
| 169 | nop | |
| 170 | ||
| 171 | UsrEvnt_wri_2: | |
| 172 | nop | |
| 173 | nop | |
| 174 | nop | |
| 175 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_2)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR2, DMA_DATA_BYP_ADDR2, "64'h40", 1 ) | |
| 176 | ||
| 177 | UsrEvnt_wri_3: | |
| 178 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_3)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR3, "64'h40", 1 ) | |
| 179 | ||
| 180 | UsrEvnt_wri_4: | |
| 181 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_4)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR4, DMA_DATA_BYP_ADDR4, "64'h40", 1 ) | |
| 182 | ||
| 183 | UsrEvnt_wri_5: | |
| 184 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_5)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR5, DMA_DATA_BYP_ADDR5, "64'h40", 1 ) | |
| 185 | ||
| 186 | UsrEvnt_wri_6: | |
| 187 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_6)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR6, DMA_DATA_BYP_ADDR6, "64'h40", 1 ) | |
| 188 | ||
| 189 | UsrEvnt_wri_7: | |
| 190 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_7)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR7, DMA_DATA_BYP_ADDR7, "64'h40", 1 ) | |
| 191 | ||
| 192 | !check that the last data from DMA is written to memory | |
| 193 | read_ADDR7: | |
| 194 | setx 0x123410c00, %g7, %g1 | |
| 195 | ld [%g1], %g3 | |
| 196 | cmp %g3, %g0 | |
| 197 | be read_ADDR7 | |
| 198 | nop | |
| 199 | ||
| 200 | set_ejr_2: | |
| 201 | stx %g2, [%g6] | |
| 202 | membar 0x40 | |
| 203 | ||
| 204 | ||
| 205 | UsrEvnt_wri_8: | |
| 206 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_8)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR8, DMA_DATA_BYP_ADDR8, "64'h40", 1 ) | |
| 207 | ||
| 208 | setx 0x100, %g7, %g5 | |
| 209 | chk_ejr_2: | |
| 210 | cmp %g5, %g0 | |
| 211 | be %xcc, test_failed | |
| 212 | nop | |
| 213 | ||
| 214 | ldx [%g6], %g1 | |
| 215 | cmp %g1, %g0 | |
| 216 | be %xcc, UsrEvnt_wri_9 | |
| 217 | nop | |
| 218 | ||
| 219 | dec %g5 | |
| 220 | ||
| 221 | ba chk_ejr_2 | |
| 222 | nop | |
| 223 | ||
| 224 | UsrEvnt_wri_9: | |
| 225 | nop | |
| 226 | nop | |
| 227 | nop | |
| 228 | ||
| 229 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_9)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR9, DMA_DATA_BYP_ADDR9, "64'h40", 1 ) | |
| 230 | ||
| 231 | UsrEvnt_wri_10: | |
| 232 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_10)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR10, DMA_DATA_BYP_ADDR10, "64'h40", 1 ) | |
| 233 | ||
| 234 | UsrEvnt_wri_11: | |
| 235 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_11)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR11, DMA_DATA_BYP_ADDR11, "64'h40", 1 ) | |
| 236 | ||
| 237 | UsrEvnt_wri_12: | |
| 238 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_12)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR12, DMA_DATA_BYP_ADDR12, "64'h40", 1 ) | |
| 239 | ||
| 240 | UsrEvnt_wri_13: | |
| 241 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_13)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR13, DMA_DATA_BYP_ADDR13, "64'h40", 1 ) | |
| 242 | ||
| 243 | ||
| 244 | !check that the last data from DMA is written to memory | |
| 245 | read_ADDR13: | |
| 246 | setx 0x123411800, %g7, %g1 | |
| 247 | ld [%g1], %g3 | |
| 248 | cmp %g3, %g0 | |
| 249 | be read_ADDR13 | |
| 250 | nop | |
| 251 | ||
| 252 | ||
| 253 | set_ejr_3: | |
| 254 | stx %g2, [%g6] | |
| 255 | membar 0x40 | |
| 256 | ||
| 257 | UsrEvnt_wri_14: | |
| 258 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_14)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR14, DMA_DATA_BYP_ADDR14, "64'h40", 1 ) | |
| 259 | ||
| 260 | setx 0x100, %g7, %g5 | |
| 261 | chk_ejr_3: | |
| 262 | cmp %g5, %g0 | |
| 263 | be %xcc, test_failed | |
| 264 | nop | |
| 265 | ||
| 266 | ldx [%g6], %g1 | |
| 267 | cmp %g1, %g0 | |
| 268 | be %xcc, UsrEvnt_wri_15 | |
| 269 | nop | |
| 270 | ||
| 271 | dec %g5 | |
| 272 | ||
| 273 | ba chk_ejr_3 | |
| 274 | nop | |
| 275 | ||
| 276 | UsrEvnt_wri_15: | |
| 277 | nop | |
| 278 | nop | |
| 279 | nop | |
| 280 | nop | |
| 281 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_15)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR15, DMA_DATA_BYP_ADDR15, "64'h40", 1 ) | |
| 282 | ||
| 283 | UsrEvnt_wri_16: | |
| 284 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_16)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR16, DMA_DATA_BYP_ADDR16, "64'h40", 1 ) | |
| 285 | ||
| 286 | UsrEvnt_wri_17: | |
| 287 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_17)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR17, DMA_DATA_BYP_ADDR17, "64'h40", 1 ) | |
| 288 | ||
| 289 | UsrEvnt_wri_18: | |
| 290 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_18)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR18, DMA_DATA_BYP_ADDR18, "64'h40", 1 ) | |
| 291 | ||
| 292 | UsrEvnt_wri_19: | |
| 293 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_19)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR19, DMA_DATA_BYP_ADDR19, "64'h40", 1 ) | |
| 294 | ||
| 295 | UsrEvnt_wri_20: | |
| 296 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_20)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR20, DMA_DATA_BYP_ADDR20, "64'h40", 1 ) | |
| 297 | ||
| 298 | UsrEvnt_wri_21: | |
| 299 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_21)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR21, DMA_DATA_BYP_ADDR21, "64'h40", 1 ) | |
| 300 | ||
| 301 | pios: | |
| 302 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
| 303 | ldx [%g2], %g3 | |
| 304 | ldx [%g2], %g3 | |
| 305 | ldx [%g2], %g3 | |
| 306 | ldx [%g2], %g3 | |
| 307 | ||
| 308 | set 0x3, %g1 | |
| 309 | setx 0x100, %g7, %g5 | |
| 310 | err_trap_loop: | |
| 311 | cmp %g5, %g0 | |
| 312 | be %xcc, test_failed | |
| 313 | nop | |
| 314 | ||
| 315 | cmp %g1, %i7 | |
| 316 | be %xcc, check_mcu_esr | |
| 317 | nop | |
| 318 | ||
| 319 | dec %g5 | |
| 320 | ||
| 321 | ba err_trap_loop | |
| 322 | nop | |
| 323 | ||
| 324 | ||
| 325 | ||
| 326 | check_mcu_esr: | |
| 327 | setx DRAM_0_ERR_STAT_REG, %g7, %g6 | |
| 328 | ldx [%g6], %g3 | |
| 329 | sub %g3, %g0, %g1 | |
| 330 | brnz %g1, test_failed | |
| 331 | nop | |
| 332 | ||
| 333 | setx DRAM_1_ERR_STAT_REG, %g7, %g6 | |
| 334 | ldx [%g6], %g3 | |
| 335 | sub %g3, %g0, %g1 | |
| 336 | brnz %g1, test_failed | |
| 337 | nop | |
| 338 | ||
| 339 | setx DRAM_2_ERR_STAT_REG, %g7, %g6 | |
| 340 | ldx [%g6], %g3 | |
| 341 | sub %g3, %g0, %g1 | |
| 342 | brnz %g1, test_failed | |
| 343 | nop | |
| 344 | ||
| 345 | setx DRAM_3_ERR_STAT_REG, %g7, %g6 | |
| 346 | ldx [%g6], %g3 | |
| 347 | sub %g3, %g0, %g1 | |
| 348 | brnz %g1, test_failed | |
| 349 | nop | |
| 350 | ||
| 351 | check_L2_ESR: | |
| 352 | setx L2_0_ERR_STAT_REG, %l3, %g5 | |
| 353 | ldx [%g5], %g3 | |
| 354 | sub %g3, %g0, %g1 | |
| 355 | brnz %g1, test_failed | |
| 356 | nop | |
| 357 | ||
| 358 | setx L2_1_ERR_STAT_REG, %l3, %g5 | |
| 359 | ldx [%g5], %g3 | |
| 360 | sub %g3, %g0, %g1 | |
| 361 | brnz %g1, test_failed | |
| 362 | nop | |
| 363 | ||
| 364 | setx L2_2_ERR_STAT_REG, %l3, %g5 | |
| 365 | ldx [%g5], %g3 | |
| 366 | sub %g3, %g0, %g1 | |
| 367 | brnz %g1, test_failed | |
| 368 | nop | |
| 369 | ||
| 370 | setx L2_3_ERR_STAT_REG, %l3, %g5 | |
| 371 | ldx [%g5], %g3 | |
| 372 | sub %g3, %g0, %g1 | |
| 373 | brnz %g1, test_failed | |
| 374 | nop | |
| 375 | ||
| 376 | setx L2_4_ERR_STAT_REG, %l3, %g5 | |
| 377 | ldx [%g5], %g3 | |
| 378 | sub %g3, %g0, %g1 | |
| 379 | brnz %g1, test_failed | |
| 380 | nop | |
| 381 | ||
| 382 | setx L2_5_ERR_STAT_REG, %l3, %g5 | |
| 383 | ldx [%g5], %g3 | |
| 384 | sub %g3, %g0, %g1 | |
| 385 | brnz %g1, test_failed | |
| 386 | nop | |
| 387 | ||
| 388 | setx L2_6_ERR_STAT_REG, %l3, %g5 | |
| 389 | ldx [%g5], %g3 | |
| 390 | sub %g3, %g0, %g1 | |
| 391 | brnz %g1, test_failed | |
| 392 | nop | |
| 393 | ||
| 394 | setx L2_7_ERR_STAT_REG, %l3, %g5 | |
| 395 | ldx [%g5], %g3 | |
| 396 | sub %g3, %g0, %g1 | |
| 397 | brnz %g1, test_failed | |
| 398 | nop | |
| 399 | ||
| 400 | ||
| 401 | check_tt_rdd: | |
| 402 | mov 0x40, %l0 | |
| 403 | cmp %o7, %l0 | |
| 404 | bne %xcc, test_failed | |
| 405 | nop | |
| 406 | ||
| 407 | test_passed: | |
| 408 | EXIT_GOOD | |
| 409 | ||
| 410 | test_failed: | |
| 411 | EXIT_BAD | |
| 412 | ||
| 413 | ||
| 414 | /************************************************************************ | |
| 415 | RAS | |
| 416 | Trap Handlers | |
| 417 | ************************************************************************/ | |
| 418 | My_Recoverable_Sw_error_trap: | |
| 419 | ! Signal trap taken | |
| 420 | setx EXECUTED, %l0, %o6 | |
| 421 | ! save trap type value | |
| 422 | rdpr %tt, %o7 | |
| 423 | ||
| 424 | inc %i7 | |
| 425 | ||
| 426 | check_desr_NcuTrap_tt40: | |
| 427 | ldxa [%g0]0x4c, %g2 | |
| 428 | nop | |
| 429 | ||
| 430 | setx 0xb300000000000000, %l0, %g3 | |
| 431 | subcc %g2, %g3, %g4 | |
| 432 | brnz %g4, test_failed | |
| 433 | nop | |
| 434 | ||
| 435 | check_per_tt40: | |
| 436 | mov 0x1, %g1 | |
| 437 | sllx %g1, ERR_FIELD, %g2 | |
| 438 | setx 0x8000000000000000, %g7, %g3 | |
| 439 | or %g2, %g3, %g1 | |
| 440 | ||
| 441 | setx SOC_PER_REG, %g7, %g2 | |
| 442 | ldx [%g2], %g3 | |
| 443 | ||
| 444 | cmp %g1, %g3 | |
| 445 | bne %xcc, test_failed | |
| 446 | nop | |
| 447 | ||
| 448 | check_synd: | |
| 449 | setx SOC_SII_SYN_REG, %g7, %g1 | |
| 450 | ldx [%g1], %g2 | |
| 451 | setx 0x8700000000000000, %g7, %g1 | |
| 452 | and %g2, %g1, %g3 | |
| 453 | setx SII_SYND, %g7, %g4 | |
| 454 | cmp %g3, %g4 | |
| 455 | bne %xcc, test_failed | |
| 456 | nop | |
| 457 | ||
| 458 | clear_synd_reg: | |
| 459 | setx SOC_SII_SYN_REG, %g7, %g1 | |
| 460 | stx %g0, [%g1] | |
| 461 | nop | |
| 462 | ||
| 463 | clear_per_tt40: | |
| 464 | setx SOC_PER_REG, %l7, %g1 | |
| 465 | stx %g0, [%g1] | |
| 466 | nop | |
| 467 | ||
| 468 | clear_ejr_tt40: | |
| 469 | setx SOC_EJR_REG, %l7, %g1 | |
| 470 | stx %g0, [%g1] | |
| 471 | nop | |
| 472 | ||
| 473 | trap_done_tt40: | |
| 474 | done | |
| 475 | nop | |
| 476 | ||
| 477 | ||
| 478 | ||
| 479 | My_Corrected_ECC_error_trap: | |
| 480 | ba test_failed | |
| 481 | nop | |
| 482 | ||
| 483 | ||
| 484 | /************************************************************************ | |
| 485 | Test case data start | |
| 486 | ************************************************************************/ | |
| 487 | ||
| 488 | SECTION .DATA DATA_VA=DMA_DATA_ADDR | |
| 489 | attr_data { | |
| 490 | Name = .DATA, | |
| 491 | hypervisor, | |
| 492 | compressimage | |
| 493 | } | |
| 494 | ||
| 495 | .data | |
| 496 | .global PCIAddr9 | |
| 497 | .xword 0x0001020304050607 | |
| 498 | .xword 0x08090a0b0c0d0e0f | |
| 499 | .xword 0x1011121314151617 | |
| 500 | .xword 0x18191a1b1c1d1e1f | |
| 501 | .xword 0x2021222324252627 | |
| 502 | .xword 0x28292a2b2c2d2e2f | |
| 503 | .xword 0x3031323334353637 | |
| 504 | .xword 0x38393a3b3c3d3e3f | |
| 505 | ||
| 506 | .xword 0x4041424344454647 | |
| 507 | .xword 0x48494a4b4c4d4e4f | |
| 508 | .xword 0x5051525354555657 | |
| 509 | .xword 0x58595a5b5c5d5e5f | |
| 510 | .xword 0x6061626364656667 | |
| 511 | .xword 0x68696a6b6c6d6e6f | |
| 512 | .xword 0x7071727374757677 | |
| 513 | .xword 0x78797a7b7c7d7e7f | |
| 514 | ||
| 515 | .xword 0x8081828384858687 | |
| 516 | .xword 0x88898a8b8c8d8e8f | |
| 517 | .xword 0x9091929394959697 | |
| 518 | .xword 0x98999a9b9c9d9e9f | |
| 519 | .xword 0xa0a1a2a3a4a5a6a7 | |
| 520 | .xword 0xa8a9aaabacadaeaf | |
| 521 | .xword 0xb0b1b2b3b4b5b6b7 | |
| 522 | .xword 0xb8b9babbbcbdbebf | |
| 523 | ||
| 524 | .xword 0xc0c1c2c3c4c5c6c7 | |
| 525 | .xword 0xc8c9cacbcccdcecf | |
| 526 | .xword 0xd0d1d2d3d4d5d6d7 | |
| 527 | .xword 0xd8d9dadbdcdddedf | |
| 528 | .xword 0xe0e1e2e3e4e5e6e7 | |
| 529 | .xword 0xe8e9eaebecedeeef | |
| 530 | .xword 0xf0f1f2f3f4f5f6f7 | |
| 531 | .xword 0xf8f9fafbfcfdfeff | |
| 532 | ||
| 533 | .xword 0x0001020304050607 | |
| 534 | .xword 0x08090a0b0c0d0e0f | |
| 535 | .xword 0x1011121314151617 | |
| 536 | .xword 0x18191a1b1c1d1e1f | |
| 537 | .xword 0x2021222324252627 | |
| 538 | .xword 0x28292a2b2c2d2e2f | |
| 539 | .xword 0x3031323334353637 | |
| 540 | .xword 0x38393a3b3c3d3e3f | |
| 541 | ||
| 542 | .xword 0x4041424344454647 | |
| 543 | .xword 0x48494a4b4c4d4e4f | |
| 544 | .xword 0x5051525354555657 | |
| 545 | .xword 0x58595a5b5c5d5e5f | |
| 546 | .xword 0x6061626364656667 | |
| 547 | .xword 0x68696a6b6c6d6e6f | |
| 548 | .xword 0x7071727374757677 | |
| 549 | .xword 0x78797a7b7c7d7e7f | |
| 550 | ||
| 551 | .xword 0x8081828384858687 | |
| 552 | .xword 0x88898a8b8c8d8e8f | |
| 553 | .xword 0x9091929394959697 | |
| 554 | .xword 0x98999a9b9c9d9e9f | |
| 555 | .xword 0xa0a1a2a3a4a5a6a7 | |
| 556 | .xword 0xa8a9aaabacadaeaf | |
| 557 | .xword 0xb0b1b2b3b4b5b6b7 | |
| 558 | .xword 0xb8b9babbbcbdbebf | |
| 559 | ||
| 560 | .xword 0xc0c1c2c3c4c5c6c7 | |
| 561 | .xword 0xc8c9cacbcccdcecf | |
| 562 | .xword 0xd0d1d2d3d4d5d6d7 | |
| 563 | .xword 0xd8d9dadbdcdddedf | |
| 564 | .xword 0xe0e1e2e3e4e5e6e7 | |
| 565 | .xword 0xe8e9eaebecedeeef | |
| 566 | .xword 0xf0f1f2f3f4f5f6f7 | |
| 567 | .xword 0xf8f9fafbfcfdfeff | |
| 568 | ||
| 569 | /************************************************************************/ | |
| 570 |