[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_piu_strm_wrm_ejr.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_adv_piu_strm_wrm_ejr.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#define  DRAM_0_ERR_STAT_REG              0x8400000280
#define  DRAM_1_ERR_STAT_REG              0x8400001280
#define  DRAM_2_ERR_STAT_REG              0x8400002280
#define  DRAM_3_ERR_STAT_REG              0x8400003280

#define  L2_0_ERR_STAT_REG                0xAB00000000
#define  L2_1_ERR_STAT_REG                0xAB00000040
#define  L2_2_ERR_STAT_REG                0xAB00000080
#define  L2_3_ERR_STAT_REG                0xAB000000c0
#define  L2_4_ERR_STAT_REG                0xAB00000100
#define  L2_5_ERR_STAT_REG                0xAB00000140
#define  L2_6_ERR_STAT_REG                0xAB00000180
#define  L2_7_ERR_STAT_REG                0xAB000001c0


#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define DMA_DATA_ADDR           0x0000000123456700

#define DMA_DATA_BYP_ADDR1      0xfffc000123410000
#define DMA_DATA_BYP_ADDR2      0xfffc000123410200
#define DMA_DATA_BYP_ADDR3      0xfffc000123410400
#define DMA_DATA_BYP_ADDR4      0xfffc000123410600
#define DMA_DATA_BYP_ADDR5      0xfffc000123410800
#define DMA_DATA_BYP_ADDR6      0xfffc000123410a00
#define DMA_DATA_BYP_ADDR7      0xfffc000123410c00
#define DMA_DATA_BYP_ADDR8      0xfffc000123410e00
#define DMA_DATA_BYP_ADDR9      0xfffc000123411000
#define DMA_DATA_BYP_ADDR10     0xfffc000123411200
#define DMA_DATA_BYP_ADDR11     0xfffc000123411400
#define DMA_DATA_BYP_ADDR12     0xfffc000123411600
#define DMA_DATA_BYP_ADDR13     0xfffc000123411800
#define DMA_DATA_BYP_ADDR14     0xfffc000123411a00
#define DMA_DATA_BYP_ADDR15     0xfffc000123411c00
#define DMA_DATA_BYP_ADDR16     0xfffc000123411e00
#define DMA_DATA_BYP_ADDR17	0xfffc000123412000
#define DMA_DATA_BYP_ADDR18	0xfffc000123412200
#define DMA_DATA_BYP_ADDR19     0xfffc000123412400
#define DMA_DATA_BYP_ADDR20	0xfffc000123412600
#define DMA_DATA_BYP_ADDR21     0xfffc000123412800
#define DMA_DATA_BYP_ADDR22     0xfffc000123412a00
#define DMA_DATA_BYP_ADDR23     0xfffc000123412c00

#define SOC_SII_SYN_REG	 0x8000003030

/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

	clr	%i7
	clr	%o6
	clr	%o7
	clr	%i0

clear_mem:
	setx	0x123410c00, %g7, %g1
	stx	%g0, [%g1]
	setx	0x123411800, %g7, %g1
	stx	%g0, [%g1]

l2_err_enable:
        set	0x3, %l1 
        mov     0xaa, %g2
        sllx    %g2, 32, %g2
        stx     %l1, [%g2]
        stx     %l1, [%g2 + 0x40]
        stx     %l1, [%g2 + 0x80]
        stx     %l1, [%g2 + 0xc0]
        stx     %l1, [%g2 + 0x100]
        stx     %l1, [%g2 + 0x140]
        stx     %l1, [%g2 + 0x180]
        stx     %l1, [%g2 + 0x1c0]

bypass_iommu:
        ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

	/*******************************************************
		RDD from DMU
	********************************************************/
set_eie:
        mov     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2
        setx    SOC_EIE_REG, %g7, %g3
        stx     %g2, [%g3]
        membar  0x40


set_ejr_1:
        setx    SOC_EJR_REG, %g7, %g6
        stx     %g2, [%g6]
        membar  0x40


UsrEvnt_wrm_1:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h10", 1 )


	setx	0x100, %g7, %g5
chk_ejr_1:
        cmp	%g5, %g0
	be	%xcc, test_failed
	nop

	ldx	[%g6], %g1
	cmp	%g1, %g0
	be	%xcc, UsrEvnt_wrm_2
	nop

	dec	%g5

	ba	chk_ejr_1
	nop

UsrEvnt_wrm_2:
	nop
	nop
	nop
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_2)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR2, DMA_DATA_BYP_ADDR2, "64'h10", 1 )

UsrEvnt_wrm_3:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_3)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR3, "64'h10", 1 )

UsrEvnt_wrm_4:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_4)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR4, DMA_DATA_BYP_ADDR4, "64'h10", 1 )

UsrEvnt_wrm_5:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_5)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR5, DMA_DATA_BYP_ADDR5, "64'h10", 1 )

UsrEvnt_wrm_6:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_6)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR6, DMA_DATA_BYP_ADDR6, "64'h10", 1 )

UsrEvnt_wrm_7:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_7)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR7, DMA_DATA_BYP_ADDR7, "64'h10", 1 )


	!check that the last data from DMA is written to memory
read_ADDR7:
	setx	0x123410c00, %g7, %g1
	ld	[%g1], %g3
	cmp	%g3, %g0
	be	read_ADDR7
	nop


set_ejr_2:
	stx	%g2, [%g6]
	membar	0x40

UsrEvnt_wrm_8:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_8)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR8, DMA_DATA_BYP_ADDR8, "64'h10", 1 )


	setx	0x100, %g7, %g5
chk_ejr_2:
        cmp	%g5, %g0
	be	%xcc, test_failed
	nop

	ldx	[%g6], %g1
	cmp	%g1, %g0
	be	%xcc, UsrEvnt_wrm_9
	nop

	dec	%g5

	ba	chk_ejr_2
	nop


UsrEvnt_wrm_9:
	nop
	nop
	nop
	nop
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_9)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR9, DMA_DATA_BYP_ADDR9, "64'h10", 1 )

UsrEvnt_wrm_10:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_10)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR10, DMA_DATA_BYP_ADDR10, "64'h10", 1 )

UsrEvnt_wrm_11:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_11)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR11, DMA_DATA_BYP_ADDR11, "64'h10", 1 )

UsrEvnt_wrm_12:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_12)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR12, DMA_DATA_BYP_ADDR12, "64'h10", 1 )

UsrEvnt_wrm_13:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_13)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR13, DMA_DATA_BYP_ADDR13, "64'h10", 1 )


	!check that the last data from DMA is written to memory
read_ADDR13:
	setx	0x123411800, %g7, %g1
	ld	[%g1], %g3
	cmp	%g3, %g0
	be	read_ADDR13
	nop

set_ejr_3:
        stx     %g2, [%g6]
        membar  0x40

UsrEvnt_wrm_14:
        nop         ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_14)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR14, DMA_DATA_BYP_ADDR14, "64'h10", 1 )


        setx    0x100, %g7, %g5
chk_ejr_3:
        cmp     %g5, %g0
        be      %xcc, test_failed
        nop

        ldx     [%g6], %g1
        cmp     %g1, %g0
        be      %xcc, UsrEvnt_wrm_15
        nop

        dec     %g5

        ba      chk_ejr_3
        nop

UsrEvnt_wrm_15:
	nop
	nop
	nop
	nop
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_15)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR15, DMA_DATA_BYP_ADDR15, "64'h10", 1 )

UsrEvnt_wrm_16:
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_16)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR16, DMA_DATA_BYP_ADDR16, "64'h10", 1 )

UsrEvnt_wrm_17:
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_17)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR17, DMA_DATA_BYP_ADDR17, "64'h10", 1 )

UsrEvnt_wrm_18:
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_18)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR18, DMA_DATA_BYP_ADDR18, "64'h10", 1 )

UsrEvnt_wrm_19:
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_19)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR19, DMA_DATA_BYP_ADDR19, "64'h10", 1 )

UsrEvnt_wrm_20:
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_20)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR20, DMA_DATA_BYP_ADDR20, "64'h10", 1 )

UsrEvnt_wrm_21:
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_21)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR21, DMA_DATA_BYP_ADDR21, "64'h10", 1 )

pios:
	setx	FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3

/*
	set	0x6, %g1		
        setx    0x100, %g7, %g5
err_trap_loop_rdd:
        cmp     %g5, %g0
        be      %xcc, test_failed
        nop

	cmp	%g1, %i7
	be	%xcc, check_mcu_esr
	nop

	dec	%g5

	ba	err_trap_loop_rdd
	nop
*/


check_mcu_esr:
        setx  	DRAM_0_ERR_STAT_REG, %g7, %g6 

        ldx   	[%g6], %g3
	setx    0xff30000000000000, %g7, %g1
	and	%g1, %g3, %g2

	mov	1, %g1
	sllx	%g1, DRAM_ES_DBU, %g3

        mov     1, %g1
        sllx    %g1, DRAM_ES_MEB, %g4

	or	%g3, %g4, %g5

	cmp	%g2, %g5
	bne	test_failed
	nop
	
check_L2_ESR:
        setx    L2_0_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %g3
        setx    0xfffffffc00000000, %g7, %g1    
        and     %g1, %g3, %g2  

        mov     1, %g1
        sllx    %g1, L2ES_DAU, %g3

        mov     1, %g1
        sllx    %g1, L2ES_MEU, %g4

        or      %g3, %g4, %g5

        mov     1, %g1
        sllx    %g1, L2ES_VEU, %g4

	or	%g5, %g4, %g3

        cmp     %g2, %g3       
        bne     test_failed    
        nop

check_tt_rdd:
        mov     0x40, %l0
        cmp     %o7, %l0
        bne     %xcc, test_failed
        nop

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

        inc	%i7

check_synd:
        setx    SOC_SII_SYN_REG, %g7, %g1
        ldx     [%g1], %g2
	setx	0x8700000000000000, %g7, %g1
	and	%g2, %g1, %g3
	setx	SII_SYND, %g7, %g4
	cmp	%g3, %g4
	bne	%xcc, test_failed
	nop


clear_synd_reg:
	setx	SOC_SII_SYN_REG, %g7, %g1
	stx	%g0, [%g1]
	nop

check_desr_NcuTrap_tt40:
        ldxa  [%g0]0x4c, %g2
        nop

        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, l2_trap 
	nop

check_per_tt40:
        mov     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2
        setx    0x8000000000000000, %g7, %g3
        or      %g2, %g3, %g1

        setx    SOC_PER_REG, %g7, %g2
        ldx     [%g2], %g3

        cmp     %g1, %g3
        bne     %xcc, test_failed
        nop

	ba 	clear_ejr_tt40
	nop

l2_trap:
        nop
        inc    %i0

check_desr_L2Trap_tt40:
        setx    0xb000000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, both_l2_soc
        nop

	mov	0x1, %g1
	sllx	%g1, L2ES_DAU, %g2

        mov     0x1, %g1 
        sllx    %g1, L2ES_DAU, %g2       

	
	ba	trap_done_tt40
	nop

both_l2_soc:
        setx    0xf300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brz     %g4, clear_ejr_tt40 
        nop

two_l2_err:
	setx	0xf000000000000000, %l0, %g3
	subcc	%g2, %g3, %g4
	brnz    %g4, test_failed 
	nop

clear_ejr_tt40:
        setx    SOC_EJR_REG, %l7, %g1
        stx     %g0, [%g1]
        nop

clear_per_tt40:
        setx    SOC_PER_REG, %l7, %g1
        stx     %g0, [%g1]
        nop

trap_done_tt40:
       	done			
        nop


My_Corrected_ECC_error_trap:
	ba	test_failed
        nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_adv_piu_strm_wrm_ejr.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#define DRAM_0_ERR_STAT_REG 0x8400000280
	46	#define DRAM_1_ERR_STAT_REG 0x8400001280
	47	#define DRAM_2_ERR_STAT_REG 0x8400002280
	48	#define DRAM_3_ERR_STAT_REG 0x8400003280
	49
	50	#define L2_0_ERR_STAT_REG 0xAB00000000
	51	#define L2_1_ERR_STAT_REG 0xAB00000040
	52	#define L2_2_ERR_STAT_REG 0xAB00000080
	53	#define L2_3_ERR_STAT_REG 0xAB000000c0
	54	#define L2_4_ERR_STAT_REG 0xAB00000100
	55	#define L2_5_ERR_STAT_REG 0xAB00000140
	56	#define L2_6_ERR_STAT_REG 0xAB00000180
	57	#define L2_7_ERR_STAT_REG 0xAB000001c0
	58
	59
	60	#include "err_defines.h"
	61	#include "hboot.s"
	62	#include "peu_defines.h"
	63
	64	#define DMA_DATA_ADDR 0x0000000123456700
65
66	#define DMA_DATA_BYP_ADDR1 0xfffc000123410000
67	#define DMA_DATA_BYP_ADDR2 0xfffc000123410200
68	#define DMA_DATA_BYP_ADDR3 0xfffc000123410400
69	#define DMA_DATA_BYP_ADDR4 0xfffc000123410600
70	#define DMA_DATA_BYP_ADDR5 0xfffc000123410800
71	#define DMA_DATA_BYP_ADDR6 0xfffc000123410a00
72	#define DMA_DATA_BYP_ADDR7 0xfffc000123410c00
73	#define DMA_DATA_BYP_ADDR8 0xfffc000123410e00
74	#define DMA_DATA_BYP_ADDR9 0xfffc000123411000
75	#define DMA_DATA_BYP_ADDR10 0xfffc000123411200
76	#define DMA_DATA_BYP_ADDR11 0xfffc000123411400
77	#define DMA_DATA_BYP_ADDR12 0xfffc000123411600
78	#define DMA_DATA_BYP_ADDR13 0xfffc000123411800
79	#define DMA_DATA_BYP_ADDR14 0xfffc000123411a00
80	#define DMA_DATA_BYP_ADDR15 0xfffc000123411c00
81	#define DMA_DATA_BYP_ADDR16 0xfffc000123411e00
82	#define DMA_DATA_BYP_ADDR17 0xfffc000123412000
83	#define DMA_DATA_BYP_ADDR18 0xfffc000123412200
84	#define DMA_DATA_BYP_ADDR19 0xfffc000123412400
85	#define DMA_DATA_BYP_ADDR20 0xfffc000123412600
86	#define DMA_DATA_BYP_ADDR21 0xfffc000123412800
87	#define DMA_DATA_BYP_ADDR22 0xfffc000123412a00
88	#define DMA_DATA_BYP_ADDR23 0xfffc000123412c00
89
90	#define SOC_SII_SYN_REG 0x8000003030
91
92	/************************************************************************
93	Test case code start
94	************************************************************************/
95	.text
96	.global main
97	.global My_Corrected_ECC_error_trap
98	.global My_Recoverable_Sw_error_trap
99
100	main:
101	ta T_CHANGE_HPRIV
102	nop
103
104	clr %i7
105	clr %o6
106	clr %o7
107	clr %i0
108
109	clear_mem:
110	setx 0x123410c00, %g7, %g1
111	stx %g0, [%g1]
112	setx 0x123411800, %g7, %g1
113	stx %g0, [%g1]
114
115	l2_err_enable:
116	set 0x3, %l1
117	mov 0xaa, %g2
118	sllx %g2, 32, %g2
119	stx %l1, [%g2]
120	stx %l1, [%g2 + 0x40]
121	stx %l1, [%g2 + 0x80]
122	stx %l1, [%g2 + 0xc0]
123	stx %l1, [%g2 + 0x100]
124	stx %l1, [%g2 + 0x140]
125	stx %l1, [%g2 + 0x180]
126	stx %l1, [%g2 + 0x1c0]
127
128	bypass_iommu:
129	! enable bypass in IOMMU
130	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
131	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
132	stx %g3, [%g2]
133	ldx [%g2], %g3
134
135	/*******************************************************
136	RDD from DMU
137	********************************************************/
138	set_eie:
139	mov 0x1, %g1
140	sllx %g1, ERR_FIELD, %g2
141	setx SOC_EIE_REG, %g7, %g3
142	stx %g2, [%g3]
143	membar 0x40
144
145
146	set_ejr_1:
147	setx SOC_EJR_REG, %g7, %g6
148	stx %g2, [%g6]
149	membar 0x40
150
151
152	UsrEvnt_wrm_1:
153	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h10", 1 )
154
155
156	setx 0x100, %g7, %g5
157	chk_ejr_1:
158	cmp %g5, %g0
159	be %xcc, test_failed
160	nop
161
162	ldx [%g6], %g1
163	cmp %g1, %g0
164	be %xcc, UsrEvnt_wrm_2
165	nop
166
167	dec %g5
168
169	ba chk_ejr_1
170	nop
171
172	UsrEvnt_wrm_2:
173	nop
174	nop
175	nop
176	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_2)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR2, DMA_DATA_BYP_ADDR2, "64'h10", 1 )
177
178	UsrEvnt_wrm_3:
179	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_3)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR3, "64'h10", 1 )
180
181	UsrEvnt_wrm_4:
182	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_4)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR4, DMA_DATA_BYP_ADDR4, "64'h10", 1 )
183
184	UsrEvnt_wrm_5:
185	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_5)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR5, DMA_DATA_BYP_ADDR5, "64'h10", 1 )
186
187	UsrEvnt_wrm_6:
188	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_6)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR6, DMA_DATA_BYP_ADDR6, "64'h10", 1 )
189
190	UsrEvnt_wrm_7:
191	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_7)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR7, DMA_DATA_BYP_ADDR7, "64'h10", 1 )
192
193
194	!check that the last data from DMA is written to memory
195	read_ADDR7:
196	setx 0x123410c00, %g7, %g1
197	ld [%g1], %g3
198	cmp %g3, %g0
199	be read_ADDR7
200	nop
201
202
203	set_ejr_2:
204	stx %g2, [%g6]
205	membar 0x40
206
207	UsrEvnt_wrm_8:
208	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_8)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR8, DMA_DATA_BYP_ADDR8, "64'h10", 1 )
209
210
211	setx 0x100, %g7, %g5
212	chk_ejr_2:
213	cmp %g5, %g0
214	be %xcc, test_failed
215	nop
216
217	ldx [%g6], %g1
218	cmp %g1, %g0
219	be %xcc, UsrEvnt_wrm_9
220	nop
221
222	dec %g5
223
224	ba chk_ejr_2
225	nop
226
227
228	UsrEvnt_wrm_9:
229	nop
230	nop
231	nop
232	nop
233	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_9)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR9, DMA_DATA_BYP_ADDR9, "64'h10", 1 )
234
235	UsrEvnt_wrm_10:
236	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_10)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR10, DMA_DATA_BYP_ADDR10, "64'h10", 1 )
237
238	UsrEvnt_wrm_11:
239	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_11)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR11, DMA_DATA_BYP_ADDR11, "64'h10", 1 )
240
241	UsrEvnt_wrm_12:
242	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_12)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR12, DMA_DATA_BYP_ADDR12, "64'h10", 1 )
243
244	UsrEvnt_wrm_13:
245	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_13)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR13, DMA_DATA_BYP_ADDR13, "64'h10", 1 )
246
247
248
249	!check that the last data from DMA is written to memory
250	read_ADDR13:
251	setx 0x123411800, %g7, %g1
252	ld [%g1], %g3
253	cmp %g3, %g0
254	be read_ADDR13
255	nop
256
257	set_ejr_3:
258	stx %g2, [%g6]
259	membar 0x40
260
261	UsrEvnt_wrm_14:
262	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_14)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR14, DMA_DATA_BYP_ADDR14, "64'h10", 1 )
263
264
265	setx 0x100, %g7, %g5
266	chk_ejr_3:
267	cmp %g5, %g0
268	be %xcc, test_failed
269	nop
270
271	ldx [%g6], %g1
272	cmp %g1, %g0
273	be %xcc, UsrEvnt_wrm_15
274	nop
275
276	dec %g5
277
278	ba chk_ejr_3
279	nop
280
281	UsrEvnt_wrm_15:
282	nop
283	nop
284	nop
285	nop
286	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_15)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR15, DMA_DATA_BYP_ADDR15, "64'h10", 1 )
287
288	UsrEvnt_wrm_16:
289	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_16)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR16, DMA_DATA_BYP_ADDR16, "64'h10", 1 )
290
291	UsrEvnt_wrm_17:
292	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_17)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR17, DMA_DATA_BYP_ADDR17, "64'h10", 1 )
293
294	UsrEvnt_wrm_18:
295	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_18)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR18, DMA_DATA_BYP_ADDR18, "64'h10", 1 )
296
297	UsrEvnt_wrm_19:
298	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_19)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR19, DMA_DATA_BYP_ADDR19, "64'h10", 1 )
299
300	UsrEvnt_wrm_20:
301	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_20)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR20, DMA_DATA_BYP_ADDR20, "64'h10", 1 )
302
303	UsrEvnt_wrm_21:
304	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wrm_21)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR21, DMA_DATA_BYP_ADDR21, "64'h10", 1 )
305
306	pios:
307	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
308	ldx [%g2], %g3
309	ldx [%g2], %g3
310	ldx [%g2], %g3
311	ldx [%g2], %g3
312
313	/*
314	set 0x6, %g1
315	setx 0x100, %g7, %g5
316	err_trap_loop_rdd:
317	cmp %g5, %g0
318	be %xcc, test_failed
319	nop
320
321	cmp %g1, %i7
322	be %xcc, check_mcu_esr
323	nop
324
325	dec %g5
326
327	ba err_trap_loop_rdd
328	nop
329	*/
330
331
332	check_mcu_esr:
333	setx DRAM_0_ERR_STAT_REG, %g7, %g6
334
335	ldx [%g6], %g3
336	setx 0xff30000000000000, %g7, %g1
337	and %g1, %g3, %g2
338
339	mov 1, %g1
340	sllx %g1, DRAM_ES_DBU, %g3
341
342	mov 1, %g1
343	sllx %g1, DRAM_ES_MEB, %g4
344
345	or %g3, %g4, %g5
346
347	cmp %g2, %g5
348	bne test_failed
349	nop
350
351	check_L2_ESR:
352	setx L2_0_ERR_STAT_REG, %l3, %g5
353	ldx [%g5], %g3
354	setx 0xfffffffc00000000, %g7, %g1
355	and %g1, %g3, %g2
356
357	mov 1, %g1
358	sllx %g1, L2ES_DAU, %g3
359
360	mov 1, %g1
361	sllx %g1, L2ES_MEU, %g4
362
363	or %g3, %g4, %g5
364
365	mov 1, %g1
366	sllx %g1, L2ES_VEU, %g4
367
368	or %g5, %g4, %g3
369
370	cmp %g2, %g3
371	bne test_failed
372	nop
373
374	check_tt_rdd:
375	mov 0x40, %l0
376	cmp %o7, %l0
377	bne %xcc, test_failed
378	nop
379
380	test_passed:
381	EXIT_GOOD
382
383	test_failed:
384	EXIT_BAD
385
386
387	/************************************************************************
388	RAS
389	Trap Handlers
390	************************************************************************/
391	My_Recoverable_Sw_error_trap:
392	! Signal trap taken
393	setx EXECUTED, %l0, %o6
394	! save trap type value
395	rdpr %tt, %o7
396
397	inc %i7
398
399	check_synd:
400	setx SOC_SII_SYN_REG, %g7, %g1
401	ldx [%g1], %g2
402	setx 0x8700000000000000, %g7, %g1
403	and %g2, %g1, %g3
404	setx SII_SYND, %g7, %g4
405	cmp %g3, %g4
406	bne %xcc, test_failed
407	nop
408
409
410	clear_synd_reg:
411	setx SOC_SII_SYN_REG, %g7, %g1
412	stx %g0, [%g1]
413	nop
414
415	check_desr_NcuTrap_tt40:
416	ldxa [%g0]0x4c, %g2
417	nop
418
419	setx 0xb300000000000000, %l0, %g3
420	subcc %g2, %g3, %g4
421	brnz %g4, l2_trap
422	nop
423
424	check_per_tt40:
425	mov 0x1, %g1
426	sllx %g1, ERR_FIELD, %g2
427	setx 0x8000000000000000, %g7, %g3
428	or %g2, %g3, %g1
429
430	setx SOC_PER_REG, %g7, %g2
431	ldx [%g2], %g3
432
433	cmp %g1, %g3
434	bne %xcc, test_failed
435	nop
436
437	ba clear_ejr_tt40
438	nop
439
440	l2_trap:
441	nop
442	inc %i0
443
444	check_desr_L2Trap_tt40:
445	setx 0xb000000000000000, %l0, %g3
446	subcc %g2, %g3, %g4
447	brnz %g4, both_l2_soc
448	nop
449
450	mov 0x1, %g1
451	sllx %g1, L2ES_DAU, %g2
452
453	mov 0x1, %g1
454	sllx %g1, L2ES_DAU, %g2
455
456
457	ba trap_done_tt40
458	nop
459
460	both_l2_soc:
461	setx 0xf300000000000000, %l0, %g3
462	subcc %g2, %g3, %g4
463	brz %g4, clear_ejr_tt40
464	nop
465
466	two_l2_err:
467	setx 0xf000000000000000, %l0, %g3
468	subcc %g2, %g3, %g4
469	brnz %g4, test_failed
470	nop
471
472	clear_ejr_tt40:
473	setx SOC_EJR_REG, %l7, %g1
474	stx %g0, [%g1]
475	nop
476
477	clear_per_tt40:
478	setx SOC_PER_REG, %l7, %g1
479	stx %g0, [%g1]
480	nop
481
482	trap_done_tt40:
483	done
484	nop
485
486
487
488	My_Corrected_ECC_error_trap:
489	ba test_failed
490	nop
491
492
493	/************************************************************************
494	Test case data start
495	************************************************************************/
496
497	SECTION .DATA DATA_VA=DMA_DATA_ADDR
498	attr_data {
499	Name = .DATA,
500	hypervisor,
501	compressimage
502	}
503
504	.data
505	.global PCIAddr9
506	.xword 0x0001020304050607
507	.xword 0x08090a0b0c0d0e0f
508	.xword 0x1011121314151617
509	.xword 0x18191a1b1c1d1e1f
510	.xword 0x2021222324252627
511	.xword 0x28292a2b2c2d2e2f
512	.xword 0x3031323334353637
513	.xword 0x38393a3b3c3d3e3f
514
515	.xword 0x4041424344454647
516	.xword 0x48494a4b4c4d4e4f
517	.xword 0x5051525354555657
518	.xword 0x58595a5b5c5d5e5f
519	.xword 0x6061626364656667
520	.xword 0x68696a6b6c6d6e6f
521	.xword 0x7071727374757677
522	.xword 0x78797a7b7c7d7e7f
523
524	.xword 0x8081828384858687
525	.xword 0x88898a8b8c8d8e8f
526	.xword 0x9091929394959697
527	.xword 0x98999a9b9c9d9e9f
528	.xword 0xa0a1a2a3a4a5a6a7
529	.xword 0xa8a9aaabacadaeaf
530	.xword 0xb0b1b2b3b4b5b6b7
531	.xword 0xb8b9babbbcbdbebf
532
533	.xword 0xc0c1c2c3c4c5c6c7
534	.xword 0xc8c9cacbcccdcecf
535	.xword 0xd0d1d2d3d4d5d6d7
536	.xword 0xd8d9dadbdcdddedf
537	.xword 0xe0e1e2e3e4e5e6e7
538	.xword 0xe8e9eaebecedeeef
539	.xword 0xf0f1f2f3f4f5f6f7
540	.xword 0xf8f9fafbfcfdfeff
541
542	.xword 0x0001020304050607
543	.xword 0x08090a0b0c0d0e0f
544	.xword 0x1011121314151617
545	.xword 0x18191a1b1c1d1e1f
546	.xword 0x2021222324252627
547	.xword 0x28292a2b2c2d2e2f
548	.xword 0x3031323334353637
549	.xword 0x38393a3b3c3d3e3f
550
551	.xword 0x4041424344454647
552	.xword 0x48494a4b4c4d4e4f
553	.xword 0x5051525354555657
554	.xword 0x58595a5b5c5d5e5f
555	.xword 0x6061626364656667
556	.xword 0x68696a6b6c6d6e6f
557	.xword 0x7071727374757677
558	.xword 0x78797a7b7c7d7e7f
559
560	.xword 0x8081828384858687
561	.xword 0x88898a8b8c8d8e8f
562	.xword 0x9091929394959697
563	.xword 0x98999a9b9c9d9e9f
564	.xword 0xa0a1a2a3a4a5a6a7
565	.xword 0xa8a9aaabacadaeaf
566	.xword 0xb0b1b2b3b4b5b6b7
567	.xword 0xb8b9babbbcbdbebf
568
569	.xword 0xc0c1c2c3c4c5c6c7
570	.xword 0xc8c9cacbcccdcecf
571	.xword 0xd0d1d2d3d4d5d6d7
572	.xword 0xd8d9dadbdcdddedf
573	.xword 0xe0e1e2e3e4e5e6e7
574	.xword 0xe8e9eaebecedeeef
575	.xword 0xf0f1f2f3f4f5f6f7
576	.xword 0xf8f9fafbfcfdfeff
577
578	/************************************************************************/
579