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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_rx.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_rx.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45#include "hboot.s"
46#include "niu_defines.h"
47
48/************************************************************************
49 Test case code start
50 ************************************************************************/
51.text
52.global main
53.global My_Corrected_ECC_error_trap
54.global My_Recoverable_Sw_error_trap
55
56main:
57 ta T_CHANGE_HPRIV
58 nop
59
60!#include "niu_init.h"
61!
62! Thread 0 Start
63!
64!
65!thread_0:
66 nop
67
68
69
70 /************************************
71 RAS
72 *************************************/
73clear_esr_first:
74 setx SOC_ESR_REG, %l7, %i0
75 stx %g0, [%i0]
76
77inj_err1:
78 nop !$EV trig_pc_d(0,@VA(.MAIN.inj_err1)) ->IosErrInj(ERR_TYPE, ERR_TAG, ERR_ADDR)
79
80
81L2_err_enable:
82 set 0x3, %l1
83 mov 0xaa, %g2
84 sllx %g2, 32, %g2
85 stx %l1, [%g2]
86 stx %l1, [%g2 + 0x40]
87 stx %l1, [%g2 + 0x80]
88 stx %l1, [%g2 + 0xc0]
89 stx %l1, [%g2 + 0x100]
90 stx %l1, [%g2 + 0x140]
91 stx %l1, [%g2 + 0x180]
92 stx %l1, [%g2 + 0x1c0]
93
94 /*************************************/
95
96
97
98/************************************************************************
99 First call the Vera, so that values are updated in Memory and
100 then read those values from assembly and program the registers
101 ************************************************************************/
102P_NIU_RxInitDma:
103 nop !$EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma)) -> NIU_InitRxDma(RXDMA_CHNL, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, NIU_Xlate_On)
104
105 setx 0x5, %g1, %g4 ! Delay for Vera to complete
106delay_loop_Rx:
107 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
108 nop
109 nop
110 nop
111 nop
112 dec %g4
113 brnz %g4, delay_loop_Rx
114 nop
115
116 nop
117 setx RXDMA_CHNL, %g1, %o0
118 setx RX_DESC_RING_LENGTH, %g1, %o1
119 setx RX_COMPL_RING_LEN, %g1, %o2
120 setx RBR_CONFIG_B_DATA, %g1, %o3
121 setx RX_INITIAL_KICK, %g1, %o4
122 call NiuInitRxDma
123 nop
124
125P_NIU_RxPkt_Conf:
126 nop !$EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxPkt_Conf)) -> NIU_RxPktConf(RXMAC_PKTCNT, MAC_ID)
127 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for Delay
128 nop
129
130
131P_NIU_Rx_GenPkt:
132 setx RXMAC_PKTCNT, %g1, %g6 ! Packet count
133 nop
134Rx_pktcnt_loop:
135 nop !$EV trig_pc_d(1, @VA(.MAIN.Rx_pktcnt_loop)) -> NIU_RxGenPkt(MAC_ID, RXDMA_CHNL, 1, MAC_PKT_LEN, 0x0, RX_NIU_MULTI_DMA, 1)
136 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! just for delay
137 nop
138 dec %g6
139 brnz %g6, Rx_pktcnt_loop
140 nop
141
142 setx loop_count, %g1, %g4
143delay_loop:
144 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
145 nop
146 nop
147 nop
148 nop
149 dec %g4
150 brnz %g4, delay_loop
151 nop
152
153
154 /************************************
155 RAS
156 *************************************/
157esr:
158 setx SOC_ESR_REG, %g7, %g5
159 setx 0x100, %g7, %g6
160
161 setx 0x8000000000000000, %g7, %g1 !valid bit
162 set 0x1, %g2
163 sllx %g2, ERR_FIELD, %g3
164 or %g3, %g1, %g2
165esr_loop:
166 dec %g6
167 cmp %g6, %g0
168 be %xcc, test_failed
169 nop
170
171 ldx [%g5], %g3
172
173 cmp %g3, %g2
174 be %xcc, eie_reg_ones
175 nop
176
177 ba esr_loop
178 nop
179
180eie_reg_ones:
181 setx SOC_EIE_REG, %g3, %g2
182 setx 0xffffffffffffffff, %g3, %g1
183 stx %g1, [%g2]
184 membar 0x40
185
186 set 0x1, %g1 ! 1 traps from rdd; 1 trap from WRI
187 setx 0x100, %g7, %g6
188err_trap_loop:
189 cmp %g6, %g0
190 be %xcc, test_failed
191 nop
192
193 cmp %g1, %i7
194 be %xcc, check_tt
195 nop
196
197 ba err_trap_loop
198 nop
199
200check_tt:
201 setx EXECUTED, %l1, %l0
202 cmp %o6, %l0
203 bne test_failed
204 nop
205
206
207test_passed:
208 nop
209 EXIT_GOOD
210
211!.global test_failed
212test_failed:
213 EXIT_BAD
214
215
216/************************************************************************
217 RAS
218 Trap Handlers
219 ************************************************************************/
220My_Recoverable_Sw_error_trap:
221 ! Signal trap taken
222 setx EXECUTED, %l0, %o6
223 ! save trap type value
224 rdpr %tt, %o7
225
226 inc %i7
227
228check_desr_tt40:
229 ldxa [%g0]0x4c, %g2
230 nop
231 setx 0xb300000000000000, %l0, %g3
232 subcc %g2, %g3, %g4
233 brnz %g4, test_failed
234 nop
235
236check_per_tt40:
237 setx SOC_PER_REG, %l7, %i0
238 ldx [%i0], %i1
239 setx 0x8000000000000000, %l7, %o3 !valid bit
240 set 0x1, %i2
241 sllx %i2, ERR_FIELD, %i3
242 or %i3, %o3, %i4
243 sub %i1, %i4, %i5
244 brnz %i5, test_failed
245 nop
246
247clear_per_tt40:
248 setx SOC_PER_REG, %l7, %i0
249 stx %g0, [%i0]
250 nop
251 done
252 nop
253
254
255
256My_Corrected_ECC_error_trap:
257 ! Signal trap taken
258 setx EXECUTED, %l0, %o6
259 ! save trap type value
260 rdpr %tt, %o7
261
262 inc %i7
263
264check_desr_tt63:
265 ldxa [%g0]0x4c, %g2
266 nop
267 setx 0x8b00000000000000, %l0, %g3
268 subcc %g2, %g3, %g4
269 brnz %g4, test_failed
270
271check_per_tt63:
272 setx SOC_PER_REG, %l7, %i0
273 ldx [%i0], %i1
274 setx 0x8000000000000000, %l7, %o3 !valid bit
275 set 0x1, %i2
276 sllx %i2, ERR_FIELD, %i3
277 or %i3, %o3, %i4
278 sub %i1, %i4, %i5
279 brnz %i5, test_failed
280 nop
281
282clear_per_tt63:
283 setx SOC_PER_REG, %l7, %i0
284 stx %g0, [%i0]
285 nop
286 retry
287 nop
288
289/************************************************************************
290 Test case data start
291 ************************************************************************/
292/* These initialization is temporary, as there looks some bug in mempli */
293!
294!SECTION SetRngConfig_init data_va=0x100000000
295!attr_data {
296! Name = SetRngConfig_init,
297! hypervisor,
298! compressimage
299! }
300!.data
301!SetRngConfig_init:
302! .xword 0x0060452301000484
303/************************************************************************/
304
305SECTION SetRxLogMask1_init data_va=0x200000100
306attr_data {
307 Name = SetRxLogMask1_init,
308 hypervisor,
309 compressimage
310 }
311.data
312SetRxLogMask1_init:
313 .xword 0x0060452301000484
314/************************************************************************/
315
316SECTION SetRxLogVal1_init data_va=0x200000200
317attr_data {
318 Name = SetRxLogVal1_init,
319 hypervisor,
320 compressimage
321 }
322.data
323SetRxLogVal1_init:
324 .xword 0x0060452301000484
325/************************************************************************/
326
327SECTION SetRxLogRelo1_init data_va=0x200000300
328attr_data {
329 Name = SetRxLogRelo1_init,
330 hypervisor,
331 compressimage
332 }
333.data
334SetRxLogRelo1_init:
335 .xword 0x0060452301000484
336/************************************************************************/
337
338SECTION SetRxLogPgVld_init data_va=0x200000400
339attr_data {
340 Name = SetRxLogPgVld_init,
341 hypervisor,
342 compressimage
343 }
344.data
345SetRxLogPgVld_init:
346 .xword 0x0060452301000484
347/************************************************************************/
348SECTION SetRbrConfig_A_init data_va=0x200000500
349attr_data {
350 Name = SetRbrConfig_A_init,
351 hypervisor,
352 compressimage
353 }
354.data
355SetRbrConfig_A_init:
356 .xword 0x0060452301000484
357/************************************************************************/
358SECTION SetRbrConfig_B_init data_va=0x200000600
359attr_data {
360 Name = SetRbrConfig_B_init,
361 hypervisor,
362 compressimage
363 }
364.data
365SetRbrConfig_B_init:
366 .xword 0x0060452301000484
367/************************************************************************/
368SECTION SetRcrConfig_A_init data_va=0x200000700
369attr_data {
370 Name = SetRcrConfig_A_init,
371 hypervisor,
372 compressimage
373 }
374.data
375SetRcrConfig_A_init:
376 .xword 0x0060452301000484
377/************************************************************************/
378SECTION SetRxDmaCfig_1_0_init data_va=0x200000800
379attr_data {
380 Name = SetRxDmaCfig_1_0_init,
381 hypervisor,
382 compressimage
383 }
384.data
385SetRxDmaCfig_1_0_init:
386 .xword 0x0060452301000484
387/************************************************************************/
388SECTION SetRxdmaCfig2Start_init data_va=0x200000900
389attr_data {
390 Name = SetRxdmaCfig2Start_init,
391 hypervisor,
392 compressimage
393 }
394.data
395SetRxdmaCfig2Start_init:
396 .xword 0x0060452301000484
397/************************************************************************/
398SECTION SetRxDmaCfig_1_1_init data_va=0x200000a00
399attr_data {
400 Name = SetRxDmaCfig_1_1_init,
401 hypervisor,
402 compressimage
403 }
404.data
405SetRxDmaCfig_1_1_init:
406 .xword 0x0060452301000484
407
408/************************************************************************/
409
410SECTION SetRxRingKick_init data_va=0x200000b00
411attr_data {
412 Name = SetRxRingKick_init,
413 hypervisor,
414 compressimage
415 }
416.data
417SetRxRingKick_init:
418 .xword 0x0060452301000484
419/************************************************************************/
420
421SECTION SetRxLogMask2_init data_va=0x200000c00
422attr_data {
423 Name = SetRxLogMask2_init,
424 hypervisor,
425 compressimage
426 }
427.data
428SetRxLogMask2_init:
429 .xword 0x0060452301000484
430/************************************************************************/
431
432SECTION SetRxLogVal2_init data_va=0x200000d00
433attr_data {
434 Name = SetRxLogVal2_init,
435 hypervisor,
436 compressimage
437 }
438.data
439SetRxLogVal2_init:
440 .xword 0x0060452301000484
441/************************************************************************/
442
443SECTION SetRxLogRelo2_init data_va=0x200000e00
444attr_data {
445 Name = SetRxLogRelo2_init,
446 hypervisor,
447 compressimage
448 }
449.data
450SetRxLogRelo2_init:
451 .xword 0x0060452301000484
452
453/************************************************************************/
Full OpenSPARC design & verification tarball including full HDL.