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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_rx_INT.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_rx_INT.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40/* **************************************MAQ********************************************* */
41#define FZC_PIO_BASE_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_PIO_BASE_ADDRESS)
42#define SMX_CFIG_DAT_Data 0xc01001ff
43#define SMX_CFIG_DAT_Addr mpeval(FZC_PIO_ADDRESS_RANGE+0x00040)
44#define SYS_ERR_MASK mpeval(FZC_PIO_ADDRESS_RANGE + 0x00090)
45#define SYS_ERR_MASK_Data 0x0 /* Enable all Errors*/
46#define SYS_ERR_STAT mpeval(FZC_PIO_ADDRESS_RANGE+0x00098)
47#define TimeOut_count 0x40
48#define PIO_IMASK0_BASE_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + PIO_IMASK0_BASE_ADDRESS)
49#define PIO_LDSV_BASE_ADDRESS 0x800000
50#define PIO_LDSV_BASE_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + PIO_LDSV_BASE_ADDRESS)
51#define NIU_SID mpeval(FZC_PIO_BASE_ADDRESS_RANGE + 0x10200)
52#define RX_DMA_CK_DIV mpeval(FZC_DMC_ADDRESS_RANGE + 0x00000)
53#define RX_DMA_CK_DIV_CNT 0xff /* System Clock divider granularity */
54#define RCRCFIG_B mpeval(DMC_ADDRESS_RANGE+0x00048)
55#define RCRCFIG_B_ENTOUT_TIMEOUT 0x8002 /* [5:0] = 2 */
56#define RCRCFIG_B_TIMEOUT_MASK 0xfffffffffffffffc
57#define RX_DMA_ENT_MSK mpeval(DMC_ADDRESS_RANGE + 0x00068)
58#define RX_DMA_ENT_MSK_STEP 0x200
59#define RX_DMA_ENT_MSK_Data 0x0 /* Enable all Errors */
60#define RDMC_PRE_PAR_ERR mpeval(FZC_DMC_ADDRESS_RANGE + 0x00078)
61#define RX_DMA_CTL_STAT_MEX 0x800000000000
62
63/* **************************************MAQ********************************************* */
64
65
66
67/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
68#define MAIN_PAGE_HV_ALSO
69/* **************************************MAQ********************************************* */
70#define H_HT0_Interrupt_0x60
71#define My_HT0_Interrupt_0x60 \
72 call FC_NIU_Timeout_Trap_Start; \
73 nop; \
74 retry; \
75 nop;
76/* **************************************MAQ********************************************* */
77
78
79#include "hboot.s"
80#include "niu_defines.h"
81#include "ncu_defines.h"
82#include "niu_macros.h"
83
84/************************************************************************
85 Test case code start
86 ************************************************************************/
87.text
88.global main
89.global My_Corrected_ECC_error_trap
90.global My_Recoverable_Sw_error_trap
91
92main:
93 ta T_CHANGE_HPRIV
94 nop
95
96!#include "niu_init.h"
97!
98! Thread 0 Start
99!
100!
101!thread_0:
102 nop
103
104 /************************************
105 RAS
106 *************************************/
107clear_esr_first:
108 setx SOC_ESR_REG, %l7, %i0
109 stx %g0, [%i0]
110
111inj_err1:
112 nop !$EV trig_pc_d(0,@VA(.MAIN.inj_err1)) ->IosErrInj(ERR_TYPE, ERR_TAG, ERR_ADDR)
113
114
115L2_err_enable:
116 set 0x3, %l1
117 mov 0xaa, %g2
118 sllx %g2, 32, %g2
119 stx %l1, [%g2]
120 stx %l1, [%g2 + 0x40]
121 stx %l1, [%g2 + 0x80]
122 stx %l1, [%g2 + 0xc0]
123 stx %l1, [%g2 + 0x100]
124 stx %l1, [%g2 + 0x140]
125 stx %l1, [%g2 + 0x180]
126 stx %l1, [%g2 + 0x1c0]
127
128 /*************************************/
129
130
131
132/************************************************************************
133 First call the Vera, so that values are updated in Memory and
134 then read those values from assembly and program the registers
135 ************************************************************************/
136P_NIU_RxInitDma:
137 nop !$EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxInitDma)) -> NIU_InitRxDma(RXDMA_CHNL, RX_DESC_RING_LENGTH, RX_COMPL_RING_LEN, RBR_CONFIG_B_DATA, RX_INITIAL_KICK, NIU_Xlate_On)
138
139 setx 0x5, %g1, %g4 ! Delay for Vera to complete
140delay_loop_Rx:
141 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
142 nop
143 nop
144 nop
145 nop
146 dec %g4
147 brnz %g4, delay_loop_Rx
148 nop
149
150 nop
151 setx RXDMA_CHNL, %g1, %o0
152 setx RX_DESC_RING_LENGTH, %g1, %o1
153 setx RX_COMPL_RING_LEN, %g1, %o2
154 setx RBR_CONFIG_B_DATA, %g1, %o3
155 setx RX_INITIAL_KICK, %g1, %o4
156 call NiuInitRxDma
157 nop
158
159/* **************************************MAQ********************************************* */
160P_NIU_SMX_CFIG_DAT:
161 setx SMX_CFIG_DAT_Addr, %g1, %g2
162 setx SMX_CFIG_DAT_Data, %g1, %g3
163 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
164 nop
165
166P_NIU_SYS_ERR_MASK:
167 setx SYS_ERR_MASK, %g1, %g2
168 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
169 nop
170 setx SYS_ERR_MASK_Data, %g1, %g3
171 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
172 nop
173
174P_NIU_LDG_NUM:
175 setx LDG_NUM, %l1, %l2
176 mov RXDMA_CHNL, %l3
177 mulx %l3, LDG_NUM_STEP, %l4
178 add %l2, %l4, %g2
179 stxa %l3, [%g2]ASI_PRIMARY_LITTLE
180 nop
181
182P_NIU_LD_IM0:
183 setx LD_IM0, %l1, %l2
184 setx LD_IM0_STEP, %l1, %l3
185 mov RXDMA_CHNL, %l4
186 mulx %l3, %l4, %l4
187 add %l2, %l4, %g2
188 stxa %g0, [%g2]ASI_PRIMARY_LITTLE ! unmask flag0 and flag1 for DMA0
189 nop
190P_NIU_LDGITMRES:
191 setx LDGITMRES, %l1, %g2
192 setx 0xff, %l1, %g3 !Res[19:0] = 0xff
193 stxa %g3, [%g2]ASI_PRIMARY_LITTLE ! unmask flag0 and flag1 for DMA0
194 nop
195P_NIU_LDGIMGN:
196 setx LDGIMGN, %l1, %l2
197 setx LDGIMGN_STEP, %l1, %l3
198 mov RXDMA_CHNL, %l4
199 mulx %l3, %l4, %l4
200 add %l2, %l4, %g2
201 setx 0x8000000f, %l1, %g3 !{arm[31] = 1, timer[5:0] = f}
202 stxa %g3, [%g2]ASI_PRIMARY_LITTLE ! unmask flag0 and flag1 for DMA0
203 nop
204P_NIU_SID:
205 setx NIU_SID, %l1, %l2
206 mov RXDMA_CHNL, %l3
207 mulx %l3, SID_STEP, %l4
208 add %l2, %l4, %g2
209 add %l3, 64, %l3 ! Setting Bit-6 = 1 always
210 stxa %l3, [%g2]ASI_PRIMARY_LITTLE
211 nop
212P_NIU_RX_DMA_CK_DIV:
213 setx RX_DMA_CK_DIV, %l1, %l2
214 setx RX_DMA_CK_DIV_CNT, %l1, %l3
215 stxa %l3, [%l2]ASI_PRIMARY_LITTLE
216 nop
217P_NIU_RCRCFIG_B:
218 setx RCRCFIG_B, %l1, %l2
219 setx RCRCFIG_B_ENTOUT_TIMEOUT, %l1, %l3
220 setx RCRCFIG_B_TIMEOUT_MASK, %l1, %l5
221 ldxa [%l2]ASI_PRIMARY_LITTLE, %l4
222 and %l4, %l5, %l4
223 or %l4, %l3, %l3
224 stxa %l3, [%l2]ASI_PRIMARY_LITTLE
225 nop
226P_RX_DMA_ENT_MSK:
227 setx RX_DMA_ENT_MSK, %l1, %l2
228 setx RX_DMA_ENT_MSK_Data, %l1, %l3
229 mov RXDMA_CHNL, %l5
230 setx RX_DMA_ENT_MSK_STEP, %l1, %l4
231 mulx %l5, %l4, %l4
232 add %l2, %l4, %l2
233 stxa %l3, [%l2]ASI_PRIMARY_LITTLE
234 nop
235P_NIU_RX_DMA_CTL_STAT_MEX:
236 setx RX_DMA_CTL_STAT, %l1, %l2
237 setx RX_DMA_CTL_STAT_STEP, %l1, %l3
238 mov RXDMA_CHNL, %l4
239 mulx %l3, %l4, %l4
240 add %l2, %l4, %l2
241 setx RX_DMA_CTL_STAT_MEX, %l1, %l3
242 stxa %l3, [%l2]ASI_PRIMARY_LITTLE
243 nop
244
245
246Clear_All_Ints:
247 rdpr %pstate, %g7
248 xor %g7, 0x2, %g7 ! Reset interrupt enable
249 wrpr %g7, %pstate
250
251P_NCU_INT_MAN:
252 setx INT_MAN, %l1, %l2
253 mov mpeval(64 + RXDMA_CHNL), %l3
254 mulx %l3, 8, %l4
255 add %l2, %l4, %g2
256 mov RXDMA_CHNL, %g3 !CPU[13:8] = 0 and Vector[5:0] = 0x20
257 stx %g3, [%g2]
258 nop
259
260HTrap_Int_En:
261 rdpr %pstate, %g7
262 or %g7, 0x2, %g7 ! Set interrupt enable
263 wrpr %g7, %pstate
264/* **************************************MAQ********************************************* */
265
266P_NIU_RxPkt_Conf:
267 nop !$EV trig_pc_d(1, @VA(.MAIN.P_NIU_RxPkt_Conf)) -> NIU_RxPktConf(RXMAC_PKTCNT, MAC_ID)
268 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for Delay
269 nop
270
271
272P_NIU_Rx_GenPkt:
273 setx RXMAC_PKTCNT, %g1, %g6 ! Packet count
274 nop
275Rx_pktcnt_loop:
276 nop !$EV trig_pc_d(1, @VA(.MAIN.Rx_pktcnt_loop)) -> NIU_RxGenPkt(MAC_ID, RXDMA_CHNL, 1, MAC_PKT_LEN, 0x0, RX_NIU_MULTI_DMA, 1)
277 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! just for delay
278 nop
279 dec %g6
280 brnz %g6, Rx_pktcnt_loop
281 nop
282
283 setx loop_count, %g1, %g4
284delay_loop:
285 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
286 nop
287 nop
288 nop
289 nop
290 dec %g4
291 brnz %g4, delay_loop
292 nop
293
294
295 /************************************
296 RAS
297 *************************************/
298esr:
299 setx SOC_ESR_REG, %g7, %g5
300 setx 0x100, %g7, %g6
301
302 setx 0x8000000000000000, %g7, %g1 !valid bit
303 set 0x1, %g2
304 sllx %g2, ERR_FIELD, %g3
305 or %g3, %g1, %g2
306esr_loop:
307 dec %g6
308 cmp %g6, %g0
309 be %xcc, test_failed
310 nop
311
312 ldx [%g5], %g3
313
314 cmp %g3, %g2
315 be %xcc, eie_reg_ones
316 nop
317
318 ba esr_loop
319 nop
320
321eie_reg_ones:
322 setx SOC_EIE_REG, %g3, %g2
323 setx 0xffffffffffffffff, %g3, %g1
324 stx %g1, [%g2]
325 membar 0x40
326
327 set 0x1, %g1 ! 1 traps from rdd; 1 trap from WRI
328 setx 0x100, %g7, %g6
329err_trap_loop:
330 cmp %g6, %g0
331 be %xcc, test_failed
332 nop
333
334 cmp %g1, %i7
335 be %xcc, check_tt
336 nop
337
338 ba err_trap_loop
339 nop
340
341check_tt:
342 setx EXECUTED, %l1, %l0
343 cmp %o6, %l0
344 bne test_failed
345 nop
346
347/* **************************************MAQ********************************************* */
348 setx TimeOut_count, %l1, %g4
349 setx TimeOut_Semaphore, %l1, %g5
350 setx SYS_ERR_STAT, %l1, %l6
351TimeOut_Sem_loop:
352 ld [%g5], %g7
353 brnz %g7, test_passed
354 nop
355 ldxa [%l6]ASI_PRIMARY_LITTLE, %l1 ! Read Error State Reg
356 nop
357 dec %g4
358 brnz %g4, TimeOut_Sem_loop
359 nop
360 ba test_failed
361 nop
362/* **************************************MAQ********************************************* */
363
364
365test_passed:
366 nop
367 EXIT_GOOD
368
369!.global test_failed
370test_failed:
371 EXIT_BAD
372
373/************************************************************************
374 MAQ Trap Handler for NIU interrupts
375 ************************************************************************/
376.global FC_NIU_Timeout_Trap_Start
377FC_NIU_Timeout_Trap_Start:
378P_CORE_ASI_INTR_RECEIVE:
379 ldxa [%g0]ASI_INTR_RECEIVE, %g6 ! Read to see if bit-32 is set for Tx DMA0
380 nop
381P_CORE_ASI_INTR_R:
382 ldxa [%g0]ASI_INTR_R, %g6 ! clear the High priority Interrupt.
383 nop
384
385P_NIU_SYS_ERR_STAT:
386 setx SYS_ERR_STAT, %g1, %l6
387 ldxa [%l6]ASI_PRIMARY_LITTLE, %l7
388 nop
389P_NIU_RX_DMA_CTL_STAT:
390 setx RX_DMA_CTL_STAT, %l1, %l2
391 setx RX_DMA_CTL_STAT_STEP, %l1, %l3
392 mov RXDMA_CHNL, %l4
393 mulx %l3, %l4, %l4
394 add %l2, %l4, %l2
395 ldxa [%l2]ASI_PRIMARY_LITTLE, %g5
396 nop
397P_NIU_RDMC_PRE_PAR_ERR:
398 setx RDMC_PRE_PAR_ERR, %l1, %l2
399 ldxa [%l2]ASI_PRIMARY_LITTLE, %g5
400 nop
401
402
403P_NIU_LDSV0:
404 setx LDSV0, %l1, %l2
405 setx LDSV0_STEP, %l1, %l3
406 mov RXDMA_CHNL, %l4
407 mulx %l3, %l4, %l4
408 add %l2, %l4, %g2
409 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! read Logical Device State Vector 0(Tx DMA0 - Flag0)
410 nop
411P_NIU_LDSV1:
412 setx LDSV1, %l1, %l2
413 setx LDSV1_STEP, %l1, %l3
414 mov RXDMA_CHNL, %l4
415 mulx %l3, %l4, %l4
416 add %l2, %l4, %g2
417 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! read Logical Device State Vector 1(Tx DMA0 - Flag1)
418 nop
419
420 setx TimeOut_Semaphore, %l1, %l2
421 mov 0x1, %l3
422 st %l3, [%l2]
423 membar #Sync
424 nop
425 jmpl %o7+0x8, %g0
426 nop
427
428FC_NIU_Timeout_Trap_End:
429
430
431/************************************************************************
432 RAS
433 Trap Handlers
434 ************************************************************************/
435My_Recoverable_Sw_error_trap:
436 ! Signal trap taken
437 setx EXECUTED, %l0, %o6
438 ! save trap type value
439 rdpr %tt, %o7
440
441 inc %i7
442
443check_desr_tt40:
444 ldxa [%g0]0x4c, %g2
445 nop
446 setx 0xb300000000000000, %l0, %g3
447 subcc %g2, %g3, %g4
448 brnz %g4, test_failed
449 nop
450
451check_per_tt40:
452 setx SOC_PER_REG, %l7, %i0
453 ldx [%i0], %i1
454 setx 0x8000000000000000, %l7, %o3 !valid bit
455 set 0x1, %i2
456 sllx %i2, ERR_FIELD, %i3
457 or %i3, %o3, %i4
458 sub %i1, %i4, %i5
459 brnz %i5, test_failed
460 nop
461
462clear_per_tt40:
463 setx SOC_PER_REG, %l7, %i0
464 stx %g0, [%i0]
465 nop
466 done
467 nop
468
469
470
471My_Corrected_ECC_error_trap:
472 ! Signal trap taken
473 setx EXECUTED, %l0, %o6
474 ! save trap type value
475 rdpr %tt, %o7
476
477 inc %i7
478
479check_desr_tt63:
480 ldxa [%g0]0x4c, %g2
481 nop
482 setx 0x8b00000000000000, %l0, %g3
483 subcc %g2, %g3, %g4
484 brnz %g4, test_failed
485
486check_per_tt63:
487 setx SOC_PER_REG, %l7, %i0
488 ldx [%i0], %i1
489 setx 0x8000000000000000, %l7, %o3 !valid bit
490 set 0x1, %i2
491 sllx %i2, ERR_FIELD, %i3
492 or %i3, %o3, %i4
493 sub %i1, %i4, %i5
494 brnz %i5, test_failed
495 nop
496
497clear_per_tt63:
498 setx SOC_PER_REG, %l7, %i0
499 stx %g0, [%i0]
500 nop
501 retry
502 nop
503
504/************************************************************************
505 Test case data start
506 ************************************************************************/
507
508.align 1024
509.data
510TimeOut_Semaphore:
511 .word 0x0
512 .word 0x0
513 .word 0x0
514 .word 0x0
515
516
517/************************************************************************
518 Test case data start
519 ************************************************************************/
520/* These initialization is temporary, as there looks some bug in mempli */
521!
522!SECTION SetRngConfig_init data_va=0x100000000
523!attr_data {
524! Name = SetRngConfig_init,
525! hypervisor,
526! compressimage
527! }
528!.data
529!SetRngConfig_init:
530! .xword 0x0060452301000484
531/************************************************************************/
532
533SECTION SetRxLogMask1_init data_va=0x200000100
534attr_data {
535 Name = SetRxLogMask1_init,
536 hypervisor,
537 compressimage
538 }
539.data
540SetRxLogMask1_init:
541 .xword 0x0060452301000484
542/************************************************************************/
543
544SECTION SetRxLogVal1_init data_va=0x200000200
545attr_data {
546 Name = SetRxLogVal1_init,
547 hypervisor,
548 compressimage
549 }
550.data
551SetRxLogVal1_init:
552 .xword 0x0060452301000484
553/************************************************************************/
554
555SECTION SetRxLogRelo1_init data_va=0x200000300
556attr_data {
557 Name = SetRxLogRelo1_init,
558 hypervisor,
559 compressimage
560 }
561.data
562SetRxLogRelo1_init:
563 .xword 0x0060452301000484
564/************************************************************************/
565
566SECTION SetRxLogPgVld_init data_va=0x200000400
567attr_data {
568 Name = SetRxLogPgVld_init,
569 hypervisor,
570 compressimage
571 }
572.data
573SetRxLogPgVld_init:
574 .xword 0x0060452301000484
575/************************************************************************/
576SECTION SetRbrConfig_A_init data_va=0x200000500
577attr_data {
578 Name = SetRbrConfig_A_init,
579 hypervisor,
580 compressimage
581 }
582.data
583SetRbrConfig_A_init:
584 .xword 0x0060452301000484
585/************************************************************************/
586SECTION SetRbrConfig_B_init data_va=0x200000600
587attr_data {
588 Name = SetRbrConfig_B_init,
589 hypervisor,
590 compressimage
591 }
592.data
593SetRbrConfig_B_init:
594 .xword 0x0060452301000484
595/************************************************************************/
596SECTION SetRcrConfig_A_init data_va=0x200000700
597attr_data {
598 Name = SetRcrConfig_A_init,
599 hypervisor,
600 compressimage
601 }
602.data
603SetRcrConfig_A_init:
604 .xword 0x0060452301000484
605/************************************************************************/
606SECTION SetRxDmaCfig_1_0_init data_va=0x200000800
607attr_data {
608 Name = SetRxDmaCfig_1_0_init,
609 hypervisor,
610 compressimage
611 }
612.data
613SetRxDmaCfig_1_0_init:
614 .xword 0x0060452301000484
615/************************************************************************/
616SECTION SetRxdmaCfig2Start_init data_va=0x200000900
617attr_data {
618 Name = SetRxdmaCfig2Start_init,
619 hypervisor,
620 compressimage
621 }
622.data
623SetRxdmaCfig2Start_init:
624 .xword 0x0060452301000484
625/************************************************************************/
626SECTION SetRxDmaCfig_1_1_init data_va=0x200000a00
627attr_data {
628 Name = SetRxDmaCfig_1_1_init,
629 hypervisor,
630 compressimage
631 }
632.data
633SetRxDmaCfig_1_1_init:
634 .xword 0x0060452301000484
635
636/************************************************************************/
637
638SECTION SetRxRingKick_init data_va=0x200000b00
639attr_data {
640 Name = SetRxRingKick_init,
641 hypervisor,
642 compressimage
643 }
644.data
645SetRxRingKick_init:
646 .xword 0x0060452301000484
647/************************************************************************/
648
649SECTION SetRxLogMask2_init data_va=0x200000c00
650attr_data {
651 Name = SetRxLogMask2_init,
652 hypervisor,
653 compressimage
654 }
655.data
656SetRxLogMask2_init:
657 .xword 0x0060452301000484
658/************************************************************************/
659
660SECTION SetRxLogVal2_init data_va=0x200000d00
661attr_data {
662 Name = SetRxLogVal2_init,
663 hypervisor,
664 compressimage
665 }
666.data
667SetRxLogVal2_init:
668 .xword 0x0060452301000484
669/************************************************************************/
670
671SECTION SetRxLogRelo2_init data_va=0x200000e00
672attr_data {
673 Name = SetRxLogRelo2_init,
674 hypervisor,
675 compressimage
676 }
677.data
678SetRxLogRelo2_init:
679 .xword 0x0060452301000484
680
681/************************************************************************/
Full OpenSPARC design & verification tarball including full HDL.