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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_tx_uev.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_tx_uev.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45#include "err_defines.h"
46#include "hboot.s"
47#include "niu_defines.h"
48
49
50/************************************************************************
51 Test case code start
52 ************************************************************************/
53.text
54.global main
55.global My_Corrected_ECC_error_trap
56.global My_Recoverable_Sw_error_trap
57
58main:
59 ta T_CHANGE_HPRIV
60 nop
61
62! #include "niu_init.h"
63!
64! Thread 0 Start
65!
66!
67! thread_0:
68
69Init_flow:
70 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)
71
72P_TxDMAActivate:
73 setx MAC_ID, %g1, %o0 ! 1st Parameter
74 setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
75 call SetTxDMAActive
76 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
77
78P_AddTxChannels :
79 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
80
81 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
82 nop
83
84P_SetTxMaxBurst :
85 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
86 setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
87 call SetTxMaxBurst
88 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
89
90 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
91 nop
92
93P_InitTxDma:
94 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
95 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
96 call InitTxDma
97 nop
98
99 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
100 nop
101
102
103 /************************************
104 RAS
105 *************************************/
106clear_esr_first:
107 setx SOC_ESR_REG, %l7, %i0
108 stx %g0, [%i0]
109
110
111inj_err1:
112 nop !$EV trig_pc_d(0,@VA(.MAIN.inj_err1)) ->IosErrInj(ERR_TYPE, 2800, 000345a800 )
113
114
115L2_err_enable:
116 set 0x3, %l1
117 mov 0xaa, %g2
118 sllx %g2, 32, %g2
119 stx %l1, [%g2]
120 stx %l1, [%g2 + 0x40]
121 stx %l1, [%g2 + 0x80]
122 stx %l1, [%g2 + 0xc0]
123 stx %l1, [%g2 + 0x100]
124 stx %l1, [%g2 + 0x140]
125 stx %l1, [%g2 + 0x180]
126 stx %l1, [%g2 + 0x1c0]
127
128 /*************************************/
129
130Gen_Packet:
131 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT, 0, 0)
132 nop
133
134 setx 0x5, %g1, %g4
135delay_loop_tmp:
136 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
137 nop
138 nop
139 nop
140 nop
141 dec %g4
142 brnz %g4, delay_loop_tmp
143 nop
144
145
146SetTxRingKick:
147 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
148 setx NIU_TxDmaNo, %g1, %o0
149 ldx [%g2], %g3
150 nop
151 mulx %o0, 0x200, %g5
152 setx TX_RING_KICK_Addr, %g1, %g2
153 add %g2, %g5, %g2
154 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
155 nop
156
157SetTxCs :
158 setx NIU_TxDmaNo, %g1, %o0
159 setx TX_CS_Data, %g1, %g3
160 mulx %o0, 0x200, %g5
161 setx TX_CS_Addr, %g1, %g2
162 add %g2, %g5, %g2
163 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
164 nop
165
166
167#ifdef JUMBO_FRAME_EN /* Extra Delay for Jumbo packets to go out */
168 setx loop_count, %g1, %g4
169delay_loop:
170 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
171 nop
172 nop
173 nop
174 nop
175 dec %g4
176 brnz %g4, delay_loop
177 nop
178#endif
179
180
181NIUTx_Pkt_Cnt_Chk:
182 setx MAC_ID, %g1, %o0
183
184#ifdef CE
185 setx 0x10, %g1, %o1
186#else
187 setx 0x9, %g1, %o1 ! one less
188#endif
189
190 call NiuTx_check_pkt_cnt
191 nop
192
193 setx loop_count, %g1, %g4
194delay_loop_end:
195 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
196 nop
197 nop
198 nop
199 nop
200 dec %g4
201 brnz %g4, delay_loop_end
202 nop
203
204 /************************************
205 RAS
206 *************************************/
207esr:
208 setx SOC_ESR_REG, %g7, %g5
209 setx 0x100, %g7, %g6
210
211 setx 0x8000000000000000, %g7, %g1 !valid bit
212 set 0x1, %g2
213 sllx %g2, ERR_FIELD, %g3
214 or %g3, %g1, %g2
215esr_loop:
216 dec %g6
217 cmp %g6, %g0
218 be %xcc, test_failed
219 nop
220
221 ldx [%g5], %g3
222
223 cmp %g3, %g2
224 be %xcc, eie_reg_ones
225 nop
226
227 ba esr_loop
228 nop
229
230eie_reg_ones:
231 setx SOC_EIE_REG, %g3, %g2
232 setx 0xffffffffffffffff, %g3, %g1
233 stx %g1, [%g2]
234 membar 0x40
235
236 set 0x1, %g1 ! 1 traps from rdd; 1 trap from WRI
237 setx 0x100, %g7, %g6
238err_trap_loop:
239 cmp %g6, %g0
240 be %xcc, test_failed
241 nop
242
243 cmp %g1, %i7
244 be %xcc, check_tt
245 nop
246
247 ba err_trap_loop
248 nop
249
250check_tt:
251 setx EXECUTED, %l1, %l0
252 cmp %o6, %l0
253 bne test_failed
254 nop
255
256#ifdef CE
257 mov 0x63, %l0
258#else
259 mov 0x40, %l0 ! TT=0x40
260#endif
261 cmp %o7, %l0
262 bne test_failed
263 nop
264 /*************************************/
265
266
267
268test_passed:
269
270#ifdef CE
271 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)
272#endif
273
274
275 EXIT_GOOD
276
277!.global test_failed
278!test_failed:
279! EXIT_BAD
280
281test_failed:
282 EXIT_BAD
283 nop
284/************************************************************************
285 RAS
286 Trap Handlers
287 ************************************************************************/
288My_Recoverable_Sw_error_trap:
289 ! Signal trap taken
290 setx EXECUTED, %l0, %o6
291 ! save trap type value
292 rdpr %tt, %o7
293
294 inc %i7
295
296check_desr_tt40:
297 ldxa [%g0]0x4c, %g2
298 nop
299 setx 0xb300000000000000, %l0, %g3
300 subcc %g2, %g3, %g4
301 brnz %g4, test_failed
302 nop
303
304check_per_tt40:
305 setx SOC_PER_REG, %l7, %i0
306 ldx [%i0], %i1
307 setx 0x8000000000000000, %l7, %o3 !valid bit
308 set 0x1, %i2
309 sllx %i2, ERR_FIELD, %i3
310 or %i3, %o3, %i4
311 sub %i1, %i4, %i5
312 brnz %i5, test_failed
313 nop
314
315clear_per_tt40:
316 setx SOC_PER_REG, %l7, %i0
317 stx %g0, [%i0]
318 nop
319 done
320 nop
321
322
323My_Corrected_ECC_error_trap:
324 ! Signal trap taken
325 setx EXECUTED, %l0, %o6
326 ! save trap type value
327 rdpr %tt, %o7
328
329 inc %i7
330
331check_desr_tt63:
332 ldxa [%g0]0x4c, %g2
333 nop
334 setx 0x8b00000000000000, %l0, %g3
335 subcc %g2, %g3, %g4
336 brnz %g4, test_failed
337
338check_per_tt63:
339 setx SOC_PER_REG, %l7, %i0
340 ldx [%i0], %i1
341 setx 0x8000000000000000, %l7, %o3 !valid bit
342 set 0x1, %i2
343 sllx %i2, ERR_FIELD, %i3
344 or %i3, %o3, %i4
345 sub %i1, %i4, %i5
346 brnz %i5, test_failed
347 nop
348
349clear_per_tt63:
350 setx SOC_PER_REG, %l7, %i0
351 stx %g0, [%i0]
352 nop
353 retry
354 nop
355
356
357/************************************************************************
358 Test case data start
359 ************************************************************************/
360/* These initialization is temporary, as there looks some bug in mempli */
361
362SECTION SetRngConfig_init data_va=0x100000000
363attr_data {
364 Name = SetRngConfig_init,
365 hypervisor,
366 compressimage
367 }
368.data
369SetRngConfig_init:
370 .xword 0x0060452301000484
371/************************************************************************/
372
373SECTION SetTxRingKick_init data_va=0x100000100
374attr_data {
375 Name = SetTxRingKick_init,
376 hypervisor,
377 compressimage
378 }
379.data
380SetTxRingKick_init:
381 .xword 0x0060452301000484
382/************************************************************************/
383
384SECTION SetTxLPMask1_init data_va=0x100000200
385attr_data {
386 Name = SetTxLPMask1_init,
387 hypervisor,
388 compressimage
389 }
390.data
391SetTxLPMask1_init:
392 .xword 0x0060452301000484
393/************************************************************************/
394
395SECTION SetTxLPValue1_init data_va=0x100000300
396attr_data {
397 Name = SetTxLPValue1_init,
398 hypervisor,
399 compressimage
400 }
401.data
402SetTxLPValue1_init:
403 .xword 0x0060452301000484
404/************************************************************************/
405
406SECTION SetTxLPRELOC1_init data_va=0x100000400
407attr_data {
408 Name = SetTxLPRELOC1_init,
409 hypervisor,
410 compressimage
411 }
412.data
413SetTxLPRELOC1_init:
414 .xword 0x0060452301000484
415/************************************************************************/
416SECTION SetTxLPMask2_init data_va=0x100000500
417attr_data {
418 Name = SetTxLPMask2_init,
419 hypervisor,
420 compressimage
421 }
422.data
423SetTxLPMask2_init:
424 .xword 0x0060452301000484
425/************************************************************************/
426SECTION SetTxLPValue2_init data_va=0x100000600
427attr_data {
428 Name = SetTxLPValue2_init,
429 hypervisor,
430 compressimage
431 }
432.data
433SetTxLPValue2_init:
434 .xword 0x0060452301000484
435
436/************************************************************************/
437SECTION SetTxLPRELOC2_init data_va=0x100000700
438attr_data {
439 Name = SetTxLPRELOC2_init,
440 hypervisor,
441 compressimage
442 }
443.data
444SetTxLPRELOC2_init:
445 .xword 0x0060452301000484
446
447/************************************************************************/
448SECTION SetTxLPValid_init data_va=0x100000800
449attr_data {
450 Name = SetTxLPValid_init,
451 hypervisor,
452 compressimage
453 }
454.data
455SetTxLPValid_init:
456 .xword 0x0060452301000484
457
458/************************************************************************/
459
Full OpenSPARC design & verification tarball including full HDL.