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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_tx_uev_INT.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_tx_uev_INT.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41/* **************************************MAQ********************************************* */
42#define FZC_PIO_BASE_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + FZC_PIO_BASE_ADDRESS)
43#define TX_ENT_MASK_NACK_PKT_RD 0xfffb
44#define NACK_PKT_RD_MASK 0x4
45#define SMX_CFIG_DAT_Data 0xc01003ff
46#define SMX_CFIG_DAT_Addr mpeval(FZC_PIO_ADDRESS_RANGE+0x00040)
47#define SYS_ERR_MASK mpeval(FZC_PIO_ADDRESS_RANGE + 0x00090)
48#define SYS_ERR_MASK_Data 0x0 /* Enable all Errors*/
49#define SYS_ERR_STAT mpeval(FZC_PIO_ADDRESS_RANGE+0x00098)
50#define TimeOut_count 0x30
51#define PIO_IMASK0_BASE_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + PIO_IMASK0_BASE_ADDRESS)
52#define PIO_LDSV_BASE_ADDRESS 0x800000
53#define PIO_LDSV_BASE_ADDRESS_RANGE mpeval(NEPTUNE_BASE_ADDRESS + PIO_LDSV_BASE_ADDRESS)
54#define NIU_SID mpeval(FZC_PIO_BASE_ADDRESS_RANGE + 0x10200)
55#define TX_ENT_MSK_STEP 0x200
56/* **************************************MAQ********************************************* */
57
58/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
59#define MAIN_PAGE_HV_ALSO
60
61/* **************************************MAQ********************************************* */
62#define H_HT0_Interrupt_0x60
63#define My_HT0_Interrupt_0x60 \
64 call FC_NIU_Timeout_Trap_Start; \
65 nop; \
66 retry; \
67 nop;
68/* **************************************MAQ********************************************* */
69
70#include "err_defines.h"
71#include "hboot.s"
72#include "niu_defines.h"
73#include "ncu_defines.h"
74#include "niu_macros.h"
75
76
77/************************************************************************
78 Test case code start
79 ************************************************************************/
80.text
81.global main
82.global My_Corrected_ECC_error_trap
83.global My_Recoverable_Sw_error_trap
84
85main:
86 ta T_CHANGE_HPRIV
87 nop
88
89! #include "niu_init.h"
90!
91! Thread 0 Start
92!
93!
94! thread_0:
95
96Init_flow:
97 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)
98
99P_TxDMAActivate:
100 setx MAC_ID, %g1, %o0 ! 1st Parameter
101 setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
102 call SetTxDMAActive
103 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
104
105P_AddTxChannels :
106 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
107
108 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
109 nop
110
111P_SetTxMaxBurst :
112 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
113 setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
114 call SetTxMaxBurst
115 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
116
117 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
118 nop
119
120P_InitTxDma:
121 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
122 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
123 call InitTxDma
124 nop
125
126 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
127 nop
128
129/* **************************************MAQ********************************************* */
130P_NIU_Tx_Ent_Mask:
131 setx TX_ENT_MSK, %g1, %l1
132 setx NIU_TxDmaNo, %g1, %l2
133 mulx %l2, TX_ENT_MSK_STEP, %l3
134 add %l3, %l1, %l3
135 setx TX_ENT_MASK_NACK_PKT_RD, %g1, %l4
136 stxa %l4, [%l3]ASI_PRIMARY_LITTLE
137 nop
138
139P_NIU_SMX_CFIG_DAT:
140 setx SMX_CFIG_DAT_Addr, %g1, %g2
141 setx SMX_CFIG_DAT_Data, %g1, %g3
142 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
143 nop
144
145P_NIU_SYS_ERR_MASK:
146 setx SYS_ERR_MASK, %g1, %g2
147 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
148 nop
149 setx SYS_ERR_MASK_Data, %g1, %g3
150 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
151 nop
152
153P_NIU_LDG_NUM:
154 setx LDG_NUM, %l1, %l2
155 mov mpeval(32 + NIU_TxDmaNo), %l3 !32 for Tx DMA0
156 mulx %l3, LDG_NUM_STEP, %l4
157 add %l2, %l4, %g2
158 stxa %l3, [%g2]ASI_PRIMARY_LITTLE
159 nop
160
161P_NIU_LD_IM0:
162 setx LD_IM0, %l1, %l2
163 setx LD_IM0_STEP, %l1, %l3
164 mov mpeval(32 + NIU_TxDmaNo), %l4
165 mulx %l3, %l4, %l4
166 add %l2, %l4, %g2
167 stxa %g0, [%g2]ASI_PRIMARY_LITTLE ! unmask flag0 and flag1 for DMA0
168 nop
169P_NIU_LDGITMRES:
170 setx LDGITMRES, %l1, %g2
171 setx 0xff, %l1, %g3 !Res[19:0] = 0xff
172 stxa %g3, [%g2]ASI_PRIMARY_LITTLE ! unmask flag0 and flag1 for DMA0
173 nop
174P_NIU_LDGIMGN:
175 setx LDGIMGN, %l1, %l2
176 setx LDGIMGN_STEP, %l1, %l3
177 mov mpeval(32 + NIU_TxDmaNo), %l4
178 mulx %l3, %l4, %l4
179 add %l2, %l4, %g2
180 setx 0x8000000f, %l1, %g3 !{arm[31] = 1, timer[5:0] = f}
181 stxa %g3, [%g2]ASI_PRIMARY_LITTLE ! unmask flag0 and flag1 for DMA0
182 nop
183P_NIU_SID:
184 setx NIU_SID, %l1, %l2
185 mov mpeval(32 + NIU_TxDmaNo), %l3
186 mulx %l3, SID_STEP, %l4
187 add %l2, %l4, %g2
188 add %l3, 64, %l3 ! Setting Bit-6 = 1 always
189 stxa %l3, [%g2]ASI_PRIMARY_LITTLE
190 nop
191
192Clear_All_Ints:
193 rdpr %pstate, %g7
194 xor %g7, 0x2, %g7 ! Reset interrupt enable
195 wrpr %g7, %pstate
196
197P_NCU_INT_MAN:
198 setx INT_MAN, %l1, %l2
199 mov mpeval(64 + 32 + NIU_TxDmaNo), %l3
200 mulx %l3, 8, %l4
201 add %l2, %l4, %g2
202 mov mpeval(0x20 + NIU_TxDmaNo), %g3 !CPU[13:8] = 0 and Vector[5:0] = 0x20
203 stx %g3, [%g2]
204 nop
205
206HTrap_Int_En:
207 rdpr %pstate, %g7
208 or %g7, 0x2, %g7 ! Set interrupt enable
209 wrpr %g7, %pstate
210/* **************************************MAQ********************************************* */
211
212
213
214 /************************************
215 RAS
216 *************************************/
217clear_esr_first:
218 setx SOC_ESR_REG, %l7, %i0
219 stx %g0, [%i0]
220
221
222inj_err1:
223 nop !$EV trig_pc_d(0,@VA(.MAIN.inj_err1)) ->IosErrInj(ERR_TYPE, 2800, 000345a800 )
224
225
226L2_err_enable:
227 set 0x3, %l1
228 mov 0xaa, %g2
229 sllx %g2, 32, %g2
230 stx %l1, [%g2]
231 stx %l1, [%g2 + 0x40]
232 stx %l1, [%g2 + 0x80]
233 stx %l1, [%g2 + 0xc0]
234 stx %l1, [%g2 + 0x100]
235 stx %l1, [%g2 + 0x140]
236 stx %l1, [%g2 + 0x180]
237 stx %l1, [%g2 + 0x1c0]
238
239 /*************************************/
240
241Gen_Packet:
242 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT, 0, 0)
243 nop
244
245 setx 0x5, %g1, %g4
246delay_loop_tmp:
247 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
248 nop
249 nop
250 nop
251 nop
252 dec %g4
253 brnz %g4, delay_loop_tmp
254 nop
255
256
257SetTxRingKick:
258 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
259 setx NIU_TxDmaNo, %g1, %o0
260 ldx [%g2], %g3
261 nop
262 mulx %o0, 0x200, %g5
263 setx TX_RING_KICK_Addr, %g1, %g2
264 add %g2, %g5, %g2
265 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
266 nop
267
268SetTxCs :
269 setx NIU_TxDmaNo, %g1, %o0
270 setx TX_CS_Data, %g1, %g3
271 mulx %o0, 0x200, %g5
272 setx TX_CS_Addr, %g1, %g2
273 add %g2, %g5, %g2
274 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
275 nop
276
277
278#ifdef JUMBO_FRAME_EN /* Extra Delay for Jumbo packets to go out */
279 setx loop_count, %g1, %g4
280delay_loop:
281 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
282 nop
283 nop
284 nop
285 nop
286 dec %g4
287 brnz %g4, delay_loop
288 nop
289#endif
290
291/* **************************************MAQ*********************************************
292NACK_PKT_RD:
293 setx NIU_TxDmaNo, %g1, %l1
294 mulx %l1, 0x200, %g5
295 setx TX_CS_Addr, %g1, %g2
296 add %g2, %g5, %g2
297 mov 0x10, %l4
298 setx SYS_ERR_STAT, %g1, %l6
299Loop_NACK_PKT_RD:
300 brz %l4, test_failed
301 ldxa [%g2]ASI_PRIMARY_LITTLE, %g3
302 nop
303 ldxa [%l6]ASI_PRIMARY_LITTLE, %l7
304 nop
305 setx NACK_PKT_RD_MASK, %g1, %l2
306 and %g3, %l2, %l3
307 cmp %l2, %l3
308 bne Loop_NACK_PKT_RD
309 dec %l4
310 **************************************MAQ********************************************* */
311
312
313NIUTx_Pkt_Cnt_Chk:
314 setx MAC_ID, %g1, %o0
315
316#ifdef CE
317 setx 0x10, %g1, %o1
318#else
319 setx 0x9, %g1, %o1 ! one less
320#endif
321
322 call NiuTx_check_pkt_cnt
323 nop
324
325 setx loop_count, %g1, %g4
326delay_loop_end:
327 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
328 nop
329 nop
330 nop
331 nop
332 dec %g4
333 brnz %g4, delay_loop_end
334 nop
335
336 /************************************
337 RAS
338 *************************************/
339esr:
340 setx SOC_ESR_REG, %g7, %g5
341 setx 0x100, %g7, %g6
342
343 setx 0x8000000000000000, %g7, %g1 !valid bit
344 set 0x1, %g2
345 sllx %g2, ERR_FIELD, %g3
346 or %g3, %g1, %g2
347esr_loop:
348 dec %g6
349 cmp %g6, %g0
350 be %xcc, test_failed
351 nop
352
353 ldx [%g5], %g3
354
355 cmp %g3, %g2
356 be %xcc, eie_reg_ones
357 nop
358
359 ba esr_loop
360 nop
361
362eie_reg_ones:
363 setx SOC_EIE_REG, %g3, %g2
364 setx 0xffffffffffffffff, %g3, %g1
365 stx %g1, [%g2]
366 membar 0x40
367
368 set 0x1, %g1 ! 1 traps from rdd; 1 trap from WRI
369 setx 0x100, %g7, %g6
370err_trap_loop:
371 cmp %g6, %g0
372 be %xcc, test_failed
373 nop
374
375 cmp %g1, %i7
376 be %xcc, check_tt
377 nop
378
379 ba err_trap_loop
380 nop
381
382check_tt:
383 setx EXECUTED, %l1, %l0
384 cmp %o6, %l0
385 bne test_failed
386 nop
387
388#ifdef CE
389 mov 0x63, %l0
390#else
391 mov 0x40, %l0 ! TT=0x40
392#endif
393 cmp %o7, %l0
394 bne test_failed
395 nop
396 /*************************************/
397
398/* **************************************MAQ********************************************* */
399 setx TimeOut_count, %l1, %g4
400 setx TimeOut_Semaphore, %l1, %g5
401 setx SYS_ERR_STAT, %l1, %l6
402TimeOut_Sem_loop:
403 ld [%g5], %g7
404 brnz %g7, test_passed
405 nop
406 ldxa [%l6]ASI_PRIMARY_LITTLE, %l1 ! Read Error State Reg
407 nop
408 dec %g4
409 brnz %g4, TimeOut_Sem_loop
410 nop
411 ba test_failed
412 nop
413/* **************************************MAQ********************************************* */
414
415
416test_passed:
417
418#ifdef CE
419 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)
420#endif
421
422
423 EXIT_GOOD
424
425!.global test_failed
426!test_failed:
427! EXIT_BAD
428
429test_failed:
430 EXIT_BAD
431 nop
432/************************************************************************
433 MAQ Trap Handler for NIU interrupts
434 ************************************************************************/
435.global FC_NIU_Timeout_Trap_Start
436FC_NIU_Timeout_Trap_Start:
437P_CORE_ASI_INTR_RECEIVE:
438 ldxa [%g0]ASI_INTR_RECEIVE, %g6 ! Read to see if bit-32 is set for Tx DMA0
439 nop
440P_CORE_ASI_INTR_R:
441 ldxa [%g0]ASI_INTR_R, %g6 ! clear the High priority Interrupt.
442 nop
443P_NIU_TX_CS:
444 setx TX_CS, %l1, %l6
445 ldxa [%l6]ASI_PRIMARY_LITTLE, %l7
446 and %l7, 0x4, %l6
447 cmp %l6, 0x4
448 bne NACK_PKT_RD_FAILED
449 nop
450
451P_NIU_LDSV1:
452 setx LDSV1, %l1, %l2
453 setx LDSV1_STEP, %l1, %l3
454 mov mpeval(32 + NIU_TxDmaNo), %l4
455 mulx %l3, %l4, %l4
456 add %l2, %l4, %g2
457 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! read Logical Device State Vector 1(Tx DMA0 - Flag1)
458 mov 1, %l3
459 sllx %l3, mpeval(32 + NIU_TxDmaNo), %l4
460 cmp %g5, %l4
461 bne NIU_LDSV1_ERROR
462 nop
463
464 setx TimeOut_Semaphore, %l1, %l2
465 mov 0x1, %l3
466 st %l3, [%l2]
467 membar #Sync
468 nop
469 jmpl %o7+0x8, %g0
470 nop
471
472NIU_LDSV1_ERROR:
473 EXIT_BAD
474 nop
475
476NACK_PKT_RD_FAILED:
477 EXIT_BAD
478 nop
479FC_NIU_Timeout_Trap_End:
480/************************************************************************
481 RAS
482 Trap Handlers
483 ************************************************************************/
484My_Recoverable_Sw_error_trap:
485 ! Signal trap taken
486 setx EXECUTED, %l0, %o6
487 ! save trap type value
488 rdpr %tt, %o7
489
490 inc %i7
491
492check_desr_tt40:
493 ldxa [%g0]0x4c, %g2
494 nop
495 setx 0xb300000000000000, %l0, %g3
496 subcc %g2, %g3, %g4
497 brnz %g4, test_failed
498 nop
499
500check_per_tt40:
501 setx SOC_PER_REG, %l7, %i0
502 ldx [%i0], %i1
503 setx 0x8000000000000000, %l7, %o3 !valid bit
504 set 0x1, %i2
505 sllx %i2, ERR_FIELD, %i3
506 or %i3, %o3, %i4
507 sub %i1, %i4, %i5
508 brnz %i5, test_failed
509 nop
510
511clear_per_tt40:
512 setx SOC_PER_REG, %l7, %i0
513 stx %g0, [%i0]
514 nop
515 done
516 nop
517
518
519My_Corrected_ECC_error_trap:
520 ! Signal trap taken
521 setx EXECUTED, %l0, %o6
522 ! save trap type value
523 rdpr %tt, %o7
524
525 inc %i7
526
527check_desr_tt63:
528 ldxa [%g0]0x4c, %g2
529 nop
530 setx 0x8b00000000000000, %l0, %g3
531 subcc %g2, %g3, %g4
532 brnz %g4, test_failed
533
534check_per_tt63:
535 setx SOC_PER_REG, %l7, %i0
536 ldx [%i0], %i1
537 setx 0x8000000000000000, %l7, %o3 !valid bit
538 set 0x1, %i2
539 sllx %i2, ERR_FIELD, %i3
540 or %i3, %o3, %i4
541 sub %i1, %i4, %i5
542 brnz %i5, test_failed
543 nop
544
545clear_per_tt63:
546 setx SOC_PER_REG, %l7, %i0
547 stx %g0, [%i0]
548 nop
549 retry
550 nop
551
552/************************************************************************
553 Test case data start
554 ************************************************************************/
555
556.align 1024
557.data
558TimeOut_Semaphore:
559 .word 0x0
560 .word 0x0
561 .word 0x0
562 .word 0x0
563
564
565/************************************************************************
566 Test case data start
567 ************************************************************************/
568/* These initialization is temporary, as there looks some bug in mempli */
569
570SECTION SetRngConfig_init data_va=0x100000000
571attr_data {
572 Name = SetRngConfig_init,
573 hypervisor,
574 compressimage
575 }
576.data
577SetRngConfig_init:
578 .xword 0x0060452301000484
579/************************************************************************/
580
581SECTION SetTxRingKick_init data_va=0x100000100
582attr_data {
583 Name = SetTxRingKick_init,
584 hypervisor,
585 compressimage
586 }
587.data
588SetTxRingKick_init:
589 .xword 0x0060452301000484
590/************************************************************************/
591
592SECTION SetTxLPMask1_init data_va=0x100000200
593attr_data {
594 Name = SetTxLPMask1_init,
595 hypervisor,
596 compressimage
597 }
598.data
599SetTxLPMask1_init:
600 .xword 0x0060452301000484
601/************************************************************************/
602
603SECTION SetTxLPValue1_init data_va=0x100000300
604attr_data {
605 Name = SetTxLPValue1_init,
606 hypervisor,
607 compressimage
608 }
609.data
610SetTxLPValue1_init:
611 .xword 0x0060452301000484
612/************************************************************************/
613
614SECTION SetTxLPRELOC1_init data_va=0x100000400
615attr_data {
616 Name = SetTxLPRELOC1_init,
617 hypervisor,
618 compressimage
619 }
620.data
621SetTxLPRELOC1_init:
622 .xword 0x0060452301000484
623/************************************************************************/
624SECTION SetTxLPMask2_init data_va=0x100000500
625attr_data {
626 Name = SetTxLPMask2_init,
627 hypervisor,
628 compressimage
629 }
630.data
631SetTxLPMask2_init:
632 .xword 0x0060452301000484
633/************************************************************************/
634SECTION SetTxLPValue2_init data_va=0x100000600
635attr_data {
636 Name = SetTxLPValue2_init,
637 hypervisor,
638 compressimage
639 }
640.data
641SetTxLPValue2_init:
642 .xword 0x0060452301000484
643
644/************************************************************************/
645SECTION SetTxLPRELOC2_init data_va=0x100000700
646attr_data {
647 Name = SetTxLPRELOC2_init,
648 hypervisor,
649 compressimage
650 }
651.data
652SetTxLPRELOC2_init:
653 .xword 0x0060452301000484
654
655/************************************************************************/
656SECTION SetTxLPValid_init data_va=0x100000800
657attr_data {
658 Name = SetTxLPValid_init,
659 hypervisor,
660 compressimage
661 }
662.data
663SetTxLPValid_init:
664 .xword 0x0060452301000484
665
666/************************************************************************/
667
668
Full OpenSPARC design & verification tarball including full HDL.