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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_adv_tx_uev_banks.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_tx_uev_banks.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41
42/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
43#define MAIN_PAGE_HV_ALSO
44
45#include "err_defines.h"
46#include "hboot.s"
47#include "niu_defines.h"
48
49
50/************************************************************************
51 Test case code start
52 ************************************************************************/
53.text
54.global main
55.global My_Corrected_ECC_error_trap
56.global My_Recoverable_Sw_error_trap
57
58main:
59 ta T_CHANGE_HPRIV
60 nop
61
62! #include "niu_init.h"
63!
64! Thread 0 Start
65!
66!
67! thread_0:
68
69Init_flow:
70 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)
71
72P_TxDMAActivate:
73 setx MAC_ID, %g1, %o0 ! 1st Parameter
74 setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
75 call SetTxDMAActive
76 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
77
78P_AddTxChannels :
79 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
80
81 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
82 nop
83
84P_SetTxMaxBurst :
85 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
86 setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
87 call SetTxMaxBurst
88 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
89
90 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
91 nop
92
93P_InitTxDma:
94 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
95 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
96 call InitTxDma
97 nop
98
99 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
100 nop
101
102
103 /************************************
104 RAS
105 *************************************/
106clear_esr_first:
107 setx SOC_ESR_REG, %l7, %i0
108 stx %g0, [%i0]
109
110
111inj_err1:
112 nop !$EV trig_pc_d(0,@VA(.MAIN.inj_err1)) ->IosErrInj(ERR_TYPE, ERR_CTAG, ERR_ADDR )
113
114
115L2_err_enable:
116 set 0x3, %l1
117 mov 0xaa, %g2
118 sllx %g2, 32, %g2
119 stx %l1, [%g2]
120 stx %l1, [%g2 + 0x40]
121 stx %l1, [%g2 + 0x80]
122 stx %l1, [%g2 + 0xc0]
123 stx %l1, [%g2 + 0x100]
124 stx %l1, [%g2 + 0x140]
125 stx %l1, [%g2 + 0x180]
126 stx %l1, [%g2 + 0x1c0]
127
128 /*************************************/
129
130Gen_Packet:
131 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT)
132 nop
133
134 setx 0x5, %g1, %g4
135delay_loop_tmp:
136 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
137 nop
138 nop
139 nop
140 nop
141 dec %g4
142 brnz %g4, delay_loop_tmp
143 nop
144
145
146SetTxRingKick:
147 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE, 0, 0)
148 setx NIU_TxDmaNo, %g1, %o0
149 ldx [%g2], %g3
150 nop
151 mulx %o0, 0x200, %g5
152 setx TX_RING_KICK_Addr, %g1, %g2
153 add %g2, %g5, %g2
154 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
155 nop
156
157SetTxCs :
158 setx NIU_TxDmaNo, %g1, %o0
159 setx TX_CS_Data, %g1, %g3
160 mulx %o0, 0x200, %g5
161 setx TX_CS_Addr, %g1, %g2
162 add %g2, %g5, %g2
163 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
164 nop
165
166
167#ifdef JUMBO_FRAME_EN /* Extra Delay for Jumbo packets to go out */
168 setx loop_count, %g1, %g4
169delay_loop:
170 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
171 nop
172 nop
173 nop
174 nop
175 dec %g4
176 brnz %g4, delay_loop
177 nop
178#endif
179
180
181NIUTx_Pkt_Cnt_Chk:
182 setx MAC_ID, %g1, %o0
183
184#ifdef CE
185 setx 0x10, %g1, %o1
186#else
187 setx 0x9, %g1, %o1
188#endif
189
190
191
192 setx loop_count, %g1, %g4
193delay_loop_end:
194 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
195 nop
196 nop
197 nop
198 nop
199 dec %g4
200 brnz %g4, delay_loop_end
201 nop
202
203 /************************************
204 RAS
205 *************************************/
206esr:
207 setx SOC_ESR_REG, %g7, %g5
208 setx 0x100, %g7, %g6
209
210 setx 0x8000000000000000, %g7, %g1 !valid bit
211 set 0x1, %g2
212 sllx %g2, ERR_FIELD, %g3
213 or %g3, %g1, %g2
214esr_loop:
215 dec %g6
216 cmp %g6, %g0
217 be %xcc, test_failed
218 nop
219
220 ldx [%g5], %g3
221
222 cmp %g3, %g2
223 be %xcc, eie_reg_ones
224 nop
225
226 ba esr_loop
227 nop
228
229eie_reg_ones:
230 setx SOC_EIE_REG, %g3, %g2
231 setx 0xffffffffffffffff, %g3, %g1
232 stx %g1, [%g2]
233 membar 0x40
234
235 set 0x1, %g1 ! 1 traps from rdd; 1 trap from WRI
236 setx 0x100, %g7, %g6
237err_trap_loop:
238 cmp %g6, %g0
239 be %xcc, test_failed
240 nop
241
242 cmp %g1, %i7
243 be %xcc, check_tt
244 nop
245
246 ba err_trap_loop
247 nop
248
249check_tt:
250 setx EXECUTED, %l1, %l0
251 cmp %o6, %l0
252 bne test_failed
253 nop
254
255#ifdef CE
256 mov 0x63, %l0
257#else
258 mov 0x40, %l0 ! TT=0x40
259#endif
260 cmp %o7, %l0
261 bne test_failed
262 nop
263 /*************************************/
264
265
266
267test_passed:
268
269#ifdef CE
270 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)
271#endif
272
273
274 EXIT_GOOD
275
276!.global test_failed
277!test_failed:
278! EXIT_BAD
279
280test_failed:
281 EXIT_BAD
282 nop
283/************************************************************************
284 RAS
285 Trap Handlers
286 ************************************************************************/
287My_Recoverable_Sw_error_trap:
288 ! Signal trap taken
289 setx EXECUTED, %l0, %o6
290 ! save trap type value
291 rdpr %tt, %o7
292
293 inc %i7
294
295check_desr_tt40:
296 ldxa [%g0]0x4c, %g2
297 nop
298 setx 0xb300000000000000, %l0, %g3
299 subcc %g2, %g3, %g4
300 brnz %g4, test_failed
301 nop
302
303check_per_tt40:
304 setx SOC_PER_REG, %l7, %i0
305 ldx [%i0], %i1
306 setx 0x8000000000000000, %l7, %o3 !valid bit
307 set 0x1, %i2
308 sllx %i2, ERR_FIELD, %i3
309 or %i3, %o3, %i4
310 sub %i1, %i4, %i5
311 brnz %i5, test_failed
312 nop
313
314clear_per_tt40:
315 setx SOC_PER_REG, %l7, %i0
316 stx %g0, [%i0]
317 nop
318 done
319 nop
320
321
322My_Corrected_ECC_error_trap:
323 ! Signal trap taken
324 setx EXECUTED, %l0, %o6
325 ! save trap type value
326 rdpr %tt, %o7
327
328 inc %i7
329
330check_desr_tt63:
331 ldxa [%g0]0x4c, %g2
332 nop
333 setx 0x8b00000000000000, %l0, %g3
334 subcc %g2, %g3, %g4
335 brnz %g4, test_failed
336
337check_per_tt63:
338 setx SOC_PER_REG, %l7, %i0
339 ldx [%i0], %i1
340 setx 0x8000000000000000, %l7, %o3 !valid bit
341 set 0x1, %i2
342 sllx %i2, ERR_FIELD, %i3
343 or %i3, %o3, %i4
344 sub %i1, %i4, %i5
345 brnz %i5, test_failed
346 nop
347
348clear_per_tt63:
349 setx SOC_PER_REG, %l7, %i0
350 stx %g0, [%i0]
351 nop
352 retry
353 nop
354
355
356/************************************************************************
357 Test case data start
358 ************************************************************************/
359/* These initialization is temporary, as there looks some bug in mempli */
360
361SECTION SetRngConfig_init data_va=0x100000000
362attr_data {
363 Name = SetRngConfig_init,
364 hypervisor,
365 compressimage
366 }
367.data
368SetRngConfig_init:
369 .xword 0x0060452301000484
370/************************************************************************/
371
372SECTION SetTxRingKick_init data_va=0x100000100
373attr_data {
374 Name = SetTxRingKick_init,
375 hypervisor,
376 compressimage
377 }
378.data
379SetTxRingKick_init:
380 .xword 0x0060452301000484
381/************************************************************************/
382
383SECTION SetTxLPMask1_init data_va=0x100000200
384attr_data {
385 Name = SetTxLPMask1_init,
386 hypervisor,
387 compressimage
388 }
389.data
390SetTxLPMask1_init:
391 .xword 0x0060452301000484
392/************************************************************************/
393
394SECTION SetTxLPValue1_init data_va=0x100000300
395attr_data {
396 Name = SetTxLPValue1_init,
397 hypervisor,
398 compressimage
399 }
400.data
401SetTxLPValue1_init:
402 .xword 0x0060452301000484
403/************************************************************************/
404
405SECTION SetTxLPRELOC1_init data_va=0x100000400
406attr_data {
407 Name = SetTxLPRELOC1_init,
408 hypervisor,
409 compressimage
410 }
411.data
412SetTxLPRELOC1_init:
413 .xword 0x0060452301000484
414/************************************************************************/
415SECTION SetTxLPMask2_init data_va=0x100000500
416attr_data {
417 Name = SetTxLPMask2_init,
418 hypervisor,
419 compressimage
420 }
421.data
422SetTxLPMask2_init:
423 .xword 0x0060452301000484
424/************************************************************************/
425SECTION SetTxLPValue2_init data_va=0x100000600
426attr_data {
427 Name = SetTxLPValue2_init,
428 hypervisor,
429 compressimage
430 }
431.data
432SetTxLPValue2_init:
433 .xword 0x0060452301000484
434
435/************************************************************************/
436SECTION SetTxLPRELOC2_init data_va=0x100000700
437attr_data {
438 Name = SetTxLPRELOC2_init,
439 hypervisor,
440 compressimage
441 }
442.data
443SetTxLPRELOC2_init:
444 .xword 0x0060452301000484
445
446/************************************************************************/
447SECTION SetTxLPValid_init data_va=0x100000800
448attr_data {
449 Name = SetTxLPValid_init,
450 hypervisor,
451 compressimage
452 }
453.data
454SetTxLPValid_init:
455 .xword 0x0060452301000484
456
457/************************************************************************/
458
Full OpenSPARC design & verification tarball including full HDL.