projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_niu_tx_wrmreset_trans_ceen.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_niu_tx_wrmreset_trans_ceen.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define RESET_STAT_CHECK
39
40/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
41#define MAIN_PAGE_HV_ALSO
42
43#include "err_defines.h"
44#include "hboot.s"
45#include "niu_defines.h"
46
47#define DRAM_0_ERR_STAT_REG 0x8400000280
48#define DRAM_1_ERR_STAT_REG 0x8400001280
49#define DRAM_2_ERR_STAT_REG 0x8400002280
50#define DRAM_3_ERR_STAT_REG 0x8400003280
51
52#define L2_0_ERR_STAT_REG 0xAB00000000
53#define L2_1_ERR_STAT_REG 0xAB00000040
54#define L2_2_ERR_STAT_REG 0xAB00000080
55#define L2_3_ERR_STAT_REG 0xAB000000c0
56
57#define L2_4_ERR_STAT_REG 0xAB00000100
58#define L2_5_ERR_STAT_REG 0xAB00000140
59#define L2_6_ERR_STAT_REG 0xAB00000180
60#define L2_7_ERR_STAT_REG 0xAB000001c0
61
62
63/************************************************************************
64 Test case code start
65 ************************************************************************/
66.text
67.global main
68
69main:
70 ta T_CHANGE_HPRIV
71 nop
72
73L2_err_enable:
74 mov 0xaa, %g2
75 sllx %g2, 32, %g2
76 stx %g0, [%g2]
77 stx %g0, [%g2 + 0x40]
78 stx %g0, [%g2 + 0x80]
79 stx %g0, [%g2 + 0xc0]
80 stx %g0, [%g2 + 0x100]
81 stx %g0, [%g2 + 0x140]
82 stx %g0, [%g2 + 0x180]
83 stx %g0, [%g2 + 0x1c0]
84
85reset_decide:
86 setx test_entered, %g1, %g2
87 ldx [%g2], %g3
88 brnz %g3, After_Warm_Reset
89 nop
90
91fee_reg_ones:
92 set 0x1, %i1
93 sllx %i1, ERR_FIELD, %i2
94 setx SOC_FEE_REG, %l7, %g5
95 stx %i2, [%g5]
96 membar 0x40
97
98control_after_reset_flow:
99 ! First time thru, Store a non-zero value there
100 dec %g3
101 stx %g3, [%g2]
102
103 ba Init_flow
104 nop
105
106After_Warm_Reset:
107 nop
108
109check_esr_after_wrm:
110 setx SOC_ESR_REG, %l7, %g6
111 ldx [%i0], %g1
112
113 setx 0x8000000000000000, %g7, %g3 !valid bit
114 set 0x1, %l2
115 sllx %l2, ERR_FIELD, %g4
116 or %g3, %g4, %g5
117
118
119 cmp %g1, %g5
120 bne test_fail
121 nop
122
123clear_ejr_after_wrm:
124 setx SOC_EJR_REG, %l7, %g6
125 stx %g0, [%g6]
126
127clear_esr_after_wrm:
128 setx SOC_ESR_REG, %l7, %g6
129 stx %g0, [%g6]
130
131clear_fee_after_wrm:
132 setx SOC_FEE_REG, %l7, %g5
133 stx %g0, [%g6]
134 membar 0x40
135
136ba test_pass
137nop
138
139!Diag_before_Warm_Reset
140
141
142Init_flow:
143 nop
144 nop
145 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)
146
147P_TxDMAActivate:
148 setx MAC_ID, %g1, %o0 ! 1st Parameter
149 setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
150 call SetTxDMAActive
151 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
152
153P_AddTxChannels :
154 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
155
156 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
157 nop
158
159P_SetTxMaxBurst :
160 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
161 setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
162 call SetTxMaxBurst
163 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
164
165 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
166 nop
167
168P_InitTxDma:
169 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
170 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
171 call InitTxDma
172 nop
173
174 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
175 nop
176
177
178 /************************************
179 RAS
180 *************************************/
181clear_esr_first:
182 setx SOC_ESR_REG, %l7, %i0
183 stx %g0, [%i0]
184
185set_ejr:
186 set 0x1, %i1
187 sllx %i1, ERR_FIELD, %i2
188 setx SOC_EJR_REG, %l7, %i3
189 stx %i2, [%i3]
190 membar 0x40
191
192 /*************************************/
193
194Gen_Packet:
195 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT, 0, 0)
196 nop
197
198 setx 0x5, %g1, %g4
199delay_loop_tmp:
200 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
201 nop
202 nop
203 nop
204 nop
205 dec %g4
206 brnz %g4, delay_loop_tmp
207 nop
208
209
210SetTxRingKick:
211 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
212 setx NIU_TxDmaNo, %g1, %o0
213 ldx [%g2], %g3
214 nop
215 mulx %o0, 0x200, %g5
216 setx TX_RING_KICK_Addr, %g1, %g2
217 add %g2, %g5, %g2
218 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
219 nop
220
221SetTxCs :
222 setx NIU_TxDmaNo, %g1, %o0
223 setx TX_CS_Data, %g1, %g3
224 mulx %o0, 0x200, %g5
225 setx TX_CS_Addr, %g1, %g2
226 add %g2, %g5, %g2
227 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
228 nop
229
230
231#ifdef JUMBO_FRAME_EN /* Extra Delay for Jumbo packets to go out */
232 setx loop_count, %g1, %g4
233delay_loop:
234 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
235 nop
236 nop
237 nop
238 nop
239 dec %g4
240 brnz %g4, delay_loop
241 nop
242#endif
243
244
245 setx 0x30, %g1, %g4
246delay_ras:
247 setx 0x2000000, %g1, %g2
248 ldx [%g2], %g3
249 nop
250 nop
251 dec %g4
252 brnz %g4, delay_ras
253 nop
254
255
256
257 /************************************
258 RAS
259 *************************************/
260read_esr_second:
261 setx SOC_ESR_REG, %l7, %i0
262 ldx [%i0], %g1
263
264 setx 0x8000000000000000, %g7, %g3 !valid bit
265 set 0x1, %g2
266 sllx %g2, ERR_FIELD, %g4
267 or %g3, %g4, %g5
268
269
270 cmp %g1, %g5
271 bne test_fail
272 nop
273 /*************************************/
274
275
276
277test_pass:
278/*
279#ifdef CE
280 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)
281#endif
282*/
283
284 EXIT_GOOD
285
286!.global test_failed
287!test_failed:
288! EXIT_BAD
289
290test_fail:
291 EXIT_BAD
292 nop
293/************************************************************************
294 RAS
295 Trap Handlers
296 ************************************************************************/
297
298 .align 64
299test_entered:
300 .xword 0
301
302/************************************************************************
303 Test case data start
304 ************************************************************************/
305/* These initialization is temporary, as there looks some bug in mempli */
306
307SECTION SetRngConfig_init data_va=0x100000000
308attr_data {
309 Name = SetRngConfig_init,
310 hypervisor,
311 compressimage
312 }
313.data
314SetRngConfig_init:
315 .xword 0x0060452301000484
316/************************************************************************/
317
318SECTION SetTxRingKick_init data_va=0x100000100
319attr_data {
320 Name = SetTxRingKick_init,
321 hypervisor,
322 compressimage
323 }
324.data
325SetTxRingKick_init:
326 .xword 0x0060452301000484
327/************************************************************************/
328
329SECTION SetTxLPMask1_init data_va=0x100000200
330attr_data {
331 Name = SetTxLPMask1_init,
332 hypervisor,
333 compressimage
334 }
335.data
336SetTxLPMask1_init:
337 .xword 0x0060452301000484
338/************************************************************************/
339
340SECTION SetTxLPValue1_init data_va=0x100000300
341attr_data {
342 Name = SetTxLPValue1_init,
343 hypervisor,
344 compressimage
345 }
346.data
347SetTxLPValue1_init:
348 .xword 0x0060452301000484
349/************************************************************************/
350
351SECTION SetTxLPRELOC1_init data_va=0x100000400
352attr_data {
353 Name = SetTxLPRELOC1_init,
354 hypervisor,
355 compressimage
356 }
357.data
358SetTxLPRELOC1_init:
359 .xword 0x0060452301000484
360/************************************************************************/
361SECTION SetTxLPMask2_init data_va=0x100000500
362attr_data {
363 Name = SetTxLPMask2_init,
364 hypervisor,
365 compressimage
366 }
367.data
368SetTxLPMask2_init:
369 .xword 0x0060452301000484
370/************************************************************************/
371SECTION SetTxLPValue2_init data_va=0x100000600
372attr_data {
373 Name = SetTxLPValue2_init,
374 hypervisor,
375 compressimage
376 }
377.data
378SetTxLPValue2_init:
379 .xword 0x0060452301000484
380
381/************************************************************************/
382SECTION SetTxLPRELOC2_init data_va=0x100000700
383attr_data {
384 Name = SetTxLPRELOC2_init,
385 hypervisor,
386 compressimage
387 }
388.data
389SetTxLPRELOC2_init:
390 .xword 0x0060452301000484
391
392/************************************************************************/
393SECTION SetTxLPValid_init data_va=0x100000800
394attr_data {
395 Name = SetTxLPValid_init,
396 hypervisor,
397 compressimage
398 }
399.data
400SetTxLPValid_init:
401 .xword 0x0060452301000484
402
403/************************************************************************/
404
Full OpenSPARC design & verification tarball including full HDL.