[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_pio_DMUSII_CMDP.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_pio_DMUSII_CMDP.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Sw_Recoverable_Error_0x40	 My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
#define MAIN_PAGE_HV_ALSO
#define SOC_EST_REG	0x9001041000

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"


#define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) | IO_ACCESS_PA)

#define MEM_LOC1 	0x42400000
#define SOC_SII_SYN_REG	 0x8000003030

/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global	 My_Recoverable_Sw_error_trap


main:
        ta T_CHANGE_HPRIV
        nop


get_th_id_o0:
        ta      T_RD_THID

        cmp     %o1, 0x0
        be      main_t0
        nop

        cmp     %o1, 0x1
        be      main_t1
        nop


        /**************************************
                THREAD 0
        **************************************/
main_t0:
	nop
        setx    MEM_LOC1, %g1, %g3
        st      %g0, [%g3]

clear_esr_first:
        setx    SOC_ESR_REG, %l7, %i0
        stx     %g0, [%i0]


inj_err1: nop
	!$EV trig_pc_d(0,@VA(.MAIN.inj_err1)) ->IosErrInj(DMUSII_CMDP, 8000, 000)


pio_addr:
        ! select an IO address in PCI address range and transmit the command to NCU
        setx IO_RD_ADDR, %g1, %g2

st_mem1:
        set     0x1, %g4
        st      %g4, [%g3]

pio:
        ! load byte - all byte offsets within an octlet
        ldub [%g2 + 1*8 + 0], %l0
	nop 				! ld hangs and not completes

	ba 	test_failed
	nop


        /**************************************
                THREAD 1
        **************************************/
main_t1:
        nop

read_mem_loc:
        setx    MEM_LOC1, %l7, %i3
	ldx	[%i3], %o0
	cmp	%o0, %g0
	be   	%xcc, read_mem_loc
	nop

delay:
	ld	[%i3+0x8], %o0
        ld     	[%i3+0x10], %o0
        ld     	[%i3+0x18], %o0
        ld     	[%i3+0x20], %o0
        ld      [%i3+0x28], %o0
        ld      [%i3+0x30], %o0
        ld      [%i3+0x40], %o0


        setx    0x8000000000000000, %g7, %g3    !valid bit
        set     0x1, %g2
        sllx    %g2, ERR_FIELD, %g4
        or      %g3, %g4, %g5

	set	0x100, %g1
read_esr:
	cmp	%g1, %g0
        be      %xcc, test_failed	! Timeout check
	nop	 

        setx    SOC_ESR_REG, %g7, %g3
        ldx     [%g3], %g6

	dec	%g1

        cmp     %g6, %g5
        bne      %xcc, read_esr 
        nop


est_reg:
        setx    SOC_EST_REG, %g3, %g2
        set     0x1, %g1
        stx     %g1, [%g2]
        membar  0x40


eie_reg_ones:
	setx	SOC_EIE_REG, %g3, %g2
        set	0x1, %i1
	sllx	%i1, ERR_FIELD, %g1
	stx	%g1, [%g2]
	membar	0x40

	setx	0x40, %g7, %g6
	 set	0x1, %g1			! 1 Trap
err_trap_loop:
	cmp	    %g6, %g0
	 be	%xcc, test_failed
        nop

	cmp	%g1, %i7
	 be	%xcc, check_tt
        nop

	ba	err_trap_loop
        nop

check_tt:
	mov	0x40, %l0
	cmp	%o7,  %l0
	 bne	%xcc, test_failed
        nop

        /********************************/
	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
	! Signal trap taken
	setx	EXECUTED, %l0, %o6
	! save trap type value
	rdpr	%tt, %o7

	inc	%i7

check_desr_tt40:
	ldxa  [%g0]0x4c, %g2
	nop
  	setx	0xb300000000000000, %l0, %g3
	subcc	%g2, %g3, %g4
	brnz	%g4, test_failed 
	nop

check_DSFSR_tt32:
	set	0x18, %g1
	ldxa	[%g1]0x58, %g2
/*
	nop
	set	0x4, %g3
	subcc	%g2, %g3, %g4
	brnz	%g4, test_failed
	nop
*/

check_per_tt40:
	setx	SOC_PER_REG, %l7, %g1
	ldx	[%g1], %g2
	setx	0x8000000000000000, %g7, %g1
	set	0x1, %g3
	sllx	%g3, ERR_FIELD, %g4
	or	%g1, %g4, %g3
	sub	%g2, %g3, %g5
	brnz	%g5, test_failed
	nop

check_synd:
	setx	SOC_SII_SYN_REG, %g7, %g1
	ldx	[%g1], %g2
	setx	0x8180000000000000, %g7, %g3		! PA=0x0; CTAG=0x8000; ETAG=0x1
	cmp	%g2, %g3
	bne	%xcc, test_failed
	nop

clear_per_tt40:
	setx	SOC_PER_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

clear_ejr_tt40:
	setx	SOC_EJR_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

clear_eie_tt40:
	setx	SOC_EIE_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

trap_done_tt40:
 	done
	nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=IO_RD_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
        .xword 0xdeadbeefdeadbeef

        .xword 0x1101010101010101
        .xword 0x0122010101010101
        .xword 0x0101330101010101
        .xword 0x0101014401010101
        .xword 0x0101010155010101
        .xword 0x0101010101660101
        .xword 0x0101010101017701
        .xword 0x0101010101010188

        .xword 0x1122010101010101
        .xword 0x0101334401010101
        .xword 0x0101010155660101
        .xword 0x0101010101017788

        .xword 0x1122334401010101
        .xword 0x0101010155667788

        .xword 0xdeadbeefdeadbeef

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_pio_DMUSII_CMDP.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	39
	40	#define ENABLE_PCIE_LINK_TRAINING
	41	#define MAIN_PAGE_HV_ALSO
	42	#define SOC_EST_REG 0x9001041000
	43
	44	#include "err_defines.h"
	45	#include "hboot.s"
	46	#include "peu_defines.h"
	47
	48
	49	#define IO_RD_ADDR mpeval((N2_PCIE_BASE_ADDR + (IOCFG_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff)) \| IO_ACCESS_PA)
	50
	51	#define MEM_LOC1 0x42400000
	52	#define SOC_SII_SYN_REG 0x8000003030
	53
	54	/************************************************************************
	55	Test case code start
	56	************************************************************************/
	57	.text
	58	.global main
	59	.global My_Recoverable_Sw_error_trap
	60
	61
	62	main:
	63	ta T_CHANGE_HPRIV
	64	nop
65
66
67	get_th_id_o0:
68	ta T_RD_THID
69
70	cmp %o1, 0x0
71	be main_t0
72	nop
73
74	cmp %o1, 0x1
75	be main_t1
76	nop
77
78
79	/**************************************
80	THREAD 0
81	**************************************/
82	main_t0:
83	nop
84	setx MEM_LOC1, %g1, %g3
85	st %g0, [%g3]
86
87	clear_esr_first:
88	setx SOC_ESR_REG, %l7, %i0
89	stx %g0, [%i0]
90
91
92	inj_err1: nop
93	!$EV trig_pc_d(0,@VA(.MAIN.inj_err1)) ->IosErrInj(DMUSII_CMDP, 8000, 000)
94
95
96	pio_addr:
97	! select an IO address in PCI address range and transmit the command to NCU
98	setx IO_RD_ADDR, %g1, %g2
99
100	st_mem1:
101	set 0x1, %g4
102	st %g4, [%g3]
103
104	pio:
105	! load byte - all byte offsets within an octlet
106	ldub [%g2 + 1*8 + 0], %l0
107	nop ! ld hangs and not completes
108
109	ba test_failed
110	nop
111
112
113
114	/**************************************
115	THREAD 1
116	**************************************/
117	main_t1:
118	nop
119
120	read_mem_loc:
121	setx MEM_LOC1, %l7, %i3
122	ldx [%i3], %o0
123	cmp %o0, %g0
124	be %xcc, read_mem_loc
125	nop
126
127	delay:
128	ld [%i3+0x8], %o0
129	ld [%i3+0x10], %o0
130	ld [%i3+0x18], %o0
131	ld [%i3+0x20], %o0
132	ld [%i3+0x28], %o0
133	ld [%i3+0x30], %o0
134	ld [%i3+0x40], %o0
135
136
137	setx 0x8000000000000000, %g7, %g3 !valid bit
138	set 0x1, %g2
139	sllx %g2, ERR_FIELD, %g4
140	or %g3, %g4, %g5
141
142	set 0x100, %g1
143	read_esr:
144	cmp %g1, %g0
145	be %xcc, test_failed ! Timeout check
146	nop
147
148	setx SOC_ESR_REG, %g7, %g3
149	ldx [%g3], %g6
150
151	dec %g1
152
153	cmp %g6, %g5
154	bne %xcc, read_esr
155	nop
156
157
158	est_reg:
159	setx SOC_EST_REG, %g3, %g2
160	set 0x1, %g1
161	stx %g1, [%g2]
162	membar 0x40
163
164
165	eie_reg_ones:
166	setx SOC_EIE_REG, %g3, %g2
167	set 0x1, %i1
168	sllx %i1, ERR_FIELD, %g1
169	stx %g1, [%g2]
170	membar 0x40
171
172	setx 0x40, %g7, %g6
173	set 0x1, %g1 ! 1 Trap
174	err_trap_loop:
175	cmp %g6, %g0
176	be %xcc, test_failed
177	nop
178
179	cmp %g1, %i7
180	be %xcc, check_tt
181	nop
182
183	ba err_trap_loop
184	nop
185
186	check_tt:
187	mov 0x40, %l0
188	cmp %o7, %l0
189	bne %xcc, test_failed
190	nop
191
192	/********************************/
193
194	test_passed:
195	EXIT_GOOD
196
197	test_failed:
198	EXIT_BAD
199
200
201
202	/************************************************************************
203	RAS
204	Trap Handlers
205	************************************************************************/
206	My_Recoverable_Sw_error_trap:
207	! Signal trap taken
208	setx EXECUTED, %l0, %o6
209	! save trap type value
210	rdpr %tt, %o7
211
212	inc %i7
213
214	check_desr_tt40:
215	ldxa [%g0]0x4c, %g2
216	nop
217	setx 0xb300000000000000, %l0, %g3
218	subcc %g2, %g3, %g4
219	brnz %g4, test_failed
220	nop
221
222	check_DSFSR_tt32:
223	set 0x18, %g1
224	ldxa [%g1]0x58, %g2
225	/*
226	nop
227	set 0x4, %g3
228	subcc %g2, %g3, %g4
229	brnz %g4, test_failed
230	nop
231	*/
232
233	check_per_tt40:
234	setx SOC_PER_REG, %l7, %g1
235	ldx [%g1], %g2
236	setx 0x8000000000000000, %g7, %g1
237	set 0x1, %g3
238	sllx %g3, ERR_FIELD, %g4
239	or %g1, %g4, %g3
240	sub %g2, %g3, %g5
241	brnz %g5, test_failed
242	nop
243
244	check_synd:
245	setx SOC_SII_SYN_REG, %g7, %g1
246	ldx [%g1], %g2
247	setx 0x8180000000000000, %g7, %g3 ! PA=0x0; CTAG=0x8000; ETAG=0x1
248	cmp %g2, %g3
249	bne %xcc, test_failed
250	nop
251
252	clear_per_tt40:
253	setx SOC_PER_REG, %l7, %g1
254	stx %g0, [%g1]
255	nop
256
257	clear_ejr_tt40:
258	setx SOC_EJR_REG, %l7, %g1
259	stx %g0, [%g1]
260	nop
261
262	clear_eie_tt40:
263	setx SOC_EIE_REG, %l7, %g1
264	stx %g0, [%g1]
265	nop
266
267	trap_done_tt40:
268	done
269	nop
270
271
272	/************************************************************************
273	Test case data start
274	************************************************************************/
275
276	SECTION .DATA DATA_VA=IO_RD_ADDR
277	attr_data {
278	Name = .DATA,
279	hypervisor,
280	compressimage
281	}
282
283	.data
284	.xword 0xdeadbeefdeadbeef
285
286	.xword 0x1101010101010101
287	.xword 0x0122010101010101
288	.xword 0x0101330101010101
289	.xword 0x0101014401010101
290	.xword 0x0101010155010101
291	.xword 0x0101010101660101
292	.xword 0x0101010101017701
293	.xword 0x0101010101010188
294
295	.xword 0x1122010101010101
296	.xword 0x0101334401010101
297	.xword 0x0101010155660101
298	.xword 0x0101010101017788
299
300	.xword 0x1122334401010101
301	.xword 0x0101010155667788
302
303	.xword 0xdeadbeefdeadbeef
304
305	/************************************************************************/