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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / adv / n2_err_siu_niu_tx_wrmreset.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_siu_niu_tx_wrmreset.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
39#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
40
41#define RESET_STAT_CHECK
42
43/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
44#define MAIN_PAGE_HV_ALSO
45
46#include "err_defines.h"
47#include "hboot.s"
48#include "niu_defines.h"
49
50#define DRAM_0_ERR_STAT_REG 0x8400000280
51#define DRAM_1_ERR_STAT_REG 0x8400001280
52#define DRAM_2_ERR_STAT_REG 0x8400002280
53#define DRAM_3_ERR_STAT_REG 0x8400003280
54
55#define L2_0_ERR_STAT_REG 0xAB00000000
56#define L2_1_ERR_STAT_REG 0xAB00000040
57#define L2_2_ERR_STAT_REG 0xAB00000080
58#define L2_3_ERR_STAT_REG 0xAB000000c0
59
60#define L2_4_ERR_STAT_REG 0xAB00000100
61#define L2_5_ERR_STAT_REG 0xAB00000140
62#define L2_6_ERR_STAT_REG 0xAB00000180
63#define L2_7_ERR_STAT_REG 0xAB000001c0
64
65
66/************************************************************************
67 Test case code start
68 ************************************************************************/
69.text
70.global main
71.global My_Corrected_ECC_error_trap
72.global My_Recoverable_Sw_error_trap
73
74main:
75 ta T_CHANGE_HPRIV
76 nop
77
78 setx 0xc03ffffc00000000, %g7, %g1
79
80 setx L2_0_ERR_STAT_REG, %g7, %g2
81 stx %g1, [%g2]
82 setx L2_1_ERR_STAT_REG, %g7, %g2
83 stx %g1, [%g2]
84 setx L2_2_ERR_STAT_REG, %g7, %g2
85 stx %g1, [%g2]
86 setx L2_3_ERR_STAT_REG, %g7, %g2
87 stx %g1, [%g2]
88 setx L2_4_ERR_STAT_REG, %g7, %g2
89 stx %g1, [%g2]
90 setx L2_5_ERR_STAT_REG, %g7, %g2
91 stx %g1, [%g2]
92 setx L2_6_ERR_STAT_REG, %g7, %g2
93 stx %g1, [%g2]
94 setx L2_7_ERR_STAT_REG, %g7, %g2
95 stx %g1, [%g2]
96
97 setx 0xffc0000000000000, %g7, %g1
98
99 setx DRAM_0_ERR_STAT_REG, %g7, %g2
100 stx %g1, [%g2]
101 setx DRAM_1_ERR_STAT_REG, %g7, %g2
102 stx %g1, [%g2]
103 setx DRAM_2_ERR_STAT_REG, %g7, %g2
104 stx %g1, [%g2]
105 setx DRAM_3_ERR_STAT_REG, %g7, %g2
106 stx %g1, [%g2]
107
108reset_decide:
109 setx test_entered, %g1, %g2
110 ldx [%g2], %g3
111 brnz %g3, After_Warm_Reset
112 nop
113
114 ! First time thru, Store a non-zero value there
115 dec %g3
116 stx %g3, [%g2]
117
118
119Init_flow:
120 nop ! $EV trig_pc_d(1, @VA(.MAIN.Init_flow)) -> pktGenConfig(MAC_ID, FRAME_TYPE, FRAME_CLASS,TX_PKT_LEN)
121
122P_TxDMAActivate:
123 setx MAC_ID, %g1, %o0 ! 1st Parameter
124 setx SetTxDMAActive_list, %g1, %o1 ! 2st parameter
125 call SetTxDMAActive
126 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_TxDMAActivate)) -> NIU_TxDMAActivate (MAC_ID, TxDmaActive_list)
127
128P_AddTxChannels :
129 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_AddTxChannels)) -> NIU_AddTxChannels(MAC_ID, NIU_TxDmaNoUE)
130
131 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
132 nop
133
134P_SetTxMaxBurst :
135 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
136 setx SetTxMaxBurst_Data, %g1, %o1 ! 2nd parameter
137 call SetTxMaxBurst
138 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_SetTxMaxBurst)) -> NIU_SetTxMaxBurst (MAC_ID, NIU_TxDmaNoUE, TxMaxBurst_Data)
139
140 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
141 nop
142
143P_InitTxDma:
144 setx NIU_TxDmaNo, %g1, %o0 ! 1st parameter :
145 nop ! $EV trig_pc_d(1, @VA(.MAIN.P_InitTxDma)) -> NIU_InitTxDma (MAC_ID, NIU_TxDmaNoUE, NIU_Xlate_On)
146 call InitTxDma
147 nop
148
149 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5 ! Just for delay
150 nop
151
152
153 /************************************
154 RAS
155 *************************************/
156clear_esr_first:
157 setx SOC_ESR_REG, %l7, %i0
158 stx %g0, [%i0]
159
160set_ejr:
161 set 0x1, %i1
162 sllx %i1, ERR_FIELD, %i2
163 setx SOC_EJR_REG, %l7, %i3
164 stx %i2, [%i3]
165 membar 0x40
166
167fee_reg_ones:
168 setx SOC_FEE_REG, %l7, %g5
169 stx %i2, [%g5]
170 membar 0x40
171 /*************************************/
172
173Gen_Packet:
174 nop ! $EV trig_pc_d(1, @VA(.MAIN.Gen_Packet)) -> TxPktGen(MAC_ID, NIU_TxDmaNoUE,NIU_TX_PKT_CNT, 0, 0)
175 nop
176
177 setx 0x5, %g1, %g4
178delay_loop_tmp:
179 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
180 nop
181 nop
182 nop
183 nop
184 dec %g4
185 brnz %g4, delay_loop_tmp
186 nop
187
188
189SetTxRingKick:
190 setx NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK, %g1, %g2 ! $EV trig_pc_d(1, @VA(.MAIN.SetTxRingKick)) -> NIU_SetTxRingKick(MAC_ID, NIU_TxDmaNoUE)
191 setx NIU_TxDmaNo, %g1, %o0
192 ldx [%g2], %g3
193 nop
194 mulx %o0, 0x200, %g5
195 setx TX_RING_KICK_Addr, %g1, %g2
196 add %g2, %g5, %g2
197 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
198 nop
199
200SetTxCs :
201 setx NIU_TxDmaNo, %g1, %o0
202 setx TX_CS_Data, %g1, %g3
203 mulx %o0, 0x200, %g5
204 setx TX_CS_Addr, %g1, %g2
205 add %g2, %g5, %g2
206 stxa %g3, [%g2]ASI_PRIMARY_LITTLE
207 nop
208
209
210#ifdef JUMBO_FRAME_EN /* Extra Delay for Jumbo packets to go out */
211 setx loop_count, %g1, %g4
212delay_loop:
213 ldxa [%g2]ASI_PRIMARY_LITTLE, %g5
214 nop
215 nop
216 nop
217 nop
218 dec %g4
219 brnz %g4, delay_loop
220 nop
221#endif
222
223 ! wait in endless loop
224delay_ras:
225 setx 0x2000000, %g1, %g2
226 ldx [%g2], %g3
227 ba delay_ras
228 nop
229
230
231
232 /************************************
233 RAS
234 *************************************/
235After_Warm_Reset:
236 nop
237 nop
238
239read_esr:
240 setx SOC_ESR_REG, %l7, %i0
241 ldx [%i0], %g1
242
243 setx 0x8000000000000000, %g7, %g3 !valid bit
244 set 0x1, %g2
245 sllx %g2, ERR_FIELD, %g4
246 or %g3, %g4, %g5
247
248
249 cmp %g1, %g5
250 bne test_fail
251 nop
252 /*************************************/
253
254
255
256test_passed:
257/*
258#ifdef CE
259 nop ! $EV trig_pc_d(1, @VA(.MAIN.test_passed)) -> NIU_EXIT_chk(MAC_ID)
260#endif
261*/
262
263 EXIT_GOOD
264
265!.global test_failed
266!test_failed:
267! EXIT_BAD
268
269test_fail:
270 EXIT_BAD
271 nop
272/************************************************************************
273 RAS
274 Trap Handlers
275 ************************************************************************/
276My_Recoverable_Sw_error_trap:
277 ! Signal trap taken
278 setx EXECUTED, %l0, %o6
279 ! save trap type value
280 rdpr %tt, %o7
281
282check_desr_tt40:
283 ldxa [%g0]0x4c, %g2
284 nop
285 setx 0xb300000000000000, %l0, %g3
286 subcc %g2, %g3, %g4
287 brnz %g4, test_fail
288 nop
289
290check_per_tt40:
291 setx SOC_PER_REG, %l7, %i0
292 ldx [%i0], %i1
293 setx 0x8000000000000000, %l7, %o3 !valid bit
294 set 0x1, %i2
295 sllx %i2, ERR_FIELD, %i3
296 or %i3, %o3, %i4
297 sub %i1, %i4, %i5
298 brnz %i5, test_fail
299 nop
300
301clear_per_tt40:
302 setx SOC_PER_REG, %l7, %i0
303 stx %g0, [%i0]
304 nop
305 done
306 nop
307
308My_Corrected_ECC_error_trap:
309 ! Signal trap taken
310 setx EXECUTED, %l0, %o6
311 ! save trap type value
312 rdpr %tt, %o7
313
314check_desr_tt63:
315 ldxa [%g0]0x4c, %g2
316 nop
317 setx 0x8b00000000000000, %l0, %g3
318 subcc %g2, %g3, %g4
319 brnz %g4, test_fail
320
321check_per_tt63:
322 setx SOC_PER_REG, %l7, %i0
323 ldx [%i0], %i1
324 setx 0x8000000000000000, %l7, %o3 !valid bit
325 set 0x1, %i2
326 sllx %i2, ERR_FIELD, %i3
327 or %i3, %o3, %i4
328 sub %i1, %i4, %i5
329 brnz %i5, test_fail
330 nop
331
332clear_per_tt63:
333 setx SOC_PER_REG, %l7, %i0
334 stx %g0, [%i0]
335 nop
336 retry
337 nop
338
339
340 .align 64
341test_entered:
342 .xword 0
343
344/************************************************************************
345 Test case data start
346 ************************************************************************/
347/* These initialization is temporary, as there looks some bug in mempli */
348
349SECTION SetRngConfig_init data_va=0x100000000
350attr_data {
351 Name = SetRngConfig_init,
352 hypervisor,
353 compressimage
354 }
355.data
356SetRngConfig_init:
357 .xword 0x0060452301000484
358/************************************************************************/
359
360SECTION SetTxRingKick_init data_va=0x100000100
361attr_data {
362 Name = SetTxRingKick_init,
363 hypervisor,
364 compressimage
365 }
366.data
367SetTxRingKick_init:
368 .xword 0x0060452301000484
369/************************************************************************/
370
371SECTION SetTxLPMask1_init data_va=0x100000200
372attr_data {
373 Name = SetTxLPMask1_init,
374 hypervisor,
375 compressimage
376 }
377.data
378SetTxLPMask1_init:
379 .xword 0x0060452301000484
380/************************************************************************/
381
382SECTION SetTxLPValue1_init data_va=0x100000300
383attr_data {
384 Name = SetTxLPValue1_init,
385 hypervisor,
386 compressimage
387 }
388.data
389SetTxLPValue1_init:
390 .xword 0x0060452301000484
391/************************************************************************/
392
393SECTION SetTxLPRELOC1_init data_va=0x100000400
394attr_data {
395 Name = SetTxLPRELOC1_init,
396 hypervisor,
397 compressimage
398 }
399.data
400SetTxLPRELOC1_init:
401 .xword 0x0060452301000484
402/************************************************************************/
403SECTION SetTxLPMask2_init data_va=0x100000500
404attr_data {
405 Name = SetTxLPMask2_init,
406 hypervisor,
407 compressimage
408 }
409.data
410SetTxLPMask2_init:
411 .xword 0x0060452301000484
412/************************************************************************/
413SECTION SetTxLPValue2_init data_va=0x100000600
414attr_data {
415 Name = SetTxLPValue2_init,
416 hypervisor,
417 compressimage
418 }
419.data
420SetTxLPValue2_init:
421 .xword 0x0060452301000484
422
423/************************************************************************/
424SECTION SetTxLPRELOC2_init data_va=0x100000700
425attr_data {
426 Name = SetTxLPRELOC2_init,
427 hypervisor,
428 compressimage
429 }
430.data
431SetTxLPRELOC2_init:
432 .xword 0x0060452301000484
433
434/************************************************************************/
435SECTION SetTxLPValid_init data_va=0x100000800
436attr_data {
437 Name = SetTxLPValid_init,
438 hypervisor,
439 compressimage
440 }
441.data
442SetTxLPValid_init:
443 .xword 0x0060452301000484
444
445/************************************************************************/
446
Full OpenSPARC design & verification tarball including full HDL.