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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_dmu_dma_rd_trap.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | #define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap | |
40 | ||
41 | #define ENABLE_PCIE_LINK_TRAINING | |
42 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ | |
43 | #define MAIN_PAGE_HV_ALSO | |
44 | ||
45 | #include "hboot.s" | |
46 | #include "peu_defines.h" | |
47 | ||
48 | #define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA) | |
49 | ||
50 | #define DMA_DATA_ADDR 0x0000000123456700 | |
51 | #define DMA_DATA_BYP_SADDR 0xfffc000123456700 | |
52 | #define DMA_DATA_BYP_EADDR 0xfffc000123456800 | |
53 | ||
54 | /************************************************************************ | |
55 | Test case code start | |
56 | ************************************************************************/ | |
57 | .text | |
58 | .global main | |
59 | .global My_Corrected_ECC_error_trap | |
60 | .global My_Recoverable_Sw_error_trap | |
61 | ||
62 | main: | |
63 | ta T_CHANGE_HPRIV | |
64 | nop | |
65 | ||
66 | ! enable bypass in IOMMU | |
67 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
68 | setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3 | |
69 | stx %g3, [%g2] | |
70 | ldx [%g2], %g3 | |
71 | ||
72 | ||
73 | clear_esr_first: | |
74 | setx SOC_ESR_REG, %l7, %i0 | |
75 | stx %g0, [%i0] | |
76 | ||
77 | set_ejr: | |
78 | set 0x1, %i1 | |
79 | sllx %i1, ERR_FIELD, %i2 | |
80 | setx SOC_EJR_REG, %l7, %i3 | |
81 | stx %i2, [%i3] | |
82 | membar 0x40 | |
83 | ||
84 | set_eie: | |
85 | setx SOC_EIE_REG, %l7, %i3 | |
86 | stx %i2, [%i3] | |
87 | membar 0x40 | |
88 | ||
89 | ||
90 | ! see if this user event works in a loop (multi-shot) | |
91 | ||
92 | setx 0x02, %g1, %g4 | |
93 | XmtUsrEvnt1: | |
94 | nop ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_EADDR, "64'h40", 1, *, * ) | |
95 | dec %g4 | |
96 | brnz %g4, XmtUsrEvnt1 | |
97 | nop | |
98 | nop | |
99 | ||
100 | ||
101 | setx 0x40, %g1, %g4 | |
102 | delay_loop: | |
103 | nop; nop; nop | |
104 | nop; nop; nop | |
105 | nop; nop; nop | |
106 | nop; nop; nop | |
107 | nop; nop; nop | |
108 | ||
109 | dec %g4 | |
110 | brnz %g4, delay_loop | |
111 | nop | |
112 | ||
113 | ||
114 | ! Check if a Corrected_ECC_Trap or Recoverable_Sw_error_trap happened | |
115 | check_error_trap: | |
116 | setx EXECUTED, %l1, %l0 | |
117 | cmp %o6, %l0 | |
118 | bne test_failed | |
119 | nop | |
120 | mov TT, %l0 | |
121 | cmp %o7, %l0 | |
122 | bne test_failed | |
123 | nop | |
124 | ||
125 | test_passed: | |
126 | EXIT_GOOD | |
127 | ||
128 | ||
129 | test_failed: | |
130 | EXIT_BAD | |
131 | ||
132 | ||
133 | /************************************************************************ | |
134 | RAS | |
135 | Trap Handlers | |
136 | ************************************************************************/ | |
137 | My_Recoverable_Sw_error_trap: | |
138 | ! Signal trap taken | |
139 | setx EXECUTED, %l0, %o6 | |
140 | ! save trap type value | |
141 | rdpr %tt, %o7 | |
142 | ||
143 | check_desr_tt40: | |
144 | ldxa [%g0]0x4c, %g2 | |
145 | nop | |
146 | setx 0xb300000000000000, %l0, %g3 | |
147 | subcc %g2, %g3, %g4 | |
148 | brnz %g4, test_failed | |
149 | nop | |
150 | ||
151 | check_per_tt40: | |
152 | setx SOC_PER_REG, %l7, %i0 | |
153 | ldx [%i0], %i1 | |
154 | setx 0x8000000000000000, %l7, %o3 !valid bit | |
155 | set 0x1, %i2 | |
156 | sllx %i2, ERR_FIELD, %i3 | |
157 | or %i3, %o3, %i4 | |
158 | sub %i1, %i4, %i5 | |
159 | brnz %i5, test_failed | |
160 | nop | |
161 | ||
162 | clear_per_tt40: | |
163 | setx SOC_PER_REG, %l7, %i0 | |
164 | stx %g0, [%i0] | |
165 | nop | |
166 | done | |
167 | nop | |
168 | ||
169 | My_Corrected_ECC_error_trap: | |
170 | ! Signal trap taken | |
171 | setx EXECUTED, %l0, %o6 | |
172 | ! save trap type value | |
173 | rdpr %tt, %o7 | |
174 | ||
175 | check_desr_tt63: | |
176 | ldxa [%g0]0x4c, %g2 | |
177 | nop | |
178 | setx 0x8b00000000000000, %l0, %g3 | |
179 | subcc %g2, %g3, %g4 | |
180 | brnz %g4, test_failed | |
181 | ||
182 | check_per_tt63: | |
183 | setx SOC_PER_REG, %l7, %i0 | |
184 | ldx [%i0], %i1 | |
185 | setx 0x8000000000000000, %l7, %o3 !valid bit | |
186 | set 0x1, %i2 | |
187 | sllx %i2, ERR_FIELD, %i3 | |
188 | or %i3, %o3, %i4 | |
189 | sub %i1, %i4, %i5 | |
190 | brnz %i5, test_failed | |
191 | nop | |
192 | ||
193 | clear_per_tt63: | |
194 | setx SOC_PER_REG, %l7, %i0 | |
195 | stx %g0, [%i0] | |
196 | nop | |
197 | done | |
198 | nop | |
199 | ||
200 | /************************************************************************ | |
201 | Test case data start | |
202 | ************************************************************************/ | |
203 | ||
204 | SECTION .DATA DATA_VA=DMA_DATA_ADDR | |
205 | attr_data { | |
206 | Name = .DATA, | |
207 | hypervisor, | |
208 | compressimage | |
209 | } | |
210 | ||
211 | .data | |
212 | .xword 0x0001020304050607 | |
213 | .xword 0x08090a0b0c0d0e0f | |
214 | .xword 0x1011121314151617 | |
215 | .xword 0x18191a1b1c1d1e1f | |
216 | .xword 0x2021222324252627 | |
217 | .xword 0x28292a2b2c2d2e2f | |
218 | .xword 0x3031323334353637 | |
219 | .xword 0x38393a3b3c3d3e3f | |
220 | ||
221 | .xword 0x4041424344454647 | |
222 | .xword 0x48494a4b4c4d4e4f | |
223 | .xword 0x5051525354555657 | |
224 | .xword 0x58595a5b5c5d5e5f | |
225 | .xword 0x6061626364656667 | |
226 | .xword 0x68696a6b6c6d6e6f | |
227 | .xword 0x7071727374757677 | |
228 | .xword 0x78797a7b7c7d7e7f | |
229 | ||
230 | .xword 0x8081828384858687 | |
231 | .xword 0x88898a8b8c8d8e8f | |
232 | .xword 0x9091929394959697 | |
233 | .xword 0x98999a9b9c9d9e9f | |
234 | .xword 0xa0a1a2a3a4a5a6a7 | |
235 | .xword 0xa8a9aaabacadaeaf | |
236 | .xword 0xb0b1b2b3b4b5b6b7 | |
237 | .xword 0xb8b9babbbcbdbebf | |
238 | ||
239 | .xword 0xc0c1c2c3c4c5c6c7 | |
240 | .xword 0xc8c9cacbcccdcecf | |
241 | .xword 0xd0d1d2d3d4d5d6d7 | |
242 | .xword 0xd8d9dadbdcdddedf | |
243 | .xword 0xe0e1e2e3e4e5e6e7 | |
244 | .xword 0xe8e9eaebecedeeef | |
245 | .xword 0xf0f1f2f3f4f5f6f7 | |
246 | .xword 0xf8f9fafbfcfdfeff | |
247 | ||
248 | .xword 0x0001020304050607 | |
249 | .xword 0x08090a0b0c0d0e0f | |
250 | .xword 0x1011121314151617 | |
251 | .xword 0x18191a1b1c1d1e1f | |
252 | .xword 0x2021222324252627 | |
253 | .xword 0x28292a2b2c2d2e2f | |
254 | .xword 0x3031323334353637 | |
255 | .xword 0x38393a3b3c3d3e3f | |
256 | ||
257 | .xword 0x4041424344454647 | |
258 | .xword 0x48494a4b4c4d4e4f | |
259 | .xword 0x5051525354555657 | |
260 | .xword 0x58595a5b5c5d5e5f | |
261 | .xword 0x6061626364656667 | |
262 | .xword 0x68696a6b6c6d6e6f | |
263 | .xword 0x7071727374757677 | |
264 | .xword 0x78797a7b7c7d7e7f | |
265 | ||
266 | .xword 0x8081828384858687 | |
267 | .xword 0x88898a8b8c8d8e8f | |
268 | .xword 0x9091929394959697 | |
269 | .xword 0x98999a9b9c9d9e9f | |
270 | .xword 0xa0a1a2a3a4a5a6a7 | |
271 | .xword 0xa8a9aaabacadaeaf | |
272 | .xword 0xb0b1b2b3b4b5b6b7 | |
273 | .xword 0xb8b9babbbcbdbebf | |
274 | ||
275 | .xword 0xc0c1c2c3c4c5c6c7 | |
276 | .xword 0xc8c9cacbcccdcecf | |
277 | .xword 0xd0d1d2d3d4d5d6d7 | |
278 | .xword 0xd8d9dadbdcdddedf | |
279 | .xword 0xe0e1e2e3e4e5e6e7 | |
280 | .xword 0xe8e9eaebecedeeef | |
281 | .xword 0xf0f1f2f3f4f5f6f7 | |
282 | .xword 0xf8f9fafbfcfdfeff | |
283 | ||
284 | /************************************************************************/ |