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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_L2_FatalErr_WrmRst.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_HV_ALSO | |
39 | ||
40 | #define L2_ENTRY_PA 0x517590000 | |
41 | #define TEST_DATA 0x555555555555555 | |
42 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
43 | #define L2ES_LVC 34 | |
44 | #define RESET_STAT_CHECK | |
45 | #define RESET_CHECK_REG | |
46 | ||
47 | ||
48 | #include "hboot.s" | |
49 | #include "asi_s.h" | |
50 | #include "err_defines.h" | |
51 | ||
52 | .text | |
53 | .global main | |
54 | ||
55 | ||
56 | main: | |
57 | ||
58 | ||
59 | ! Boot code does not provide TLB translation for IO address space | |
60 | ta T_CHANGE_HPRIV | |
61 | ||
62 | ! Check if Warm Reset is done, or first time entering diag | |
63 | setx warm_reset_done, %g1, %g2 | |
64 | ldx [%g2], %g3 | |
65 | brnz %g3, Warm_Reset_Complt | |
66 | nop | |
67 | ||
68 | ! First time thru, Store a non-zero value there | |
69 | dec %g3 | |
70 | stx %g3, [%g2] | |
71 | ||
72 | ||
73 | setx L2_ES_W1C_VALUE, %l0, %g4 | |
74 | ||
75 | ! Now access L2 control and status registers | |
76 | disable_l1: | |
77 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
78 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
79 | andn %l0, 0x3, %l0 | |
80 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
81 | ||
82 | ! Write 1 to clear L2 Error status registers | |
83 | ||
84 | enable_err_reporting: | |
85 | setx L2EE_PA0, %l0, %l1 | |
86 | ldx [%l1], %l2 | |
87 | mov 0x1, %l0 | |
88 | or %l2, %l0, %l2 | |
89 | stx %l2, [%l1] | |
90 | ||
91 | clear_l2_ESR: | |
92 | setx L2ES_PA0, %l3, %l4 | |
93 | stx %g4, [%l4] | |
94 | nop | |
95 | ||
96 | ||
97 | set_L2_Directly_Mapped_Mode: | |
98 | setx L2CS_PA0, %l6, %g1 | |
99 | mov 0x2, %l0 | |
100 | stx %l0, [%g1] | |
101 | ||
102 | set_warm_reset_reg: | |
103 | setx 0x8900000820,%l1,%l2 | |
104 | setx 0xff00,%l3,%l4 | |
105 | stx %l4,[%l2] | |
106 | membar #Sync | |
107 | ||
108 | store_to_L2_way0: | |
109 | setx TEST_DATA, %l0, %g5 | |
110 | setx 0x22000000, %l0, %g1 | |
111 | stx %g5, [%g1] | |
112 | stx %g5, [%g1+8] | |
113 | membar #Sync | |
114 | ||
115 | ||
116 | generate_VD_addr: | |
117 | ! Generate L2 VD Diag read address | |
118 | ! Addressing: [39:32] See PRM, [22] 1 for V/D, [17:8] set, [7:6] bank, [2:0] = 0 | |
119 | setx 0x3ffc0, %l0, %l2 ! Mask for extracting [17:6] | |
120 | and %g1, %l2, %l7 | |
121 | ||
122 | mov 0xb6, %l0 | |
123 | sllx %l0, 32, %l0 ! Bits [39:32] | |
124 | or %l7, %l0, %l7 | |
125 | ||
126 | mov 0x1, %l0 | |
127 | sllx %l0, 22, %l0 ! Bit [22] | |
128 | or %l7, %l0, %l7 | |
129 | ||
130 | read_l2_VD_diag: | |
131 | ldx [%l7], %l6 | |
132 | xor %l6, 0xc,%l6 | |
133 | stx %l6,[%l7] | |
134 | ||
135 | store_to_L2_way0_wb: | |
136 | setx TEST_DATA, %l0, %g5 | |
137 | setx 0x22000000, %l0, %g1 | |
138 | setx 0x22000000, %l1, %g2 | |
139 | stx %g5, [%g1] | |
140 | membar #Sync | |
141 | stx %g5, [%g2] | |
142 | membar #Sync | |
143 | ||
144 | ||
145 | enable_l1: | |
146 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
147 | or %l0, 0x3, %l0 | |
148 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
149 | ||
150 | ! Compute expected value of L2 error status register | |
151 | compute_expected_L2_ESR: | |
152 | mov 0x1, %l1 | |
153 | sllx %l1, L2ES_LVU, %l0 | |
154 | sllx %l1, L2ES_VEU, %l3 ! VEC bit | |
155 | or %l0, %l3, %l0 | |
156 | setx L2ES_PA0, %l2, %l3 | |
157 | ||
158 | ||
159 | check_l2_ESR: | |
160 | ldx [%l3], %l4 | |
161 | ||
162 | setx 0xfc00000000, %l5,%g2 | |
163 | and %l4, %g2, %l4 | |
164 | cmp %l4, %l0 | |
165 | bne test_fail | |
166 | nop | |
167 | ||
168 | setx L2EA_PA0, %l2, %l3 | |
169 | setx 0x22000000, %l0, %g1 | |
170 | ||
171 | check_l2_EAR: | |
172 | ldx [%l3], %l4 ! Error address is the physical address of the cache line (PA[5:0] 0) | |
173 | cmp %g1,%l4 | |
174 | bne test_fail | |
175 | nop | |
176 | ||
177 | ba test_fail | |
178 | nop | |
179 | Warm_Reset_Complt: | |
180 | compute_expected_L2_ESR_rst: | |
181 | mov 0x1, %l1 | |
182 | sllx %l1, L2ES_LVU, %l0 | |
183 | sllx %l1, L2ES_VEU, %l3 ! VEC bit | |
184 | or %l0, %l3, %l0 | |
185 | setx L2ES_PA0, %l2, %l3 | |
186 | ||
187 | ||
188 | check_l2_ESR_rst: | |
189 | ldx [%l3], %l4 | |
190 | ||
191 | setx 0xfc00000000, %l5,%g2 | |
192 | and %l4, %g2, %l4 | |
193 | cmp %l4, %l0 | |
194 | bne test_fail | |
195 | nop | |
196 | ||
197 | setx L2EA_PA0, %l2, %l3 | |
198 | setx 0x22000000, %l0, %g1 | |
199 | ||
200 | check_l2_EAR_rst: | |
201 | ldx [%l3], %l4 ! Error address is the physical address of the cache line (PA[5:0] 0) | |
202 | cmp %g1,%l4 | |
203 | bne test_fail | |
204 | nop | |
205 | ||
206 | ba test_pass | |
207 | nop | |
208 | ||
209 | ||
210 | ||
211 | ||
212 | /******************************************************* | |
213 | * Exit code | |
214 | *******************************************************/ | |
215 | ||
216 | test_pass: | |
217 | ta T_GOOD_TRAP | |
218 | ||
219 | test_fail: | |
220 | ta T_BAD_TRAP | |
221 | ||
222 | ||
223 | .align 64 | |
224 | warm_reset_done: | |
225 | .xword 0 | |
226 |