Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / l2 / n2_err_L2_LDWU_uecc.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_L2_LDWU_uecc.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO


#define  L2_ENTRY_PA        0xa000000000
#define  TEST_DATA1         0x5555555555555555
#define	 L2_ENTRY_PA0       0x2020000008
#define L2_ES_W1C_VALUE     0xc03ffff800000000

#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"

.text
.global	 main

main:


  ! Boot code does not provide TLB translation for IO address space
  ta    T_CHANGE_HPRIV

disable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove bit 2
  andn  %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL


clear_l2_ESR:
  setx  L2_ES_W1C_VALUE, %l0, %l1
  setx  L2ES_PA0, %l6, %g1
  stx   %l1, [%g1]


set_L2_Directly_Mapped_Mode:
  setx  L2CS_PA0, %l6, %g1
  mov   0x2, %l0
  stx   %l0, [%g1]

store_to_L2:
  setx  TEST_DATA1, %l0, %g5

store_to_L2_way0:
  set	0x2000aa00, %g2
  stx %g5, [%g2] 
  stx %g5, [%g2+8]
  membar #Sync

clr %l6
set 0x7, %l5
loop:
   inc %l6
   cmp %l6,%l5
   bne loop
   nop


L2_diag_load:
  setx  0x3ffff8, %l0, %l2      ! Mask for extracting [21:3]
  setx	L2_ENTRY_PA, %l0, %g4
  and   %g2, %l2, %g5
  or	%g5, %g4, %g5
  ldx	[%g5], %g6
  membar #Sync

! Flip two  bits
  xor	 %g6, 0x600, %g6
  stx	%g6, [%g5]
  membar #Sync

store_for_wb:
  set  0x55555555,%l6
  set  0x3000aa00, %g2
  stx  %l6, [%g2]
  membar #Sync  

store_to_L2_way0_meu:
  set  0x55555555,%g5
  set   0x2020aa00, %g2
  stx %g5, [%g2]
  stx %g5, [%g2+8]
  membar #Sync

clr %l6
set 0x7, %l5
loop_meu:
   inc %l6
   cmp %l6,%l5
   bne loop_meu
   nop


L2_diag_load_meu:
  setx  0x3ffff8, %l0, %l2      ! Mask for extracting [21:3]
  setx  L2_ENTRY_PA, %l0, %g4
  and   %g2, %l2, %g5
  or    %g5, %g4, %g5
  ldx   [%g5], %g6
  membar #Sync

! Flip two  bits
  xor    %g6, 0x600, %g6
  stx   %g6, [%g5]
  membar #Sync

store_for_wb_meu:
  set  0x55555555,%l6
  set  0x3020aa00, %g2
  stx  %l6, [%g2]
  membar #Sync


compute_error:
  mov   0x1, %l1
  sllx  %l1, L2ES_LDWU, %l7
  sllx  %l1, L2ES_VEU, %l3
  or    %l7, %l3, %l7
  sllx  %l1, L2ES_MEU, %l3
  or    %l7, %l3, %l7

  !mov   0x46, %l1                ! 7-bit Syndrome
  !sllx  %l1, 21, %l3             ! Syndrome for [127:96] at [27:21]
  !or    %l7, %l3, %l7
  !sllx  %g4, L2ES_TID, %l3       ! ID of thread that encountered error
  !or    %l7, %l3, %l7            ! %l7 has expected value
  membar #Sync


check_l2_ESR:
  setx  L2ES_PA0, %l6, %g1
  ldx   [%g1], %l4
  membar #Sync

! Not Checking SYND in this test
  set  0xffffffff, %l3
  andn   %l4, %l3, %l4
  cmp   %l7,  %l4
  !bne test_fail
  nop
  nop


check_l2_EAR:
  setx  L2EA_PA0, %l6, %l3
  ldx   [%l3], %l4
  membar #Sync
  set  0x2020aa00, %g2
  cmp %g2,%l4
  !bne test_fail
  nop

reading_back_1: ! For MEU
  setx  0x202000aa00, %l0, %g2
  ldx   [%g2], %l6
  membar #Sync



enable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  or    %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

compute_error_meu:
  mov   0x1, %l1
  sllx  %l1, L2ES_LDAU, %l7
  sllx  %l1, L2ES_VEU, %l3
  or    %l7, %l3, %l7
  sllx  %l1, L2ES_MEU, %l3
  or    %l7, %l3, %l7
  !mov   0x46, %l1                ! 7-bit Syndrome
  !sllx  %l1, 21, %l3             ! Syndrome for [127:96] at [27:21]
  !or    %l7, %l3, %l7
  !sllx  %g4, L2ES_TID, %l3       ! ID of thread that encountered error
  !or    %l7, %l3, %l7            ! %l7 has expected value
  membar #Sync


check_l2_ESR_meu:
  setx  L2ES_PA0, %l6, %g1
  ldx   [%g1], %l4
  membar #Sync

! Not Checking SYND in this test
  set  0xffffffff, %l3
  andn   %l4, %l3, %l4
  cmp   %l7,  %l4
  bne test_fail
  nop
  nop


check_l2_EAR_meu:
  setx  L2EA_PA0, %l6, %l3
  ldx   [%l3], %l4
  membar #Sync
  setx  0x202000aa00, %l0, %g2
  cmp %g2,%l4
  bne test_fail
  nop


  ba    test_pass
  nop



/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP

test_fail:
ta  T_BAD_TRAP