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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_L2_LVC_cecc_SyndCheck.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_HV_ALSO | |
39 | ||
40 | #define L2_ENTRY_PA 0x517590000 | |
41 | #define TEST_DATA 0x555555555555555 | |
42 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
43 | #define L2ES_LVC 34 | |
44 | ||
45 | ||
46 | #include "hboot.s" | |
47 | #include "asi_s.h" | |
48 | #include "err_defines.h" | |
49 | ||
50 | .text | |
51 | .global main | |
52 | .global My_Corrected_ECC_error_trap | |
53 | ||
54 | ||
55 | main: | |
56 | ||
57 | ||
58 | ! Boot code does not provide TLB translation for IO address space | |
59 | ta T_CHANGE_HPRIV | |
60 | ||
61 | ||
62 | ! Now access L2 control and status registers | |
63 | disable_l1: | |
64 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
65 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
66 | andn %l0, 0x3, %l0 | |
67 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
68 | ||
69 | ! Write 1 to clear L2 Error status registers | |
70 | ||
71 | set_L2_Directly_Mapped_Mode: | |
72 | setx L2CS_PA0, %l6, %g1 | |
73 | mov 0x2, %l0 | |
74 | stx %l0, [%g1] | |
75 | ||
76 | !mov 0x0,%o0 | |
77 | mov 0x1,%o1 | |
78 | mov 0x2,%o2 | |
79 | mov 0x3,%o3 | |
80 | mov 0x4,%o4 | |
81 | mov 0x5,%o5 | |
82 | mov 0x6,%o6 | |
83 | mov 0x0,%i0 | |
84 | ||
85 | clear_l2_ESR: | |
86 | setx L2_ES_W1C_VALUE, %l0, %g4 | |
87 | setx L2ES_PA0, %l3, %l4 | |
88 | stx %g4, [%l4] | |
89 | nop | |
90 | ||
91 | store_to_L2_way0: | |
92 | setx TEST_DATA, %l0, %g5 | |
93 | ||
94 | cmp %i0,%g0 | |
95 | be flip_c0 | |
96 | cmp %i0,%o1 | |
97 | be flip_c1 | |
98 | cmp %i0,%o2 | |
99 | be flip_c2 | |
100 | cmp %i0,%o3 | |
101 | be flip_c3 | |
102 | cmp %i0,%o4 | |
103 | be flip_c4 | |
104 | cmp %i0,%o5 | |
105 | be flip_c5 | |
106 | ||
107 | flip_c0: | |
108 | mov 0x1, %l0 | |
109 | mov 0x41,%i3 ! 0x41 is the syndrome , bit 0 of ecc flipped | |
110 | setx 0x22000000, %l3, %g1 | |
111 | ba store_diff_index | |
112 | nop | |
113 | flip_c1: | |
114 | mov 0x2, %l0 | |
115 | mov 0x42,%i3 ! 0x42 is the syndrome , bit 1 of ecc flipped | |
116 | setx 0x22000400, %l3, %g1 | |
117 | ba store_diff_index | |
118 | nop | |
119 | flip_c2: | |
120 | mov 0x4, %l0 | |
121 | mov 0x44,%i3 ! 0x44 is the syndrome , bit 2 of ecc flipped | |
122 | setx 0x22000800, %l3, %g1 | |
123 | ba store_diff_index | |
124 | nop | |
125 | flip_c3: | |
126 | mov 0x8, %l0 | |
127 | mov 0x48,%i3 ! 0x48 is the syndrome , bit 3 of ecc flipped | |
128 | setx 0x22000c00, %l3, %g1 | |
129 | ba store_diff_index | |
130 | nop | |
131 | flip_c4: | |
132 | mov 0x10, %l0 | |
133 | mov 0x50,%i3 ! 0x50 is the syndrome , bit 4 of ecc flipped | |
134 | setx 0x22001000, %l3, %g1 | |
135 | ba store_diff_index | |
136 | nop | |
137 | flip_c5: | |
138 | mov 0x20, %l0 | |
139 | mov 0x60,%i3 ! 0x60 is the syndrome , bit 5 of ecc flipped | |
140 | setx 0x22002000, %l3, %g1 | |
141 | ||
142 | store_diff_index: | |
143 | stx %g5, [%g1] | |
144 | stx %g5, [%g1+8] | |
145 | membar #Sync | |
146 | ||
147 | generate_UA_addr: | |
148 | ! Generate L2 VD Diag read address | |
149 | ! Addressing: [39:32] See PRM, [22] 1 for V/D, [17:9] set, [8:6] bank, [2:0] = 0 | |
150 | setx 0x3ffc0, %l1, %l2 ! Mask for extracting [17:6] | |
151 | and %g1, %l2, %l7 | |
152 | ||
153 | mov 0xb6, %l2 | |
154 | sllx %l2, 32, %l2 ! Bits [39:32] | |
155 | or %l7, %l2, %l7 | |
156 | mov 0x0, %l2 | |
157 | sllx %l2, 22, %l1 ! L2_VD and L2_UA addressing differ on bit 22 | |
158 | xor %l7, %l1, %l7 ! change %l7 from L2_VD to L2_UA address | |
159 | ||
160 | read_l2_UA_diag: | |
161 | ldx [%l7], %l6 | |
162 | ||
163 | flip_bit_inject_err: | |
164 | sllx %l0, 32, %l0 | |
165 | xor %l6, %l0, %l6 | |
166 | ||
167 | write_l2_UA_diag: | |
168 | stx %l6, [%l7] | |
169 | membar #Sync | |
170 | ||
171 | Ld_to_get_err: | |
172 | !setx 0x2200aa00, %l0, %g1 | |
173 | ldx [%g1],%g2 | |
174 | membar #Sync | |
175 | ||
176 | ! Compute expected value of L2 error status register | |
177 | compute_expected_L2_ESR: | |
178 | mov 0x1, %l1 | |
179 | sllx %l1, L2ES_LVC, %l0 | |
180 | sllx %l1, L2ES_VEC, %l3 ! VEC bit | |
181 | or %l0, %l3, %l0 | |
182 | or %l0, %i3, %l0 ! Syndrome | |
183 | ||
184 | check_l2_ESR: | |
185 | setx L2ES_PA0, %l2, %l3 | |
186 | ldx [%l3], %l4 | |
187 | cmp %l4, %l0 | |
188 | bne test_fail | |
189 | nop | |
190 | ||
191 | inc_i0: | |
192 | inc %i0 | |
193 | cmp %i0,%o6 | |
194 | bne clear_l2_ESR | |
195 | nop | |
196 | ||
197 | done: | |
198 | ba test_pass | |
199 | nop | |
200 | ||
201 | ||
202 | /******************************************************* | |
203 | * Exit code | |
204 | *******************************************************/ | |
205 | ||
206 | test_pass: | |
207 | ta T_GOOD_TRAP | |
208 | ||
209 | test_fail: | |
210 | ta T_BAD_TRAP | |
211 | ||
212 |