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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_L2_NotData_NDDM_meu.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define ENABLE_PCIE_LINK_TRAINING | |
39 | #define MAIN_PAGE_NUCLEUS_ALSO | |
40 | #define MAIN_PAGE_HV_ALSO | |
41 | ||
42 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
43 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
44 | #define L2_ERR_STAT_REG 0xAB00000000 | |
45 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
46 | #define L2_NDDM_REG 0xAE00000000 | |
47 | ||
48 | #define TT_SW_Error 0x40 | |
49 | ||
50 | ||
51 | #define ERROR_ADDR 0x20200000 | |
52 | #define TEST_DATA0 0x1000100081c3e008 | |
53 | #define TEST_DATA1 0x2000200081c3e008 | |
54 | #define TEST_DATA2 0x3000300081c3e008 | |
55 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
56 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
57 | #define DMA_DATA_BYP_ADDR1 0xfffc00002000aa00 | |
58 | ||
59 | #include "hboot.s" | |
60 | #include "asi_s.h" | |
61 | #include "err_defines.h" | |
62 | #include "peu_defines.h" | |
63 | ||
64 | ||
65 | ||
66 | .text | |
67 | .global main | |
68 | ||
69 | ||
70 | ||
71 | ||
72 | main: | |
73 | ||
74 | ta T_CHANGE_HPRIV | |
75 | ||
76 | ||
77 | disable_l1: | |
78 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
79 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
80 | andn %l0, 0x3, %l0 | |
81 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
82 | ||
83 | setx 0x20040000, %l0, %g6 | |
84 | ||
85 | ||
86 | clear_dram_esr_0: | |
87 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) | |
88 | setx DRAM_ES_W1C_VALUE, %l0, %g4 | |
89 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
90 | stx %g4, [%g5] | |
91 | ||
92 | set_DRAM_error_inject_ch0: | |
93 | mov 0x602, %l1 ! ECC Mask (2-bit error) | |
94 | mov 0x1, %l2 | |
95 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
96 | Or %l1, %l3, %l1 ! Set single shot ; | |
97 | mov 0x1, %l2 | |
98 | sllx %l2, DRAM_EI_ENB, %l3 | |
99 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
100 | setx DRAM_ERR_INJ_REG, %l3, %g5 | |
101 | stx %l1, [%g5] | |
102 | membar 0x40 | |
103 | ||
104 | !enable_err_reporting: | |
105 | ! setx L2EE_PA0, %l0, %l1 | |
106 | ! ldx [%l1], %l2 | |
107 | ! mov 0x3, %l0 | |
108 | ! or %l2, %l0, %l2 | |
109 | ! stx %l2, [%l1] | |
110 | ||
111 | ! Write 1 to clear L2 Error status registers | |
112 | clear_l2_ESR: | |
113 | setx L2ES_PA0, %l3, %l4 | |
114 | stx %g4, [%l4] | |
115 | nop | |
116 | ||
117 | store_to_L2: | |
118 | setx TEST_DATA1, %l0, %g5 | |
119 | ||
120 | ||
121 | set_L2_Directly_Mapped_Mode: | |
122 | setx L2CS_PA0, %l6, %g1 | |
123 | mov 0x2, %l0 | |
124 | stx %l0, [%g1] | |
125 | ||
126 | ||
127 | store_to_L2_way0: | |
128 | setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way | |
129 | stx %g5, [%g2] | |
130 | stx %g5, [%g2+8] | |
131 | membar #Sync | |
132 | ||
133 | ! Storing to same L2 way0 but different tag,this will write to mcu | |
134 | write_mcu_channel_0: | |
135 | setx 0x1000aa00, %l0, %g3 ! bits [21:18] select way | |
136 | stx %g5, [%g3] | |
137 | stx %g5, [%g3+8] | |
138 | membar #Sync | |
139 | ||
140 | read_error_address_ch0: | |
141 | ldx [%g2], %l1 | |
142 | membar #Sync | |
143 | ||
144 | Wr_Evnt: nop; | |
145 | ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 ) | |
146 | ||
147 | clr %i7 | |
148 | set 0x30,%l7 | |
149 | loop: | |
150 | inc %i7 | |
151 | cmp %i7,%l7 | |
152 | bne loop | |
153 | nop | |
154 | ||
155 | Wr_Evnt_meu: nop; | |
156 | ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt_meu) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 ) | |
157 | ||
158 | clr %i7 | |
159 | set 0x20,%l7 | |
160 | loop_meu: | |
161 | inc %i7 | |
162 | cmp %i7,%l7 | |
163 | bne loop_meu | |
164 | nop | |
165 | ||
166 | Wr_Evnt1: nop; | |
167 | ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt1) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 ) | |
168 | ||
169 | ||
170 | ||
171 | check_DRAM_ESR_0: | |
172 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
173 | ldx [%g5], %l6 | |
174 | ||
175 | compute_dram_ESR: | |
176 | setx 0xffffffffffff0000, %l0,%o2 | |
177 | and %l6,%o2,%l6 | |
178 | mov 0x1, %l1 | |
179 | sllx %l1, DRAM_ES_DAU, %l0 | |
180 | ||
181 | verify_dram_ESR: | |
182 | cmp %l0, %l6 | |
183 | bne %xcc, test_fail | |
184 | nop | |
185 | ||
186 | check_L2_ESR_0: | |
187 | setx L2_ERR_STAT_REG, %l3, %g5 | |
188 | ldx [%g5], %l6 | |
189 | ||
190 | compute_L2_ESR: | |
191 | setx 0xfffffffff0000000, %l3, %l0 | |
192 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits | |
193 | mov 0x1, %l1 | |
194 | sllx %l1, L2ES_DAU, %l0 | |
195 | mov 0x1, %l1 | |
196 | sllx %l1, L2ES_VEU, %l2 | |
197 | or %l0, %l2, %l3 | |
198 | ||
199 | verify_L2_ESR: | |
200 | cmp %l6, %l3 | |
201 | bne %xcc, test_fail | |
202 | nop | |
203 | ||
204 | check_notData_reg: | |
205 | setx L2_NDDM_REG, %l3, %g5 | |
206 | ldx [%g5], %l6 | |
207 | ||
208 | compute_notData_reg: | |
209 | setx 0xa00002000aa00, %l0, %l1 ! bits [21:18] select way | |
210 | setx 0xfffffffffffc0, %l0,%o2 | |
211 | and %l6, %o2, %l6 | |
212 | cmp %l6, %l1 | |
213 | bne %xcc, test_fail | |
214 | nop | |
215 | ||
216 | setx L2EA_PA0, %l2, %l3 | |
217 | check_l2_EAR: | |
218 | ldx [%l3], %l4 | |
219 | ! Error address is the physical address of the cache line (PA[5:0] 0) | |
220 | setx 0x2000aa00, %l0, %l1 ! bits [21:18] select way | |
221 | setx 0xffffffffc0, %l0,%o2 | |
222 | and %l4, %o2, %l4 | |
223 | cmp %l4, %l1 | |
224 | bne %xcc, test_fail | |
225 | nop | |
226 | ||
227 | ||
228 | ba test_pass | |
229 | nop | |
230 | ||
231 | /******************************************************* | |
232 | * Exit code | |
233 | *******************************************************/ | |
234 | ||
235 | test_pass: | |
236 | ta T_GOOD_TRAP | |
237 | ||
238 | ||
239 | test_fail: | |
240 | ta T_BAD_TRAP | |
241 | ||
242 | ||
243 |