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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_L2_NotData_NDDM_meu_trap.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define ENABLE_PCIE_LINK_TRAINING | |
39 | #define MAIN_PAGE_NUCLEUS_ALSO | |
40 | #define MAIN_PAGE_HV_ALSO | |
41 | ||
42 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
43 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
44 | #define L2_ERR_STAT_REG 0xAB00000000 | |
45 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
46 | #define L2_NDDM_REG 0xAE00000000 | |
47 | ||
48 | #define TT_SW_Error 0x40 | |
49 | ||
50 | ||
51 | #define ERROR_ADDR 0x20200000 | |
52 | #define TEST_DATA0 0x1000100081c3e008 | |
53 | #define TEST_DATA1 0x2000200081c3e008 | |
54 | #define TEST_DATA2 0x3000300081c3e008 | |
55 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
56 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
57 | ||
58 | #ifdef L20 | |
59 | #define L2_BANK_ADDR 0x0 | |
60 | #define DMA_DATA_BYP_ADDR1 0xfffc00002000aa00 | |
61 | #endif | |
62 | #ifdef L21 | |
63 | #define L2_BANK_ADDR 0x40 | |
64 | #define DMA_DATA_BYP_ADDR1 0xfffc00002000aa40 | |
65 | #endif | |
66 | #ifdef L22 | |
67 | #define L2_BANK_ADDR 0x80 | |
68 | #define DMA_DATA_BYP_ADDR1 0xfffc00002000aa80 | |
69 | #endif | |
70 | #ifdef L23 | |
71 | #define L2_BANK_ADDR 0xc0 | |
72 | #define DMA_DATA_BYP_ADDR1 0xfffc00002000aac0 | |
73 | #endif | |
74 | #ifdef L24 | |
75 | #define L2_BANK_ADDR 0x100 | |
76 | #define DMA_DATA_BYP_ADDR1 0xfffc00002000ac00 | |
77 | #endif | |
78 | #ifdef L25 | |
79 | #define L2_BANK_ADDR 0x140 | |
80 | #define DMA_DATA_BYP_ADDR1 0xfffc00002000ac40 | |
81 | #endif | |
82 | #ifdef L26 | |
83 | #define L2_BANK_ADDR 0x180 | |
84 | #define DMA_DATA_BYP_ADDR1 0xfffc00002000ac80 | |
85 | #endif | |
86 | #ifdef L27 | |
87 | #define L2_BANK_ADDR 0x1c0 | |
88 | #define DMA_DATA_BYP_ADDR1 0xfffc00002000acc0 | |
89 | #endif | |
90 | ||
91 | #include "hboot.s" | |
92 | #include "asi_s.h" | |
93 | #include "err_defines.h" | |
94 | #include "peu_defines.h" | |
95 | ||
96 | ||
97 | ||
98 | .text | |
99 | .global main | |
100 | ||
101 | ||
102 | ||
103 | ||
104 | main: | |
105 | ||
106 | ta T_CHANGE_HPRIV | |
107 | ||
108 | ||
109 | disable_l1: | |
110 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
111 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
112 | andn %l0, 0x3, %l0 | |
113 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
114 | ||
115 | setx 0x20040000, %l0, %g6 | |
116 | ||
117 | ||
118 | clear_dram_esr_0: | |
119 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) | |
120 | setx DRAM_ES_W1C_VALUE, %l0, %g4 | |
121 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
122 | stx %g4, [%g5] | |
123 | ||
124 | set_DRAM_error_inject_ch0: | |
125 | mov 0x602, %l1 ! ECC Mask (2-bit error) | |
126 | mov 0x1, %l2 | |
127 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
128 | Or %l1, %l3, %l1 ! Set single shot ; | |
129 | mov 0x1, %l2 | |
130 | sllx %l2, DRAM_EI_ENB, %l3 | |
131 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
132 | setx DRAM_ERR_INJ_REG, %l3, %g5 | |
133 | stx %l1, [%g5] | |
134 | membar 0x40 | |
135 | ||
136 | !enable_err_reporting: | |
137 | ! setx L2EE_PA0, %l0, %l1 | |
138 | ! ldx [%l1], %l2 | |
139 | !mov 0x3, %l0 | |
140 | !or %l2, %l0, %l2 | |
141 | !stx %l2, [%l1] | |
142 | ||
143 | ! Write 1 to clear L2 Error status registers | |
144 | clear_l2_ESR: | |
145 | setx L2ES_PA0, %l3, %l4 | |
146 | !add %l4, L2_BANK_ADDR, %l4 | |
147 | stx %g4, [%l4] | |
148 | nop | |
149 | ||
150 | store_to_L2: | |
151 | setx TEST_DATA1, %l0, %g5 | |
152 | ||
153 | ||
154 | set_L2_Directly_Mapped_Mode: | |
155 | setx L2CS_PA0, %l6, %g1 | |
156 | ! add %g1, L2_BANK_ADDR, %g1 | |
157 | mov 0x2, %l0 | |
158 | stx %l0, [%g1] | |
159 | ||
160 | ||
161 | store_to_L2_way0: | |
162 | setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way | |
163 | ! add %g2, L2_BANK_ADDR, %g2 | |
164 | stx %g5, [%g2] | |
165 | stx %g5, [%g2+8] | |
166 | membar #Sync | |
167 | ||
168 | ! Storing to same L2 way0 but different tag,this will write to mcu | |
169 | write_mcu_channel_0: | |
170 | setx 0x1000aa00, %l0, %g3 ! bits [21:18] select way | |
171 | ! add %g3, L2_BANK_ADDR, %g3 | |
172 | stx %g5, [%g3] | |
173 | stx %g5, [%g3+8] | |
174 | membar #Sync | |
175 | ||
176 | read_error_address_ch0: | |
177 | ldx [%g2], %l1 | |
178 | membar #Sync | |
179 | ||
180 | enable_err_reporting: | |
181 | setx L2EE_PA0, %l0, %l1 | |
182 | ! add %l1, L2_BANK_ADDR, %l1 | |
183 | ldx [%l1], %l2 | |
184 | mov 0x3, %l0 | |
185 | or %l2, %l0, %l2 | |
186 | stx %l2, [%l1] | |
187 | ||
188 | Wr_Evnt: nop; | |
189 | ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 ) | |
190 | ||
191 | clr %i7 | |
192 | set 0x30,%l7 | |
193 | loop: | |
194 | inc %i7 | |
195 | cmp %i7,%l7 | |
196 | bne loop | |
197 | nop | |
198 | ||
199 | Wr_Evnt_meu: nop; | |
200 | ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt_meu) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 ) | |
201 | ||
202 | clr %i7 | |
203 | set 0x20,%l7 | |
204 | loop_meu: | |
205 | inc %i7 | |
206 | cmp %i7,%l7 | |
207 | bne loop_meu | |
208 | nop | |
209 | ||
210 | Wr_Evnt1: nop; | |
211 | ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt1) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 ) | |
212 | ||
213 | ||
214 | miss_for_trap: | |
215 | setx 0x3000ca00, %l3, %g5 | |
216 | ! add %g5, L2_BANK_ADDR, %g5 | |
217 | stx %g4, [%g5] ! Store miss to create fill, thus an error trap | |
218 | membar #Sync | |
219 | ||
220 | check_DRAM_ESR_0: | |
221 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
222 | ldx [%g5], %l6 | |
223 | ||
224 | compute_dram_ESR: | |
225 | setx 0xffffffffffff0000, %l0,%o2 | |
226 | and %l6,%o2,%l6 | |
227 | mov 0x1, %l1 | |
228 | sllx %l1, DRAM_ES_DAU, %l0 | |
229 | ||
230 | verify_dram_ESR: | |
231 | cmp %l0, %l6 | |
232 | !bne %xcc, test_fail | |
233 | nop | |
234 | ||
235 | check_L2_ESR_0: | |
236 | setx L2_ERR_STAT_REG, %l3, %g5 | |
237 | ! add %g5, L2_BANK_ADDR, %g5 | |
238 | ldx [%g5], %l6 | |
239 | ||
240 | compute_L2_ESR: | |
241 | setx 0xfffffffff0000000, %l3, %l0 | |
242 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits | |
243 | mov 0x1, %l1 | |
244 | sllx %l1, L2ES_DAU, %l0 | |
245 | mov 0x1, %l1 | |
246 | sllx %l1, L2ES_VEU, %l2 | |
247 | or %l0, %l2, %l3 | |
248 | ||
249 | verify_L2_ESR: | |
250 | cmp %l6, %l3 | |
251 | bne %xcc, test_fail | |
252 | nop | |
253 | ||
254 | check_notData_reg: | |
255 | setx L2_NDDM_REG, %l3, %g5 | |
256 | ! add %g5, L2_BANK_ADDR, %g5 | |
257 | ldx [%g5], %l6 | |
258 | ||
259 | compute_notData_reg: | |
260 | setx 0x200002000aa00, %l0, %l1 ! bits [21:18] select way | |
261 | setx 0x3ffffffffffc0, %l0,%o2 | |
262 | and %l6, %o2, %l6 | |
263 | cmp %l6, %l1 | |
264 | bne %xcc, test_fail | |
265 | nop | |
266 | ||
267 | setx L2EA_PA0, %l2, %l3 | |
268 | ! add %l3, L2_BANK_ADDR, %l3 | |
269 | ||
270 | check_l2_EAR: | |
271 | ldx [%l3], %l4 | |
272 | ! Error address is the physical address of the cache line (PA[5:0] 0) | |
273 | setx 0x2000aa00, %l0, %l1 ! bits [21:18] select way | |
274 | setx 0xffffffffc0, %l0,%o2 | |
275 | and %l4, %o2, %l4 | |
276 | cmp %l4, %l1 | |
277 | bne %xcc, test_fail | |
278 | nop | |
279 | ||
280 | check_sw_err_trap: | |
281 | ! Check if a Software Recoverable Error Trap happened | |
282 | set EXECUTED, %l0 | |
283 | cmp %o0, %l0 | |
284 | bne test_fail | |
285 | nop | |
286 | mov TT_SW_Error, %l0 | |
287 | cmp %o1, %l0 | |
288 | bne test_fail | |
289 | nop | |
290 | ||
291 | ||
292 | ba test_pass | |
293 | nop | |
294 | ||
295 | /******************************************************* | |
296 | * Exit code | |
297 | *******************************************************/ | |
298 | ||
299 | test_pass: | |
300 | ta T_GOOD_TRAP | |
301 | ||
302 | ||
303 | test_fail: | |
304 | ta T_BAD_TRAP | |
305 | ||
306 |